Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42436

1

T5

1

T6

125

T27

13

auto[1]

17429

1

T4

1

T10

461

T26

14

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44216

1

T4

1

T5

1

T6

83

auto[1]

15649

1

T6

42

T27

6

T28

86

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	30741	1			T4	1		T5	1		T6	62
others[1]	5059	1			T6	12		T10	37		T27	2
others[2]	5056	1			T6	12		T10	49		T27	2
others[3]	5723	1			T6	9		T10	38		T27	2
interest[1]	3351	1			T6	9		T10	24		T27	1
interest[4]	19954	1			T4	1		T5	1		T6	42
interest[64]	9935	1			T6	21		T10	77		T27	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	13744	1			T5	1		T6	44		T27	2
auto[0]	auto[0]	others[1]	2333	1			T6	9		T28	15		T30	18
auto[0]	auto[0]	others[2]	2233	1			T6	6		T27	2		T28	8
auto[0]	auto[0]	others[3]	2533	1			T6	5		T27	1		T28	11
auto[0]	auto[0]	interest[1]	1475	1			T6	7		T27	1		T28	9
auto[0]	auto[0]	interest[4]	8894	1			T5	1		T6	29		T27	1
auto[0]	auto[0]	interest[64]	4469	1			T6	12		T27	1		T28	24
auto[0]	auto[1]	others[0]	9015	1			T4	1		T10	236		T26	14
auto[0]	auto[1]	others[1]	1423	1			T10	37		T28	5		T29	31
auto[0]	auto[1]	others[2]	1486	1			T10	49		T28	3		T29	27
auto[0]	auto[1]	others[3]	1651	1			T10	38		T28	7		T29	35
auto[0]	auto[1]	interest[1]	964	1			T10	24		T28	2		T29	28
auto[0]	auto[1]	interest[4]	5920	1			T4	1		T10	138		T26	14
auto[0]	auto[1]	interest[64]	2890	1			T10	77		T28	15		T29	78
auto[1]	auto[0]	others[0]	7982	1			T6	18		T27	3		T28	46
auto[1]	auto[0]	others[1]	1303	1			T6	3		T27	2		T28	10
auto[1]	auto[0]	others[2]	1337	1			T6	6		T28	8		T30	5
auto[1]	auto[0]	others[3]	1539	1			T6	4		T27	1		T28	5
auto[1]	auto[0]	interest[1]	912	1			T6	2		T28	7		T30	4
auto[1]	auto[0]	interest[4]	5140	1			T6	13		T27	3		T28	28
auto[1]	auto[0]	interest[64]	2576	1			T6	9		T28	10		T30	16

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal