Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2686577	1			T1	1		T3	1		T4	1
all_values[1]	2686577	1			T1	1		T3	1		T4	1
all_values[2]	2686577	1			T1	1		T3	1		T4	1
all_values[3]	2686577	1			T1	1		T3	1		T4	1
all_values[4]	2686577	1			T1	1		T3	1		T4	1
all_values[5]	2686577	1			T1	1		T3	1		T4	1
all_values[6]	2686577	1			T1	1		T3	1		T4	1
all_values[7]	2686577	1			T1	1		T3	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20711877

1

T1

8

T3

8

T4

8

auto[1]

780739

1

T18

45

T34

24

T37

61

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21465138

1

T1

8

T3

8

T4

8

auto[1]

27478

1

T12

1

T18

30

T34

18

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2461726	1			T1	1		T3	1		T4	1
all_values[0]	auto[0]	auto[1]	11908	1			T18	1		T38	7		T52	41
all_values[0]	auto[1]	auto[0]	211808	1			T18	2		T34	1		T37	9
all_values[0]	auto[1]	auto[1]	1135	1			T18	3		T34	4		T37	1
all_values[1]	auto[0]	auto[0]	2587835	1			T1	1		T3	1		T4	1
all_values[1]	auto[0]	auto[1]	8446	1			T18	1		T34	1		T37	3
all_values[1]	auto[1]	auto[0]	89831	1			T18	5		T34	1		T37	6
all_values[1]	auto[1]	auto[1]	465	1			T18	3		T34	3		T37	4
all_values[2]	auto[0]	auto[0]	2611563	1			T1	1		T3	1		T4	1
all_values[2]	auto[0]	auto[1]	3230	1			T18	3		T34	1		T37	2
all_values[2]	auto[1]	auto[0]	71524	1			T18	1		T34	1		T37	6
all_values[2]	auto[1]	auto[1]	260	1			T18	2		T37	5		T38	9
all_values[3]	auto[0]	auto[0]	2616510	1			T1	1		T3	1		T4	1
all_values[3]	auto[0]	auto[1]	199	1			T18	1		T34	4		T37	3
all_values[3]	auto[1]	auto[0]	69641	1			T18	3		T37	1		T38	2
all_values[3]	auto[1]	auto[1]	227	1			T18	4		T37	4		T38	7
all_values[4]	auto[0]	auto[0]	2610453	1			T1	1		T3	1		T4	1
all_values[4]	auto[0]	auto[1]	200	1			T12	1		T18	1		T37	2
all_values[4]	auto[1]	auto[0]	75704	1			T18	7		T34	2		T37	8
all_values[4]	auto[1]	auto[1]	220	1			T18	2		T34	3		T37	1
all_values[5]	auto[0]	auto[0]	2643597	1			T1	1		T3	1		T4	1
all_values[5]	auto[0]	auto[1]	176	1			T18	1		T37	2		T38	5
all_values[5]	auto[1]	auto[0]	42619	1			T18	1		T37	3		T38	9
all_values[5]	auto[1]	auto[1]	185	1			T18	1		T37	1		T38	6
all_values[6]	auto[0]	auto[0]	2529880	1			T1	1		T3	1		T4	1
all_values[6]	auto[0]	auto[1]	205	1			T18	3		T37	4		T38	5
all_values[6]	auto[1]	auto[0]	156280	1			T18	2		T34	3		T37	1
all_values[6]	auto[1]	auto[1]	212	1			T18	1		T34	1		T37	2
all_values[7]	auto[0]	auto[0]	2625733	1			T1	1		T3	1		T4	1
all_values[7]	auto[0]	auto[1]	216	1			T18	2		T37	4		T38	4
all_values[7]	auto[1]	auto[0]	60434	1			T18	7		T34	4		T37	8
all_values[7]	auto[1]	auto[1]	194	1			T18	1		T34	1		T37	1