Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.77 98.70 96.89 99.01 89.36 98.59 95.56 99.26


Total tests in report: 1151
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
62.82 62.82 92.35 92.35 83.31 83.31 83.99 83.99 15.56 15.56 90.56 90.56 72.78 72.78 1.19 1.19 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.1975229245
75.07 12.25 95.19 2.85 89.19 5.87 84.39 0.40 62.22 46.67 94.44 3.88 80.28 7.50 19.80 18.61 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.1769787078
79.11 4.04 95.76 0.57 90.80 1.61 84.88 0.49 77.78 15.56 94.97 0.53 80.28 0.00 29.31 9.50 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.1683745996
82.62 3.51 96.23 0.47 91.92 1.13 86.56 1.68 80.00 2.22 95.52 0.55 80.56 0.28 47.52 18.22 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.2986288400
85.71 3.09 97.83 1.60 94.48 2.56 88.74 2.17 84.44 4.44 97.61 2.09 85.42 4.86 51.44 3.91 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.1819498496
87.41 1.70 97.86 0.04 94.60 0.12 88.74 0.00 88.89 4.44 97.72 0.10 85.42 0.00 58.66 7.23 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.1243454828
88.84 1.42 97.92 0.06 94.68 0.08 88.74 0.00 88.89 0.00 97.85 0.14 85.42 0.00 68.37 9.70 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.306157997
89.95 1.11 97.92 0.00 94.70 0.03 88.74 0.00 88.89 0.00 97.85 0.00 93.19 7.78 68.37 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1249486038
91.02 1.07 98.32 0.40 94.70 0.00 93.77 5.04 88.89 0.00 98.11 0.26 93.19 0.00 70.15 1.78 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.3308012420
91.65 0.63 98.37 0.05 94.93 0.23 93.77 0.00 91.11 2.22 98.20 0.09 93.19 0.00 71.98 1.83 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1375418551
92.21 0.56 98.37 0.00 95.84 0.91 94.17 0.40 91.11 0.00 98.23 0.03 93.89 0.69 73.86 1.88 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.3792773811
92.75 0.54 98.38 0.01 95.88 0.04 97.33 3.16 91.11 0.00 98.25 0.02 94.17 0.28 74.16 0.30 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.1020790299
93.24 0.49 98.46 0.08 95.93 0.05 97.73 0.40 93.33 2.22 98.34 0.09 94.17 0.00 74.75 0.59 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.2366111418
93.72 0.48 98.46 0.00 95.93 0.00 97.73 0.00 93.33 0.00 98.34 0.00 94.17 0.00 78.12 3.37 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.1076016873
94.09 0.37 98.46 0.00 95.93 0.00 97.73 0.00 93.33 0.00 98.34 0.00 94.17 0.00 80.69 2.57 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.3988739764
94.43 0.34 98.54 0.08 96.14 0.20 98.42 0.69 93.33 0.00 98.44 0.10 94.44 0.28 81.68 0.99 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3321584900
94.75 0.33 98.54 0.00 96.14 0.00 98.42 0.00 93.33 0.00 98.44 0.00 94.44 0.00 83.96 2.28 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1281253648
95.02 0.27 98.54 0.00 96.14 0.00 98.42 0.00 93.33 0.00 98.44 0.00 94.44 0.00 85.84 1.88 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.1077733165
95.26 0.24 98.55 0.01 96.17 0.04 98.42 0.00 93.33 0.00 98.46 0.02 95.14 0.69 86.73 0.89 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.1778797338
95.49 0.23 98.55 0.00 96.38 0.20 98.42 0.00 93.33 0.00 98.46 0.00 95.14 0.00 88.17 1.44 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.1675588493
95.71 0.22 98.55 0.00 96.38 0.00 98.42 0.00 93.33 0.00 98.46 0.00 95.14 0.00 89.70 1.53 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.527133097
95.90 0.19 98.55 0.00 96.38 0.00 98.42 0.00 93.33 0.00 98.46 0.00 95.14 0.00 91.04 1.34 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_all.3991451167
96.03 0.13 98.55 0.00 96.38 0.00 98.42 0.00 93.33 0.00 98.46 0.00 95.14 0.00 91.93 0.89 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.2679965155
96.15 0.12 98.55 0.00 96.38 0.00 98.42 0.00 93.33 0.00 98.46 0.00 95.14 0.00 92.77 0.84 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.3765361153
96.26 0.11 98.61 0.06 96.57 0.19 98.81 0.40 93.33 0.00 98.56 0.10 95.14 0.00 92.77 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.3462650105
96.36 0.10 98.61 0.00 96.57 0.00 98.81 0.00 93.33 0.00 98.56 0.00 95.14 0.00 93.47 0.69 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.2292819189
96.45 0.09 98.61 0.00 96.57 0.00 98.81 0.00 93.33 0.00 98.56 0.00 95.28 0.14 93.96 0.50 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.594265736
96.53 0.08 98.61 0.00 96.57 0.00 98.81 0.00 93.33 0.00 98.56 0.00 95.28 0.00 94.55 0.59 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.3029103073
96.61 0.08 98.61 0.00 96.58 0.01 98.81 0.00 93.33 0.00 98.56 0.00 95.28 0.00 95.10 0.54 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.4172433997
96.68 0.07 98.61 0.00 96.58 0.00 98.81 0.00 93.33 0.00 98.56 0.00 95.28 0.00 95.59 0.50 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.1695292832
96.75 0.07 98.64 0.03 96.58 0.00 98.81 0.00 93.33 0.00 98.58 0.02 95.28 0.00 96.04 0.45 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1495025597
96.79 0.04 98.64 0.00 96.58 0.00 98.81 0.00 93.33 0.00 98.58 0.00 95.28 0.00 96.34 0.30 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.518287973
96.83 0.04 98.67 0.03 96.62 0.04 99.01 0.20 93.33 0.00 98.58 0.00 95.28 0.00 96.34 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.1753975799
96.87 0.04 98.67 0.00 96.62 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.28 0.00 96.58 0.25 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/19.spi_device_stress_all.3846245239
96.90 0.04 98.67 0.00 96.62 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.28 0.00 96.83 0.25 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.325119606
96.94 0.04 98.68 0.02 96.63 0.01 99.01 0.00 93.33 0.00 98.59 0.02 95.28 0.00 97.03 0.20 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.3789780629
96.97 0.03 98.68 0.00 96.69 0.05 99.01 0.00 93.33 0.00 98.59 0.00 95.28 0.00 97.18 0.15 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.13468224
96.99 0.03 98.68 0.00 96.69 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.28 0.00 97.38 0.20 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_all.3677879476
97.02 0.03 98.68 0.00 96.83 0.14 99.01 0.00 93.33 0.00 98.59 0.00 95.28 0.00 97.43 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.414875739
97.04 0.02 98.68 0.00 96.83 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.28 0.00 97.57 0.15 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.1136999898
97.06 0.02 98.68 0.00 96.83 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.28 0.00 97.72 0.15 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.1839215352
97.09 0.02 98.68 0.00 96.83 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.28 0.00 97.87 0.15 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode.4189677273
97.11 0.02 98.68 0.00 96.83 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.28 0.00 98.02 0.15 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.92696821
97.13 0.02 98.68 0.00 96.83 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.42 0.14 98.02 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2238281269
97.15 0.02 98.68 0.00 96.83 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.14 98.02 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.1914169555
97.16 0.01 98.68 0.00 96.83 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 98.12 0.10 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.86921232
97.17 0.01 98.68 0.00 96.83 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 98.22 0.10 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/15.spi_device_stress_all.1081268080
97.19 0.01 98.68 0.00 96.83 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 98.32 0.10 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.1132705885
97.20 0.01 98.68 0.00 96.83 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 98.42 0.10 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode.3105670822
97.22 0.01 98.68 0.00 96.83 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 98.51 0.10 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.224367631
97.23 0.01 98.68 0.00 96.83 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 98.61 0.10 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.2058676291
97.24 0.01 98.68 0.00 96.84 0.01 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 98.66 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.759233312
97.25 0.01 98.68 0.00 96.84 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 98.71 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.3510359634
97.25 0.01 98.68 0.00 96.84 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 98.76 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.1407495001
97.26 0.01 98.68 0.00 96.84 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 98.81 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.3853723513
97.27 0.01 98.68 0.00 96.84 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 98.86 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.845524862
97.28 0.01 98.68 0.00 96.84 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 98.91 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.1482601962
97.28 0.01 98.68 0.00 96.84 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.1878706538
97.29 0.01 98.68 0.00 96.84 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.159714174
97.30 0.01 98.68 0.00 96.84 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.4005616332
97.30 0.01 98.68 0.00 96.84 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/16.spi_device_stress_all.215136506
97.31 0.01 98.68 0.00 96.84 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.3219326304
97.32 0.01 98.68 0.00 96.84 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/26.spi_device_cfg_cmd.3087750262
97.32 0.01 98.68 0.00 96.84 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 99.26 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.4281385937
97.33 0.01 98.70 0.02 96.86 0.03 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.2619060928
97.33 0.01 98.70 0.00 96.89 0.03 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.3435254381

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.3719345343
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1157461523
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1926297945
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2118668739
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.1009043882
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1851981445
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.3477976138
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.184718093
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.936845917
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.1606513024
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2181503642
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4217066683
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2184200013
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.129042772
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.1395182718
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.2870518487
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/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.1282247479
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.596070972
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.3349849019
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.1564234017
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.1451587745
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.3972476156
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1190970633
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.1143257169
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.3262304941
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.3521574331
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.2021589919
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.3438192937
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.4206256710
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.707838146
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.792614054
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.1653241101
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.4200554349
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.190300292
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.1003964186
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.3925543801
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.1875678890
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.3218863749
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.621600343
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.1312577873
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.201547884
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.3778215325
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.4273191017
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.2666402222
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.2334242669
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.3497194870
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.1335091660
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.1432392998
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.558095958
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.1737325772
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.1158353042
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.2078777732
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.3039489545
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2274382603
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.2267200400
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.1283349718
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.2223733505
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.1247872588
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.206509516
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.3181254272
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.4105631603
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.2319235627
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.4102788454
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.1767542169
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.958547
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3216651882
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.17192078
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.2900667042
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1313976371
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.4176538260
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.1005893504
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.2200320563
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.186968079
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.3122708354
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.3669892702
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.2616426454
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.1616697066
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.2501378164
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.1281116204
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.3423280295
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.1845550723
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.3944469751
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.2646862024
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.3767952550
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.540233859
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.3048665860
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.2347897510



Total test records in report: 1151
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.2619060928 Oct 12 02:18:22 PM UTC 24 Oct 12 02:18:31 PM UTC 24 38161682 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.1558082084 Oct 12 02:18:22 PM UTC 24 Oct 12 02:18:31 PM UTC 24 24945120 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.3308012420 Oct 12 02:18:27 PM UTC 24 Oct 12 02:18:32 PM UTC 24 17207899 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3321584900 Oct 12 02:18:27 PM UTC 24 Oct 12 02:18:35 PM UTC 24 686057924 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.86921232 Oct 12 02:18:33 PM UTC 24 Oct 12 02:18:36 PM UTC 24 274962353 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.1020790299 Oct 12 02:18:39 PM UTC 24 Oct 12 02:18:41 PM UTC 24 56563753 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.3470296006 Oct 12 02:18:37 PM UTC 24 Oct 12 02:18:42 PM UTC 24 39270696 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.2809590582 Oct 12 02:18:33 PM UTC 24 Oct 12 02:18:42 PM UTC 24 102117399 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.3385691180 Oct 12 02:18:33 PM UTC 24 Oct 12 02:18:44 PM UTC 24 99351396 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.1975229245 Oct 12 02:18:37 PM UTC 24 Oct 12 02:18:44 PM UTC 24 96712414 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.4213021084 Oct 12 02:18:33 PM UTC 24 Oct 12 02:18:45 PM UTC 24 1690409481 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.3464043115 Oct 12 02:18:37 PM UTC 24 Oct 12 02:18:46 PM UTC 24 145121672 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.2707454482 Oct 12 02:18:43 PM UTC 24 Oct 12 02:18:47 PM UTC 24 57330828 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.2441855301 Oct 12 02:18:43 PM UTC 24 Oct 12 02:18:47 PM UTC 24 390889450 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.3860226223 Oct 12 02:18:44 PM UTC 24 Oct 12 02:18:48 PM UTC 24 45289762 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.3197060122 Oct 12 02:18:43 PM UTC 24 Oct 12 02:18:48 PM UTC 24 209245838 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.18549987 Oct 12 02:18:45 PM UTC 24 Oct 12 02:18:48 PM UTC 24 108552304 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.2543614596 Oct 12 02:18:45 PM UTC 24 Oct 12 02:18:49 PM UTC 24 1546922726 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.3183011906 Oct 12 02:18:46 PM UTC 24 Oct 12 02:18:51 PM UTC 24 68297320 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.3161382109 Oct 12 02:18:49 PM UTC 24 Oct 12 02:18:51 PM UTC 24 11560402 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.2497709287 Oct 12 02:18:48 PM UTC 24 Oct 12 02:18:51 PM UTC 24 19312115 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.539449938 Oct 12 02:18:42 PM UTC 24 Oct 12 02:18:51 PM UTC 24 17525629 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.1753975799 Oct 12 02:18:42 PM UTC 24 Oct 12 02:18:51 PM UTC 24 18250972 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.1683745996 Oct 12 02:18:44 PM UTC 24 Oct 12 02:18:52 PM UTC 24 404712208 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.3462650105 Oct 12 02:18:48 PM UTC 24 Oct 12 02:18:52 PM UTC 24 34742915 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.3718282180 Oct 12 02:19:07 PM UTC 24 Oct 12 02:19:09 PM UTC 24 200313937 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.1249577963 Oct 12 02:18:43 PM UTC 24 Oct 12 02:18:52 PM UTC 24 1225702641 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.3577385095 Oct 12 02:18:47 PM UTC 24 Oct 12 02:18:52 PM UTC 24 13172385 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.565712832 Oct 12 02:18:51 PM UTC 24 Oct 12 02:18:53 PM UTC 24 41450721 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.1554645625 Oct 12 02:18:47 PM UTC 24 Oct 12 02:18:53 PM UTC 24 80496863 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2746496849 Oct 12 02:18:33 PM UTC 24 Oct 12 02:18:53 PM UTC 24 14758332430 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.3445285632 Oct 12 02:18:51 PM UTC 24 Oct 12 02:18:54 PM UTC 24 231682701 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.681784872 Oct 12 02:18:34 PM UTC 24 Oct 12 02:18:54 PM UTC 24 1406722262 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.3740051950 Oct 12 02:18:52 PM UTC 24 Oct 12 02:18:55 PM UTC 24 50301811 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.3789780629 Oct 12 02:18:44 PM UTC 24 Oct 12 02:18:55 PM UTC 24 1275294142 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.1593678152 Oct 12 02:18:45 PM UTC 24 Oct 12 02:18:56 PM UTC 24 644777560 ps
T400 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.895196706 Oct 12 02:18:53 PM UTC 24 Oct 12 02:18:56 PM UTC 24 81383607 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.812275475 Oct 12 02:18:54 PM UTC 24 Oct 12 02:18:57 PM UTC 24 61908004 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.1055467081 Oct 12 02:18:54 PM UTC 24 Oct 12 02:18:57 PM UTC 24 90141329 ps
T401 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.1967999859 Oct 12 02:18:56 PM UTC 24 Oct 12 02:18:58 PM UTC 24 46960760 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.1825012154 Oct 12 02:18:56 PM UTC 24 Oct 12 02:18:58 PM UTC 24 11413827 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.2617175865 Oct 12 02:18:52 PM UTC 24 Oct 12 02:18:58 PM UTC 24 592471071 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.866781724 Oct 12 02:18:45 PM UTC 24 Oct 12 02:18:58 PM UTC 24 3085093308 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.960828658 Oct 12 02:18:51 PM UTC 24 Oct 12 02:18:58 PM UTC 24 2379074295 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.97623242 Oct 12 02:18:53 PM UTC 24 Oct 12 02:18:59 PM UTC 24 136270085 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.3110675452 Oct 12 02:18:53 PM UTC 24 Oct 12 02:19:00 PM UTC 24 138999996 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.1819498496 Oct 12 02:18:32 PM UTC 24 Oct 12 02:19:02 PM UTC 24 2272981246 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.97093491 Oct 12 02:18:57 PM UTC 24 Oct 12 02:19:02 PM UTC 24 27751061 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.959945418 Oct 12 02:18:57 PM UTC 24 Oct 12 02:19:02 PM UTC 24 256781180 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.710684820 Oct 12 02:18:52 PM UTC 24 Oct 12 02:19:03 PM UTC 24 2630938695 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.845524862 Oct 12 02:18:36 PM UTC 24 Oct 12 02:19:03 PM UTC 24 209269786 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.2067677296 Oct 12 02:18:53 PM UTC 24 Oct 12 02:19:03 PM UTC 24 676166913 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.1236615122 Oct 12 02:18:57 PM UTC 24 Oct 12 02:19:03 PM UTC 24 53521394 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.105646444 Oct 12 02:18:34 PM UTC 24 Oct 12 02:19:04 PM UTC 24 7757604377 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.1438575389 Oct 12 02:18:59 PM UTC 24 Oct 12 02:19:04 PM UTC 24 112874463 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.1365984666 Oct 12 02:18:58 PM UTC 24 Oct 12 02:19:05 PM UTC 24 2987619043 ps
T402 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.2752920604 Oct 12 02:19:03 PM UTC 24 Oct 12 02:19:05 PM UTC 24 37660285 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.552004477 Oct 12 02:18:58 PM UTC 24 Oct 12 02:19:06 PM UTC 24 194167497 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.727797472 Oct 12 02:19:04 PM UTC 24 Oct 12 02:19:06 PM UTC 24 13122531 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.3328431824 Oct 12 02:19:04 PM UTC 24 Oct 12 02:19:06 PM UTC 24 157935769 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.1760286878 Oct 12 02:19:01 PM UTC 24 Oct 12 02:19:06 PM UTC 24 6217355874 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.426837314 Oct 12 02:19:04 PM UTC 24 Oct 12 02:19:07 PM UTC 24 151381111 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.3128324943 Oct 12 02:19:04 PM UTC 24 Oct 12 02:19:07 PM UTC 24 63335096 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.3619959555 Oct 12 02:18:43 PM UTC 24 Oct 12 02:19:08 PM UTC 24 34233716513 ps
T120 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.3865958693 Oct 12 02:19:05 PM UTC 24 Oct 12 02:19:08 PM UTC 24 58093891 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.2594920173 Oct 12 02:19:05 PM UTC 24 Oct 12 02:19:08 PM UTC 24 60026984 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.759233312 Oct 12 02:18:37 PM UTC 24 Oct 12 02:19:09 PM UTC 24 1652176967 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.2366111418 Oct 12 02:18:53 PM UTC 24 Oct 12 02:19:10 PM UTC 24 7607000776 ps
T118 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2418791275 Oct 12 02:19:05 PM UTC 24 Oct 12 02:19:11 PM UTC 24 515586268 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.3518766253 Oct 12 02:18:59 PM UTC 24 Oct 12 02:19:16 PM UTC 24 945409845 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.4281385937 Oct 12 02:18:58 PM UTC 24 Oct 12 02:19:11 PM UTC 24 1825040803 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.3317804610 Oct 12 02:19:07 PM UTC 24 Oct 12 02:19:11 PM UTC 24 1571003592 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.220534920 Oct 12 02:19:08 PM UTC 24 Oct 12 02:19:13 PM UTC 24 279037416 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.2063681521 Oct 12 02:19:05 PM UTC 24 Oct 12 02:19:14 PM UTC 24 504549253 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.1722641189 Oct 12 02:19:11 PM UTC 24 Oct 12 02:19:14 PM UTC 24 154335301 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.1769787078 Oct 12 02:18:37 PM UTC 24 Oct 12 02:19:15 PM UTC 24 14831278898 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.824292177 Oct 12 02:19:13 PM UTC 24 Oct 12 02:19:15 PM UTC 24 66474161 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.619469743 Oct 12 02:19:14 PM UTC 24 Oct 12 02:19:16 PM UTC 24 17915425 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.2189130141 Oct 12 02:19:14 PM UTC 24 Oct 12 02:19:16 PM UTC 24 45896359 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.1224311301 Oct 12 02:19:08 PM UTC 24 Oct 12 02:19:17 PM UTC 24 1913754279 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.501716674 Oct 12 02:19:15 PM UTC 24 Oct 12 02:19:18 PM UTC 24 26773251 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.2251872027 Oct 12 02:19:10 PM UTC 24 Oct 12 02:19:18 PM UTC 24 1000923152 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.1375454624 Oct 12 02:19:16 PM UTC 24 Oct 12 02:19:18 PM UTC 24 64647098 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.13468224 Oct 12 02:19:09 PM UTC 24 Oct 12 02:19:18 PM UTC 24 456796102 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.4131931720 Oct 12 02:19:16 PM UTC 24 Oct 12 02:19:20 PM UTC 24 102602400 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.3020916944 Oct 12 02:18:49 PM UTC 24 Oct 12 02:19:20 PM UTC 24 3851939274 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.4210982352 Oct 12 02:18:59 PM UTC 24 Oct 12 02:19:21 PM UTC 24 2803962300 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.1270304927 Oct 12 02:18:57 PM UTC 24 Oct 12 02:19:21 PM UTC 24 20912080240 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.2251475126 Oct 12 02:19:15 PM UTC 24 Oct 12 02:19:21 PM UTC 24 2000171935 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.2221936916 Oct 12 02:19:19 PM UTC 24 Oct 12 02:19:24 PM UTC 24 264034841 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.2788230795 Oct 12 02:19:18 PM UTC 24 Oct 12 02:19:25 PM UTC 24 344272043 ps
T405 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.3041205116 Oct 12 02:19:09 PM UTC 24 Oct 12 02:19:25 PM UTC 24 18787196902 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.1731391957 Oct 12 02:19:07 PM UTC 24 Oct 12 02:19:26 PM UTC 24 13163603625 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.2625544814 Oct 12 02:19:19 PM UTC 24 Oct 12 02:19:26 PM UTC 24 302999996 ps
T406 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.1040599971 Oct 12 02:19:25 PM UTC 24 Oct 12 02:19:28 PM UTC 24 196677543 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.3203137274 Oct 12 02:19:16 PM UTC 24 Oct 12 02:19:28 PM UTC 24 4419432929 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.3793621696 Oct 12 02:19:27 PM UTC 24 Oct 12 02:19:29 PM UTC 24 15484482 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.3161300149 Oct 12 02:19:17 PM UTC 24 Oct 12 02:19:29 PM UTC 24 633047986 ps
T408 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.3972476156 Oct 12 02:19:27 PM UTC 24 Oct 12 02:19:29 PM UTC 24 32225636 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.3836653784 Oct 12 02:19:21 PM UTC 24 Oct 12 02:19:31 PM UTC 24 2461720375 ps
T409 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.4206256710 Oct 12 02:19:29 PM UTC 24 Oct 12 02:19:31 PM UTC 24 93529873 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.2832992231 Oct 12 02:19:19 PM UTC 24 Oct 12 02:19:32 PM UTC 24 1714357990 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.4263035003 Oct 12 02:19:20 PM UTC 24 Oct 12 02:19:33 PM UTC 24 5617912072 ps
T124 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.3924423825 Oct 12 02:18:58 PM UTC 24 Oct 12 02:19:34 PM UTC 24 33218480404 ps
T396 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.3438192937 Oct 12 02:19:30 PM UTC 24 Oct 12 02:19:38 PM UTC 24 570990804 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.485596142 Oct 12 02:18:54 PM UTC 24 Oct 12 02:19:39 PM UTC 24 2724162132 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.707838146 Oct 12 02:19:32 PM UTC 24 Oct 12 02:19:39 PM UTC 24 327570650 ps
T410 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.2021589919 Oct 12 02:19:27 PM UTC 24 Oct 12 02:19:39 PM UTC 24 11933033839 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1495025597 Oct 12 02:19:30 PM UTC 24 Oct 12 02:19:41 PM UTC 24 323306426 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.1589921398 Oct 12 02:18:45 PM UTC 24 Oct 12 02:19:42 PM UTC 24 2279930850 ps
T392 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.1179792594 Oct 12 02:19:16 PM UTC 24 Oct 12 02:19:44 PM UTC 24 1715677055 ps
T121 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.274226396 Oct 12 02:19:33 PM UTC 24 Oct 12 02:19:44 PM UTC 24 794755804 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.1675588493 Oct 12 02:18:37 PM UTC 24 Oct 12 02:19:44 PM UTC 24 15522058258 ps
T411 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.4146561548 Oct 12 02:19:45 PM UTC 24 Oct 12 02:19:48 PM UTC 24 50945559 ps
T412 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.4200554349 Oct 12 02:19:45 PM UTC 24 Oct 12 02:19:48 PM UTC 24 74048736 ps
T413 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.621600343 Oct 12 02:19:45 PM UTC 24 Oct 12 02:19:48 PM UTC 24 14585244 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.596070972 Oct 12 02:19:34 PM UTC 24 Oct 12 02:19:49 PM UTC 24 771528514 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.1143257169 Oct 12 02:19:40 PM UTC 24 Oct 12 02:19:50 PM UTC 24 5713398224 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.1335091660 Oct 12 02:19:49 PM UTC 24 Oct 12 02:19:52 PM UTC 24 35786232 ps
T415 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.3497194870 Oct 12 02:19:49 PM UTC 24 Oct 12 02:19:52 PM UTC 24 35093388 ps
T416 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.2334242669 Oct 12 02:19:49 PM UTC 24 Oct 12 02:19:54 PM UTC 24 223299423 ps
T417 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.1451587745 Oct 12 02:19:32 PM UTC 24 Oct 12 02:19:54 PM UTC 24 6748194437 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.2666402222 Oct 12 02:19:49 PM UTC 24 Oct 12 02:19:55 PM UTC 24 196122323 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.1282247479 Oct 12 02:19:41 PM UTC 24 Oct 12 02:19:56 PM UTC 24 4105098747 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1190970633 Oct 12 02:19:30 PM UTC 24 Oct 12 02:19:57 PM UTC 24 17152946923 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.1875678890 Oct 12 02:19:53 PM UTC 24 Oct 12 02:20:00 PM UTC 24 126930286 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.1312577873 Oct 12 02:19:53 PM UTC 24 Oct 12 02:20:00 PM UTC 24 4959053343 ps
T418 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.3218863749 Oct 12 02:19:55 PM UTC 24 Oct 12 02:20:00 PM UTC 24 122706326 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.1653241101 Oct 12 02:19:56 PM UTC 24 Oct 12 02:20:00 PM UTC 24 182497072 ps
T129 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.201547884 Oct 12 02:19:52 PM UTC 24 Oct 12 02:20:02 PM UTC 24 981739246 ps
T119 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.3544521428 Oct 12 02:18:57 PM UTC 24 Oct 12 02:20:05 PM UTC 24 6647281923 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.543457461 Oct 12 02:18:44 PM UTC 24 Oct 12 02:20:06 PM UTC 24 33650469090 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.1432392998 Oct 12 02:19:55 PM UTC 24 Oct 12 02:20:07 PM UTC 24 7212356095 ps
T122 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.3778215325 Oct 12 02:20:00 PM UTC 24 Oct 12 02:20:07 PM UTC 24 259478385 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.1564234017 Oct 12 02:19:32 PM UTC 24 Oct 12 02:20:08 PM UTC 24 10192999688 ps
T419 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.792614054 Oct 12 02:20:06 PM UTC 24 Oct 12 02:20:08 PM UTC 24 16391379 ps
T420 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.1158353042 Oct 12 02:20:07 PM UTC 24 Oct 12 02:20:09 PM UTC 24 125172785 ps
T421 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.206509516 Oct 12 02:20:08 PM UTC 24 Oct 12 02:20:11 PM UTC 24 33912478 ps
T422 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3216651882 Oct 12 02:20:09 PM UTC 24 Oct 12 02:20:12 PM UTC 24 80833515 ps
T398 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.958547 Oct 12 02:20:10 PM UTC 24 Oct 12 02:20:12 PM UTC 24 11779088 ps
T423 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.3181254272 Oct 12 02:20:11 PM UTC 24 Oct 12 02:20:15 PM UTC 24 94693570 ps
T424 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.1767542169 Oct 12 02:20:08 PM UTC 24 Oct 12 02:20:15 PM UTC 24 712132977 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.2891249654 Oct 12 02:19:22 PM UTC 24 Oct 12 02:20:16 PM UTC 24 9353724677 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.4231937739 Oct 12 02:19:08 PM UTC 24 Oct 12 02:20:16 PM UTC 24 71521019000 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.2223733505 Oct 12 02:20:13 PM UTC 24 Oct 12 02:20:18 PM UTC 24 109922249 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.3925543801 Oct 12 02:19:58 PM UTC 24 Oct 12 02:20:20 PM UTC 24 11468963265 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.17192078 Oct 12 02:20:17 PM UTC 24 Oct 12 02:20:25 PM UTC 24 5021910057 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.1737325772 Oct 12 02:20:17 PM UTC 24 Oct 12 02:20:26 PM UTC 24 317400097 ps
T394 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.3521574331 Oct 12 02:19:29 PM UTC 24 Oct 12 02:20:26 PM UTC 24 15482951450 ps
T425 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.4105631603 Oct 12 02:20:21 PM UTC 24 Oct 12 02:20:27 PM UTC 24 489442904 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.1003964186 Oct 12 02:19:57 PM UTC 24 Oct 12 02:20:27 PM UTC 24 4150724589 ps
T426 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.558095958 Oct 12 02:20:28 PM UTC 24 Oct 12 02:20:30 PM UTC 24 108216170 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.2319235627 Oct 12 02:20:28 PM UTC 24 Oct 12 02:20:31 PM UTC 24 38696786 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.559477492 Oct 12 02:19:03 PM UTC 24 Oct 12 02:20:32 PM UTC 24 27146751074 ps
T427 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.4176538260 Oct 12 02:20:31 PM UTC 24 Oct 12 02:20:34 PM UTC 24 13579397 ps
T428 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.2501378164 Oct 12 02:20:32 PM UTC 24 Oct 12 02:20:34 PM UTC 24 34401951 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.92696821 Oct 12 02:20:12 PM UTC 24 Oct 12 02:20:35 PM UTC 24 3716887855 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1375418551 Oct 12 02:20:02 PM UTC 24 Oct 12 02:20:36 PM UTC 24 32087715423 ps
T429 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.3048665860 Oct 12 02:20:35 PM UTC 24 Oct 12 02:20:38 PM UTC 24 222652007 ps
T397 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.540233859 Oct 12 02:20:35 PM UTC 24 Oct 12 02:20:38 PM UTC 24 23414042 ps
T430 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.2267200400 Oct 12 02:20:18 PM UTC 24 Oct 12 02:20:38 PM UTC 24 4483760572 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.3660189256 Oct 12 02:19:01 PM UTC 24 Oct 12 02:20:46 PM UTC 24 57235103711 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.2347897510 Oct 12 02:20:40 PM UTC 24 Oct 12 02:20:51 PM UTC 24 1191184798 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.2616426454 Oct 12 02:20:38 PM UTC 24 Oct 12 02:20:53 PM UTC 24 3701704434 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.1482601962 Oct 12 02:18:45 PM UTC 24 Oct 12 02:20:53 PM UTC 24 191108122206 ps
T390 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.4102788454 Oct 12 02:20:09 PM UTC 24 Oct 12 02:20:53 PM UTC 24 24638673023 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2274382603 Oct 12 02:20:27 PM UTC 24 Oct 12 02:20:54 PM UTC 24 1600841408 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.1281116204 Oct 12 02:20:37 PM UTC 24 Oct 12 02:20:54 PM UTC 24 2035251881 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.1616697066 Oct 12 02:20:40 PM UTC 24 Oct 12 02:20:54 PM UTC 24 2586189087 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1313976371 Oct 12 02:20:47 PM UTC 24 Oct 12 02:20:57 PM UTC 24 931635257 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.3039489545 Oct 12 02:20:27 PM UTC 24 Oct 12 02:20:58 PM UTC 24 11976494714 ps
T431 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.2900667042 Oct 12 02:20:57 PM UTC 24 Oct 12 02:21:00 PM UTC 24 21543189 ps
T432 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.298059820 Oct 12 02:20:59 PM UTC 24 Oct 12 02:21:02 PM UTC 24 24693070 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.3423280295 Oct 12 02:20:35 PM UTC 24 Oct 12 02:21:03 PM UTC 24 9608398513 ps
T433 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.2773745939 Oct 12 02:21:01 PM UTC 24 Oct 12 02:21:03 PM UTC 24 25372355 ps
T434 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.3767952550 Oct 12 02:20:33 PM UTC 24 Oct 12 02:21:04 PM UTC 24 19857934106 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.2241130512 Oct 12 02:18:45 PM UTC 24 Oct 12 02:21:06 PM UTC 24 35652720186 ps
T435 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.1575159538 Oct 12 02:21:04 PM UTC 24 Oct 12 02:21:06 PM UTC 24 320391927 ps
T436 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.1845550723 Oct 12 02:20:54 PM UTC 24 Oct 12 02:21:07 PM UTC 24 737258355 ps
T437 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.331150267 Oct 12 02:21:05 PM UTC 24 Oct 12 02:21:09 PM UTC 24 122544661 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.2586709379 Oct 12 02:21:08 PM UTC 24 Oct 12 02:21:17 PM UTC 24 352470936 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.568696044 Oct 12 02:21:07 PM UTC 24 Oct 12 02:21:18 PM UTC 24 4712150330 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.3522615909 Oct 12 02:19:10 PM UTC 24 Oct 12 02:21:19 PM UTC 24 58170207215 ps
T438 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.1507880257 Oct 12 02:21:10 PM UTC 24 Oct 12 02:21:21 PM UTC 24 508663740 ps
T439 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.3122708354 Oct 12 02:20:52 PM UTC 24 Oct 12 02:21:23 PM UTC 24 9056535274 ps
T440 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.615160010 Oct 12 02:21:19 PM UTC 24 Oct 12 02:21:26 PM UTC 24 533055186 ps
T441 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.3852754697 Oct 12 02:21:18 PM UTC 24 Oct 12 02:21:27 PM UTC 24 381507255 ps
T442 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.1745571290 Oct 12 02:21:22 PM UTC 24 Oct 12 02:21:27 PM UTC 24 1067737759 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.1272501148 Oct 12 02:21:12 PM UTC 24 Oct 12 02:21:32 PM UTC 24 2253106044 ps
T443 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.3680784314 Oct 12 02:21:32 PM UTC 24 Oct 12 02:21:35 PM UTC 24 12520682 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.1243454828 Oct 12 02:19:21 PM UTC 24 Oct 12 02:21:36 PM UTC 24 18048703654 ps
T444 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.250985917 Oct 12 02:21:03 PM UTC 24 Oct 12 02:21:36 PM UTC 24 24457150675 ps
T445 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.1387816167 Oct 12 02:21:36 PM UTC 24 Oct 12 02:21:38 PM UTC 24 45124938 ps
T446 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.2656959804 Oct 12 02:21:37 PM UTC 24 Oct 12 02:21:40 PM UTC 24 39003267 ps
T391 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.1981284818 Oct 12 02:21:04 PM UTC 24 Oct 12 02:21:42 PM UTC 24 4560174945 ps
T447 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.1485225377 Oct 12 02:21:37 PM UTC 24 Oct 12 02:21:42 PM UTC 24 725538680 ps
T448 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.3908577416 Oct 12 02:21:40 PM UTC 24 Oct 12 02:21:43 PM UTC 24 958271628 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.1247872588 Oct 12 02:20:17 PM UTC 24 Oct 12 02:21:43 PM UTC 24 25431371477 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.1283349718 Oct 12 02:20:19 PM UTC 24 Oct 12 02:21:45 PM UTC 24 16819488039 ps
T393 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.2646862024 Oct 12 02:20:34 PM UTC 24 Oct 12 02:21:45 PM UTC 24 75717376750 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.518287973 Oct 12 02:19:40 PM UTC 24 Oct 12 02:21:45 PM UTC 24 6454738793 ps
T395 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.1137528097 Oct 12 02:21:39 PM UTC 24 Oct 12 02:21:47 PM UTC 24 435834761 ps
T449 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.3010537287 Oct 12 02:21:43 PM UTC 24 Oct 12 02:21:47 PM UTC 24 31133850 ps
T450 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.1988964094 Oct 12 02:21:44 PM UTC 24 Oct 12 02:21:48 PM UTC 24 70955170 ps
T451 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.2185410598 Oct 12 02:21:43 PM UTC 24 Oct 12 02:21:50 PM UTC 24 101240667 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.3370080617 Oct 12 02:18:53 PM UTC 24 Oct 12 02:21:50 PM UTC 24 36121741700 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.2986288400 Oct 12 02:19:24 PM UTC 24 Oct 12 02:21:51 PM UTC 24 22358284934 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.749615142 Oct 12 02:21:48 PM UTC 24 Oct 12 02:21:54 PM UTC 24 265982363 ps
T452 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.629455850 Oct 12 02:21:49 PM UTC 24 Oct 12 02:21:55 PM UTC 24 115185292 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.2574529603 Oct 12 02:21:46 PM UTC 24 Oct 12 02:21:55 PM UTC 24 2821240196 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.306157997 Oct 12 02:19:11 PM UTC 24 Oct 12 02:21:58 PM UTC 24 25002344073 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.2627408291 Oct 12 02:21:07 PM UTC 24 Oct 12 02:21:58 PM UTC 24 9751463260 ps
T453 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.2543522100 Oct 12 02:21:56 PM UTC 24 Oct 12 02:21:58 PM UTC 24 19075358 ps
T454 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.3956215133 Oct 12 02:21:56 PM UTC 24 Oct 12 02:21:58 PM UTC 24 17008361 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.408056306 Oct 12 02:21:44 PM UTC 24 Oct 12 02:21:59 PM UTC 24 725089509 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.3347928594 Oct 12 02:21:46 PM UTC 24 Oct 12 02:22:00 PM UTC 24 990436033 ps
T455 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.1115002600 Oct 12 02:21:58 PM UTC 24 Oct 12 02:22:01 PM UTC 24 26147898 ps
T456 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.3206111929 Oct 12 02:22:00 PM UTC 24 Oct 12 02:22:02 PM UTC 24 30034884 ps
T457 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.1390647978 Oct 12 02:22:00 PM UTC 24 Oct 12 02:22:03 PM UTC 24 60991134 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.1076016873 Oct 12 02:18:38 PM UTC 24 Oct 12 02:22:07 PM UTC 24 7671533195 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mailbox.4226060949 Oct 12 02:21:45 PM UTC 24 Oct 12 02:22:08 PM UTC 24 1466984903 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.3413031417 Oct 12 02:19:11 PM UTC 24 Oct 12 02:22:09 PM UTC 24 43649593774 ps
T458 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.552302969 Oct 12 02:22:00 PM UTC 24 Oct 12 02:22:12 PM UTC 24 2833364516 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.671260960 Oct 12 02:22:02 PM UTC 24 Oct 12 02:22:12 PM UTC 24 5483216343 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1281253648 Oct 12 02:20:01 PM UTC 24 Oct 12 02:22:13 PM UTC 24 5371175925 ps
T459 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.574006715 Oct 12 02:22:10 PM UTC 24 Oct 12 02:22:14 PM UTC 24 103001304 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.773804230 Oct 12 02:22:09 PM UTC 24 Oct 12 02:22:14 PM UTC 24 1206019373 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.2522938636 Oct 12 02:22:05 PM UTC 24 Oct 12 02:22:15 PM UTC 24 1745911184 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.2601689664 Oct 12 02:22:02 PM UTC 24 Oct 12 02:22:18 PM UTC 24 3784974435 ps
T460 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.4221803129 Oct 12 02:22:16 PM UTC 24 Oct 12 02:22:18 PM UTC 24 14288470 ps
T461 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.68225416 Oct 12 02:22:13 PM UTC 24 Oct 12 02:22:21 PM UTC 24 139958824 ps
T462 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.1553457140 Oct 12 02:22:19 PM UTC 24 Oct 12 02:22:21 PM UTC 24 56131351 ps
T463 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.986846355 Oct 12 02:22:19 PM UTC 24 Oct 12 02:22:21 PM UTC 24 161080688 ps
T464 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.2445577795 Oct 12 02:22:05 PM UTC 24 Oct 12 02:22:22 PM UTC 24 2451360079 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_all.2867850006 Oct 12 02:22:13 PM UTC 24 Oct 12 02:22:22 PM UTC 24 362404317 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.3970929791 Oct 12 02:22:10 PM UTC 24 Oct 12 02:22:23 PM UTC 24 438038631 ps
T465 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.205850929 Oct 12 02:22:22 PM UTC 24 Oct 12 02:22:24 PM UTC 24 41322537 ps
T466 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.1706085298 Oct 12 02:22:23 PM UTC 24 Oct 12 02:22:25 PM UTC 24 41124069 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.3765361153 Oct 12 02:21:27 PM UTC 24 Oct 12 02:22:29 PM UTC 24 9214681649 ps
T467 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.3073065075 Oct 12 02:22:22 PM UTC 24 Oct 12 02:22:31 PM UTC 24 616590190 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mailbox.2101199275 Oct 12 02:22:27 PM UTC 24 Oct 12 02:22:31 PM UTC 24 519258080 ps
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