Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg
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Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
72.73 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 5 1 4 80.00
Crosses 6 2 4 66.67


Variables for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_mode 3 1 2 66.67 100 1 1 0
cp_tpm_enabled 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 6 2 4 66.67 100 1 1 0


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 1 2 66.67


Automatically Generated Bins for cp_mode

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[DisabledMode] 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[FlashMode] 77666 1 T4 135 T5 5 T8 8
auto[PassthroughMode] 49505 1 T9 4 T11 4 T14 2


Summary for Variable cp_tpm_enabled

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_tpm_enabled

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 31291 1 T9 4 T11 4 T12 1
auto[1] 95880 1 T4 135 T5 5 T8 8


Summary for Cross cr_all

Samples crossed: cp_mode cp_tpm_enabled
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 6 2 4 66.67 2


Automatically Generated Cross Bins for cr_all

Element holes
cp_modecp_tpm_enabledCOUNTAT LEASTNUMBERSTATUS
[auto[DisabledMode]] * -- -- 2


Covered bins
cp_mode   cp_tpm_enabled   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[FlashMode] auto[0] 15736 1 T12 1 T17 1 T204 3
auto[FlashMode] auto[1] 61930 1 T4 135 T5 5 T8 8
auto[PassthroughMode] auto[0] 15555 1 T9 4 T11 4 T14 2
auto[PassthroughMode] auto[1] 33950 1 T67 246 T50 488 T73 670