Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35849	1			T16	4		T21	2		T22	4
auto[SpiFlashAddrCfg]	7657	1			T14	2		T23	4		T25	2
auto[SpiFlashAddr3b]	9612	1			T9	2		T11	2		T12	1
auto[SpiFlashAddr4b]	7902	1			T21	2		T63	8		T56	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34116

1

T9

2

T11

2

T12

1

auto[1]

26904

1

T22

4

T25

8

T63

8

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32558

1

T11

2

T12

1

T14

2

auto[1]

28462

1

T9

2

T21

2

T22

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40880	1			T14	2		T16	4		T21	4
values[1]	1084	1			T52	1		T69	2		T54	12
values[2]	1586	1			T23	2		T58	4		T52	4
values[3]	1565	1			T52	2		T55	1		T128	2
values[4]	1476	1			T56	2		T76	2		T140	4
values[5]	1494	1			T25	2		T57	2		T139	2
values[6]	1525	1			T23	2		T63	4		T57	2
values[7]	1471	1			T12	1		T58	4		T52	2
values[8]	9939	1			T9	2		T11	2		T21	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28891

1

T9

2

T11

2

T14

2

auto[1]

32129

1

T12

1

T139

2

T52

97

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

57445

1

T9

2

T11

2

T12

1

write

3575

1

T57

4

T58

2

T52

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19962

1

T9

2

T11

2

T12

1

valids[0x1]

41058

1

T21

4

T22

4

T23

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1717	1			T98	2		T99	4		T126	6
internal_process_ops[0x5a]	1563	1			T24	2		T99	2		T61	2
internal_process_ops[0x05]	21195	1			T21	2		T22	2		T23	4
internal_process_ops[0x35]	1640	1			T22	2		T23	4		T56	2
internal_process_ops[0x15]	1705	1			T23	4		T98	2		T77	2
internal_process_ops[0x03]	1050	1			T56	2		T57	2		T55	1
internal_process_ops[0x0b]	1027	1			T21	2		T98	2		T61	4
internal_process_ops[0x3b]	1086	1			T56	4		T79	2		T140	2
internal_process_ops[0x6b]	1075	1			T11	2		T58	4		T55	1
internal_process_ops[0xbb]	1064	1			T12	1		T21	2		T23	2
internal_process_ops[0xeb]	1047	1			T9	2		T57	2		T139	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59145

1

T9

2

T11

2

T12

1

auto[1]

1875

1

T58

2

T52

2

T59

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58477

1

T9

2

T11

2

T12

1

auto[1]

2543

1

T52

3

T62

2

T53

9

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9885

1

T16

4

T21

2

T23

14

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5788

1

T22

4

T25

4

T58

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1931

1

T14

2

T23

4

T64

12

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1628

1

T25

2

T58

2

T70

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2327

1

T9

2

T11

2

T21

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2081

1

T25

2

T58

6

T59

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1860

1

T21

2

T56

2

T126

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1803

1

T63

8

T58

4

T59

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

127

1

T72

1

T71

1

T205

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

93

1

T71

1

T50

3

T206

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

93

1

T68

2

T205

1

T207

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

85

1

T66

2

T72

1

T73

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

114

1

T208

2

T129

2

T67

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

118

1

T65

2

T50

3

T74

7

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

63

1

T65

3

T72

1

T50

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

90

1

T72

2

T73

1

T206

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

99

1

T73

1

T206

1

T205

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

111

1

T50

2

T73

2

T74

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

78

1

T71

1

T50

2

T206

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

96

1

T58

2

T59

2

T50

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

121

1

T57

4

T62

2

T72

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

93

1

T67

1

T71

1

T50

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

84

1

T68

1

T71

1

T74

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

123

1

T72

2

T71

1

T74

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10809

1

T52

39

T53

25

T54

173

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8508

1

T52

5

T53

42

T54

141

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1620

1

T52

13

T55

1

T209

1

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1577

1

T52

3

T53

6

T54

14

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2189

1

T12

1

T139

2

T52

4

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2116

1

T52

13

T53

10

T54

27

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1630

1

T52

3

T55

1

T53

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1693

1

T52

11

T53

12

T54

23

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

97

1

T54

2

T91

5

T112

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

124

1

T53

2

T110

1

T111

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

114

1

T54

2

T91

6

T41

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

126

1

T53

2

T41

2

T49

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

121

1

T53

3

T54

1

T91

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

126

1

T54

3

T41

3

T94

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

123

1

T53

1

T92

2

T41

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

146

1

T54

4

T91

2

T92

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

115

1

T93

1

T41

3

T49

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

161

1

T53

3

T54

1

T93

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

127

1

T52

2

T53

1

T91

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

112

1

T52

2

T53

1

T92

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

121

1

T52

2

T91

1

T93

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

124

1

T54

2

T49

2

T50

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

103

1

T54

1

T94

1

T110

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

147

1

T53

1

T54

4

T91

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3667	1			T14	2		T16	4		T23	4
auto[0]	values[0]	valids[0x1]	14768	1			T21	4		T22	4		T23	12
auto[0]	values[1]	valids[0x1]	479	1			T69	2		T65	4		T68	3
auto[0]	values[2]	valids[0x0]	593	1			T58	2		T79	2		T66	2
auto[0]	values[2]	valids[0x1]	276	1			T23	2		T58	2		T66	2
auto[0]	values[3]	valids[0x0]	523	1			T59	2		T208	6		T70	8
auto[0]	values[3]	valids[0x1]	295	1			T128	2		T67	4		T65	4
auto[0]	values[4]	valids[0x0]	473	1			T76	2		T208	4		T210	4
auto[0]	values[4]	valids[0x1]	312	1			T56	2		T140	4		T211	2
auto[0]	values[5]	valids[0x0]	500	1			T25	2		T57	2		T128	2
auto[0]	values[5]	valids[0x1]	264	1			T62	2		T212	2		T67	1
auto[0]	values[6]	valids[0x0]	547	1			T23	2		T63	4		T57	2
auto[0]	values[6]	valids[0x1]	258	1			T67	1		T72	4		T50	1
auto[0]	values[7]	valids[0x0]	494	1			T58	4		T140	2		T208	4
auto[0]	values[7]	valids[0x1]	251	1			T213	4		T72	4		T50	2
auto[0]	values[8]	valids[0x0]	3306	1			T9	2		T11	2		T21	2
auto[0]	values[8]	valids[0x1]	1885	1			T24	2		T56	4		T57	4
auto[1]	values[0]	valids[0x0]	4428	1			T52	17		T53	24		T54	36
auto[1]	values[0]	valids[0x1]	18017	1			T52	39		T55	1		T53	71
auto[1]	values[1]	valids[0x1]	605	1			T52	1		T54	12		T91	9
auto[1]	values[2]	valids[0x0]	411	1			T52	3		T53	1		T54	3
auto[1]	values[2]	valids[0x1]	306	1			T52	1		T54	5		T91	2
auto[1]	values[3]	valids[0x0]	418	1			T52	1		T55	1		T53	1
auto[1]	values[3]	valids[0x1]	329	1			T52	1		T54	4		T91	3
auto[1]	values[4]	valids[0x0]	391	1			T53	4		T54	4		T41	2
auto[1]	values[4]	valids[0x1]	300	1			T53	1		T54	2		T91	6
auto[1]	values[5]	valids[0x0]	443	1			T139	2		T52	1		T54	1
auto[1]	values[5]	valids[0x1]	287	1			T54	1		T214	2		T92	1
auto[1]	values[6]	valids[0x0]	446	1			T52	7		T54	1		T91	5
auto[1]	values[6]	valids[0x1]	274	1			T52	1		T53	3		T214	1
auto[1]	values[7]	valids[0x0]	434	1			T12	1		T52	1		T53	1
auto[1]	values[7]	valids[0x1]	292	1			T52	1		T54	3		T91	5
auto[1]	values[8]	valids[0x0]	2888	1			T52	17		T55	3		T209	1
auto[1]	values[8]	valids[0x1]	1860	1			T52	6		T55	1		T53	4