Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3319221

1

T7

1

T9

1

T11

735

auto[1]

33833

1

T52

17

T62

8

T53

36

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

761981

1

T7

1

T9

1

T11

735

auto[1]

2591073

1

T21

512

T23

12300

T52

2576

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	596466	1			T7	1		T9	1		T12	491
auto[524288:1048575]	408798	1			T21	30		T60	152		T204	187
auto[1048576:1572863]	408404	1			T21	29		T60	6		T98	1886
auto[1572864:2097151]	393723	1			T12	2		T16	3		T21	30
auto[2097152:2621439]	352574	1			T21	480		T60	8		T99	115
auto[2621440:3145727]	351456	1			T11	330		T21	72		T60	2
auto[3145728:3670015]	401855	1			T21	32		T24	1		T102	135
auto[3670016:4194303]	439778	1			T11	405		T21	109		T60	162

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2623701

1

T7

1

T9

1

T11

4

auto[1]

729353

1

T11

731

T12

491

T21

586

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2838832

1

T7

1

T9

1

T11

735

auto[1]

514222

1

T16

1

T60

314

T101

20

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	159425	1			T7	1		T9	1		T12	491
auto[0]	auto[0]	auto[0:524287]	auto[1]	348565	1			T21	181		T23	12300		T52	512
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	94151	1			T21	30		T60	151		T204	187
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	248285	1			T52	639		T53	2		T54	773
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	63147	1			T21	29		T60	6		T98	1886
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	272464	1			T53	1390		T91	2291		T92	227
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	69394	1			T12	2		T16	2		T21	30
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	254367	1			T53	128		T54	899		T91	512
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	71487	1			T21	150		T60	8		T99	115
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	225325	1			T21	330		T54	385		T91	512
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	90515	1			T11	330		T21	71		T60	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	212690	1			T21	1		T52	128		T54	642
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	85085	1			T21	32		T24	1		T102	135
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	240077	1			T52	256		T53	384		T54	128
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	115601	1			T11	405		T21	109		T98	353
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	260389	1			T53	1		T91	2218		T41	377
auto[0]	auto[1]	auto[0:524287]	auto[0]	995	1			T60	147		T101	18		T52	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	81350	1			T54	512		T92	4102		T94	256
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	659	1			T60	1		T54	3		T91	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	59496	1			T54	1549		T91	513		T72	549
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	565	1			T52	2		T54	4		T93	7
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	67674	1			T54	258		T93	512		T94	512
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	2489	1			T16	1		T60	4		T53	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	64231	1			T91	256		T92	893		T93	768
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	599	1			T101	2		T54	1		T91	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	52370	1			T54	256		T91	128		T49	2949
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1133	1			T54	1		T92	5		T49	8
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	43533	1			T54	2794		T91	256		T92	773
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1611	1			T54	1		T91	3		T93	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	70714	1			T54	1		T91	1		T67	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	976	1			T60	162		T52	14		T91	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	59859	1			T52	1027		T91	694		T92	2
auto[1]	auto[0]	auto[0:524287]	auto[0]	538	1			T62	2		T53	5		T54	4
auto[1]	auto[0]	auto[0:524287]	auto[1]	5193	1			T62	6		T53	16		T54	71
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	414	1			T53	2		T93	2		T41	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	4505	1			T53	4		T41	26		T49	21
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	409	1			T53	1		T91	2		T41	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2862	1			T53	6		T91	50		T41	5
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	395	1			T54	2		T93	5		T110	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2318	1			T54	6		T93	64		T110	16
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	465	1			T54	1		T41	1		T67	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1818	1			T54	10		T67	10		T49	19
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	448	1			T54	2		T91	1		T41	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2621	1			T54	43		T91	7		T41	38
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	396	1			T91	1		T93	4		T72	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3187	1			T91	5		T111	4		T50	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	375	1			T53	1		T41	3		T49	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1921	1			T53	1		T41	25		T110	44
auto[1]	auto[1]	auto[0:524287]	auto[0]	92	1			T92	1		T93	8		T72	4
auto[1]	auto[1]	auto[0:524287]	auto[1]	308	1			T92	3		T73	12		T257	70
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	94	1			T54	2		T91	1		T49	4
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	1194	1			T54	3		T91	30		T74	17
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	102	1			T54	2		T49	6		T111	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1181	1			T54	54		T111	25		T73	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	93	1			T41	3		T110	1		T111	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	436	1			T41	6		T110	6		T111	25
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	72	1			T49	5		T73	1		T227	5
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	438	1			T73	6		T297	2		T295	29
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	85	1			T92	2		T111	1		T50	5
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	431	1			T92	1		T50	9		T205	16
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	103	1			T54	1		T91	1		T67	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	682	1			T54	54		T91	25		T67	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	68	1			T52	3		T91	2		T110	4
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	589	1			T52	14		T91	84		T110	42

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2086258	1			T7	1		T9	1		T11	4
auto[0]	auto[0]	auto[1]	724709	1			T11	731		T12	491		T21	586
auto[0]	auto[1]	auto[0]	504409	1			T16	1		T60	6		T101	20
auto[0]	auto[1]	auto[1]	3845	1			T60	308		T54	2		T91	3
auto[1]	auto[0]	auto[0]	27238	1			T62	7		T53	36		T54	138
auto[1]	auto[0]	auto[1]	627	1			T62	1		T54	1		T93	2
auto[1]	auto[1]	auto[0]	5796	1			T52	17		T54	115		T91	140
auto[1]	auto[1]	auto[1]	172	1			T54	1		T91	3		T49	1