Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2686577	1			T1	1		T3	1		T4	1
all_pins[1]	2686577	1			T1	1		T3	1		T4	1
all_pins[2]	2686577	1			T1	1		T3	1		T4	1
all_pins[3]	2686577	1			T1	1		T3	1		T4	1
all_pins[4]	2686577	1			T1	1		T3	1		T4	1
all_pins[5]	2686577	1			T1	1		T3	1		T4	1
all_pins[6]	2686577	1			T1	1		T3	1		T4	1
all_pins[7]	2686577	1			T1	1		T3	1		T4	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21332999	1			T1	8		T3	8		T4	8
values[0x1]	159617	1			T18	17		T34	12		T37	19
transitions[0x0=>0x1]	158221	1			T18	14		T34	8		T37	12
transitions[0x1=>0x0]	158237	1			T18	14		T34	8		T37	12

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2685359	1			T1	1		T3	1		T4	1
all_pins[0]	values[0x1]	1218	1			T18	3		T34	4		T37	1
all_pins[0]	transitions[0x0=>0x1]	918	1			T18	2		T34	1		T38	2
all_pins[0]	transitions[0x1=>0x0]	190	1			T18	2		T37	3		T38	1
all_pins[1]	values[0x0]	2686087	1			T1	1		T3	1		T4	1
all_pins[1]	values[0x1]	490	1			T18	3		T34	3		T37	4
all_pins[1]	transitions[0x0=>0x1]	429	1			T18	3		T34	3		T37	2
all_pins[1]	transitions[0x1=>0x0]	209	1			T18	2		T37	3		T38	7
all_pins[2]	values[0x0]	2686307	1			T1	1		T3	1		T4	1
all_pins[2]	values[0x1]	270	1			T18	2		T37	5		T38	9
all_pins[2]	transitions[0x0=>0x1]	210	1			T18	1		T37	4		T38	6
all_pins[2]	transitions[0x1=>0x0]	167	1			T18	3		T37	3		T38	4
all_pins[3]	values[0x0]	2686350	1			T1	1		T3	1		T4	1
all_pins[3]	values[0x1]	227	1			T18	4		T37	4		T38	7
all_pins[3]	transitions[0x0=>0x1]	165	1			T18	4		T37	3		T38	4
all_pins[3]	transitions[0x1=>0x0]	158	1			T18	2		T34	3		T38	4
all_pins[4]	values[0x0]	2686357	1			T1	1		T3	1		T4	1
all_pins[4]	values[0x1]	220	1			T18	2		T34	3		T37	1
all_pins[4]	transitions[0x0=>0x1]	176	1			T18	2		T34	3		T38	6
all_pins[4]	transitions[0x1=>0x0]	960	1			T18	1		T38	5		T40	3
all_pins[5]	values[0x0]	2685573	1			T1	1		T3	1		T4	1
all_pins[5]	values[0x1]	1004	1			T18	1		T37	1		T38	6
all_pins[5]	transitions[0x0=>0x1]	234	1			T18	1		T37	1		T38	5
all_pins[5]	transitions[0x1=>0x0]	155224	1			T18	1		T34	1		T37	2
all_pins[6]	values[0x0]	2530583	1			T1	1		T3	1		T4	1
all_pins[6]	values[0x1]	155994	1			T18	1		T34	1		T37	2
all_pins[6]	transitions[0x0=>0x1]	155945	1			T18	1		T34	1		T37	2
all_pins[6]	transitions[0x1=>0x0]	145	1			T18	1		T34	1		T37	1
all_pins[7]	values[0x0]	2686383	1			T1	1		T3	1		T4	1
all_pins[7]	values[0x1]	194	1			T18	1		T34	1		T37	1
all_pins[7]	transitions[0x0=>0x1]	144	1			T38	4		T40	4		T50	2
all_pins[7]	transitions[0x1=>0x0]	1184	1			T18	2		T34	3		T38	4