Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16879

1

T9

2

T11

2

T14

2

auto[1]

12012

1

T22

4

T25

8

T63

8

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3610	1			T63	8		T58	20		T140	18
values[1]	3445	1			T16	4		T21	6		T22	4
values[2]	3638	1			T64	12		T56	18		T211	14
values[3]	4216	1			T11	2		T60	24		T102	14
values[4]	3809	1			T9	2		T121	14		T100	10
values[5]	3725	1			T23	20		T98	8		T125	14
values[6]	2948	1			T126	24		T76	4		T79	6
values[7]	3500	1			T14	2		T24	2		T25	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3575	1			T21	6		T60	24		T99	6
values[1]	3214	1			T9	2		T25	8		T58	20
values[2]	4468	1			T98	8		T57	12		T79	6
values[3]	3292	1			T22	4		T102	14		T62	12
values[4]	2857	1			T56	18		T76	4		T77	2
values[5]	3233	1			T101	24		T126	24		T127	10
values[6]	4059	1			T11	2		T14	2		T23	20
values[7]	4193	1			T16	4		T63	8		T211	14

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	240	1			T72	9		T298	6		T299	8
auto[0]	values[0]	values[1]	232	1			T206	8		T300	10		T237	11
auto[0]	values[0]	values[2]	413	1			T124	6		T74	11		T51	10
auto[0]	values[0]	values[3]	144	1			T72	15		T205	16		T207	10
auto[0]	values[0]	values[4]	201	1			T123	16		T205	15		T51	28
auto[0]	values[0]	values[5]	276	1			T128	8		T283	4		T232	9
auto[0]	values[0]	values[6]	322	1			T140	18		T301	10		T205	29
auto[0]	values[0]	values[7]	318	1			T258	20		T242	16		T236	10
auto[0]	values[1]	values[0]	246	1			T21	6		T68	12		T205	16
auto[0]	values[1]	values[1]	236	1			T206	14		T242	24		T302	14
auto[0]	values[1]	values[2]	328	1			T51	11		T232	43		T303	18
auto[0]	values[1]	values[3]	177	1			T234	15		T267	14		T304	10
auto[0]	values[1]	values[4]	162	1			T129	18		T50	9		T74	10
auto[0]	values[1]	values[5]	129	1			T233	9		T305	2		T306	12
auto[0]	values[1]	values[6]	273	1			T67	10		T73	12		T307	4
auto[0]	values[1]	values[7]	181	1			T16	4		T308	6		T309	8
auto[0]	values[2]	values[0]	220	1			T72	6		T207	14		T310	79
auto[0]	values[2]	values[1]	234	1			T278	8		T287	8		T171	7
auto[0]	values[2]	values[2]	575	1			T311	2		T71	15		T205	110
auto[0]	values[2]	values[3]	288	1			T312	2		T242	36		T200	13
auto[0]	values[2]	values[4]	224	1			T56	18		T71	8		T206	8
auto[0]	values[2]	values[5]	147	1			T300	16		T313	9		T314	2
auto[0]	values[2]	values[6]	155	1			T64	12		T253	12		T315	8
auto[0]	values[2]	values[7]	327	1			T211	14		T72	14		T74	10
auto[0]	values[3]	values[0]	259	1			T60	24		T212	6		T50	14
auto[0]	values[3]	values[1]	231	1			T50	20		T74	4		T207	17
auto[0]	values[3]	values[2]	497	1			T316	16		T68	37		T50	38
auto[0]	values[3]	values[3]	181	1			T102	14		T62	12		T269	10
auto[0]	values[3]	values[4]	203	1			T77	2		T213	14		T310	13
auto[0]	values[3]	values[5]	410	1			T101	24		T71	12		T255	60
auto[0]	values[3]	values[6]	340	1			T11	2		T61	6		T210	12
auto[0]	values[3]	values[7]	356	1			T71	14		T50	7		T317	10
auto[0]	values[4]	values[0]	254	1			T318	2		T268	10		T233	34
auto[0]	values[4]	values[1]	110	1			T9	2		T319	8		T271	12
auto[0]	values[4]	values[2]	316	1			T65	13		T73	26		T206	11
auto[0]	values[4]	values[3]	386	1			T205	41		T207	9		T233	32
auto[0]	values[4]	values[4]	440	1			T121	14		T270	74		T309	7
auto[0]	values[4]	values[5]	219	1			T100	10		T72	13		T73	24
auto[0]	values[4]	values[6]	174	1			T71	13		T242	39		T238	15
auto[0]	values[4]	values[7]	527	1			T320	6		T242	95		T234	8
auto[0]	values[5]	values[0]	256	1			T255	6		T166	11		T262	13
auto[0]	values[5]	values[1]	284	1			T250	2		T72	18		T242	7
auto[0]	values[5]	values[2]	306	1			T98	8		T125	14		T242	93
auto[0]	values[5]	values[3]	285	1			T321	8		T322	10		T207	10
auto[0]	values[5]	values[4]	191	1			T291	51		T207	9		T236	10
auto[0]	values[5]	values[5]	178	1			T50	13		T73	23		T205	31
auto[0]	values[5]	values[6]	508	1			T23	20		T141	4		T208	26
auto[0]	values[5]	values[7]	247	1			T73	10		T74	14		T51	11
auto[0]	values[6]	values[0]	230	1			T72	9		T71	14		T50	25
auto[0]	values[6]	values[1]	170	1			T323	14		T207	11		T255	10
auto[0]	values[6]	values[2]	119	1			T79	6		T233	13		T239	14
auto[0]	values[6]	values[3]	165	1			T65	8		T324	2		T282	4
auto[0]	values[6]	values[4]	222	1			T76	4		T73	13		T325	12
auto[0]	values[6]	values[5]	182	1			T126	24		T127	10		T68	9
auto[0]	values[6]	values[6]	316	1			T72	8		T255	40		T166	16
auto[0]	values[6]	values[7]	273	1			T72	12		T50	10		T232	10
auto[0]	values[7]	values[0]	214	1			T99	6		T72	14		T292	12
auto[0]	values[7]	values[1]	247	1			T326	12		T206	13		T327	42
auto[0]	values[7]	values[2]	195	1			T57	12		T286	4		T72	15
auto[0]	values[7]	values[3]	248	1			T233	53		T242	13		T259	11
auto[0]	values[7]	values[4]	202	1			T205	41		T245	14		T255	12
auto[0]	values[7]	values[5]	329	1			T233	10		T166	10		T171	10
auto[0]	values[7]	values[6]	352	1			T14	2		T24	2		T246	20
auto[0]	values[7]	values[7]	209	1			T50	24		T328	2		T267	17
auto[1]	values[0]	values[0]	138	1			T72	11		T299	12		T171	6
auto[1]	values[0]	values[1]	129	1			T58	20		T206	12		T329	4
auto[1]	values[0]	values[2]	232	1			T272	18		T74	32		T51	10
auto[1]	values[0]	values[3]	68	1			T72	5		T205	4		T207	10
auto[1]	values[0]	values[4]	159	1			T205	11		T51	7		T232	14
auto[1]	values[0]	values[5]	195	1			T232	11		T300	4		T237	23
auto[1]	values[0]	values[6]	301	1			T205	8		T233	10		T262	4
auto[1]	values[0]	values[7]	242	1			T63	8		T242	4		T236	13
auto[1]	values[1]	values[0]	292	1			T59	6		T68	8		T205	103
auto[1]	values[1]	values[1]	287	1			T206	6		T242	61		T302	9
auto[1]	values[1]	values[2]	318	1			T69	8		T249	26		T51	9
auto[1]	values[1]	values[3]	157	1			T22	4		T234	6		T267	11
auto[1]	values[1]	values[4]	119	1			T50	11		T74	10		T205	9
auto[1]	values[1]	values[5]	116	1			T233	11		T306	16		T330	10
auto[1]	values[1]	values[6]	203	1			T67	10		T73	9		T205	8
auto[1]	values[1]	values[7]	221	1			T309	12		T233	9		T166	12
auto[1]	values[2]	values[0]	101	1			T72	14		T207	6		T310	4
auto[1]	values[2]	values[1]	216	1			T171	44		T331	7		T199	2
auto[1]	values[2]	values[2]	249	1			T71	5		T205	6		T236	25
auto[1]	values[2]	values[3]	270	1			T242	7		T243	24		T200	15
auto[1]	values[2]	values[4]	125	1			T71	12		T206	25		T207	6
auto[1]	values[2]	values[5]	245	1			T332	12		T300	4		T313	104
auto[1]	values[2]	values[6]	83	1			T234	9		T267	12		T262	19
auto[1]	values[2]	values[7]	179	1			T72	6		T74	21		T233	2
auto[1]	values[3]	values[0]	298	1			T50	6		T242	100		T236	6
auto[1]	values[3]	values[1]	102	1			T74	20		T207	3		T236	13
auto[1]	values[3]	values[2]	259	1			T68	9		T50	75		T281	6
auto[1]	values[3]	values[3]	149	1			T67	21		T333	18		T166	6
auto[1]	values[3]	values[4]	159	1			T310	7		T248	12		T334	8
auto[1]	values[3]	values[5]	145	1			T66	10		T71	8		T335	24
auto[1]	values[3]	values[6]	312	1			T74	27		T205	20		T309	8
auto[1]	values[3]	values[7]	315	1			T71	6		T50	38		T255	6
auto[1]	values[4]	values[0]	189	1			T233	8		T281	28		T231	31
auto[1]	values[4]	values[1]	66	1			T207	7		T259	6		T241	8
auto[1]	values[4]	values[2]	176	1			T65	7		T73	9		T206	9
auto[1]	values[4]	values[3]	211	1			T205	27		T207	11		T233	8
auto[1]	values[4]	values[4]	131	1			T309	15		T166	11		T238	35
auto[1]	values[4]	values[5]	234	1			T72	7		T73	6		T237	9
auto[1]	values[4]	values[6]	143	1			T71	7		T242	11		T238	51
auto[1]	values[4]	values[7]	233	1			T242	7		T234	14		T236	8
auto[1]	values[5]	values[0]	230	1			T265	24		T255	14		T166	9
auto[1]	values[5]	values[1]	247	1			T72	22		T242	18		T234	6
auto[1]	values[5]	values[2]	202	1			T242	11		T281	8		T238	35
auto[1]	values[5]	values[3]	172	1			T207	10		T242	11		T255	5
auto[1]	values[5]	values[4]	84	1			T207	11		T236	16		T262	8
auto[1]	values[5]	values[5]	119	1			T50	7		T73	6		T205	13
auto[1]	values[5]	values[6]	224	1			T50	6		T236	15		T267	6
auto[1]	values[5]	values[7]	192	1			T73	14		T74	8		T51	15
auto[1]	values[6]	values[0]	206	1			T70	18		T72	11		T71	6
auto[1]	values[6]	values[1]	131	1			T336	2		T207	9		T255	25
auto[1]	values[6]	values[2]	94	1			T233	7		T200	6		T237	9
auto[1]	values[6]	values[3]	180	1			T65	12		T75	18		T233	13
auto[1]	values[6]	values[4]	160	1			T73	7		T337	20		T207	8
auto[1]	values[6]	values[5]	141	1			T68	27		T207	6		T300	8
auto[1]	values[6]	values[6]	194	1			T72	12		T255	17		T166	4
auto[1]	values[6]	values[7]	165	1			T72	8		T50	10		T232	15
auto[1]	values[7]	values[0]	202	1			T72	6		T299	7		T338	49
auto[1]	values[7]	values[1]	292	1			T25	8		T206	8		T242	97
auto[1]	values[7]	values[2]	189	1			T72	5		T233	60		T281	21
auto[1]	values[7]	values[3]	211	1			T233	8		T242	7		T259	9
auto[1]	values[7]	values[4]	75	1			T205	9		T255	27		T177	6
auto[1]	values[7]	values[5]	168	1			T233	10		T166	10		T171	15
auto[1]	values[7]	values[6]	159	1			T242	10		T166	3		T256	16
auto[1]	values[7]	values[7]	208	1			T50	9		T267	7		T339	22