Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	376	1			T21	4		T67	1		T278	8
auto[ReadAddrCrossIntoMailbox]	248	1			T67	2		T271	2		T68	3
auto[ReadAddrCrossOutOfMailbox]	277	1			T269	2		T68	2		T72	9
auto[ReadAddrCrossAllMailbox]	200	1			T269	2		T271	4		T68	1
auto[ReadAddrOutsideMailbox]	3452	1			T9	2		T11	2		T23	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2213

1

T9

1

T11

1

T21

2

auto[1]

2340

1

T9

1

T11

1

T21

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	744	1			T56	2		T57	2		T208	2
read_ops[0x0b]	732	1			T21	2		T98	2		T61	4
read_ops[0x3b]	794	1			T56	4		T79	2		T140	2
read_ops[0x6b]	773	1			T11	2		T58	4		T127	4
read_ops[0xbb]	785	1			T21	2		T23	2		T25	2
read_ops[0xeb]	725	1			T9	2		T57	2		T140	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T311	1		T72	2		T50	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T311	1		T309	1		T340	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T68	1		T50	1		T205	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	14	1			T72	1		T50	2		T267	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T269	1		T72	1		T233	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T269	1		T72	1		T73	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T269	1		T68	1		T72	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T269	1		T72	1		T50	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	270	1			T56	1		T57	1		T208	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	286	1			T56	1		T57	1		T208	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T21	1		T278	1		T50	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T21	1		T278	1		T72	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T67	1		T72	2		T233	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T207	1		T255	2		T338	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T207	1		T233	3		T310	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T72	2		T71	1		T232	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T50	1		T340	1		T300	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T72	2		T309	1		T267	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	260	1			T98	1		T61	2		T58	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	296	1			T98	1		T61	2		T58	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T278	2		T50	1		T310	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T278	2		T68	1		T50	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T271	1		T72	1		T292	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T271	1		T292	2		T71	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T68	1		T205	1		T234	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T68	1		T50	1		T236	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T271	1		T71	2		T51	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T271	1		T50	1		T205	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	295	1			T56	2		T79	1		T140	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	307	1			T56	2		T79	1		T140	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T292	1		T50	1		T235	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T65	1		T292	1		T50	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	12	1			T72	1		T341	1		T342	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T67	1		T68	1		T72	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T205	1		T267	1		T306	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T72	1		T50	1		T74	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T50	2		T341	2		T342	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	9	1			T50	1		T206	1		T256	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	312	1			T11	1		T58	2		T127	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	290	1			T11	1		T58	2		T127	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T21	1		T72	1		T207	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T21	1		T65	1		T71	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T72	1		T205	2		T242	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T68	1		T73	1		T242	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T72	3		T71	1		T205	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T71	1		T73	1		T206	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T292	1		T207	1		T233	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T292	1		T73	1		T233	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	287	1			T23	1		T25	1		T126	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	306	1			T23	1		T25	1		T126	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T278	1		T72	1		T235	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T67	1		T278	1		T235	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T72	2		T205	1		T309	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T50	1		T207	1		T233	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T73	1		T242	1		T300	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T72	1		T71	1		T50	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T271	1		T72	1		T73	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T271	1		T72	1		T50	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	270	1			T9	1		T57	1		T140	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	273	1			T9	1		T57	1		T140	2