Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4008	1			T11	2		T102	14		T57	12
values[1]	3487	1			T9	2		T56	18		T210	12
values[2]	3237	1			T14	2		T16	4		T77	2
values[3]	3459	1			T22	4		T98	8		T126	24
values[4]	3597	1			T21	6		T99	6		T101	24
values[5]	4060	1			T24	2		T25	8		T64	12
values[6]	3205	1			T23	20		T60	24		T58	20
values[7]	3838	1			T63	8		T79	6		T127	10

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3756	1			T11	2		T14	2		T102	14
values[1]	4022	1			T25	8		T64	12		T56	18
values[2]	2872	1			T326	12		T69	8		T210	12
values[3]	3602	1			T63	8		T101	24		T77	2
values[4]	3547	1			T9	2		T21	6		T22	4
values[5]	3590	1			T16	4		T60	24		T61	6
values[6]	4179	1			T124	6		T121	14		T67	33
values[7]	3323	1			T23	20		T98	8		T140	18

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28082

1

T9

2

T11

2

T14

2

auto[1]

809

1

T58

2

T59

2

T66

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	332	1			T11	2		T102	14		T283	4
auto[0]	values[0]	values[1]	679	1			T57	12		T70	18		T72	20
auto[0]	values[0]	values[2]	368	1			T286	4		T50	19		T205	20
auto[0]	values[0]	values[3]	572	1			T207	20		T255	37		T262	20
auto[0]	values[0]	values[4]	370	1			T208	26		T258	20		T271	12
auto[0]	values[0]	values[5]	593	1			T72	18		T324	2		T323	14
auto[0]	values[0]	values[6]	340	1			T332	12		T325	12		T236	21
auto[0]	values[0]	values[7]	641	1			T278	8		T213	14		T232	40
auto[0]	values[1]	values[0]	330	1			T272	18		T205	47		T207	19
auto[0]	values[1]	values[1]	654	1			T56	18		T71	19		T321	8
auto[0]	values[1]	values[2]	436	1			T210	12		T129	18		T277	12
auto[0]	values[1]	values[3]	364	1			T73	49		T205	20		T242	85
auto[0]	values[1]	values[4]	484	1			T9	2		T233	20		T299	19
auto[0]	values[1]	values[5]	465	1			T67	20		T50	36		T279	20
auto[0]	values[1]	values[6]	464	1			T72	20		T50	30		T73	30
auto[0]	values[1]	values[7]	202	1			T72	20		T343	4		T171	19
auto[0]	values[2]	values[0]	401	1			T14	2		T250	2		T72	20
auto[0]	values[2]	values[1]	469	1			T50	43		T318	2		T320	6
auto[0]	values[2]	values[2]	496	1			T69	8		T72	19		T309	21
auto[0]	values[2]	values[3]	227	1			T77	2		T231	19		T342	29
auto[0]	values[2]	values[4]	344	1			T212	6		T65	20		T299	19
auto[0]	values[2]	values[5]	245	1			T16	4		T307	4		T236	19
auto[0]	values[2]	values[6]	603	1			T67	32		T50	73		T265	24
auto[0]	values[2]	values[7]	360	1			T233	18		T166	27		T260	16
auto[0]	values[3]	values[0]	692	1			T126	24		T328	2		T74	37
auto[0]	values[3]	values[1]	232	1			T50	20		T312	2		T310	19
auto[0]	values[3]	values[2]	229	1			T233	41		T239	14		T242	24
auto[0]	values[3]	values[3]	447	1			T128	8		T100	10		T68	20
auto[0]	values[3]	values[4]	464	1			T22	4		T211	14		T72	20
auto[0]	values[3]	values[5]	450	1			T207	17		T329	4		T310	54
auto[0]	values[3]	values[6]	465	1			T124	6		T71	20		T74	29
auto[0]	values[3]	values[7]	372	1			T98	8		T206	39		T51	26
auto[0]	values[4]	values[0]	570	1			T72	18		T74	20		T287	8
auto[0]	values[4]	values[1]	541	1			T99	6		T123	16		T51	18
auto[0]	values[4]	values[2]	307	1			T68	46		T308	6		T333	18
auto[0]	values[4]	values[3]	481	1			T101	24		T73	20		T344	4
auto[0]	values[4]	values[4]	260	1			T21	6		T269	10		T294	12
auto[0]	values[4]	values[5]	367	1			T61	6		T68	36		T51	35
auto[0]	values[4]	values[6]	682	1			T253	12		T317	10		T266	4
auto[0]	values[4]	values[7]	284	1			T125	14		T206	32		T256	45
auto[0]	values[5]	values[0]	562	1			T76	4		T74	38		T345	6
auto[0]	values[5]	values[1]	613	1			T25	8		T64	12		T62	12
auto[0]	values[5]	values[2]	385	1			T66	8		T50	19		T205	19
auto[0]	values[5]	values[3]	350	1			T346	2		T262	23		T347	2
auto[0]	values[5]	values[4]	536	1			T24	2		T59	4		T301	10
auto[0]	values[5]	values[5]	403	1			T72	20		T303	18		T166	22
auto[0]	values[5]	values[6]	599	1			T121	14		T72	20		T233	60
auto[0]	values[5]	values[7]	493	1			T249	26		T75	16		T206	17
auto[0]	values[6]	values[0]	476	1			T242	20		T348	10		T231	62
auto[0]	values[6]	values[1]	253	1			T58	18		T316	16		T331	20
auto[0]	values[6]	values[2]	216	1			T326	12		T319	8		T74	24
auto[0]	values[6]	values[3]	582	1			T72	20		T205	140		T315	8
auto[0]	values[6]	values[4]	340	1			T236	24		T174	2		T349	20
auto[0]	values[6]	values[5]	440	1			T60	24		T207	19		T255	68
auto[0]	values[6]	values[6]	392	1			T311	2		T72	20		T234	20
auto[0]	values[6]	values[7]	416	1			T23	20		T338	57		T350	54
auto[0]	values[7]	values[0]	292	1			T79	6		T127	10		T141	4
auto[0]	values[7]	values[1]	482	1			T50	20		T235	26		T73	20
auto[0]	values[7]	values[2]	367	1			T50	31		T232	25		T233	85
auto[0]	values[7]	values[3]	463	1			T63	8		T351	2		T267	44
auto[0]	values[7]	values[4]	639	1			T207	19		T242	19		T331	20
auto[0]	values[7]	values[5]	516	1			T71	20		T205	30		T233	20
auto[0]	values[7]	values[6]	527	1			T281	33		T231	20		T313	25
auto[0]	values[7]	values[7]	458	1			T140	18		T65	18		T291	51
auto[1]	values[0]	values[0]	6	1			T313	1		T177	2		T352	2
auto[1]	values[0]	values[1]	13	1			T71	2		T236	1		T262	2
auto[1]	values[0]	values[2]	12	1			T50	1		T232	4		T255	2
auto[1]	values[0]	values[3]	17	1			T313	1		T330	2		T177	3
auto[1]	values[0]	values[4]	22	1			T248	3		T330	3		T353	8
auto[1]	values[0]	values[5]	18	1			T72	2		T171	2		T262	1
auto[1]	values[0]	values[6]	20	1			T236	1		T352	5		T354	4
auto[1]	values[0]	values[7]	5	1			T232	2		T242	1		T238	1
auto[1]	values[1]	values[0]	16	1			T205	1		T207	1		T300	1
auto[1]	values[1]	values[1]	11	1			T71	1		T166	4		T313	1
auto[1]	values[1]	values[2]	9	1			T236	1		T255	2		T355	3
auto[1]	values[1]	values[3]	16	1			T73	4		T281	2		T330	4
auto[1]	values[1]	values[4]	8	1			T299	1		T240	2		T356	2
auto[1]	values[1]	values[5]	15	1			T50	1		T166	1		T171	2
auto[1]	values[1]	values[6]	11	1			T50	3		T281	1		T313	1
auto[1]	values[1]	values[7]	2	1			T171	1		T354	1		-	-
auto[1]	values[2]	values[0]	14	1			T50	1		T74	7		T309	1
auto[1]	values[2]	values[1]	13	1			T50	2		T339	2		T357	1
auto[1]	values[2]	values[2]	4	1			T72	1		T309	2		T358	1
auto[1]	values[2]	values[3]	5	1			T231	1		T359	1		T88	3
auto[1]	values[2]	values[4]	8	1			T299	1		T171	1		T360	2
auto[1]	values[2]	values[5]	12	1			T236	3		T313	1		T350	3
auto[1]	values[2]	values[6]	11	1			T67	1		T50	3		T242	2
auto[1]	values[2]	values[7]	25	1			T233	2		T361	2		T330	2
auto[1]	values[3]	values[0]	19	1			T74	6		T259	4		T357	1
auto[1]	values[3]	values[1]	7	1			T310	1		T362	2		T285	1
auto[1]	values[3]	values[2]	8	1			T233	1		T242	1		T334	2
auto[1]	values[3]	values[3]	22	1			T73	2		T242	4		T356	3
auto[1]	values[3]	values[4]	15	1			T50	1		T207	2		T302	2
auto[1]	values[3]	values[5]	15	1			T207	3		T310	1		T281	2
auto[1]	values[3]	values[6]	11	1			T74	2		T199	4		T237	2
auto[1]	values[3]	values[7]	11	1			T206	2		T275	2		T259	1
auto[1]	values[4]	values[0]	16	1			T72	2		T337	4		T255	1
auto[1]	values[4]	values[1]	21	1			T51	2		T310	3		T200	1
auto[1]	values[4]	values[2]	2	1			T280	2		-	-		-	-
auto[1]	values[4]	values[3]	21	1			T73	1		T233	1		T338	1
auto[1]	values[4]	values[4]	11	1			T357	1		T363	3		T364	3
auto[1]	values[4]	values[5]	13	1			T242	2		T248	5		T342	3
auto[1]	values[4]	values[6]	14	1			T242	1		T255	1		T365	1
auto[1]	values[4]	values[7]	7	1			T206	1		T358	1		T366	1
auto[1]	values[5]	values[0]	8	1			T74	1		T237	2		T238	1
auto[1]	values[5]	values[1]	19	1			T276	2		T367	1		T181	1
auto[1]	values[5]	values[2]	12	1			T66	2		T50	1		T205	1
auto[1]	values[5]	values[3]	11	1			T310	6		T368	5		-	-
auto[1]	values[5]	values[4]	19	1			T59	2		T205	3		T234	1
auto[1]	values[5]	values[5]	18	1			T267	1		T306	2		T310	2
auto[1]	values[5]	values[6]	12	1			T233	1		T231	2		T350	1
auto[1]	values[5]	values[7]	20	1			T75	2		T206	3		T233	1
auto[1]	values[6]	values[0]	11	1			T231	1		T366	3		T263	1
auto[1]	values[6]	values[1]	2	1			T58	2		-	-		-	-
auto[1]	values[6]	values[2]	6	1			T205	2		T267	1		T238	1
auto[1]	values[6]	values[3]	13	1			T205	2		T242	2		T310	3
auto[1]	values[6]	values[4]	15	1			T237	1		T238	3		T276	4
auto[1]	values[6]	values[5]	10	1			T207	1		T255	1		T267	1
auto[1]	values[6]	values[6]	18	1			T234	1		T362	3		T369	1
auto[1]	values[6]	values[7]	15	1			T350	1		T352	2		T367	1
auto[1]	values[7]	values[0]	11	1			T207	1		T256	2		T300	3
auto[1]	values[7]	values[1]	13	1			T234	2		T338	2		T358	1
auto[1]	values[7]	values[2]	15	1			T50	2		T233	2		T243	2
auto[1]	values[7]	values[3]	11	1			T267	1		T256	1		T354	1
auto[1]	values[7]	values[4]	12	1			T207	1		T242	1		T310	3
auto[1]	values[7]	values[5]	10	1			T205	3		T171	1		T199	1
auto[1]	values[7]	values[6]	10	1			T281	2		T365	2		T366	2
auto[1]	values[7]	values[7]	12	1			T65	2		T205	1		T255	1