Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	877	1			T18	10		T34	4		T37	10
all_values[1]	877	1			T18	10		T34	4		T37	10
all_values[2]	877	1			T18	10		T34	4		T37	10
all_values[3]	877	1			T18	10		T34	4		T37	10
all_values[4]	877	1			T18	10		T34	4		T37	10
all_values[5]	877	1			T18	10		T34	4		T37	10
all_values[6]	877	1			T18	10		T34	4		T37	10
all_values[7]	877	1			T18	10		T34	4		T37	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3704

1

T18

48

T34

13

T37

43

auto[1]

3312

1

T18

32

T34

19

T37

37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2891

1

T18

35

T34

11

T37

29

auto[1]

4125

1

T18

45

T34

21

T37

51

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4051

1

T18

47

T34

19

T37

46

auto[1]

2965

1

T18

33

T34

13

T37

34

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	215	1			T18	4		T37	3		T38	2
all_values[0]	auto[0]	auto[0]	auto[1]	76	1			T18	1		T38	3		T40	1
all_values[0]	auto[0]	auto[1]	auto[0]	152	1			T18	1		T37	2		T38	4
all_values[0]	auto[0]	auto[1]	auto[1]	82	1			T34	1		T37	1		T38	3
all_values[0]	auto[1]	auto[0]	auto[1]	188	1			T18	1		T37	1		T38	6
all_values[0]	auto[1]	auto[1]	auto[1]	164	1			T18	3		T34	3		T37	3
all_values[1]	auto[0]	auto[0]	auto[0]	162	1			T18	2		T38	3		T40	2
all_values[1]	auto[0]	auto[0]	auto[1]	69	1			T37	1		T38	2		T40	1
all_values[1]	auto[0]	auto[1]	auto[0]	182	1			T18	2		T37	1		T38	3
all_values[1]	auto[0]	auto[1]	auto[1]	85	1			T18	2		T34	2		T37	2
all_values[1]	auto[1]	auto[0]	auto[1]	193	1			T18	3		T34	1		T37	2
all_values[1]	auto[1]	auto[1]	auto[1]	186	1			T18	1		T34	1		T37	4
all_values[2]	auto[0]	auto[0]	auto[0]	162	1			T18	1		T34	1		T37	1
all_values[2]	auto[0]	auto[0]	auto[1]	84	1			T18	2		T38	1		T40	6
all_values[2]	auto[0]	auto[1]	auto[0]	185	1			T18	1		T34	1		T38	4
all_values[2]	auto[0]	auto[1]	auto[1]	89	1			T18	1		T34	1		T37	4
all_values[2]	auto[1]	auto[0]	auto[1]	207	1			T18	4		T34	1		T37	2
all_values[2]	auto[1]	auto[1]	auto[1]	150	1			T18	1		T37	3		T38	7
all_values[3]	auto[0]	auto[0]	auto[0]	172	1			T18	4		T37	1		T38	5
all_values[3]	auto[0]	auto[0]	auto[1]	84	1			T34	1		T37	2		T38	2
all_values[3]	auto[0]	auto[1]	auto[0]	138	1			T38	2		T40	5		T50	1
all_values[3]	auto[0]	auto[1]	auto[1]	91	1			T18	2		T37	2		T38	3
all_values[3]	auto[1]	auto[0]	auto[1]	212	1			T18	2		T34	3		T37	4
all_values[3]	auto[1]	auto[1]	auto[1]	180	1			T18	2		T37	1		T38	4
all_values[4]	auto[0]	auto[0]	auto[0]	187	1			T18	1		T37	3		T38	5
all_values[4]	auto[0]	auto[0]	auto[1]	72	1			T18	1		T38	1		T40	3
all_values[4]	auto[0]	auto[1]	auto[0]	148	1			T18	2		T37	3		T38	6
all_values[4]	auto[0]	auto[1]	auto[1]	87	1			T18	1		T34	2		T37	1
all_values[4]	auto[1]	auto[0]	auto[1]	210	1			T18	2		T37	3		T38	3
all_values[4]	auto[1]	auto[1]	auto[1]	173	1			T18	3		T34	2		T38	5
all_values[5]	auto[0]	auto[0]	auto[0]	287	1			T18	6		T34	4		T37	5
all_values[5]	auto[0]	auto[1]	auto[0]	229	1			T18	2		T37	2		T38	7
all_values[5]	auto[1]	auto[0]	auto[1]	206	1			T18	1		T37	3		T38	5
all_values[5]	auto[1]	auto[1]	auto[1]	155	1			T18	1		T38	6		T40	5
all_values[6]	auto[0]	auto[0]	auto[0]	154	1			T18	3		T34	1		T37	3
all_values[6]	auto[0]	auto[0]	auto[1]	87	1			T18	1		T34	1		T37	4
all_values[6]	auto[0]	auto[1]	auto[0]	168	1			T18	1		T34	1		T38	4
all_values[6]	auto[0]	auto[1]	auto[1]	84	1			T38	1		T40	1		T50	2
all_values[6]	auto[1]	auto[0]	auto[1]	211	1			T18	5		T37	1		T38	5
all_values[6]	auto[1]	auto[1]	auto[1]	173	1			T34	1		T37	2		T38	5
all_values[7]	auto[0]	auto[0]	auto[0]	187	1			T18	1		T37	1		T38	3
all_values[7]	auto[0]	auto[0]	auto[1]	97	1			T18	1		T38	2		T40	3
all_values[7]	auto[0]	auto[1]	auto[0]	163	1			T18	4		T34	3		T37	4
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T38	1		T40	2		T50	1
all_values[7]	auto[1]	auto[0]	auto[1]	182	1			T18	2		T37	3		T38	6
all_values[7]	auto[1]	auto[1]	auto[1]	175	1			T18	2		T34	1		T37	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal