Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1732

1

T4

5

T5

1

T13

2

auto[1]

1768

1

T4

4

T5

4

T13

6

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1937

1

T28

5

T30

9

T45

10

auto[1]

1563

1

T4

9

T5

5

T13

8

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2794

1

T4

9

T5

5

T13

8

auto[1]

706

1

T28

3

T30

4

T45

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	705	1			T5	2		T30	2		T31	2
valid[1]	680	1			T4	2		T5	2		T13	1
valid[2]	679	1			T4	2		T13	2		T28	1
valid[3]	738	1			T4	3		T13	2		T28	1
valid[4]	698	1			T4	2		T5	1		T13	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	130	1			T95	1		T119	2		T394	4
auto[0]	auto[0]	valid[0]	auto[1]	165	1			T5	1		T31	2		T117	4
auto[0]	auto[0]	valid[1]	auto[0]	122	1			T45	3		T52	1		T95	1
auto[0]	auto[0]	valid[1]	auto[1]	159	1			T4	1		T31	1		T117	4
auto[0]	auto[0]	valid[2]	auto[0]	111	1			T30	1		T52	1		T53	1
auto[0]	auto[0]	valid[2]	auto[1]	154	1			T4	2		T117	4		T52	1
auto[0]	auto[0]	valid[3]	auto[0]	112	1			T54	1		T119	3		T393	1
auto[0]	auto[0]	valid[3]	auto[1]	157	1			T4	1		T117	2		T96	3
auto[0]	auto[0]	valid[4]	auto[0]	131	1			T30	2		T45	1		T95	3
auto[0]	auto[0]	valid[4]	auto[1]	152	1			T4	1		T13	2		T117	7
auto[0]	auto[1]	valid[0]	auto[0]	119	1			T30	1		T53	1		T119	1
auto[0]	auto[1]	valid[0]	auto[1]	159	1			T5	1		T117	2		T96	4
auto[0]	auto[1]	valid[1]	auto[0]	115	1			T45	1		T78	1		T52	1
auto[0]	auto[1]	valid[1]	auto[1]	140	1			T4	1		T5	2		T13	1
auto[0]	auto[1]	valid[2]	auto[0]	120	1			T28	1		T45	1		T52	1
auto[0]	auto[1]	valid[2]	auto[1]	159	1			T13	2		T31	1		T117	6
auto[0]	auto[1]	valid[3]	auto[0]	134	1			T30	1		T52	2		T95	1
auto[0]	auto[1]	valid[3]	auto[1]	165	1			T4	2		T13	2		T31	1
auto[0]	auto[1]	valid[4]	auto[0]	137	1			T28	1		T52	1		T95	1
auto[0]	auto[1]	valid[4]	auto[1]	153	1			T4	1		T5	1		T13	1
auto[1]	auto[0]	valid[0]	auto[0]	60	1			T30	1		T119	3		T394	2
auto[1]	auto[0]	valid[1]	auto[0]	59	1			T28	1		T52	1		T95	1
auto[1]	auto[0]	valid[2]	auto[0]	67	1			T30	1		T45	1		T53	1
auto[1]	auto[0]	valid[3]	auto[0]	91	1			T28	1		T30	1		T45	1
auto[1]	auto[0]	valid[4]	auto[0]	62	1			T52	1		T390	1		T384	1
auto[1]	auto[1]	valid[0]	auto[0]	72	1			T45	1		T392	1		T119	2
auto[1]	auto[1]	valid[1]	auto[0]	85	1			T45	1		T52	2		T119	1
auto[1]	auto[1]	valid[2]	auto[0]	68	1			T30	1		T384	1		T393	1
auto[1]	auto[1]	valid[3]	auto[0]	79	1			T119	3		T41	1		T393	3
auto[1]	auto[1]	valid[4]	auto[0]	63	1			T28	1		T52	1		T95	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal