Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48430

1

T8

8

T15

11

T27

8

auto[1]

16171

1

T4

135

T5

5

T13

8

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46816

1

T4

135

T5

5

T8

1

auto[1]

17785

1

T8

7

T15

4

T27

6

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33245	1			T4	71		T5	5		T8	2
others[1]	5358	1			T4	16		T8	1		T15	1
others[2]	5300	1			T4	5		T8	1		T28	6
others[3]	6298	1			T4	12		T8	1		T15	2
interest[1]	3557	1			T4	6		T8	1		T28	3
interest[4]	21723	1			T4	50		T5	5		T8	1
interest[64]	10843	1			T4	25		T8	2		T15	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15621	1			T15	4		T27	2		T28	16
auto[0]	auto[0]	others[1]	2529	1			T15	1		T28	3		T30	11
auto[0]	auto[0]	others[2]	2551	1			T28	4		T30	17		T45	21
auto[0]	auto[0]	others[3]	3034	1			T15	1		T28	7		T30	23
auto[0]	auto[0]	interest[1]	1686	1			T28	2		T30	12		T45	13
auto[0]	auto[0]	interest[4]	10202	1			T15	3		T27	2		T28	10
auto[0]	auto[0]	interest[64]	5224	1			T8	1		T15	1		T28	7
auto[0]	auto[1]	others[0]	8443	1			T4	71		T5	5		T13	8
auto[0]	auto[1]	others[1]	1303	1			T4	16		T30	1		T117	40
auto[0]	auto[1]	others[2]	1304	1			T4	5		T30	1		T117	47
auto[0]	auto[1]	others[3]	1536	1			T4	12		T30	4		T117	54
auto[0]	auto[1]	interest[1]	890	1			T4	6		T30	1		T117	35
auto[0]	auto[1]	interest[4]	5560	1			T4	50		T5	5		T13	8
auto[0]	auto[1]	interest[64]	2695	1			T4	25		T30	6		T117	78
auto[1]	auto[0]	others[0]	9181	1			T8	2		T15	3		T27	4
auto[1]	auto[0]	others[1]	1526	1			T8	1		T28	1		T30	12
auto[1]	auto[0]	others[2]	1445	1			T8	1		T28	2		T30	14
auto[1]	auto[0]	others[3]	1728	1			T8	1		T15	1		T27	1
auto[1]	auto[0]	interest[1]	981	1			T8	1		T28	1		T30	5
auto[1]	auto[0]	interest[4]	5961	1			T8	1		T15	2		T27	4
auto[1]	auto[0]	interest[64]	2924	1			T8	1		T27	1		T28	8

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal