Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.76 98.70 96.89 99.01 89.36 98.59 95.56 99.21


Total tests in report: 1130
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
59.86 59.86 92.15 92.15 80.74 80.74 62.75 62.75 11.11 11.11 89.68 89.68 70.42 70.42 12.18 12.18 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.2892528515
72.57 12.71 95.55 3.40 90.52 9.78 87.55 24.80 35.56 24.44 94.34 4.65 78.61 8.19 25.89 13.71 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.1616095665
80.59 8.02 97.63 2.08 93.37 2.85 90.02 2.47 71.11 35.56 96.86 2.52 85.14 6.53 30.00 4.11 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.1584479325
85.80 5.21 97.98 0.35 94.00 0.63 90.02 0.00 86.67 15.56 97.41 0.55 85.28 0.14 49.26 19.26 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.2451184998
88.47 2.67 98.22 0.23 94.57 0.58 90.22 0.20 93.33 6.67 97.80 0.39 85.28 0.00 59.90 10.64 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.531022117
90.25 1.78 98.27 0.06 94.66 0.09 90.22 0.00 93.33 0.00 97.92 0.12 85.28 0.00 72.08 12.18 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.3555516657
91.80 1.55 98.27 0.00 94.87 0.20 90.61 0.40 93.33 0.00 97.96 0.03 93.75 8.47 73.81 1.73 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3893729261
92.50 0.70 98.28 0.01 94.89 0.03 95.45 4.84 93.33 0.00 97.96 0.00 93.75 0.00 73.81 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.3120411050
93.06 0.56 98.28 0.00 94.93 0.04 95.45 0.00 93.33 0.00 97.96 0.00 93.75 0.00 77.72 3.91 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.2865604861
93.49 0.43 98.34 0.06 95.00 0.06 95.45 0.00 93.33 0.00 98.03 0.07 93.75 0.00 80.54 2.82 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.363790188
93.85 0.36 98.51 0.17 95.61 0.61 96.25 0.79 93.33 0.00 98.35 0.33 94.31 0.56 80.59 0.05 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.2933425232
94.20 0.35 98.52 0.01 95.65 0.04 98.22 1.98 93.33 0.00 98.37 0.02 94.44 0.14 80.84 0.25 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.3419062740
94.53 0.33 98.52 0.00 95.65 0.00 98.22 0.00 93.33 0.00 98.37 0.00 94.44 0.00 83.17 2.33 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.2476926945
94.79 0.26 98.52 0.00 95.66 0.01 98.22 0.00 93.33 0.00 98.37 0.00 94.44 0.00 85.00 1.83 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.2524620855
95.03 0.24 98.52 0.00 95.66 0.00 98.22 0.00 93.33 0.00 98.37 0.00 94.58 0.14 86.53 1.53 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.2531092830
95.23 0.20 98.52 0.00 95.66 0.00 98.22 0.00 93.33 0.00 98.37 0.00 94.58 0.00 87.92 1.39 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.2907569564
95.41 0.18 98.52 0.00 95.66 0.00 98.22 0.00 93.33 0.00 98.37 0.00 94.58 0.00 89.16 1.24 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.1031707287
95.56 0.15 98.60 0.08 95.80 0.14 98.42 0.20 93.33 0.00 98.47 0.10 94.58 0.00 89.70 0.54 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3977282607
95.70 0.14 98.61 0.01 95.84 0.04 98.42 0.00 93.33 0.00 98.49 0.02 94.58 0.00 90.64 0.94 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.3517610074
95.84 0.14 98.61 0.00 95.84 0.00 98.42 0.00 93.33 0.00 98.49 0.00 94.58 0.00 91.63 0.99 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.2133681630
95.98 0.13 98.61 0.00 95.84 0.00 98.42 0.00 93.33 0.00 98.49 0.00 94.72 0.14 92.43 0.79 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.2883328969
96.10 0.12 98.61 0.00 95.85 0.01 98.42 0.00 93.33 0.00 98.49 0.00 95.56 0.83 92.43 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3058219855
96.22 0.12 98.61 0.00 96.48 0.63 98.42 0.00 93.33 0.00 98.49 0.00 95.56 0.00 92.62 0.20 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.2224058325
96.31 0.10 98.61 0.00 96.48 0.00 98.42 0.00 93.33 0.00 98.49 0.00 95.56 0.00 93.32 0.69 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.852986230
96.41 0.09 98.61 0.00 96.48 0.00 98.42 0.00 93.33 0.00 98.49 0.00 95.56 0.00 93.96 0.64 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.3306058777
96.50 0.09 98.67 0.06 96.57 0.09 98.81 0.40 93.33 0.00 98.58 0.09 95.56 0.00 93.96 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.1785978364
96.57 0.08 98.67 0.00 96.57 0.00 98.81 0.00 93.33 0.00 98.58 0.00 95.56 0.00 94.50 0.54 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.3995370254
96.64 0.07 98.67 0.00 96.57 0.00 98.81 0.00 93.33 0.00 98.58 0.00 95.56 0.00 95.00 0.50 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_stress_all.3972265633
96.71 0.06 98.67 0.00 96.57 0.00 98.81 0.00 93.33 0.00 98.58 0.00 95.56 0.00 95.45 0.45 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.199081456
96.77 0.06 98.67 0.00 96.57 0.00 98.81 0.00 93.33 0.00 98.58 0.00 95.56 0.00 95.84 0.40 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.3326116361
96.81 0.04 98.67 0.00 96.58 0.01 98.81 0.00 93.33 0.00 98.58 0.00 95.56 0.00 96.14 0.30 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.2524176009
96.85 0.04 98.67 0.00 96.58 0.00 98.81 0.00 93.33 0.00 98.58 0.00 95.56 0.00 96.44 0.30 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.3147516282
96.89 0.04 98.67 0.00 96.58 0.00 98.81 0.00 93.33 0.00 98.58 0.00 95.56 0.00 96.73 0.30 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.3758184588
96.94 0.04 98.67 0.00 96.58 0.00 98.81 0.00 93.33 0.00 98.58 0.00 95.56 0.00 97.03 0.30 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.1732197307
96.97 0.04 98.69 0.03 96.62 0.04 99.01 0.20 93.33 0.00 98.58 0.00 95.56 0.00 97.03 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.3954347743
97.01 0.04 98.69 0.00 96.62 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 97.28 0.25 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.2903688736
97.04 0.03 98.69 0.00 96.62 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 97.48 0.20 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.3349804265
97.07 0.03 98.69 0.00 96.62 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 97.67 0.20 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.4167946192
97.09 0.03 98.69 0.00 96.81 0.19 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 97.67 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3763932006
97.11 0.02 98.69 0.00 96.81 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 97.82 0.15 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.1397567273
97.14 0.02 98.69 0.00 96.81 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 97.97 0.15 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.2840688870
97.15 0.02 98.69 0.00 96.83 0.01 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 98.07 0.10 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.1405632123
97.17 0.01 98.69 0.00 96.83 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 98.17 0.10 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.3749052854
97.18 0.01 98.69 0.00 96.83 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 98.27 0.10 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.2302922800
97.19 0.01 98.69 0.00 96.83 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 98.37 0.10 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.1786038184
97.21 0.01 98.69 0.00 96.83 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 98.47 0.10 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_all.2166949181
97.22 0.01 98.69 0.00 96.83 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 98.56 0.10 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/18.spi_device_stress_all.3779734783
97.24 0.01 98.69 0.00 96.83 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 98.66 0.10 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.102364317
97.25 0.01 98.69 0.00 96.83 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 98.76 0.10 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode.1580635994
97.27 0.01 98.69 0.00 96.83 0.00 99.01 0.00 93.33 0.00 98.58 0.00 95.56 0.00 98.86 0.10 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.1388647856
97.28 0.01 98.70 0.01 96.83 0.00 99.01 0.00 93.33 0.00 98.59 0.02 95.56 0.00 98.91 0.05 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.2209692402
97.28 0.01 98.70 0.00 96.88 0.05 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 98.91 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.2474593585
97.29 0.01 98.70 0.00 96.88 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.2368417356
97.30 0.01 98.70 0.00 96.88 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.4024235423
97.30 0.01 98.70 0.00 96.88 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode.3822117043
97.31 0.01 98.70 0.00 96.88 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.233738818
97.32 0.01 98.70 0.00 96.88 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/22.spi_device_stress_all.2333449718
97.33 0.01 98.70 0.00 96.88 0.00 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode.1624028750
97.33 0.01 98.70 0.00 96.89 0.01 99.01 0.00 93.33 0.00 98.59 0.00 95.56 0.00 99.21 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2549832494

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1846194268
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1688563751
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3520234634
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.347705132
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.3777957311
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.3284579333
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.1985087332
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1996249132
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.712477283
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.42434481
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3936534730
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.962191408
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4271503436
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4057337090
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.3972113723
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3793660244
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.4072377958
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.3758480169
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2432391788
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.2852215689
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1863817887
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.4141468426
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.3836273086
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.577247805
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.2258632783
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.4016038601
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.433804758
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.1635993592
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/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.3319339031
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.4228860372
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.3136763880
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.2186512498
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.4158598810
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.1043151324
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.2621119636
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.270429901
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.1156801226
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.2356833931
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.964684506
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.177470302
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.3979911946
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.4261678707
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.2501262022
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2995751647
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.441161820
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.2497879270
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.3015288522
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.3806812865
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.3801684266
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3585912884
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.2471050671
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.1158041450
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.4278795964
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.994525
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.3770196532
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.2288670888
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.4129541800
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.647047342
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.1547939919
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.4292988304
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.4264771046
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.1688214299
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.849518628
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.3134432022
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.2535748436
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.560935577
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.2047704222
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.3971267105
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.1071672747
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.1903576368



Total test records in report: 1130
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.1733258705 Oct 15 12:27:49 PM UTC 24 Oct 15 12:27:52 PM UTC 24 23473674 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.3120411050 Oct 15 12:27:49 PM UTC 24 Oct 15 12:27:52 PM UTC 24 15966840 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.560143950 Oct 15 12:27:49 PM UTC 24 Oct 15 12:27:52 PM UTC 24 313993602 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.1785978364 Oct 15 12:27:49 PM UTC 24 Oct 15 12:27:52 PM UTC 24 27704554 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.3688913255 Oct 15 12:27:50 PM UTC 24 Oct 15 12:27:53 PM UTC 24 21698274 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.2315542881 Oct 15 12:27:51 PM UTC 24 Oct 15 12:27:56 PM UTC 24 297305479 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.3954347743 Oct 15 12:27:54 PM UTC 24 Oct 15 12:27:56 PM UTC 24 42792854 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.3419062740 Oct 15 12:27:54 PM UTC 24 Oct 15 12:27:56 PM UTC 24 41607171 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.2892528515 Oct 15 12:27:51 PM UTC 24 Oct 15 12:27:57 PM UTC 24 452550423 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.1944098221 Oct 15 12:27:51 PM UTC 24 Oct 15 12:27:58 PM UTC 24 8628243408 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.2089120797 Oct 15 12:27:57 PM UTC 24 Oct 15 12:27:59 PM UTC 24 18309182 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.147338493 Oct 15 12:27:57 PM UTC 24 Oct 15 12:27:59 PM UTC 24 96814890 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.2933425232 Oct 15 12:27:52 PM UTC 24 Oct 15 12:28:00 PM UTC 24 232600046 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.1185882538 Oct 15 12:27:58 PM UTC 24 Oct 15 12:28:00 PM UTC 24 11779386 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.867659952 Oct 15 12:27:57 PM UTC 24 Oct 15 12:28:01 PM UTC 24 128300833 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.263389916 Oct 15 12:28:00 PM UTC 24 Oct 15 12:28:02 PM UTC 24 269094544 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.3630126452 Oct 15 12:27:51 PM UTC 24 Oct 15 12:28:03 PM UTC 24 1103532083 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.3644886008 Oct 15 12:27:51 PM UTC 24 Oct 15 12:28:05 PM UTC 24 2146475504 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.1579038301 Oct 15 12:28:00 PM UTC 24 Oct 15 12:28:05 PM UTC 24 208115716 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.4200655194 Oct 15 12:27:51 PM UTC 24 Oct 15 12:28:05 PM UTC 24 1168180097 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3977282607 Oct 15 12:27:49 PM UTC 24 Oct 15 12:28:06 PM UTC 24 3061027114 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.891283323 Oct 15 12:28:00 PM UTC 24 Oct 15 12:28:07 PM UTC 24 645054359 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.857877928 Oct 15 12:28:04 PM UTC 24 Oct 15 12:28:10 PM UTC 24 611681534 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.1584479325 Oct 15 12:28:04 PM UTC 24 Oct 15 12:28:14 PM UTC 24 430159793 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.1775706249 Oct 15 12:28:01 PM UTC 24 Oct 15 12:28:15 PM UTC 24 2205398977 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.2524176009 Oct 15 12:28:06 PM UTC 24 Oct 15 12:28:16 PM UTC 24 711849609 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.4291026248 Oct 15 12:28:14 PM UTC 24 Oct 15 12:28:17 PM UTC 24 148362987 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.3991129163 Oct 15 12:28:15 PM UTC 24 Oct 15 12:28:17 PM UTC 24 23748905 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.2193729811 Oct 15 12:28:16 PM UTC 24 Oct 15 12:28:19 PM UTC 24 84790205 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.2931172113 Oct 15 12:28:06 PM UTC 24 Oct 15 12:28:20 PM UTC 24 4278406410 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.610735545 Oct 15 12:28:19 PM UTC 24 Oct 15 12:28:21 PM UTC 24 35266864 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.2289971671 Oct 15 12:28:21 PM UTC 24 Oct 15 12:28:23 PM UTC 24 33231385 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.4055339372 Oct 15 12:27:52 PM UTC 24 Oct 15 12:28:24 PM UTC 24 11983880457 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.1379983380 Oct 15 12:28:22 PM UTC 24 Oct 15 12:28:25 PM UTC 24 37026130 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.369071340 Oct 15 12:28:02 PM UTC 24 Oct 15 12:28:25 PM UTC 24 3864692520 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.1438334698 Oct 15 12:28:24 PM UTC 24 Oct 15 12:28:30 PM UTC 24 242010629 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.1616095665 Oct 15 12:28:13 PM UTC 24 Oct 15 12:28:31 PM UTC 24 5720303348 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.4132849831 Oct 15 12:28:20 PM UTC 24 Oct 15 12:28:31 PM UTC 24 612913111 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.3545677186 Oct 15 12:28:19 PM UTC 24 Oct 15 12:28:33 PM UTC 24 3080621086 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.3219004228 Oct 15 12:28:25 PM UTC 24 Oct 15 12:28:34 PM UTC 24 286645386 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.3147516282 Oct 15 12:27:58 PM UTC 24 Oct 15 12:28:37 PM UTC 24 2779660869 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.3100354086 Oct 15 12:28:31 PM UTC 24 Oct 15 12:28:37 PM UTC 24 147919976 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.2519713505 Oct 15 12:28:35 PM UTC 24 Oct 15 12:28:42 PM UTC 24 154296547 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.2302922800 Oct 15 12:27:49 PM UTC 24 Oct 15 12:28:43 PM UTC 24 7521846541 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.207301345 Oct 15 12:28:33 PM UTC 24 Oct 15 12:28:44 PM UTC 24 3144281572 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.3213070227 Oct 15 12:28:44 PM UTC 24 Oct 15 12:28:47 PM UTC 24 39944505 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.283938177 Oct 15 12:28:30 PM UTC 24 Oct 15 12:28:47 PM UTC 24 3516506989 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.2439607259 Oct 15 12:28:45 PM UTC 24 Oct 15 12:28:48 PM UTC 24 39593730 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.2023606469 Oct 15 12:28:47 PM UTC 24 Oct 15 12:28:49 PM UTC 24 16179656 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.2667768129 Oct 15 12:28:48 PM UTC 24 Oct 15 12:28:51 PM UTC 24 12196593 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.2523136513 Oct 15 12:28:48 PM UTC 24 Oct 15 12:28:51 PM UTC 24 227377082 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.2621391345 Oct 15 12:28:25 PM UTC 24 Oct 15 12:28:53 PM UTC 24 17739958842 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.3629046609 Oct 15 12:28:52 PM UTC 24 Oct 15 12:28:54 PM UTC 24 43649646 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.2249881128 Oct 15 12:28:54 PM UTC 24 Oct 15 12:28:59 PM UTC 24 225588696 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.4000114596 Oct 15 12:28:52 PM UTC 24 Oct 15 12:28:59 PM UTC 24 105261588 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.3617560690 Oct 15 12:28:55 PM UTC 24 Oct 15 12:29:01 PM UTC 24 99571707 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.1318866837 Oct 15 12:28:49 PM UTC 24 Oct 15 12:29:01 PM UTC 24 755537342 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.3717307650 Oct 15 12:29:01 PM UTC 24 Oct 15 12:29:06 PM UTC 24 272374548 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.2877509171 Oct 15 12:29:02 PM UTC 24 Oct 15 12:29:10 PM UTC 24 153249461 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.561194536 Oct 15 12:29:00 PM UTC 24 Oct 15 12:29:11 PM UTC 24 3112840938 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.531022117 Oct 15 12:27:53 PM UTC 24 Oct 15 12:29:14 PM UTC 24 22228754727 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.4056478295 Oct 15 12:29:11 PM UTC 24 Oct 15 12:29:17 PM UTC 24 103184612 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.616464516 Oct 15 12:28:51 PM UTC 24 Oct 15 12:29:18 PM UTC 24 14041468105 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.1113219697 Oct 15 12:28:55 PM UTC 24 Oct 15 12:29:20 PM UTC 24 4299704730 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.3167682111 Oct 15 12:29:19 PM UTC 24 Oct 15 12:29:22 PM UTC 24 184974445 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.3330312416 Oct 15 12:29:19 PM UTC 24 Oct 15 12:29:22 PM UTC 24 120334733 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.649859865 Oct 15 12:29:21 PM UTC 24 Oct 15 12:29:23 PM UTC 24 12371360 ps
T373 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.260245507 Oct 15 12:29:22 PM UTC 24 Oct 15 12:29:24 PM UTC 24 51508276 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.1773355494 Oct 15 12:29:23 PM UTC 24 Oct 15 12:29:26 PM UTC 24 117144691 ps
T375 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.1492331080 Oct 15 12:29:25 PM UTC 24 Oct 15 12:29:27 PM UTC 24 38199103 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.706977335 Oct 15 12:29:27 PM UTC 24 Oct 15 12:29:29 PM UTC 24 19411141 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.3465502811 Oct 15 12:29:29 PM UTC 24 Oct 15 12:29:32 PM UTC 24 385864721 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.3085660928 Oct 15 12:29:30 PM UTC 24 Oct 15 12:29:35 PM UTC 24 126512217 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.227983623 Oct 15 12:29:33 PM UTC 24 Oct 15 12:29:37 PM UTC 24 247215375 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2295345041 Oct 15 12:29:24 PM UTC 24 Oct 15 12:29:38 PM UTC 24 1425538581 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.3297810991 Oct 15 12:28:59 PM UTC 24 Oct 15 12:29:41 PM UTC 24 8123127366 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.1554387894 Oct 15 12:29:36 PM UTC 24 Oct 15 12:29:43 PM UTC 24 916524249 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.3619501983 Oct 15 12:29:37 PM UTC 24 Oct 15 12:29:43 PM UTC 24 1137459353 ps
T121 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.2903688736 Oct 15 12:27:51 PM UTC 24 Oct 15 12:29:46 PM UTC 24 8520225095 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.4224408029 Oct 15 12:29:41 PM UTC 24 Oct 15 12:29:47 PM UTC 24 290112969 ps
T122 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.2744649618 Oct 15 12:29:44 PM UTC 24 Oct 15 12:29:53 PM UTC 24 177523044 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.3028371486 Oct 15 12:29:39 PM UTC 24 Oct 15 12:29:53 PM UTC 24 2176816517 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.750656571 Oct 15 12:29:46 PM UTC 24 Oct 15 12:29:54 PM UTC 24 169348656 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.3737473427 Oct 15 12:30:01 PM UTC 24 Oct 15 12:30:03 PM UTC 24 91934757 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.3219788478 Oct 15 12:30:04 PM UTC 24 Oct 15 12:30:06 PM UTC 24 62188238 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.116613455 Oct 15 12:30:07 PM UTC 24 Oct 15 12:30:09 PM UTC 24 17495853 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.363790188 Oct 15 12:28:43 PM UTC 24 Oct 15 12:30:11 PM UTC 24 16335595995 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.1816394989 Oct 15 12:30:10 PM UTC 24 Oct 15 12:30:13 PM UTC 24 125346937 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.1786038184 Oct 15 12:28:10 PM UTC 24 Oct 15 12:30:13 PM UTC 24 9005586645 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.4073135032 Oct 15 12:30:14 PM UTC 24 Oct 15 12:30:17 PM UTC 24 67818986 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.3332413490 Oct 15 12:30:12 PM UTC 24 Oct 15 12:30:20 PM UTC 24 1266432400 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.4246469256 Oct 15 12:30:17 PM UTC 24 Oct 15 12:30:23 PM UTC 24 72101931 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.1866068886 Oct 15 12:30:13 PM UTC 24 Oct 15 12:30:24 PM UTC 24 6020730494 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.471559481 Oct 15 12:28:26 PM UTC 24 Oct 15 12:30:25 PM UTC 24 51660433142 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.2209692402 Oct 15 12:30:25 PM UTC 24 Oct 15 12:30:29 PM UTC 24 163573936 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.1011434076 Oct 15 12:30:21 PM UTC 24 Oct 15 12:30:29 PM UTC 24 685175004 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.1961547906 Oct 15 12:28:39 PM UTC 24 Oct 15 12:30:31 PM UTC 24 10628352401 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.631542848 Oct 15 12:29:15 PM UTC 24 Oct 15 12:30:35 PM UTC 24 19149125562 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.2941491531 Oct 15 12:30:30 PM UTC 24 Oct 15 12:30:35 PM UTC 24 221693147 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.805492020 Oct 15 12:30:30 PM UTC 24 Oct 15 12:30:36 PM UTC 24 211511092 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.2947265046 Oct 15 12:30:32 PM UTC 24 Oct 15 12:30:40 PM UTC 24 337113562 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.2923380370 Oct 15 12:30:24 PM UTC 24 Oct 15 12:30:41 PM UTC 24 3991160994 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.3493979486 Oct 15 12:28:07 PM UTC 24 Oct 15 12:30:43 PM UTC 24 36494538914 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.2354743570 Oct 15 12:30:44 PM UTC 24 Oct 15 12:30:46 PM UTC 24 14703353 ps
T386 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.3072270196 Oct 15 12:30:47 PM UTC 24 Oct 15 12:30:49 PM UTC 24 43995052 ps
T387 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.3302879217 Oct 15 12:30:50 PM UTC 24 Oct 15 12:30:52 PM UTC 24 93811888 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.381391244 Oct 15 12:30:26 PM UTC 24 Oct 15 12:30:53 PM UTC 24 1064129022 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.1252422187 Oct 15 12:30:36 PM UTC 24 Oct 15 12:30:59 PM UTC 24 5967792316 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.270612100 Oct 15 12:30:54 PM UTC 24 Oct 15 12:31:01 PM UTC 24 337440825 ps
T388 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.1658980594 Oct 15 12:30:59 PM UTC 24 Oct 15 12:31:02 PM UTC 24 239477335 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.3737211499 Oct 15 12:27:51 PM UTC 24 Oct 15 12:31:03 PM UTC 24 154084587234 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.705183278 Oct 15 12:31:01 PM UTC 24 Oct 15 12:31:05 PM UTC 24 43034670 ps
T389 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.2045719599 Oct 15 12:30:53 PM UTC 24 Oct 15 12:31:05 PM UTC 24 9393067777 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.2964814821 Oct 15 12:31:06 PM UTC 24 Oct 15 12:31:10 PM UTC 24 128404145 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1060358252 Oct 15 12:31:04 PM UTC 24 Oct 15 12:31:11 PM UTC 24 195444613 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.1528873377 Oct 15 12:30:42 PM UTC 24 Oct 15 12:31:12 PM UTC 24 1316663889 ps
T390 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.1383112668 Oct 15 12:31:08 PM UTC 24 Oct 15 12:31:12 PM UTC 24 240118396 ps
T391 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.3871281411 Oct 15 12:31:10 PM UTC 24 Oct 15 12:31:13 PM UTC 24 65431936 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.2043603147 Oct 15 12:29:12 PM UTC 24 Oct 15 12:31:16 PM UTC 24 10678806582 ps
T392 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.3353834385 Oct 15 12:31:12 PM UTC 24 Oct 15 12:31:18 PM UTC 24 113729339 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2756041999 Oct 15 12:31:13 PM UTC 24 Oct 15 12:31:20 PM UTC 24 307534059 ps
T393 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.2521690127 Oct 15 12:31:23 PM UTC 24 Oct 15 12:31:25 PM UTC 24 16448229 ps
T394 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.2239131721 Oct 15 12:31:24 PM UTC 24 Oct 15 12:31:26 PM UTC 24 15496458 ps
T395 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.1602742029 Oct 15 12:31:26 PM UTC 24 Oct 15 12:31:29 PM UTC 24 95681606 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1729600328 Oct 15 12:31:03 PM UTC 24 Oct 15 12:31:32 PM UTC 24 29518663261 ps
T396 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.2795368405 Oct 15 12:31:27 PM UTC 24 Oct 15 12:31:35 PM UTC 24 1151328783 ps
T397 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.4228860372 Oct 15 12:31:33 PM UTC 24 Oct 15 12:31:36 PM UTC 24 160428868 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.3692392720 Oct 15 12:31:06 PM UTC 24 Oct 15 12:31:38 PM UTC 24 13208498319 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.3319339031 Oct 15 12:31:36 PM UTC 24 Oct 15 12:31:39 PM UTC 24 102954435 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.2218978258 Oct 15 12:31:29 PM UTC 24 Oct 15 12:31:39 PM UTC 24 423315958 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.2072758620 Oct 15 12:31:40 PM UTC 24 Oct 15 12:31:52 PM UTC 24 992630063 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.2081207442 Oct 15 12:31:37 PM UTC 24 Oct 15 12:31:55 PM UTC 24 22723895800 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.591324246 Oct 15 12:31:39 PM UTC 24 Oct 15 12:31:58 PM UTC 24 3173405177 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.2451184998 Oct 15 12:27:53 PM UTC 24 Oct 15 12:32:01 PM UTC 24 67738416353 ps
T398 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.2531802305 Oct 15 12:31:55 PM UTC 24 Oct 15 12:32:03 PM UTC 24 384335044 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.615804581 Oct 15 12:30:36 PM UTC 24 Oct 15 12:32:05 PM UTC 24 16167865340 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.4239946502 Oct 15 12:31:14 PM UTC 24 Oct 15 12:32:08 PM UTC 24 6173619856 ps
T399 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.275521258 Oct 15 12:32:04 PM UTC 24 Oct 15 12:32:11 PM UTC 24 454091215 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.3085438926 Oct 15 12:31:12 PM UTC 24 Oct 15 12:32:11 PM UTC 24 7233242782 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.2531092830 Oct 15 12:30:41 PM UTC 24 Oct 15 12:32:12 PM UTC 24 27576986590 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.456071220 Oct 15 12:32:13 PM UTC 24 Oct 15 12:32:15 PM UTC 24 40762154 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.1043151324 Oct 15 12:32:16 PM UTC 24 Oct 15 12:32:18 PM UTC 24 46547264 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.3136763880 Oct 15 12:31:53 PM UTC 24 Oct 15 12:32:18 PM UTC 24 13023612003 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.1126037731 Oct 15 12:28:38 PM UTC 24 Oct 15 12:32:21 PM UTC 24 27020389249 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.4261678707 Oct 15 12:32:19 PM UTC 24 Oct 15 12:32:22 PM UTC 24 29840209 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3585912884 Oct 15 12:32:22 PM UTC 24 Oct 15 12:32:25 PM UTC 24 49760516 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.1348892960 Oct 15 12:31:21 PM UTC 24 Oct 15 12:32:26 PM UTC 24 27666958702 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.3801684266 Oct 15 12:32:25 PM UTC 24 Oct 15 12:32:29 PM UTC 24 94943420 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.4107934510 Oct 15 12:29:54 PM UTC 24 Oct 15 12:32:30 PM UTC 24 11630738766 ps
T400 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.3806812865 Oct 15 12:32:19 PM UTC 24 Oct 15 12:32:32 PM UTC 24 1351098952 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.2756282486 Oct 15 12:31:59 PM UTC 24 Oct 15 12:32:35 PM UTC 24 1724704308 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.4158598810 Oct 15 12:32:36 PM UTC 24 Oct 15 12:32:42 PM UTC 24 173653141 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.177470302 Oct 15 12:32:31 PM UTC 24 Oct 15 12:32:42 PM UTC 24 4113463163 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.2501262022 Oct 15 12:32:30 PM UTC 24 Oct 15 12:32:43 PM UTC 24 647134396 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2995751647 Oct 15 12:32:26 PM UTC 24 Oct 15 12:32:48 PM UTC 24 9483362171 ps
T401 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.2621119636 Oct 15 12:32:48 PM UTC 24 Oct 15 12:32:50 PM UTC 24 15468429 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.3015288522 Oct 15 12:32:21 PM UTC 24 Oct 15 12:32:55 PM UTC 24 1349146157 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.2471050671 Oct 15 12:32:36 PM UTC 24 Oct 15 12:32:58 PM UTC 24 14810600409 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.2323205457 Oct 15 12:31:41 PM UTC 24 Oct 15 12:33:04 PM UTC 24 13214197112 ps
T402 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.2186512498 Oct 15 12:33:05 PM UTC 24 Oct 15 12:33:07 PM UTC 24 16809034 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.441161820 Oct 15 12:32:43 PM UTC 24 Oct 15 12:33:09 PM UTC 24 10770020726 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.994525 Oct 15 12:33:08 PM UTC 24 Oct 15 12:33:10 PM UTC 24 150547054 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.686517927 Oct 15 12:32:09 PM UTC 24 Oct 15 12:33:10 PM UTC 24 14963617895 ps
T405 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.4264771046 Oct 15 12:33:09 PM UTC 24 Oct 15 12:33:12 PM UTC 24 83893186 ps
T406 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.1071672747 Oct 15 12:33:11 PM UTC 24 Oct 15 12:33:14 PM UTC 24 77334282 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.3971267105 Oct 15 12:33:12 PM UTC 24 Oct 15 12:33:15 PM UTC 24 22400453 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.2497879270 Oct 15 12:32:59 PM UTC 24 Oct 15 12:33:19 PM UTC 24 3631386545 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.3995370254 Oct 15 12:29:54 PM UTC 24 Oct 15 12:33:26 PM UTC 24 17496567313 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.1732197307 Oct 15 12:31:17 PM UTC 24 Oct 15 12:33:27 PM UTC 24 17723834126 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.1903576368 Oct 15 12:33:28 PM UTC 24 Oct 15 12:33:32 PM UTC 24 32289833 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.2476926945 Oct 15 12:27:53 PM UTC 24 Oct 15 12:33:33 PM UTC 24 27108038832 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.270429901 Oct 15 12:32:51 PM UTC 24 Oct 15 12:33:34 PM UTC 24 6472722746 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.2356833931 Oct 15 12:32:43 PM UTC 24 Oct 15 12:33:34 PM UTC 24 27724948666 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.4292988304 Oct 15 12:33:27 PM UTC 24 Oct 15 12:33:35 PM UTC 24 2415958568 ps
T408 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.2047704222 Oct 15 12:33:11 PM UTC 24 Oct 15 12:33:36 PM UTC 24 3477989957 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.849518628 Oct 15 12:33:14 PM UTC 24 Oct 15 12:33:37 PM UTC 24 53178552330 ps
T409 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.647047342 Oct 15 12:33:35 PM UTC 24 Oct 15 12:33:38 PM UTC 24 37733929 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.2535748436 Oct 15 12:33:39 PM UTC 24 Oct 15 12:33:42 PM UTC 24 119383036 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.4129541800 Oct 15 12:33:34 PM UTC 24 Oct 15 12:33:43 PM UTC 24 606488991 ps
T410 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.3134432022 Oct 15 12:33:35 PM UTC 24 Oct 15 12:33:43 PM UTC 24 5992914801 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.1547939919 Oct 15 12:33:20 PM UTC 24 Oct 15 12:33:44 PM UTC 24 3202636907 ps
T411 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.1158041450 Oct 15 12:33:43 PM UTC 24 Oct 15 12:33:45 PM UTC 24 41903679 ps
T412 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.3218147506 Oct 15 12:33:44 PM UTC 24 Oct 15 12:33:46 PM UTC 24 56751939 ps
T413 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.2594709744 Oct 15 12:33:44 PM UTC 24 Oct 15 12:33:47 PM UTC 24 42272764 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.4278795964 Oct 15 12:33:32 PM UTC 24 Oct 15 12:33:50 PM UTC 24 1105118411 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.692854688 Oct 15 12:33:48 PM UTC 24 Oct 15 12:33:50 PM UTC 24 13173263 ps
T415 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.1210191730 Oct 15 12:33:48 PM UTC 24 Oct 15 12:33:50 PM UTC 24 36475058 ps
T416 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.548235107 Oct 15 12:33:51 PM UTC 24 Oct 15 12:33:55 PM UTC 24 106985312 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.560935577 Oct 15 12:33:11 PM UTC 24 Oct 15 12:33:55 PM UTC 24 7613270682 ps
T417 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.559816037 Oct 15 12:33:51 PM UTC 24 Oct 15 12:33:55 PM UTC 24 83909740 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.1688214299 Oct 15 12:33:16 PM UTC 24 Oct 15 12:33:56 PM UTC 24 12165572528 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.964684506 Oct 15 12:32:43 PM UTC 24 Oct 15 12:33:59 PM UTC 24 7086837487 ps
T418 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.756785498 Oct 15 12:33:56 PM UTC 24 Oct 15 12:34:00 PM UTC 24 31917190 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.2017972069 Oct 15 12:33:56 PM UTC 24 Oct 15 12:34:07 PM UTC 24 324374983 ps
T419 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.3807284734 Oct 15 12:34:02 PM UTC 24 Oct 15 12:34:08 PM UTC 24 87529117 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.4172688707 Oct 15 12:33:51 PM UTC 24 Oct 15 12:34:08 PM UTC 24 3093533961 ps
T420 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.1385608383 Oct 15 12:34:08 PM UTC 24 Oct 15 12:34:10 PM UTC 24 16597184 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.3555516657 Oct 15 12:29:55 PM UTC 24 Oct 15 12:34:13 PM UTC 24 29630176478 ps
T421 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.2137201899 Oct 15 12:33:45 PM UTC 24 Oct 15 12:34:13 PM UTC 24 5649311550 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.3765055951 Oct 15 12:33:46 PM UTC 24 Oct 15 12:34:15 PM UTC 24 1708374601 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.2130485117 Oct 15 12:32:06 PM UTC 24 Oct 15 12:34:15 PM UTC 24 38442330229 ps
T422 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.1076344622 Oct 15 12:34:15 PM UTC 24 Oct 15 12:34:17 PM UTC 24 26466176 ps
T423 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.2842527181 Oct 15 12:34:14 PM UTC 24 Oct 15 12:34:17 PM UTC 24 38401207 ps
T424 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.331541227 Oct 15 12:34:16 PM UTC 24 Oct 15 12:34:18 PM UTC 24 63134936 ps
T425 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.3741640823 Oct 15 12:34:18 PM UTC 24 Oct 15 12:34:20 PM UTC 24 39287277 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.3979911946 Oct 15 12:32:33 PM UTC 24 Oct 15 12:34:22 PM UTC 24 7596706070 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.7721669 Oct 15 12:32:02 PM UTC 24 Oct 15 12:34:22 PM UTC 24 31300529479 ps
T426 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.2880584631 Oct 15 12:34:20 PM UTC 24 Oct 15 12:34:24 PM UTC 24 55239899 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.1427509367 Oct 15 12:34:19 PM UTC 24 Oct 15 12:34:25 PM UTC 24 181167292 ps
T427 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.483519244 Oct 15 12:34:21 PM UTC 24 Oct 15 12:34:26 PM UTC 24 28988651 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.2380778410 Oct 15 12:34:23 PM UTC 24 Oct 15 12:34:28 PM UTC 24 483632629 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.4167946192 Oct 15 12:33:38 PM UTC 24 Oct 15 12:34:30 PM UTC 24 1422753229 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.1796001578 Oct 15 12:28:06 PM UTC 24 Oct 15 12:34:32 PM UTC 24 65681597658 ps
T428 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.3767890624 Oct 15 12:33:57 PM UTC 24 Oct 15 12:34:33 PM UTC 24 3326286232 ps
T429 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.4155817893 Oct 15 12:34:27 PM UTC 24 Oct 15 12:34:35 PM UTC 24 286591161 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mailbox.3624998509 Oct 15 12:34:24 PM UTC 24 Oct 15 12:34:37 PM UTC 24 358644808 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.1360620393 Oct 15 12:34:25 PM UTC 24 Oct 15 12:34:42 PM UTC 24 1512489736 ps
T430 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.793545306 Oct 15 12:34:43 PM UTC 24 Oct 15 12:34:45 PM UTC 24 32975191 ps
T431 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.3793780748 Oct 15 12:34:31 PM UTC 24 Oct 15 12:34:45 PM UTC 24 2779784011 ps
T432 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3180989629 Oct 15 12:34:16 PM UTC 24 Oct 15 12:34:47 PM UTC 24 11379409406 ps
T433 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.1484989854 Oct 15 12:34:46 PM UTC 24 Oct 15 12:34:49 PM UTC 24 32478139 ps
T434 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.2436540350 Oct 15 12:34:46 PM UTC 24 Oct 15 12:34:49 PM UTC 24 29893587 ps
T435 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.3617988115 Oct 15 12:34:49 PM UTC 24 Oct 15 12:34:51 PM UTC 24 15176473 ps
T436 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.3086782834 Oct 15 12:33:56 PM UTC 24 Oct 15 12:34:51 PM UTC 24 5275510012 ps
T437 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.3158723252 Oct 15 12:34:50 PM UTC 24 Oct 15 12:34:52 PM UTC 24 232775197 ps
T438 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.3347022674 Oct 15 12:34:52 PM UTC 24 Oct 15 12:34:54 PM UTC 24 45446417 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.290352413 Oct 15 12:34:09 PM UTC 24 Oct 15 12:34:58 PM UTC 24 9177842575 ps
T439 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.2229353163 Oct 15 12:34:55 PM UTC 24 Oct 15 12:34:59 PM UTC 24 66052169 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.2553149113 Oct 15 12:28:35 PM UTC 24 Oct 15 12:35:00 PM UTC 24 122846603570 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.286051068 Oct 15 12:32:12 PM UTC 24 Oct 15 12:35:02 PM UTC 24 15547875568 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.3306058777 Oct 15 12:31:19 PM UTC 24 Oct 15 12:35:02 PM UTC 24 104947187963 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.1826611042 Oct 15 12:34:18 PM UTC 24 Oct 15 12:35:02 PM UTC 24 4475421025 ps
T440 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.194578294 Oct 15 12:35:00 PM UTC 24 Oct 15 12:35:05 PM UTC 24 131831718 ps
T441 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.3949357150 Oct 15 12:34:26 PM UTC 24 Oct 15 12:35:05 PM UTC 24 4616002595 ps
T442 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.111443781 Oct 15 12:35:04 PM UTC 24 Oct 15 12:35:13 PM UTC 24 230680905 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.3851193353 Oct 15 12:34:52 PM UTC 24 Oct 15 12:35:13 PM UTC 24 23327918694 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.2115722645 Oct 15 12:34:50 PM UTC 24 Oct 15 12:35:17 PM UTC 24 3752637117 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.800683561 Oct 15 12:34:11 PM UTC 24 Oct 15 12:35:18 PM UTC 24 3374615763 ps
T443 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.2155344261 Oct 15 12:35:18 PM UTC 24 Oct 15 12:35:21 PM UTC 24 87725069 ps
T444 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.3269094791 Oct 15 12:35:18 PM UTC 24 Oct 15 12:35:21 PM UTC 24 15663856 ps
T445 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.4241086258 Oct 15 12:35:00 PM UTC 24 Oct 15 12:35:22 PM UTC 24 4337600816 ps
T446 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.1570479502 Oct 15 12:35:22 PM UTC 24 Oct 15 12:35:24 PM UTC 24 26500851 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.3727568698 Oct 15 12:34:53 PM UTC 24 Oct 15 12:35:26 PM UTC 24 24888817228 ps
T447 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.2966501292 Oct 15 12:35:25 PM UTC 24 Oct 15 12:35:27 PM UTC 24 361952505 ps
T448 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.878619947 Oct 15 12:35:22 PM UTC 24 Oct 15 12:35:28 PM UTC 24 1463814293 ps
T449 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.2181349118 Oct 15 12:35:03 PM UTC 24 Oct 15 12:35:30 PM UTC 24 3460264361 ps
T450 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.3184350328 Oct 15 12:35:27 PM UTC 24 Oct 15 12:35:31 PM UTC 24 82168127 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.2435104579 Oct 15 12:35:29 PM UTC 24 Oct 15 12:35:35 PM UTC 24 128658202 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.2373431266 Oct 15 12:35:06 PM UTC 24 Oct 15 12:35:36 PM UTC 24 2702038816 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/coverage/default/13.spi_device_intercept.2220363162 Oct 15 12:35:32 PM UTC 24 Oct 15 12:35:36 PM UTC 24 566971929 ps