Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2703498	1			T1	1		T2	1		T3	1
all_values[1]	2703498	1			T1	1		T2	1		T3	1
all_values[2]	2703498	1			T1	1		T2	1		T3	1
all_values[3]	2703498	1			T1	1		T2	1		T3	1
all_values[4]	2703498	1			T1	1		T2	1		T3	1
all_values[5]	2703498	1			T1	1		T2	1		T3	1
all_values[6]	2703498	1			T1	1		T2	1		T3	1
all_values[7]	2703498	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21344082

1

T1

8

T2

8

T3

8

auto[1]

283902

1

T22

69

T23

78

T33

22

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21602538

1

T1

8

T2

8

T3

8

auto[1]

25446

1

T22

49

T23

59

T50

305

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2659260	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	12094	1			T22	4		T23	3		T50	227
all_values[0]	auto[1]	auto[0]	31735	1			T22	5		T23	3		T33	1
all_values[0]	auto[1]	auto[1]	409	1			T22	1		T23	6		T36	2
all_values[1]	auto[0]	auto[0]	2628289	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	7631	1			T22	3		T23	9		T50	78
all_values[1]	auto[1]	auto[0]	67133	1			T22	11		T23	3		T36	5
all_values[1]	auto[1]	auto[1]	445	1			T22	2		T23	1		T37	49
all_values[2]	auto[0]	auto[0]	2655257	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2927	1			T23	4		T62	2		T63	59
all_values[2]	auto[1]	auto[0]	45063	1			T22	13		T23	8		T33	6
all_values[2]	auto[1]	auto[1]	251	1			T22	4		T23	4		T36	3
all_values[3]	auto[0]	auto[0]	2692913	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	181	1			T22	4		T23	2		T33	2
all_values[3]	auto[1]	auto[0]	10254	1			T22	1		T23	4		T33	1
all_values[3]	auto[1]	auto[1]	150	1			T22	1		T23	5		T36	1
all_values[4]	auto[0]	auto[0]	2645366	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	157	1			T22	6		T23	2		T107	2
all_values[4]	auto[1]	auto[0]	57802	1			T22	3		T23	7		T33	3
all_values[4]	auto[1]	auto[1]	173	1			T22	2		T23	6		T33	2
all_values[5]	auto[0]	auto[0]	2702918	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	172	1			T22	4		T23	2		T37	6
all_values[5]	auto[1]	auto[0]	244	1			T22	1		T23	9		T33	4
all_values[5]	auto[1]	auto[1]	164	1			T22	5		T23	4		T33	1
all_values[6]	auto[0]	auto[0]	2700837	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	175	1			T22	2		T23	5		T36	1
all_values[6]	auto[1]	auto[0]	2313	1			T22	10		T23	8		T33	2
all_values[6]	auto[1]	auto[1]	173	1			T22	6		T23	2		T33	2
all_values[7]	auto[0]	auto[0]	2635728	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	177	1			T22	3		T23	4		T33	1
all_values[7]	auto[1]	auto[0]	67426	1			T22	2		T23	8		T36	3
all_values[7]	auto[1]	auto[1]	167	1			T22	2		T36	1		T37	7