Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2362415	1			T1	1		T2	1		T4	1
all_values[1]	2362415	1			T1	1		T2	1		T4	1
all_values[2]	2362415	1			T1	1		T2	1		T4	1
all_values[3]	2362415	1			T1	1		T2	1		T4	1
all_values[4]	2362415	1			T1	1		T2	1		T4	1
all_values[5]	2362415	1			T1	1		T2	1		T4	1
all_values[6]	2362415	1			T1	1		T2	1		T4	1
all_values[7]	2362415	1			T1	1		T2	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18323128

1

T1

8

T2

8

T4

8

auto[1]

576192

1

T24

35

T35

36

T38

69

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18874997

1

T1

8

T2

8

T4

8

auto[1]

24323

1

T24

51

T46

16

T53

79

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2257170	1			T1	1		T2	1		T4	1
all_values[0]	auto[0]	auto[1]	11795	1			T24	4		T46	8		T53	40
all_values[0]	auto[1]	auto[0]	92981	1			T24	4		T35	4		T38	6
all_values[0]	auto[1]	auto[1]	469	1			T24	5		T35	2		T38	3
all_values[1]	auto[0]	auto[0]	2321206	1			T1	1		T2	1		T4	1
all_values[1]	auto[0]	auto[1]	7311	1			T24	4		T46	4		T53	36
all_values[1]	auto[1]	auto[0]	33656	1			T24	4		T35	1		T183	6
all_values[1]	auto[1]	auto[1]	242	1			T24	3		T35	1		T38	7
all_values[2]	auto[0]	auto[0]	2220935	1			T1	1		T2	1		T4	1
all_values[2]	auto[0]	auto[1]	2490	1			T24	6		T46	4		T53	3
all_values[2]	auto[1]	auto[0]	138729	1			T35	4		T38	4		T39	1
all_values[2]	auto[1]	auto[1]	261	1			T24	4		T35	1		T39	1
all_values[3]	auto[0]	auto[0]	2296502	1			T1	1		T2	1		T4	1
all_values[3]	auto[0]	auto[1]	200	1			T24	2		T35	2		T38	2
all_values[3]	auto[1]	auto[0]	65536	1			T24	1		T35	3		T38	4
all_values[3]	auto[1]	auto[1]	177	1			T24	2		T35	3		T38	4
all_values[4]	auto[0]	auto[0]	2357937	1			T1	1		T2	1		T4	1
all_values[4]	auto[0]	auto[1]	178	1			T24	1		T35	2		T38	3
all_values[4]	auto[1]	auto[0]	4104	1			T24	3		T35	5		T38	6
all_values[4]	auto[1]	auto[1]	196	1			T24	2		T35	1		T38	4
all_values[5]	auto[0]	auto[0]	2268323	1			T1	1		T2	1		T4	1
all_values[5]	auto[0]	auto[1]	190	1			T24	6		T35	1		T38	4
all_values[5]	auto[1]	auto[0]	93762	1			T35	1		T38	8		T39	2306
all_values[5]	auto[1]	auto[1]	140	1			T24	1		T35	2		T38	2
all_values[6]	auto[0]	auto[0]	2253212	1			T1	1		T2	1		T4	1
all_values[6]	auto[0]	auto[1]	158	1			T24	5		T38	1		T183	4
all_values[6]	auto[1]	auto[0]	108844	1			T24	1		T35	5		T38	14
all_values[6]	auto[1]	auto[1]	201	1			T24	1		T39	3		T183	4
all_values[7]	auto[0]	auto[0]	2325363	1			T1	1		T2	1		T4	1
all_values[7]	auto[0]	auto[1]	158	1			T24	3		T35	1		T38	4
all_values[7]	auto[1]	auto[0]	36737	1			T24	2		T35	1		T38	4
all_values[7]	auto[1]	auto[1]	157	1			T24	2		T35	2		T38	3