Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total tests in report: 1151
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
47.71 47.71 75.63 75.63 48.95 48.95 52.85 52.85 17.78 17.78 59.05 59.05 72.57 72.57 7.13 7.13 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.3409472061
71.25 23.54 95.31 19.68 84.94 35.99 84.06 31.20 48.89 31.11 92.68 33.63 79.43 6.86 13.42 6.29 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.1949426013
80.29 9.04 97.42 2.11 89.96 5.02 84.94 0.89 82.22 33.33 95.82 3.15 84.29 4.86 27.38 13.96 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.3251226362
83.67 3.38 97.91 0.48 91.09 1.13 86.81 1.87 88.89 6.67 96.43 0.61 84.43 0.14 40.15 12.77 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.3457277369
85.84 2.16 97.98 0.07 91.30 0.21 86.81 0.00 91.11 2.22 96.55 0.12 84.57 0.14 52.52 12.38 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.3336694961
87.24 1.40 98.00 0.02 91.40 0.10 87.40 0.59 91.11 0.00 96.58 0.03 92.57 8.00 53.61 1.09 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.2366202114
88.41 1.17 98.00 0.00 91.49 0.09 87.80 0.39 91.11 0.00 96.60 0.02 92.71 0.14 61.14 7.52 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.107127611
89.42 1.02 98.12 0.12 91.81 0.32 87.99 0.20 93.33 2.22 96.80 0.20 92.71 0.00 65.20 4.06 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.3211784963
90.29 0.86 98.18 0.06 91.87 0.06 87.99 0.00 93.33 0.00 96.92 0.12 92.86 0.14 70.84 5.64 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.6296300
90.96 0.68 98.19 0.01 91.87 0.00 92.72 4.72 93.33 0.00 96.92 0.00 92.86 0.00 70.84 0.00 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.2220699724
91.62 0.66 98.19 0.00 91.89 0.01 92.72 0.00 93.33 0.00 96.94 0.02 92.86 0.00 75.45 4.60 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.4225349543
92.23 0.61 98.19 0.00 91.89 0.00 92.72 0.00 93.33 0.00 96.94 0.00 92.86 0.00 79.70 4.26 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.434838797
92.79 0.56 98.19 0.00 92.79 0.91 93.11 0.39 93.33 0.00 96.97 0.03 93.57 0.71 81.58 1.88 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.55953829
93.33 0.54 98.19 0.00 92.82 0.02 96.46 3.35 93.33 0.00 96.97 0.00 93.71 0.14 81.83 0.25 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.4114571693
93.86 0.53 98.31 0.12 93.36 0.55 98.03 1.57 93.33 0.00 97.14 0.17 94.43 0.71 82.43 0.59 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.483273027
94.16 0.30 98.32 0.01 93.38 0.01 98.03 0.00 93.33 0.00 97.14 0.00 94.43 0.00 84.50 2.08 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.2792356257
94.43 0.27 98.32 0.00 93.41 0.04 98.03 0.00 93.33 0.00 97.14 0.00 94.43 0.00 86.34 1.83 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.2193442598
94.64 0.21 98.32 0.00 93.43 0.01 98.03 0.00 93.33 0.00 97.14 0.00 94.43 0.00 87.77 1.44 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.2120173413
94.83 0.19 98.32 0.00 93.49 0.06 98.03 0.00 93.33 0.00 97.14 0.00 94.43 0.00 89.06 1.29 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.2269447472
94.99 0.16 98.32 0.00 93.50 0.01 98.03 0.00 93.33 0.00 97.14 0.00 94.43 0.00 90.15 1.09 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.168477779
95.13 0.15 98.37 0.06 93.59 0.09 98.43 0.39 93.33 0.00 97.23 0.08 94.43 0.00 90.54 0.40 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.2998246248
95.26 0.13 98.37 0.00 93.59 0.00 98.43 0.00 93.33 0.00 97.23 0.00 94.43 0.00 91.44 0.89 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.1607571106
95.38 0.12 98.37 0.00 93.59 0.00 98.43 0.00 93.33 0.00 97.23 0.00 95.29 0.86 91.44 0.00 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.1885301095
95.49 0.11 98.37 0.00 93.74 0.15 98.43 0.00 93.33 0.00 97.23 0.00 95.29 0.00 92.08 0.64 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.3801260339
95.60 0.11 98.37 0.00 93.74 0.00 98.43 0.00 93.33 0.00 97.23 0.00 95.29 0.00 92.82 0.74 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.2140488287
95.70 0.10 98.37 0.00 93.74 0.00 98.43 0.00 93.33 0.00 97.23 0.00 95.29 0.00 93.51 0.69 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.1081434912
95.80 0.10 98.37 0.00 93.74 0.00 98.43 0.00 93.33 0.00 97.23 0.00 95.43 0.14 94.06 0.54 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.4083824895
95.89 0.09 98.37 0.00 93.75 0.01 98.43 0.00 93.33 0.00 97.23 0.00 95.43 0.00 94.70 0.64 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.2087772338
95.98 0.08 98.37 0.00 93.75 0.00 98.43 0.00 93.33 0.00 97.23 0.00 95.43 0.00 95.30 0.59 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.2439937230
96.05 0.07 98.37 0.00 93.75 0.00 98.43 0.00 93.33 0.00 97.23 0.00 95.43 0.00 95.79 0.50 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_all.3448662810
96.10 0.06 98.37 0.00 93.75 0.00 98.43 0.00 93.33 0.00 97.23 0.00 95.43 0.00 96.19 0.40 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.371977019
96.15 0.04 98.40 0.03 93.79 0.04 98.62 0.20 93.33 0.00 97.23 0.00 95.43 0.00 96.24 0.05 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.1528494501
96.19 0.04 98.40 0.00 93.79 0.00 98.62 0.00 93.33 0.00 97.23 0.00 95.43 0.00 96.53 0.30 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.537057591
96.23 0.04 98.40 0.00 93.87 0.09 98.62 0.00 93.33 0.00 97.23 0.00 95.43 0.00 96.73 0.20 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.4220442883
96.27 0.04 98.40 0.00 93.92 0.05 98.62 0.00 93.33 0.00 97.26 0.03 95.43 0.00 96.93 0.20 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.2777975762
96.30 0.03 98.40 0.00 93.92 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 97.13 0.20 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.3619942041
96.32 0.02 98.41 0.01 93.92 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 97.28 0.15 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2007811867
96.34 0.02 98.41 0.00 93.92 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 97.43 0.15 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.1036630777
96.36 0.02 98.41 0.00 93.92 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 97.57 0.15 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.3043681057
96.39 0.02 98.41 0.00 93.92 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 97.72 0.15 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.1745817511
96.41 0.02 98.41 0.00 93.92 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 97.87 0.15 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.565483038
96.43 0.02 98.41 0.00 93.92 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.02 0.15 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.418998293
96.44 0.02 98.41 0.00 93.99 0.06 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.07 0.05 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.1285162692
96.46 0.01 98.41 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.17 0.10 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.3168493578
96.47 0.01 98.41 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.27 0.10 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.1003242862
96.49 0.01 98.41 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.37 0.10 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.564339662
96.50 0.01 98.41 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.47 0.10 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.588683309
96.51 0.01 98.41 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.56 0.10 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/17.spi_device_stress_all.3524454926
96.53 0.01 98.41 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.66 0.10 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.1978585855
96.54 0.01 98.41 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.76 0.10 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode.3160188643
96.56 0.01 98.41 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.86 0.10 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.730809219
96.57 0.01 98.42 0.01 93.99 0.00 98.62 0.00 93.33 0.00 97.28 0.02 95.43 0.00 98.91 0.05 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.1632889908
96.58 0.01 98.42 0.00 94.01 0.02 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.1321857883
96.59 0.01 98.42 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.1119620177
96.59 0.01 98.42 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/20.spi_device_stress_all.3129329862
96.60 0.01 98.42 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_all.93607217
96.61 0.01 98.42 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode.815206378
96.61 0.01 98.42 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.3004489126
96.62 0.01 98.42 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.05 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.2341493407
96.63 0.01 98.44 0.02 94.04 0.02 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.1392915772
96.63 0.01 98.44 0.00 94.06 0.02 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3249033486
96.63 0.01 98.44 0.00 94.08 0.02 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.3773284899

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1763276807
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3517682553
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2213850906
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3859247607
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2083159298
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2753287963
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.2596094317
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.4077267988
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1270034677
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.3835873578
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.134784947
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3228861766
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2753266561
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3982895196
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.851195509
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.372326765
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1637218708
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2490892312
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3855409268
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.2888429922
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.4138375889
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2621671178
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.472680511
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.277463258
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.61249496
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1487113001
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.3162533350
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3298954219
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.3490458598
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.2515497535
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3657096940
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3860960667
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.3725674346
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/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.2621703946
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.3191169114
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.2478074781
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.1986568423
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.1684134749
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.2786885866
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.640061182
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.2133767640
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.4013983664
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.3039774821
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2900087294
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.1122567625
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.3303862168
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.1018868631
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.3017263135
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.65306516
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.3337307906
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.725188276
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.1900457136
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.3533315461
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1902575502
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.1239610649
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.3916876915
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.121485511
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.65554716
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.3830555904
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.117527830
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.1693280619
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.3371883919
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.3431249438
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.4241655135
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.3392332547
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.1191989483
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.3081411434
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.1707323251
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.1812791917
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.1933424368
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.3289941472
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.4017245314
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.4034084024
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.3439819048
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.2150255018
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.3109546766
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.1944052547
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.629317037
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.1518523019
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.3644797623
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.3009255713
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.1338219137
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.1521012843
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.1407402923
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.1288105765
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.298090063
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.2540754705
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1518682692
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.299464733
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.2444692704
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.3160739559
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2571818880
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.3105431733
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.2260249880
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.2722299829
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.1939446588
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.1146171123
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.3732274636
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.2897988428
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.2427616114
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.1603089128
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.2014947093
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.3454067038
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.1292588907
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.4010193816
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.3774768134



Total test records in report: 1151
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.1392915772 Feb 08 06:29:43 PM UTC 25 Feb 08 06:29:45 PM UTC 25 68891839 ps
T2 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.2220699724 Feb 08 06:29:43 PM UTC 25 Feb 08 06:29:45 PM UTC 25 39726695 ps
T3 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.1623622082 Feb 08 06:29:43 PM UTC 25 Feb 08 06:29:45 PM UTC 25 117603265 ps
T4 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.2784708908 Feb 08 06:29:44 PM UTC 25 Feb 08 06:29:47 PM UTC 25 134027768 ps
T5 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.3409472061 Feb 08 06:29:44 PM UTC 25 Feb 08 06:29:47 PM UTC 25 198583601 ps
T6 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.1528494501 Feb 08 06:29:46 PM UTC 25 Feb 08 06:29:48 PM UTC 25 26498646 ps
T7 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.1826217208 Feb 08 06:29:46 PM UTC 25 Feb 08 06:29:48 PM UTC 25 16108349 ps
T8 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.2998246248 Feb 08 06:29:46 PM UTC 25 Feb 08 06:29:49 PM UTC 25 41361343 ps
T9 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.4114571693 Feb 08 06:29:46 PM UTC 25 Feb 08 06:29:49 PM UTC 25 62545201 ps
T10 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.265334874 Feb 08 06:29:47 PM UTC 25 Feb 08 06:29:49 PM UTC 25 28344768 ps
T11 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2007811867 Feb 08 06:29:44 PM UTC 25 Feb 08 06:29:51 PM UTC 25 979249754 ps
T12 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.3789490710 Feb 08 06:29:46 PM UTC 25 Feb 08 06:29:51 PM UTC 25 164759385 ps
T13 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.3833798336 Feb 08 06:29:48 PM UTC 25 Feb 08 06:29:51 PM UTC 25 97421084 ps
T14 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.1949426013 Feb 08 06:29:44 PM UTC 25 Feb 08 06:29:52 PM UTC 25 690888315 ps
T15 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.1752384046 Feb 08 06:29:44 PM UTC 25 Feb 08 06:29:52 PM UTC 25 1550724569 ps
T16 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.2594989297 Feb 08 06:29:49 PM UTC 25 Feb 08 06:29:53 PM UTC 25 50184740 ps
T17 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.3211784963 Feb 08 06:29:49 PM UTC 25 Feb 08 06:29:54 PM UTC 25 415865182 ps
T40 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.3715357425 Feb 08 06:29:53 PM UTC 25 Feb 08 06:29:55 PM UTC 25 81466014 ps
T18 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.4014784149 Feb 08 06:29:48 PM UTC 25 Feb 08 06:29:56 PM UTC 25 461037000 ps
T41 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.3392171550 Feb 08 06:29:55 PM UTC 25 Feb 08 06:29:57 PM UTC 25 40224148 ps
T19 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.3238235078 Feb 08 06:29:55 PM UTC 25 Feb 08 06:29:58 PM UTC 25 158540574 ps
T20 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.2428647605 Feb 08 06:29:56 PM UTC 25 Feb 08 06:29:58 PM UTC 25 21937282 ps
T21 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.1301887869 Feb 08 06:29:46 PM UTC 25 Feb 08 06:29:59 PM UTC 25 397452363 ps
T45 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.2306703792 Feb 08 06:29:56 PM UTC 25 Feb 08 06:29:59 PM UTC 25 83827009 ps
T22 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.547774705 Feb 08 06:29:49 PM UTC 25 Feb 08 06:30:00 PM UTC 25 482819562 ps
T23 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.823929738 Feb 08 06:29:53 PM UTC 25 Feb 08 06:30:00 PM UTC 25 341673444 ps
T27 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.800444616 Feb 08 06:29:58 PM UTC 25 Feb 08 06:30:01 PM UTC 25 51464741 ps
T31 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.225408188 Feb 08 06:29:59 PM UTC 25 Feb 08 06:30:02 PM UTC 25 15613329 ps
T28 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1518666349 Feb 08 06:29:46 PM UTC 25 Feb 08 06:30:03 PM UTC 25 3665539083 ps
T116 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.1664960317 Feb 08 06:29:59 PM UTC 25 Feb 08 06:30:03 PM UTC 25 62864981 ps
T55 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.3743971772 Feb 08 06:29:44 PM UTC 25 Feb 08 06:30:04 PM UTC 25 3698408555 ps
T29 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.3801260339 Feb 08 06:29:56 PM UTC 25 Feb 08 06:30:05 PM UTC 25 3752250376 ps
T63 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.647848173 Feb 08 06:29:59 PM UTC 25 Feb 08 06:30:05 PM UTC 25 82288372 ps
T30 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.1920553255 Feb 08 06:29:44 PM UTC 25 Feb 08 06:30:05 PM UTC 25 39131807666 ps
T56 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.438883913 Feb 08 06:30:00 PM UTC 25 Feb 08 06:30:07 PM UTC 25 490309396 ps
T57 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.1572342594 Feb 08 06:29:44 PM UTC 25 Feb 08 06:30:08 PM UTC 25 3641875009 ps
T32 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.12686381 Feb 08 06:29:43 PM UTC 25 Feb 08 06:30:10 PM UTC 25 56736440513 ps
T61 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.4060079287 Feb 08 06:30:01 PM UTC 25 Feb 08 06:30:10 PM UTC 25 959923273 ps
T60 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.3615862338 Feb 08 06:30:03 PM UTC 25 Feb 08 06:30:10 PM UTC 25 746310646 ps
T24 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.476769805 Feb 08 06:30:08 PM UTC 25 Feb 08 06:30:11 PM UTC 25 147798426 ps
T25 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.2253786985 Feb 08 06:30:08 PM UTC 25 Feb 08 06:30:11 PM UTC 25 305059581 ps
T98 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.2495916703 Feb 08 06:30:10 PM UTC 25 Feb 08 06:30:12 PM UTC 25 22036191 ps
T99 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.2805283525 Feb 08 06:30:10 PM UTC 25 Feb 08 06:30:12 PM UTC 25 24780456 ps
T76 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.1632889908 Feb 08 06:29:49 PM UTC 25 Feb 08 06:30:12 PM UTC 25 6459902031 ps
T47 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.3825052364 Feb 08 06:30:10 PM UTC 25 Feb 08 06:30:13 PM UTC 25 45118308 ps
T49 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.483273027 Feb 08 06:30:04 PM UTC 25 Feb 08 06:30:13 PM UTC 25 297820886 ps
T33 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.2801606153 Feb 08 06:30:11 PM UTC 25 Feb 08 06:30:14 PM UTC 25 27204143 ps
T34 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.1408536115 Feb 08 06:30:06 PM UTC 25 Feb 08 06:30:15 PM UTC 25 5035896750 ps
T91 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.1321857883 Feb 08 06:29:50 PM UTC 25 Feb 08 06:30:16 PM UTC 25 1659673624 ps
T92 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.640428933 Feb 08 06:29:50 PM UTC 25 Feb 08 06:30:16 PM UTC 25 3348001228 ps
T93 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.1516975317 Feb 08 06:30:01 PM UTC 25 Feb 08 06:30:17 PM UTC 25 487970047 ps
T48 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.1553670192 Feb 08 06:30:11 PM UTC 25 Feb 08 06:30:18 PM UTC 25 128456785 ps
T97 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.934181942 Feb 08 06:30:05 PM UTC 25 Feb 08 06:30:19 PM UTC 25 970543959 ps
T413 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.2014672075 Feb 08 06:30:18 PM UTC 25 Feb 08 06:30:20 PM UTC 25 31820501 ps
T58 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.1793701786 Feb 08 06:30:14 PM UTC 25 Feb 08 06:30:21 PM UTC 25 1550065668 ps
T112 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.3114547356 Feb 08 06:30:14 PM UTC 25 Feb 08 06:30:21 PM UTC 25 114827177 ps
T62 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.2034132029 Feb 08 06:30:15 PM UTC 25 Feb 08 06:30:21 PM UTC 25 3676004960 ps
T96 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.169255880 Feb 08 06:30:14 PM UTC 25 Feb 08 06:30:21 PM UTC 25 236453724 ps
T110 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.2578540424 Feb 08 06:30:11 PM UTC 25 Feb 08 06:30:22 PM UTC 25 2027960158 ps
T59 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.3468591223 Feb 08 06:30:14 PM UTC 25 Feb 08 06:30:23 PM UTC 25 1238767432 ps
T26 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.2865828562 Feb 08 06:30:21 PM UTC 25 Feb 08 06:30:24 PM UTC 25 31781620 ps
T46 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.3251226362 Feb 08 06:29:46 PM UTC 25 Feb 08 06:30:24 PM UTC 25 3838015987 ps
T414 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.3515023788 Feb 08 06:30:22 PM UTC 25 Feb 08 06:30:25 PM UTC 25 43180760 ps
T415 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.463452698 Feb 08 06:30:22 PM UTC 25 Feb 08 06:30:25 PM UTC 25 52367655 ps
T416 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.230839928 Feb 08 06:30:22 PM UTC 25 Feb 08 06:30:25 PM UTC 25 32663440 ps
T53 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.305449319 Feb 08 06:29:53 PM UTC 25 Feb 08 06:30:27 PM UTC 25 4145483424 ps
T111 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.131894136 Feb 08 06:30:25 PM UTC 25 Feb 08 06:30:27 PM UTC 25 59216010 ps
T73 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.2295472724 Feb 08 06:30:25 PM UTC 25 Feb 08 06:30:27 PM UTC 25 192545475 ps
T74 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.1003242862 Feb 08 06:29:47 PM UTC 25 Feb 08 06:30:29 PM UTC 25 6875684056 ps
T209 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.886241662 Feb 08 06:30:26 PM UTC 25 Feb 08 06:30:32 PM UTC 25 69421817 ps
T171 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.1989095860 Feb 08 06:30:17 PM UTC 25 Feb 08 06:30:32 PM UTC 25 2229460991 ps
T75 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.3376664502 Feb 08 06:29:58 PM UTC 25 Feb 08 06:30:34 PM UTC 25 4894340517 ps
T226 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.2882805037 Feb 08 06:30:28 PM UTC 25 Feb 08 06:30:36 PM UTC 25 376563900 ps
T54 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.2777975762 Feb 08 06:29:53 PM UTC 25 Feb 08 06:30:36 PM UTC 25 2296652014 ps
T50 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.1278083541 Feb 08 06:30:05 PM UTC 25 Feb 08 06:30:36 PM UTC 25 32146732539 ps
T201 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.4263004215 Feb 08 06:30:26 PM UTC 25 Feb 08 06:30:36 PM UTC 25 1646976602 ps
T272 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.4220442883 Feb 08 06:30:14 PM UTC 25 Feb 08 06:30:37 PM UTC 25 1227440604 ps
T66 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.2485159227 Feb 08 06:30:06 PM UTC 25 Feb 08 06:30:37 PM UTC 25 2337026578 ps
T35 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.970436257 Feb 08 06:30:36 PM UTC 25 Feb 08 06:30:38 PM UTC 25 72394002 ps
T172 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.725333938 Feb 08 06:30:28 PM UTC 25 Feb 08 06:30:39 PM UTC 25 1070909400 ps
T173 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.4107046596 Feb 08 06:30:31 PM UTC 25 Feb 08 06:30:39 PM UTC 25 380925202 ps
T417 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.2013954659 Feb 08 06:30:37 PM UTC 25 Feb 08 06:30:39 PM UTC 25 11695315 ps
T418 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.991499775 Feb 08 06:30:37 PM UTC 25 Feb 08 06:30:39 PM UTC 25 63361077 ps
T401 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.2036109275 Feb 08 06:30:24 PM UTC 25 Feb 08 06:30:40 PM UTC 25 3966379719 ps
T36 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.3868422506 Feb 08 06:30:37 PM UTC 25 Feb 08 06:30:41 PM UTC 25 80013229 ps
T419 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.3133218686 Feb 08 06:30:37 PM UTC 25 Feb 08 06:30:41 PM UTC 25 29483085 ps
T420 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2563729582 Feb 08 06:30:24 PM UTC 25 Feb 08 06:30:41 PM UTC 25 10390041759 ps
T421 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.3763564697 Feb 08 06:30:39 PM UTC 25 Feb 08 06:30:42 PM UTC 25 141902209 ps
T402 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.2428547998 Feb 08 06:30:39 PM UTC 25 Feb 08 06:30:42 PM UTC 25 104682537 ps
T422 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.921503601 Feb 08 06:30:40 PM UTC 25 Feb 08 06:30:45 PM UTC 25 168354610 ps
T247 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.2951735157 Feb 08 06:30:41 PM UTC 25 Feb 08 06:30:45 PM UTC 25 867771707 ps
T423 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.3265711614 Feb 08 06:30:41 PM UTC 25 Feb 08 06:30:46 PM UTC 25 108308124 ps
T203 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.2149476029 Feb 08 06:30:42 PM UTC 25 Feb 08 06:30:47 PM UTC 25 505670149 ps
T213 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.2163893209 Feb 08 06:30:42 PM UTC 25 Feb 08 06:30:48 PM UTC 25 54323589 ps
T424 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.3480641058 Feb 08 06:30:38 PM UTC 25 Feb 08 06:30:48 PM UTC 25 1895366369 ps
T425 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.3433397675 Feb 08 06:30:42 PM UTC 25 Feb 08 06:30:49 PM UTC 25 229927322 ps
T426 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.2532016380 Feb 08 06:30:48 PM UTC 25 Feb 08 06:30:50 PM UTC 25 44478367 ps
T427 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.3685114730 Feb 08 06:30:48 PM UTC 25 Feb 08 06:30:51 PM UTC 25 18464202 ps
T109 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.2254986790 Feb 08 06:30:38 PM UTC 25 Feb 08 06:30:51 PM UTC 25 5902649619 ps
T428 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.2133767640 Feb 08 06:30:49 PM UTC 25 Feb 08 06:30:52 PM UTC 25 170825890 ps
T429 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.3303862168 Feb 08 06:30:49 PM UTC 25 Feb 08 06:30:53 PM UTC 25 339535734 ps
T267 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.3043032957 Feb 08 06:30:26 PM UTC 25 Feb 08 06:30:53 PM UTC 25 20117457796 ps
T430 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.3017263135 Feb 08 06:30:51 PM UTC 25 Feb 08 06:30:54 PM UTC 25 380488321 ps
T89 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.1332502628 Feb 08 06:30:46 PM UTC 25 Feb 08 06:30:55 PM UTC 25 526601386 ps
T405 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.1018868631 Feb 08 06:30:53 PM UTC 25 Feb 08 06:30:55 PM UTC 25 16048427 ps
T125 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.1516519782 Feb 08 06:30:43 PM UTC 25 Feb 08 06:30:58 PM UTC 25 4045289584 ps
T251 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.2786885866 Feb 08 06:30:54 PM UTC 25 Feb 08 06:30:59 PM UTC 25 109111334 ps
T67 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.4050572247 Feb 08 06:30:27 PM UTC 25 Feb 08 06:31:00 PM UTC 25 5952716542 ps
T431 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.65306516 Feb 08 06:30:56 PM UTC 25 Feb 08 06:31:00 PM UTC 25 201477920 ps
T227 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.3221575570 Feb 08 06:30:56 PM UTC 25 Feb 08 06:31:00 PM UTC 25 442747181 ps
T262 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.1625817026 Feb 08 06:30:40 PM UTC 25 Feb 08 06:31:01 PM UTC 25 3265420405 ps
T259 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.3039774821 Feb 08 06:30:53 PM UTC 25 Feb 08 06:31:03 PM UTC 25 357996043 ps
T174 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2900087294 Feb 08 06:31:01 PM UTC 25 Feb 08 06:31:11 PM UTC 25 1340145022 ps
T432 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.2713270458 Feb 08 06:31:09 PM UTC 25 Feb 08 06:31:12 PM UTC 25 14826895 ps
T403 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.1122567625 Feb 08 06:30:51 PM UTC 25 Feb 08 06:31:13 PM UTC 25 2080648936 ps
T433 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.1900457136 Feb 08 06:31:12 PM UTC 25 Feb 08 06:31:14 PM UTC 25 23316513 ps
T211 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.1981068360 Feb 08 06:30:16 PM UTC 25 Feb 08 06:31:14 PM UTC 25 6291389023 ps
T404 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.96768005 Feb 08 06:30:11 PM UTC 25 Feb 08 06:31:15 PM UTC 25 11660715651 ps
T434 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.3830555904 Feb 08 06:31:13 PM UTC 25 Feb 08 06:31:15 PM UTC 25 47801324 ps
T210 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.4013983664 Feb 08 06:30:54 PM UTC 25 Feb 08 06:31:15 PM UTC 25 6098197024 ps
T435 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.1191989483 Feb 08 06:31:15 PM UTC 25 Feb 08 06:31:17 PM UTC 25 60673034 ps
T212 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.1596505079 Feb 08 06:29:46 PM UTC 25 Feb 08 06:31:17 PM UTC 25 27204492169 ps
T90 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.2269447472 Feb 08 06:30:33 PM UTC 25 Feb 08 06:31:18 PM UTC 25 2658614348 ps
T436 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.3392332547 Feb 08 06:31:16 PM UTC 25 Feb 08 06:31:19 PM UTC 25 38082079 ps
T392 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.1986568423 Feb 08 06:30:59 PM UTC 25 Feb 08 06:31:22 PM UTC 25 5511720758 ps
T437 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.4241655135 Feb 08 06:31:14 PM UTC 25 Feb 08 06:31:23 PM UTC 25 2706327571 ps
T37 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.608985710 Feb 08 06:30:47 PM UTC 25 Feb 08 06:31:23 PM UTC 25 7999995483 ps
T311 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.121485511 Feb 08 06:31:18 PM UTC 25 Feb 08 06:31:24 PM UTC 25 113414761 ps
T275 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.65554716 Feb 08 06:31:18 PM UTC 25 Feb 08 06:31:25 PM UTC 25 141443912 ps
T306 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.725188276 Feb 08 06:31:19 PM UTC 25 Feb 08 06:31:27 PM UTC 25 168875942 ps
T95 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.2792356257 Feb 08 06:30:20 PM UTC 25 Feb 08 06:31:28 PM UTC 25 12747125230 ps
T438 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.3337307906 Feb 08 06:31:29 PM UTC 25 Feb 08 06:31:31 PM UTC 25 28098379 ps
T229 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.1239610649 Feb 08 06:31:19 PM UTC 25 Feb 08 06:31:31 PM UTC 25 288446818 ps
T439 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.1933424368 Feb 08 06:31:32 PM UTC 25 Feb 08 06:31:34 PM UTC 25 16726122 ps
T440 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.1944052547 Feb 08 06:31:32 PM UTC 25 Feb 08 06:31:34 PM UTC 25 56369657 ps
T441 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.3371883919 Feb 08 06:31:24 PM UTC 25 Feb 08 06:31:40 PM UTC 25 1460680516 ps
T442 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.1288105765 Feb 08 06:31:39 PM UTC 25 Feb 08 06:31:42 PM UTC 25 411228326 ps
T443 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.1407402923 Feb 08 06:31:39 PM UTC 25 Feb 08 06:31:42 PM UTC 25 48653811 ps
T277 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.640061182 Feb 08 06:30:55 PM UTC 25 Feb 08 06:31:44 PM UTC 25 3916157797 ps
T444 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.1521012843 Feb 08 06:31:35 PM UTC 25 Feb 08 06:31:44 PM UTC 25 1776057178 ps
T282 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.3664771878 Feb 08 06:30:26 PM UTC 25 Feb 08 06:31:47 PM UTC 25 26916552033 ps
T64 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.629317037 Feb 08 06:31:42 PM UTC 25 Feb 08 06:31:50 PM UTC 25 189428241 ps
T400 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.1338219137 Feb 08 06:31:35 PM UTC 25 Feb 08 06:31:50 PM UTC 25 29690597661 ps
T94 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.1036630777 Feb 08 06:29:46 PM UTC 25 Feb 08 06:31:51 PM UTC 25 3605938477 ps
T397 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.3431249438 Feb 08 06:31:15 PM UTC 25 Feb 08 06:31:52 PM UTC 25 10234359869 ps
T104 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.424001541 Feb 08 06:30:43 PM UTC 25 Feb 08 06:31:53 PM UTC 25 3857337056 ps
T245 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.117527830 Feb 08 06:31:16 PM UTC 25 Feb 08 06:31:57 PM UTC 25 20834263493 ps
T278 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.1518523019 Feb 08 06:31:41 PM UTC 25 Feb 08 06:31:57 PM UTC 25 5641986314 ps
T38 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.3009255713 Feb 08 06:31:57 PM UTC 25 Feb 08 06:32:00 PM UTC 25 165088431 ps
T445 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.1707323251 Feb 08 06:31:58 PM UTC 25 Feb 08 06:32:01 PM UTC 25 11558053 ps
T446 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.299464733 Feb 08 06:31:58 PM UTC 25 Feb 08 06:32:01 PM UTC 25 13911298 ps
T113 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.1812791917 Feb 08 06:31:46 PM UTC 25 Feb 08 06:32:01 PM UTC 25 4495842079 ps
T447 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.1146171123 Feb 08 06:32:00 PM UTC 25 Feb 08 06:32:03 PM UTC 25 27361532 ps
T39 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.3457277369 Feb 08 06:31:28 PM UTC 25 Feb 08 06:32:04 PM UTC 25 4958498941 ps
T260 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.3109546766 Feb 08 06:31:45 PM UTC 25 Feb 08 06:32:04 PM UTC 25 764255082 ps
T448 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.4010193816 Feb 08 06:32:02 PM UTC 25 Feb 08 06:32:04 PM UTC 25 25005710 ps
T449 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.3454067038 Feb 08 06:32:02 PM UTC 25 Feb 08 06:32:04 PM UTC 25 17686798 ps
T255 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.3081411434 Feb 08 06:31:18 PM UTC 25 Feb 08 06:32:05 PM UTC 25 119257896283 ps
T266 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.2150255018 Feb 08 06:31:43 PM UTC 25 Feb 08 06:32:06 PM UTC 25 6983996292 ps
T204 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.1693280619 Feb 08 06:31:16 PM UTC 25 Feb 08 06:32:06 PM UTC 25 23531538892 ps
T450 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.1292588907 Feb 08 06:32:04 PM UTC 25 Feb 08 06:32:07 PM UTC 25 115339503 ps
T300 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.2897988428 Feb 08 06:32:04 PM UTC 25 Feb 08 06:32:09 PM UTC 25 1234460817 ps
T323 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1518682692 Feb 08 06:32:06 PM UTC 25 Feb 08 06:32:11 PM UTC 25 111970467 ps
T283 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.3105431733 Feb 08 06:32:06 PM UTC 25 Feb 08 06:32:15 PM UTC 25 234776139 ps
T321 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.3774768134 Feb 08 06:32:05 PM UTC 25 Feb 08 06:32:16 PM UTC 25 2514241040 ps
T353 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.298090063 Feb 08 06:31:46 PM UTC 25 Feb 08 06:32:17 PM UTC 25 4212428128 ps
T183 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.1603089128 Feb 08 06:32:17 PM UTC 25 Feb 08 06:32:19 PM UTC 25 198074629 ps
T192 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.3644797623 Feb 08 06:31:51 PM UTC 25 Feb 08 06:32:20 PM UTC 25 2202880438 ps
T193 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.2540754705 Feb 08 06:32:18 PM UTC 25 Feb 08 06:32:20 PM UTC 25 51373642 ps
T115 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.2722299829 Feb 08 06:32:05 PM UTC 25 Feb 08 06:32:20 PM UTC 25 1084005775 ps
T65 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.3336694961 Feb 08 06:30:35 PM UTC 25 Feb 08 06:32:22 PM UTC 25 23099418698 ps
T194 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.2704844408 Feb 08 06:32:20 PM UTC 25 Feb 08 06:32:22 PM UTC 25 232184873 ps
T195 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.3732274636 Feb 08 06:32:05 PM UTC 25 Feb 08 06:32:23 PM UTC 25 7459932755 ps
T196 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.2203314438 Feb 08 06:32:21 PM UTC 25 Feb 08 06:32:23 PM UTC 25 50741124 ps
T197 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.2014947093 Feb 08 06:32:02 PM UTC 25 Feb 08 06:32:25 PM UTC 25 1353341215 ps
T198 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.294032906 Feb 08 06:32:23 PM UTC 25 Feb 08 06:32:25 PM UTC 25 53944936 ps
T451 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.3223206877 Feb 08 06:32:23 PM UTC 25 Feb 08 06:32:27 PM UTC 25 42528578 ps
T328 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.1939446588 Feb 08 06:32:05 PM UTC 25 Feb 08 06:32:27 PM UTC 25 6861975126 ps
T312 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.1611466450 Feb 08 06:32:24 PM UTC 25 Feb 08 06:32:29 PM UTC 25 124620447 ps
T68 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.194027775 Feb 08 06:32:24 PM UTC 25 Feb 08 06:32:29 PM UTC 25 69806589 ps
T452 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.3710816571 Feb 08 06:32:26 PM UTC 25 Feb 08 06:32:31 PM UTC 25 158649280 ps
T453 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.2427616114 Feb 08 06:32:08 PM UTC 25 Feb 08 06:32:31 PM UTC 25 1515279252 ps
T393 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.4034084024 Feb 08 06:31:48 PM UTC 25 Feb 08 06:32:31 PM UTC 25 14117518271 ps
T330 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.666877544 Feb 08 06:32:27 PM UTC 25 Feb 08 06:32:33 PM UTC 25 663284614 ps
T454 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.4148621879 Feb 08 06:32:32 PM UTC 25 Feb 08 06:32:34 PM UTC 25 16064495 ps
T69 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.1277650943 Feb 08 06:30:30 PM UTC 25 Feb 08 06:32:34 PM UTC 25 28317907994 ps
T305 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.4063372830 Feb 08 06:32:27 PM UTC 25 Feb 08 06:32:35 PM UTC 25 3103923262 ps
T455 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.3248395466 Feb 08 06:32:35 PM UTC 25 Feb 08 06:32:37 PM UTC 25 13565528 ps
T456 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.1014027786 Feb 08 06:32:36 PM UTC 25 Feb 08 06:32:38 PM UTC 25 33847959 ps
T457 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.158344787 Feb 08 06:32:32 PM UTC 25 Feb 08 06:32:38 PM UTC 25 317997255 ps
T458 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.3937853700 Feb 08 06:32:36 PM UTC 25 Feb 08 06:32:39 PM UTC 25 152143937 ps
T51 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.3533315461 Feb 08 06:31:24 PM UTC 25 Feb 08 06:32:39 PM UTC 25 47979187169 ps
T459 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.4178518197 Feb 08 06:32:39 PM UTC 25 Feb 08 06:32:41 PM UTC 25 22665381 ps
T410 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.190647832 Feb 08 06:32:39 PM UTC 25 Feb 08 06:32:41 PM UTC 25 30128015 ps
T70 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.1944598997 Feb 08 06:29:46 PM UTC 25 Feb 08 06:32:43 PM UTC 25 18185659753 ps
T244 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.2503397531 Feb 08 06:32:26 PM UTC 25 Feb 08 06:32:46 PM UTC 25 7973602549 ps
T264 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.561280377 Feb 08 06:32:42 PM UTC 25 Feb 08 06:32:47 PM UTC 25 175144592 ps
T206 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.2230037399 Feb 08 06:30:06 PM UTC 25 Feb 08 06:32:48 PM UTC 25 14196032475 ps
T100 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.6296300 Feb 08 06:31:03 PM UTC 25 Feb 08 06:32:51 PM UTC 25 24880547325 ps
T460 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3513398389 Feb 08 06:32:38 PM UTC 25 Feb 08 06:32:51 PM UTC 25 1003956881 ps
T461 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.4123677284 Feb 08 06:32:50 PM UTC 25 Feb 08 06:32:52 PM UTC 25 34823742 ps
T225 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.4224873685 Feb 08 06:32:48 PM UTC 25 Feb 08 06:32:52 PM UTC 25 403924414 ps
T462 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.2715091607 Feb 08 06:32:48 PM UTC 25 Feb 08 06:32:53 PM UTC 25 159684777 ps
T301 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.3563884011 Feb 08 06:32:47 PM UTC 25 Feb 08 06:32:56 PM UTC 25 1073283617 ps
T207 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.2478074781 Feb 08 06:31:01 PM UTC 25 Feb 08 06:32:56 PM UTC 25 7025086797 ps
T395 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.564339662 Feb 08 06:32:29 PM UTC 25 Feb 08 06:32:57 PM UTC 25 912765092 ps
T208 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.1351587765 Feb 08 06:30:32 PM UTC 25 Feb 08 06:32:58 PM UTC 25 101709158867 ps
T463 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.1623207056 Feb 08 06:32:56 PM UTC 25 Feb 08 06:32:58 PM UTC 25 196389115 ps
T464 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.1939704711 Feb 08 06:32:56 PM UTC 25 Feb 08 06:32:58 PM UTC 25 56544627 ps
T465 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.617888641 Feb 08 06:32:52 PM UTC 25 Feb 08 06:32:58 PM UTC 25 391131129 ps
T466 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.475159129 Feb 08 06:32:21 PM UTC 25 Feb 08 06:32:58 PM UTC 25 5852013045 ps
T467 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.3956646146 Feb 08 06:32:57 PM UTC 25 Feb 08 06:33:00 PM UTC 25 14627093 ps
T468 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.2386443957 Feb 08 06:32:59 PM UTC 25 Feb 08 06:33:02 PM UTC 25 43925676 ps
T298 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2571818880 Feb 08 06:32:15 PM UTC 25 Feb 08 06:33:02 PM UTC 25 1449150608 ps
T412 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.825643463 Feb 08 06:32:59 PM UTC 25 Feb 08 06:33:03 PM UTC 25 132465127 ps
T279 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mailbox.1212608704 Feb 08 06:32:43 PM UTC 25 Feb 08 06:33:03 PM UTC 25 781774988 ps
T71 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.2120173413 Feb 08 06:30:46 PM UTC 25 Feb 08 06:33:05 PM UTC 25 42400417971 ps
T469 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.2173593030 Feb 08 06:32:57 PM UTC 25 Feb 08 06:33:05 PM UTC 25 2790972092 ps
T406 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.2140488287 Feb 08 06:32:21 PM UTC 25 Feb 08 06:33:09 PM UTC 25 7434669621 ps
T268 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.2060952292 Feb 08 06:33:01 PM UTC 25 Feb 08 06:33:09 PM UTC 25 810403214 ps
T470 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.2520059672 Feb 08 06:33:04 PM UTC 25 Feb 08 06:33:10 PM UTC 25 78420610 ps
T471 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.2045886522 Feb 08 06:33:04 PM UTC 25 Feb 08 06:33:10 PM UTC 25 118833645 ps
T52 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.2193442598 Feb 08 06:31:53 PM UTC 25 Feb 08 06:33:11 PM UTC 25 7324037993 ps
T472 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.41842853 Feb 08 06:33:06 PM UTC 25 Feb 08 06:33:13 PM UTC 25 430583623 ps
T101 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.1891666244 Feb 08 06:30:19 PM UTC 25 Feb 08 06:33:13 PM UTC 25 15404609325 ps
T473 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.3072835654 Feb 08 06:33:11 PM UTC 25 Feb 08 06:33:14 PM UTC 25 15110675 ps
T474 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.3571655837 Feb 08 06:33:12 PM UTC 25 Feb 08 06:33:15 PM UTC 25 16817888 ps
T344 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.3115394019 Feb 08 06:33:00 PM UTC 25 Feb 08 06:33:15 PM UTC 25 3836902489 ps
T475 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.442178228 Feb 08 06:33:13 PM UTC 25 Feb 08 06:33:16 PM UTC 25 126251520 ps
T476 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.4051175717 Feb 08 06:33:16 PM UTC 25 Feb 08 06:33:18 PM UTC 25 80949344 ps
T477 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.3278544674 Feb 08 06:33:16 PM UTC 25 Feb 08 06:33:18 PM UTC 25 53664748 ps
T72 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.3289941472 Feb 08 06:31:52 PM UTC 25 Feb 08 06:33:24 PM UTC 25 42855371738 ps
T478 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.982742173 Feb 08 06:33:19 PM UTC 25 Feb 08 06:33:24 PM UTC 25 387166150 ps
T307 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.1696157028 Feb 08 06:33:00 PM UTC 25 Feb 08 06:33:25 PM UTC 25 2622486023 ps
T280 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.1214515823 Feb 08 06:32:42 PM UTC 25 Feb 08 06:33:26 PM UTC 25 7333604376 ps
T399 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.1985030218 Feb 08 06:32:39 PM UTC 25 Feb 08 06:33:26 PM UTC 25 14424743830 ps
T230 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_intercept.3632632940 Feb 08 06:33:19 PM UTC 25 Feb 08 06:33:27 PM UTC 25 524490709 ps
T102 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.4017245314 Feb 08 06:31:54 PM UTC 25 Feb 08 06:33:28 PM UTC 25 4658134691 ps
T327 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.840562465 Feb 08 06:33:17 PM UTC 25 Feb 08 06:33:29 PM UTC 25 707306372 ps
T42 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.2087772338 Feb 08 06:29:53 PM UTC 25 Feb 08 06:33:30 PM UTC 25 18137966922 ps
T274 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.118988812 Feb 08 06:33:03 PM UTC 25 Feb 08 06:33:30 PM UTC 25 16882001055 ps
T345 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_upload.4005726975 Feb 08 06:33:25 PM UTC 25 Feb 08 06:33:31 PM UTC 25 845171237 ps
T284 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.593162211 Feb 08 06:32:40 PM UTC 25 Feb 08 06:33:32 PM UTC 25 33157277340 ps
T479 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_alert_test.2098527206 Feb 08 06:33:32 PM UTC 25 Feb 08 06:33:34 PM UTC 25 47085093 ps
T319 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.1997620796 Feb 08 06:33:03 PM UTC 25 Feb 08 06:33:34 PM UTC 25 1297452382 ps
T117 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.1599087463 Feb 08 06:29:46 PM UTC 25 Feb 08 06:33:34 PM UTC 25 84156070564 ps
T480 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_csb_read.4231959852 Feb 08 06:33:33 PM UTC 25 Feb 08 06:33:35 PM UTC 25 36812300 ps
T481 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_cfg_cmd.3180399757 Feb 08 06:33:26 PM UTC 25 Feb 08 06:33:36 PM UTC 25 3323924372 ps
T482 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mem_parity.1790411472 Feb 08 06:33:35 PM UTC 25 Feb 08 06:33:37 PM UTC 25 34309927 ps
T407 /workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_all.757884679 Feb 08 06:33:15 PM UTC 25 Feb 08 06:33:38 PM UTC 25 5306997939 ps