Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34005	1			T6	6		T9	16		T17	2
auto[SpiFlashAddrCfg]	7605	1			T15	1		T17	8		T18	6
auto[SpiFlashAddr3b]	9274	1			T6	4		T17	4		T18	4
auto[SpiFlashAddr4b]	7733	1			T10	2		T16	2		T17	8

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33050

1

T6

10

T9

16

T15

1

auto[1]

25567

1

T10

2

T18

12

T55

3

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31736

1

T6

6

T9

16

T10

2

auto[1]

26881

1

T6

4

T15

1

T16

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38481	1			T6	6		T9	16		T10	2
values[1]	1112	1			T55	1		T50	3		T62	7
values[2]	1437	1			T18	2		T39	2		T40	1
values[3]	1571	1			T18	4		T40	2		T55	2
values[4]	1501	1			T6	4		T17	2		T18	2
values[5]	1526	1			T65	4		T50	3		T175	2
values[6]	1494	1			T20	2		T91	2		T50	3
values[7]	1479	1			T55	1		T56	2		T121	6
values[8]	10016	1			T16	2		T17	16		T18	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29915

1

T6

10

T9

16

T10

2

auto[1]

28702

1

T15

1

T40

3

T53

7

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55384

1

T6

10

T9

16

T15

1

write

3233

1

T10

2

T20

6

T56

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19446

1

T6

4

T9

16

T16

2

valids[0x1]

39171

1

T6

6

T10

2

T15

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1604	1			T6	2		T17	2		T64	2
internal_process_ops[0x5a]	1555	1			T6	4		T39	2		T55	1
internal_process_ops[0x05]	19848	1			T18	2		T20	72		T55	1
internal_process_ops[0x35]	1604	1			T39	4		T55	1		T50	5
internal_process_ops[0x15]	1525	1			T20	2		T91	2		T50	5
internal_process_ops[0x03]	1127	1			T15	1		T18	2		T55	1
internal_process_ops[0x0b]	1153	1			T55	1		T65	2		T50	5
internal_process_ops[0x3b]	1063	1			T16	2		T40	2		T53	3
internal_process_ops[0x6b]	1100	1			T17	4		T20	2		T40	1
internal_process_ops[0xbb]	1098	1			T39	6		T88	2		T50	3
internal_process_ops[0xeb]	1062	1			T18	2		T20	2		T39	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57077

1

T6

10

T9

16

T15

1

auto[1]

1540

1

T10

2

T56

2

T50

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56255

1

T6

10

T9

16

T10

2

auto[1]

2362

1

T20

4

T60

2

T50

15

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9905

1

T6

6

T9

16

T17

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5551

1

T18

2

T56

2

T61

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2144

1

T17

8

T55

2

T88

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1825

1

T18

6

T56

2

T61

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2606

1

T6

4

T17

4

T20

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2229

1

T18

4

T55

2

T56

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2176

1

T16

2

T17

8

T39

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1839

1

T55

1

T56

2

T62

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

103

1

T60

4

T36

1

T48

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

74

1

T67

2

T36

2

T176

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

85

1

T67

1

T69

1

T176

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

104

1

T67

1

T36

1

T48

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

132

1

T60

6

T63

1

T177

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

116

1

T67

1

T178

2

T69

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

82

1

T36

4

T178

2

T176

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

81

1

T150

1

T69

2

T179

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

112

1

T62

2

T63

3

T67

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

99

1

T62

3

T36

1

T150

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

124

1

T69

4

T166

2

T180

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

89

1

T56

2

T66

2

T58

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

118

1

T20

6

T67

1

T48

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

112

1

T62

2

T67

1

T36

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

102

1

T62

1

T36

1

T48

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

107

1

T10

2

T62

1

T63

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9744

1

T50

93

T51

72

T52

124

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8027

1

T50

96

T51

62

T52

219

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1418

1

T15

1

T40

3

T53

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1407

1

T50

16

T51

19

T52

22

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1882

1

T53

5

T54

3

T50

8

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1748

1

T50

10

T51

24

T52

19

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1496

1

T50

14

T122

4

T51

22

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1387

1

T50

26

T51

11

T52

18

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

106

1

T50

2

T51

1

T86

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

91

1

T95

1

T96

1

T69

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

117

1

T50

5

T51

1

T52

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

98

1

T51

1

T181

2

T49

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

101

1

T52

4

T49

3

T96

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

100

1

T87

1

T181

1

T111

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

96

1

T51

1

T86

1

T87

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

103

1

T50

1

T52

2

T86

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

102

1

T50

2

T51

4

T86

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

95

1

T51

5

T86

5

T111

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

104

1

T50

2

T52

2

T86

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

84

1

T49

6

T37

1

T96

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

116

1

T50

1

T52

3

T86

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

102

1

T86

2

T87

1

T111

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

93

1

T50

2

T52

5

T181

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

85

1

T50

1

T51

1

T52

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3950	1			T6	4		T9	16		T17	2
auto[0]	values[0]	valids[0x1]	14402	1			T6	2		T10	2		T17	2
auto[0]	values[1]	valids[0x1]	592	1			T55	1		T62	7		T63	6
auto[0]	values[2]	valids[0x0]	513	1			T39	2		T55	1		T88	2
auto[0]	values[2]	valids[0x1]	319	1			T18	2		T62	2		T67	5
auto[0]	values[3]	valids[0x0]	582	1			T18	2		T62	1		T63	2
auto[0]	values[3]	valids[0x1]	333	1			T18	2		T55	2		T62	1
auto[0]	values[4]	valids[0x0]	555	1			T18	2		T20	2		T39	6
auto[0]	values[4]	valids[0x1]	307	1			T6	4		T17	2		T60	2
auto[0]	values[5]	valids[0x0]	554	1			T65	2		T62	4		T63	4
auto[0]	values[5]	valids[0x1]	359	1			T65	2		T175	2		T63	2
auto[0]	values[6]	valids[0x0]	518	1			T20	2		T62	1		T63	3
auto[0]	values[6]	valids[0x1]	316	1			T91	2		T110	2		T62	2
auto[0]	values[7]	valids[0x0]	578	1			T121	6		T57	10		T66	2
auto[0]	values[7]	valids[0x1]	318	1			T55	1		T56	2		T62	1
auto[0]	values[8]	valids[0x0]	3685	1			T16	2		T17	14		T20	2
auto[0]	values[8]	valids[0x1]	2034	1			T17	2		T18	2		T55	1
auto[1]	values[0]	valids[0x0]	3847	1			T50	34		T51	49		T52	47
auto[1]	values[0]	valids[0x1]	16282	1			T15	1		T50	192		T122	1
auto[1]	values[1]	valids[0x1]	520	1			T50	3		T51	2		T52	13
auto[1]	values[2]	valids[0x0]	369	1			T40	1		T50	3		T51	15
auto[1]	values[2]	valids[0x1]	236	1			T50	3		T51	2		T52	4
auto[1]	values[3]	valids[0x0]	392	1			T40	2		T53	5		T50	4
auto[1]	values[3]	valids[0x1]	264	1			T50	4		T51	2		T86	5
auto[1]	values[4]	valids[0x0]	377	1			T50	5		T51	5		T52	7
auto[1]	values[4]	valids[0x1]	262	1			T50	4		T51	2		T52	1
auto[1]	values[5]	valids[0x0]	334	1			T50	2		T51	3		T52	3
auto[1]	values[5]	valids[0x1]	279	1			T50	1		T52	2		T86	2
auto[1]	values[6]	valids[0x0]	401	1			T50	2		T51	7		T52	6
auto[1]	values[6]	valids[0x1]	259	1			T50	1		T51	2		T52	2
auto[1]	values[7]	valids[0x0]	327	1			T51	3		T52	1		T86	3
auto[1]	values[7]	valids[0x1]	256	1			T51	4		T52	5		T86	2
auto[1]	values[8]	valids[0x0]	2464	1			T53	2		T54	3		T50	30
auto[1]	values[8]	valids[0x1]	1833	1			T50	13		T122	1		T51	14