Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35316	1			T12	22		T14	10		T17	4
auto[SpiFlashAddrCfg]	7152	1			T11	4		T15	2		T16	2
auto[SpiFlashAddr3b]	8690	1			T11	6		T14	4		T15	4
auto[SpiFlashAddr4b]	7244	1			T14	4		T15	4		T55	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32960

1

T12

22

T14

18

T15

10

auto[1]

25442

1

T11

10

T17

8

T63

4

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30947

1

T11

8

T12

22

T14

8

auto[1]

27455

1

T11

2

T14

10

T15

8

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39891	1			T11	6		T12	22		T14	10
values[1]	1137	1			T14	2		T63	2		T53	4
values[2]	1327	1			T57	2		T76	2		T59	2
values[3]	1316	1			T16	2		T55	2		T61	2
values[4]	1324	1			T14	2		T46	1		T53	2
values[5]	1369	1			T57	2		T46	5		T53	2
values[6]	1373	1			T17	2		T18	2		T56	2
values[7]	1423	1			T11	2		T61	2		T76	2
values[8]	9242	1			T11	2		T14	4		T15	10

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23740

1

T11

10

T12

22

T14

18

auto[1]

34662

1

T49

4

T91

1

T53

173

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55206

1

T11

8

T12

22

T14

18

write

3196

1

T11

2

T58

2

T59

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18433

1

T11

4

T12

22

T14

4

valids[0x1]

39969

1

T11

6

T14

14

T15

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1537	1			T55	2		T61	2		T58	2
internal_process_ops[0x5a]	1551	1			T14	2		T22	2		T63	2
internal_process_ops[0x05]	21433	1			T14	6		T22	4		T55	2
internal_process_ops[0x35]	1532	1			T14	4		T22	4		T112	2
internal_process_ops[0x15]	1561	1			T116	2		T55	2		T63	2
internal_process_ops[0x03]	923	1			T11	2		T56	2		T61	2
internal_process_ops[0x0b]	932	1			T14	2		T15	4		T17	4
internal_process_ops[0x3b]	942	1			T14	2		T15	2		T18	2
internal_process_ops[0x6b]	928	1			T11	2		T46	1		T53	2
internal_process_ops[0xbb]	926	1			T14	2		T18	2		T76	2
internal_process_ops[0xeb]	897	1			T15	4		T56	2		T49	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56845

1

T11

8

T12

22

T14

18

auto[1]

1557

1

T11

2

T53

11

T54

7

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56056

1

T11

10

T12

22

T14

18

auto[1]

2346

1

T61

2

T58

2

T46

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7973

1

T12

22

T14

10

T22

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5339

1

T17

4

T63

2

T96

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1634

1

T15

2

T16

2

T18

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1310

1

T11

4

T46

6

T66

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1872

1

T14

4

T15

4

T16

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1546

1

T11

4

T17

4

T63

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1597

1

T14

4

T15

4

T55

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1303

1

T96

4

T46

4

T66

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

89

1

T46

1

T201

4

T37

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

73

1

T65

1

T51

2

T71

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

70

1

T117

2

T43

4

T202

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

73

1

T70

5

T71

1

T52

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

94

1

T59

2

T201

2

T71

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

56

1

T66

2

T65

2

T69

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

64

1

T69

3

T103

2

T43

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

79

1

T65

1

T69

1

T51

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

104

1

T58

2

T65

3

T51

7

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

45

1

T65

1

T69

3

T51

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

64

1

T69

1

T71

5

T117

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

79

1

T11

2

T95

2

T64

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

74

1

T203

4

T204

2

T72

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

56

1

T52

2

T72

1

T205

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

71

1

T66

3

T65

1

T71

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

75

1

T65

2

T68

2

T51

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12464

1

T53

63

T54

50

T50

12

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8715

1

T53

49

T54

12

T50

10

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1735

1

T49

1

T53

5

T54

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1692

1

T53

15

T54

10

T50

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2268

1

T49

2

T91

1

T53

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2180

1

T53

7

T54

19

T50

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1820

1

T49

1

T53

7

T54

13

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1758

1

T53

7

T54

4

T50

7

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

137

1

T94

1

T206

2

T100

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

115

1

T94

2

T104

1

T39

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

136

1

T53

1

T94

3

T104

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

132

1

T53

5

T54

5

T89

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

126

1

T54

3

T104

2

T206

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

135

1

T54

1

T104

3

T207

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

103

1

T206

2

T208

1

T101

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

124

1

T53

3

T94

2

T39

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

131

1

T53

1

T50

1

T94

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

124

1

T104

2

T206

4

T100

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

129

1

T89

1

T90

1

T206

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

148

1

T50

1

T90

1

T104

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

100

1

T54

1

T104

1

T39

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

138

1

T53

3

T54

1

T90

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

147

1

T54

2

T90

1

T94

7

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

105

1

T104

2

T206

1

T100

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	2967	1			T12	22		T18	2		T61	2
auto[0]	values[0]	valids[0x1]	12461	1			T11	6		T14	10		T17	2
auto[0]	values[1]	valids[0x1]	470	1			T14	2		T63	2		T201	2
auto[0]	values[2]	valids[0x0]	391	1			T57	2		T203	2		T37	1
auto[0]	values[2]	valids[0x1]	219	1			T76	2		T59	2		T67	4
auto[0]	values[3]	valids[0x0]	391	1			T55	2		T46	1		T201	4
auto[0]	values[3]	valids[0x1]	193	1			T16	2		T61	2		T46	2
auto[0]	values[4]	valids[0x0]	402	1			T14	2		T46	1		T209	2
auto[0]	values[4]	valids[0x1]	196	1			T65	2		T69	1		T70	2
auto[0]	values[5]	valids[0x0]	372	1			T57	2		T46	5		T66	2
auto[0]	values[5]	valids[0x1]	235	1			T209	2		T37	1		T65	3
auto[0]	values[6]	valids[0x0]	412	1			T18	2		T56	2		T61	2
auto[0]	values[6]	valids[0x1]	184	1			T17	2		T66	1		T69	1
auto[0]	values[7]	valids[0x0]	403	1			T11	2		T76	2		T112	2
auto[0]	values[7]	valids[0x1]	235	1			T61	2		T210	4		T95	1
auto[0]	values[8]	valids[0x0]	2614	1			T11	2		T14	2		T15	6
auto[0]	values[8]	valids[0x1]	1595	1			T14	2		T15	4		T17	4
auto[1]	values[0]	valids[0x0]	4822	1			T53	24		T54	35		T50	14
auto[1]	values[0]	valids[0x1]	19641	1			T49	1		T53	111		T54	52
auto[1]	values[1]	valids[0x1]	667	1			T53	4		T50	1		T94	6
auto[1]	values[2]	valids[0x0]	445	1			T53	2		T54	2		T50	1
auto[1]	values[2]	valids[0x1]	272	1			T53	1		T54	1		T90	3
auto[1]	values[3]	valids[0x0]	415	1			T54	4		T50	3		T211	1
auto[1]	values[3]	valids[0x1]	317	1			T53	1		T54	2		T50	6
auto[1]	values[4]	valids[0x0]	432	1			T53	2		T50	3		T90	2
auto[1]	values[4]	valids[0x1]	294	1			T212	2		T94	2		T104	2
auto[1]	values[5]	valids[0x0]	446	1			T53	1		T54	2		T213	1
auto[1]	values[5]	valids[0x1]	316	1			T53	1		T54	1		T94	6
auto[1]	values[6]	valids[0x0]	464	1			T54	3		T50	6		T89	2
auto[1]	values[6]	valids[0x1]	313	1			T54	1		T94	1		T104	5
auto[1]	values[7]	valids[0x0]	494	1			T53	2		T54	7		T50	2
auto[1]	values[7]	valids[0x1]	291	1			T53	2		T50	2		T94	1
auto[1]	values[8]	valids[0x0]	2963	1			T49	3		T53	12		T54	22
auto[1]	values[8]	valids[0x1]	2070	1			T91	1		T53	10		T54	8