Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3000209

1

T11

1

T12

338

T14

3067

auto[1]

31462

1

T61

7

T58

12

T46

6

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

790460

1

T11

1

T12

338

T14

765

auto[1]

2241211

1

T14

2302

T55

18

T61

7

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	573485	1			T11	1		T14	2176		T15	102
auto[524288:1048575]	385326	1			T12	245		T14	80		T15	68
auto[1048576:1572863]	350179	1			T14	48		T15	55		T22	480
auto[1572864:2097151]	357684	1			T14	135		T15	67		T76	445
auto[2097152:2621439]	372030	1			T12	53		T14	185		T22	3
auto[2621440:3145727]	305569	1			T12	36		T14	337		T15	141
auto[3145728:3670015]	369328	1			T14	103		T15	62		T56	92
auto[3670016:4194303]	318070	1			T12	4		T14	3		T22	338

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2276680

1

T11

1

T12

308

T14

2339

auto[1]

754991

1

T12

30

T14

728

T15

476

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2574802

1

T11

1

T12

4

T14

3067

auto[1]

456869

1

T12

334

T60

64

T46

9

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	160575	1			T11	1		T14	129		T15	102
auto[0]	auto[0]	auto[0:524287]	auto[1]	339463	1			T14	2047		T55	18		T61	2
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	101883	1			T14	80		T15	68		T56	97
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	220591	1			T46	1		T54	8		T37	2979
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	69628	1			T14	48		T15	55		T22	480
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	207219	1			T53	1		T54	2		T66	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	78329	1			T14	78		T15	67		T76	445
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	231407	1			T14	57		T53	257		T54	439
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	113160	1			T14	146		T22	3		T56	57
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	198218	1			T14	39		T46	4		T53	256
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	78832	1			T14	201		T15	141		T76	2309
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	190592	1			T14	136		T46	256		T53	2911
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	108683	1			T14	81		T15	62		T56	92
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	195960	1			T14	22		T53	2		T54	756
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	63758	1			T12	4		T14	2		T22	338
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	190609	1			T14	1		T54	512		T50	5
auto[0]	auto[1]	auto[0:524287]	auto[0]	2601	1			T53	6		T94	1		T65	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	67451	1			T53	2		T70	1		T206	2366
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1673	1			T12	245		T60	11		T54	10
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	57353	1			T54	223		T207	512		T208	1578
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	817	1			T60	1		T50	4		T89	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	68719	1			T53	128		T94	256		T39	512
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	496	1			T53	1		T50	2		T37	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	42730	1			T53	256		T37	3		T65	2412
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1321	1			T12	53		T46	3		T53	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	54349	1			T46	1		T94	2794		T104	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1761	1			T12	36		T60	52		T46	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	30750	1			T53	2		T208	6		T42	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1822	1			T54	29		T94	2		T39	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	58822	1			T54	628		T39	3		T69	2331
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1013	1			T54	3		T90	8		T37	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	59624	1			T53	516		T90	517		T94	2353
auto[1]	auto[0]	auto[0:524287]	auto[0]	457	1			T61	2		T58	2		T53	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2240	1			T61	5		T58	10		T53	3
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	421	1			T46	1		T37	1		T94	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2666	1			T46	1		T37	7		T94	10
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	427	1			T54	7		T66	1		T90	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2503	1			T66	23		T90	2		T37	6
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	396	1			T53	1		T54	7		T66	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3651	1			T53	34		T66	28		T104	11
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	414	1			T54	12		T89	1		T94	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	4101	1			T54	5		T89	7		T94	31
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	418	1			T54	5		T94	2		T104	19
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2311	1			T94	2		T65	10		T51	61
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	449	1			T53	2		T54	5		T95	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3101	1			T53	3		T54	15		T95	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	290	1			T54	2		T50	2		T66	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2050	1			T66	1		T37	3		T94	37
auto[1]	auto[1]	auto[0:524287]	auto[0]	127	1			T53	2		T70	1		T298	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	571	1			T53	13		T70	6		T103	24
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	104	1			T208	2		T298	1		T72	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	635	1			T208	13		T298	1		T72	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	111	1			T52	3		T102	1		T42	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	755	1			T52	90		T42	4		T261	7
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	103	1			T51	1		T70	2		T208	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	572	1			T51	44		T70	30		T208	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	86	1			T46	1		T65	1		T51	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	381	1			T46	3		T51	15		T71	5
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	110	1			T53	2		T208	1		T42	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	795	1			T53	12		T208	2		T42	4
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	90	1			T39	1		T299	12		T293	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	401	1			T299	71		T293	44		T77	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	105	1			T90	1		T206	1		T100	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	621	1			T90	1		T206	1		T100	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1801142	1			T11	1		T12	1		T14	2339
auto[0]	auto[0]	auto[1]	747765	1			T12	3		T14	728		T15	476
auto[0]	auto[1]	auto[0]	444696	1			T12	307		T60	60		T46	5
auto[0]	auto[1]	auto[1]	6606	1			T12	27		T60	4		T53	1
auto[1]	auto[0]	auto[0]	25403	1			T61	7		T58	12		T46	2
auto[1]	auto[0]	auto[1]	492	1			T54	2		T50	1		T66	1
auto[1]	auto[1]	auto[0]	5439	1			T46	4		T53	29		T90	2
auto[1]	auto[1]	auto[1]	128	1			T70	1		T208	1		T42	2