Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3367976

1

T6

1

T9

530

T10

1

auto[1]

31913

1

T20

72

T60

39

T50

141

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1007182

1

T6

1

T9

530

T10

1

auto[1]

2392707

1

T20

82

T55

768

T60

5471

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	636026	1			T6	1		T9	2		T10	1
auto[524288:1048575]	448616	1			T9	89		T15	492		T39	1041
auto[1048576:1572863]	424504	1			T15	283		T16	1		T39	160
auto[1572864:2097151]	366733	1			T9	158		T16	1111		T39	2142
auto[2097152:2621439]	349894	1			T9	107		T16	1111		T19	6
auto[2621440:3145727]	377453	1			T9	167		T19	206		T55	770
auto[3145728:3670015]	390194	1			T15	1219		T16	3		T39	12
auto[3670016:4194303]	406469	1			T9	7		T55	1		T88	1044

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2427078

1

T6

1

T9

211

T10

1

auto[1]

972811

1

T9

319

T15

2404

T16

3040

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2944737

1

T6

1

T9

530

T10

1

auto[1]

455152

1

T19

4

T55

770

T92

71

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	203979	1			T6	1		T9	2		T10	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	361495	1			T20	14		T60	5434		T91	8
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	123802	1			T9	89		T15	492		T39	1041
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	257707	1			T50	130		T62	2502		T63	3269
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	98145	1			T15	283		T16	1		T39	160
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	265170	1			T62	1		T51	1438		T52	2241
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	100738	1			T9	158		T16	1111		T39	2142
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	202771	1			T50	3098		T51	1031		T67	3166
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	101056	1			T9	107		T16	1111		T19	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	193545	1			T50	5		T62	256		T51	257
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	109284	1			T9	167		T19	206		T88	286
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	205810	1			T50	258		T63	679		T51	260
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	105419	1			T15	1219		T16	3		T39	12
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	221123	1			T50	641		T62	133		T63	513
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	153826	1			T9	7		T55	1		T88	1044
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	214009	1			T50	2711		T51	775		T67	640
auto[0]	auto[1]	auto[0:524287]	auto[0]	856	1			T62	8		T52	3		T86	6
auto[0]	auto[1]	auto[0:524287]	auto[1]	65925	1			T50	512		T62	1		T52	1289
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	856	1			T92	3		T63	2		T51	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	61466	1			T63	256		T181	1		T48	24
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	646	1			T52	1		T67	1		T86	12
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	54609	1			T67	2544		T86	256		T49	259
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	574	1			T51	1		T52	1		T86	65
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	59936	1			T51	1050		T52	256		T86	2401
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	564	1			T19	4		T92	4		T50	10
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	51615	1			T50	3367		T51	773		T52	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1779	1			T55	2		T92	50		T62	9
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	56736	1			T55	768		T62	259		T63	256
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	872	1			T63	1		T51	1		T86	10
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	58814	1			T63	257		T37	161		T301	2579
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	543	1			T92	14		T51	1		T52	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	34306	1			T52	787		T86	259		T181	384
auto[1]	auto[0]	auto[0:524287]	auto[0]	470	1			T20	4		T60	2		T50	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2683	1			T20	68		T60	37		T50	3
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	405	1			T50	2		T63	1		T51	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3759	1			T50	6		T63	2		T51	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	466	1			T62	1		T52	4		T86	16
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	4671	1			T52	50		T87	23		T36	5
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	369	1			T50	4		T51	2		T86	9
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1794	1			T50	76		T51	7		T86	14
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	477	1			T51	1		T52	1		T67	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2054	1			T51	1		T52	34		T67	10
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	506	1			T50	2		T63	1		T67	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2938	1			T50	10		T67	27		T181	115
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	473	1			T50	1		T62	5		T63	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2758	1			T62	9		T63	5		T52	95
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	404	1			T50	1		T51	4		T36	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2631	1			T50	14		T51	6		T36	12
auto[1]	auto[1]	auto[0:524287]	auto[0]	97	1			T62	1		T37	1		T96	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	521	1			T62	10		T37	3		T96	11
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	88	1			T181	1		T318	2		T321	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	533	1			T181	36		T318	7		T321	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	75	1			T150	1		T301	1		T95	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	722	1			T150	5		T301	2		T95	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	70	1			T86	6		T49	1		T69	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	481	1			T49	35		T69	10		T316	6
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	63	1			T50	3		T51	2		T52	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	520	1			T50	17		T51	8		T52	51
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	78	1			T62	1		T49	1		T150	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	322	1			T62	4		T49	5		T150	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	114	1			T63	1		T96	4		T112	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	621	1			T63	2		T96	8		T112	326
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	88	1			T86	7		T113	3		T318	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	662	1			T318	6		T317	2		T322	41

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1947548	1			T6	1		T9	211		T10	1
auto[0]	auto[0]	auto[1]	970331	1			T9	319		T15	2404		T16	3040
auto[0]	auto[1]	auto[0]	448385	1			T19	4		T55	770		T92	53
auto[0]	auto[1]	auto[1]	1712	1			T92	18		T181	1		T96	4
auto[1]	auto[0]	auto[0]	26211	1			T20	72		T60	39		T50	121
auto[1]	auto[0]	auto[1]	647	1			T52	3		T67	3		T86	11
auto[1]	auto[1]	auto[0]	4934	1			T50	20		T62	16		T63	2
auto[1]	auto[1]	auto[1]	121	1			T63	1		T86	2		T181	1