Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2703498	1			T1	1		T2	1		T3	1
all_pins[1]	2703498	1			T1	1		T2	1		T3	1
all_pins[2]	2703498	1			T1	1		T2	1		T3	1
all_pins[3]	2703498	1			T1	1		T2	1		T3	1
all_pins[4]	2703498	1			T1	1		T2	1		T3	1
all_pins[5]	2703498	1			T1	1		T2	1		T3	1
all_pins[6]	2703498	1			T1	1		T2	1		T3	1
all_pins[7]	2703498	1			T1	1		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21623981	1			T1	8		T2	8		T3	8
values[0x1]	4003	1			T22	23		T23	28		T33	5
transitions[0x0=>0x1]	3483	1			T22	18		T23	23		T33	3
transitions[0x1=>0x0]	3496	1			T22	18		T23	23		T33	3

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2703064	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	434	1			T22	1		T23	6		T36	2
all_pins[0]	transitions[0x0=>0x1]	274	1			T22	1		T23	6		T36	2
all_pins[0]	transitions[0x1=>0x0]	307	1			T22	2		T23	1		T37	2
all_pins[1]	values[0x0]	2703031	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	467	1			T22	2		T23	1		T37	51
all_pins[1]	transitions[0x0=>0x1]	365	1			T22	2		T23	1		T37	50
all_pins[1]	transitions[0x1=>0x0]	156	1			T22	4		T23	4		T36	3
all_pins[2]	values[0x0]	2703240	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	258	1			T22	4		T23	4		T36	3
all_pins[2]	transitions[0x0=>0x1]	210	1			T22	4		T23	2		T36	2
all_pins[2]	transitions[0x1=>0x0]	102	1			T22	1		T23	3		T37	2
all_pins[3]	values[0x0]	2703348	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	150	1			T22	1		T23	5		T36	1
all_pins[3]	transitions[0x0=>0x1]	113	1			T22	1		T23	3		T37	1
all_pins[3]	transitions[0x1=>0x0]	136	1			T22	2		T23	4		T33	2
all_pins[4]	values[0x0]	2703325	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	173	1			T22	2		T23	6		T33	2
all_pins[4]	transitions[0x0=>0x1]	136	1			T22	2		T23	6		T33	1
all_pins[4]	transitions[0x1=>0x0]	127	1			T22	5		T23	4		T37	2
all_pins[5]	values[0x0]	2703334	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	164	1			T22	5		T23	4		T33	1
all_pins[5]	transitions[0x0=>0x1]	120	1			T22	3		T23	3		T37	2
all_pins[5]	transitions[0x1=>0x0]	2146	1			T22	4		T23	1		T33	1
all_pins[6]	values[0x0]	2701308	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	2190	1			T22	6		T23	2		T33	2
all_pins[6]	transitions[0x0=>0x1]	2147	1			T22	4		T23	2		T33	2
all_pins[6]	transitions[0x1=>0x0]	124	1			T37	5		T173	4		T174	1
all_pins[7]	values[0x0]	2703331	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	167	1			T22	2		T36	1		T37	7
all_pins[7]	transitions[0x0=>0x1]	118	1			T22	1		T37	5		T173	3
all_pins[7]	transitions[0x1=>0x0]	398	1			T23	6		T36	2		T37	69