Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2362415	1			T1	1		T2	1		T4	1
all_pins[1]	2362415	1			T1	1		T2	1		T4	1
all_pins[2]	2362415	1			T1	1		T2	1		T4	1
all_pins[3]	2362415	1			T1	1		T2	1		T4	1
all_pins[4]	2362415	1			T1	1		T2	1		T4	1
all_pins[5]	2362415	1			T1	1		T2	1		T4	1
all_pins[6]	2362415	1			T1	1		T2	1		T4	1
all_pins[7]	2362415	1			T1	1		T2	1		T4	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	18789104	1			T1	8		T2	8		T4	8
values[0x1]	110216	1			T24	20		T35	12		T38	23
transitions[0x0=>0x1]	109024	1			T24	10		T35	10		T38	21
transitions[0x1=>0x0]	109033	1			T24	10		T35	10		T38	21

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2361902	1			T1	1		T2	1		T4	1
all_pins[0]	values[0x1]	513	1			T24	5		T35	2		T38	3
all_pins[0]	transitions[0x0=>0x1]	414	1			T24	2		T35	2		T38	2
all_pins[0]	transitions[0x1=>0x0]	162	1			T35	1		T38	6		T183	2
all_pins[1]	values[0x0]	2362154	1			T1	1		T2	1		T4	1
all_pins[1]	values[0x1]	261	1			T24	3		T35	1		T38	7
all_pins[1]	transitions[0x0=>0x1]	210	1			T24	2		T35	1		T38	7
all_pins[1]	transitions[0x1=>0x0]	222	1			T24	3		T35	1		T39	1
all_pins[2]	values[0x0]	2362142	1			T1	1		T2	1		T4	1
all_pins[2]	values[0x1]	273	1			T24	4		T35	1		T39	1
all_pins[2]	transitions[0x0=>0x1]	226	1			T24	3		T39	1		T183	6
all_pins[2]	transitions[0x1=>0x0]	130	1			T24	1		T35	2		T38	4
all_pins[3]	values[0x0]	2362238	1			T1	1		T2	1		T4	1
all_pins[3]	values[0x1]	177	1			T24	2		T35	3		T38	4
all_pins[3]	transitions[0x0=>0x1]	122	1			T24	1		T35	3		T38	4
all_pins[3]	transitions[0x1=>0x0]	141	1			T24	1		T35	1		T38	4
all_pins[4]	values[0x0]	2362219	1			T1	1		T2	1		T4	1
all_pins[4]	values[0x1]	196	1			T24	2		T35	1		T38	4
all_pins[4]	transitions[0x0=>0x1]	161	1			T24	1		T38	3		T183	4
all_pins[4]	transitions[0x1=>0x0]	1526	1			T35	1		T38	1		T39	301
all_pins[5]	values[0x0]	2360854	1			T1	1		T2	1		T4	1
all_pins[5]	values[0x1]	1561	1			T24	1		T35	2		T38	2
all_pins[5]	transitions[0x0=>0x1]	743	1			T24	1		T35	2		T38	2
all_pins[5]	transitions[0x1=>0x0]	106260	1			T24	1		T39	1983		T183	4
all_pins[6]	values[0x0]	2255337	1			T1	1		T2	1		T4	1
all_pins[6]	values[0x1]	107078	1			T24	1		T39	2278		T183	4
all_pins[6]	transitions[0x0=>0x1]	107039	1			T39	2278		T183	3		T100	1
all_pins[6]	transitions[0x1=>0x0]	118	1			T24	1		T35	2		T38	3
all_pins[7]	values[0x0]	2362258	1			T1	1		T2	1		T4	1
all_pins[7]	values[0x1]	157	1			T24	2		T35	2		T38	3
all_pins[7]	transitions[0x0=>0x1]	109	1			T35	2		T38	3		T183	5
all_pins[7]	transitions[0x1=>0x0]	474	1			T24	3		T35	2		T38	3