Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13667

1

T12

22

T14

18

T15

10

auto[1]

10073

1

T11

10

T17

8

T63

4

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2225	1			T251	6		T210	12		T37	20
values[1]	3378	1			T12	22		T201	14		T272	22
values[2]	3436	1			T63	4		T209	8		T66	46
values[3]	2640	1			T55	10		T56	8		T61	27
values[4]	3099	1			T18	6		T22	10		T62	2
values[5]	3004	1			T15	10		T16	4		T57	6
values[6]	2676	1			T11	10		T14	18		T116	2
values[7]	3282	1			T17	8		T112	10		T300	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2991	1			T11	10		T22	10		T55	10
values[1]	3129	1			T17	8		T209	8		T272	22
values[2]	2931	1			T14	18		T62	2		T226	2
values[3]	2668	1			T16	4		T18	6		T56	8
values[4]	3508	1			T15	10		T57	6		T96	12
values[5]	2678	1			T63	4		T61	27		T60	8
values[6]	2470	1			T59	18		T247	2		T203	6
values[7]	3365	1			T12	22		T116	2		T201	14

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	201	1			T103	28		T233	12		T162	11
auto[0]	values[0]	values[1]	213	1			T37	16		T95	13		T117	5
auto[0]	values[0]	values[2]	142	1			T301	10		T52	13		T43	4
auto[0]	values[0]	values[3]	171	1			T242	6		T302	14		T303	12
auto[0]	values[0]	values[4]	82	1			T100	9		T246	23		T152	17
auto[0]	values[0]	values[5]	175	1			T251	6		T52	12		T249	26
auto[0]	values[0]	values[6]	123	1			T266	12		T43	12		T202	12
auto[0]	values[0]	values[7]	202	1			T71	13		T72	56		T230	26
auto[0]	values[1]	values[0]	310	1			T227	2		T69	26		T51	13
auto[0]	values[1]	values[1]	181	1			T272	22		T292	20		T304	4
auto[0]	values[1]	values[2]	193	1			T52	10		T287	46		T235	15
auto[0]	values[1]	values[3]	280	1			T37	32		T51	13		T71	61
auto[0]	values[1]	values[4]	212	1			T69	10		T305	4		T286	6
auto[0]	values[1]	values[5]	289	1			T244	8		T205	12		T202	10
auto[0]	values[1]	values[6]	127	1			T306	4		T307	14		T308	14
auto[0]	values[1]	values[7]	386	1			T12	22		T201	14		T66	46
auto[0]	values[2]	values[0]	173	1			T43	67		T234	15		T162	17
auto[0]	values[2]	values[1]	469	1			T209	8		T113	12		T65	16
auto[0]	values[2]	values[2]	199	1			T66	14		T95	30		T309	12
auto[0]	values[2]	values[3]	116	1			T277	20		T278	14		T279	14
auto[0]	values[2]	values[4]	298	1			T71	33		T103	53		T310	16
auto[0]	values[2]	values[5]	350	1			T51	53		T250	139		T243	11
auto[0]	values[2]	values[6]	123	1			T52	13		T43	23		T256	10
auto[0]	values[2]	values[7]	323	1			T71	7		T72	14		T88	18
auto[0]	values[3]	values[0]	229	1			T55	10		T65	8		T248	13
auto[0]	values[3]	values[1]	158	1			T275	8		T65	8		T71	62
auto[0]	values[3]	values[2]	219	1			T311	2		T264	2		T309	10
auto[0]	values[3]	values[3]	190	1			T56	8		T51	12		T70	16
auto[0]	values[3]	values[4]	351	1			T312	2		T287	29		T313	6
auto[0]	values[3]	values[5]	96	1			T61	27		T78	11		T241	11
auto[0]	values[3]	values[6]	181	1			T59	18		T100	15		T72	16
auto[0]	values[3]	values[7]	192	1			T314	8		T78	15		T254	8
auto[0]	values[4]	values[0]	221	1			T22	10		T259	8		T69	4
auto[0]	values[4]	values[1]	238	1			T291	16		T315	20		T232	11
auto[0]	values[4]	values[2]	200	1			T62	2		T51	47		T117	13
auto[0]	values[4]	values[3]	275	1			T18	6		T234	12		T152	9
auto[0]	values[4]	values[4]	338	1			T51	4		T71	12		T316	2
auto[0]	values[4]	values[5]	143	1			T234	15		T317	12		T240	18
auto[0]	values[4]	values[6]	175	1			T318	6		T234	28		T157	6
auto[0]	values[4]	values[7]	177	1			T319	6		T103	11		T320	12
auto[0]	values[5]	values[0]	186	1			T76	12		T115	8		T52	8
auto[0]	values[5]	values[1]	229	1			T204	16		T321	6		T52	9
auto[0]	values[5]	values[2]	300	1			T226	2		T67	24		T95	9
auto[0]	values[5]	values[3]	188	1			T16	4		T58	18		T46	9
auto[0]	values[5]	values[4]	186	1			T15	10		T57	6		T103	78
auto[0]	values[5]	values[5]	262	1			T60	8		T70	10		T103	17
auto[0]	values[5]	values[6]	305	1			T247	2		T203	6		T260	4
auto[0]	values[5]	values[7]	103	1			T205	6		T322	4		T231	6
auto[0]	values[6]	values[0]	206	1			T323	4		T71	87		T252	9
auto[0]	values[6]	values[1]	218	1			T52	36		T284	18		T233	12
auto[0]	values[6]	values[2]	188	1			T14	18		T262	12		T65	14
auto[0]	values[6]	values[3]	128	1			T51	46		T248	23		T249	11
auto[0]	values[6]	values[4]	148	1			T70	18		T184	9		T324	10
auto[0]	values[6]	values[5]	162	1			T46	12		T255	18		T325	2
auto[0]	values[6]	values[6]	257	1			T71	2		T326	20		T202	14
auto[0]	values[6]	values[7]	234	1			T116	2		T71	14		T103	51
auto[0]	values[7]	values[0]	323	1			T112	10		T65	9		T327	10
auto[0]	values[7]	values[1]	121	1			T228	12		T235	13		T271	13
auto[0]	values[7]	values[2]	217	1			T328	10		T69	13		T70	7
auto[0]	values[7]	values[3]	206	1			T65	23		T234	7		T329	8
auto[0]	values[7]	values[4]	173	1			T225	22		T103	13		T271	10
auto[0]	values[7]	values[5]	168	1			T69	7		T248	20		T43	11
auto[0]	values[7]	values[6]	152	1			T300	4		T103	15		T202	12
auto[0]	values[7]	values[7]	286	1			T65	9		T330	2		T51	33
auto[1]	values[0]	values[0]	135	1			T103	5		T233	8		T162	54
auto[1]	values[0]	values[1]	164	1			T37	4		T95	7		T117	15
auto[1]	values[0]	values[2]	109	1			T52	49		T43	16		T152	12
auto[1]	values[0]	values[3]	87	1			T302	6		T239	8		T331	6
auto[1]	values[0]	values[4]	76	1			T210	12		T100	11		T332	24
auto[1]	values[0]	values[5]	66	1			T52	8		T249	6		T232	12
auto[1]	values[0]	values[6]	146	1			T43	23		T202	10		T333	8
auto[1]	values[0]	values[7]	133	1			T71	30		T72	7		T228	5
auto[1]	values[1]	values[0]	120	1			T69	14		T51	10		T202	5
auto[1]	values[1]	values[1]	337	1			T162	26		T241	75		T334	51
auto[1]	values[1]	values[2]	223	1			T52	18		T287	5		T235	118
auto[1]	values[1]	values[3]	191	1			T37	7		T51	7		T71	7
auto[1]	values[1]	values[4]	111	1			T69	10		T335	6		T336	12
auto[1]	values[1]	values[5]	114	1			T245	20		T205	8		T202	10
auto[1]	values[1]	values[6]	98	1			T285	16		T337	13		T162	9
auto[1]	values[1]	values[7]	206	1			T66	5		T52	8		T72	94
auto[1]	values[2]	values[0]	76	1			T43	7		T234	5		T162	11
auto[1]	values[2]	values[1]	256	1			T64	12		T65	4		T52	12
auto[1]	values[2]	values[2]	207	1			T66	32		T95	7		T309	14
auto[1]	values[2]	values[3]	79	1			T338	2		T256	8		T252	22
auto[1]	values[2]	values[4]	116	1			T71	11		T103	9		T335	3
auto[1]	values[2]	values[5]	291	1			T63	4		T51	12		T243	9
auto[1]	values[2]	values[6]	70	1			T52	7		T43	8		T256	10
auto[1]	values[2]	values[7]	290	1			T71	81		T72	6		T43	4
auto[1]	values[3]	values[0]	90	1			T65	18		T248	8		T336	7
auto[1]	values[3]	values[1]	106	1			T65	21		T71	7		T184	7
auto[1]	values[3]	values[2]	212	1			T309	12		T235	32		T337	11
auto[1]	values[3]	values[3]	155	1			T51	8		T70	4		T72	55
auto[1]	values[3]	values[4]	185	1			T287	7		T152	39		T317	11
auto[1]	values[3]	values[5]	78	1			T78	9		T241	9		T339	37
auto[1]	values[3]	values[6]	100	1			T100	5		T72	4		T228	7
auto[1]	values[3]	values[7]	98	1			T78	5		T335	3		T238	23
auto[1]	values[4]	values[0]	101	1			T69	16		T103	6		T184	12
auto[1]	values[4]	values[1]	109	1			T232	12		T238	18		T187	6
auto[1]	values[4]	values[2]	129	1			T51	10		T117	7		T202	11
auto[1]	values[4]	values[3]	116	1			T234	12		T152	14		T340	18
auto[1]	values[4]	values[4]	285	1			T96	12		T51	16		T71	8
auto[1]	values[4]	values[5]	107	1			T234	5		T317	11		T341	4
auto[1]	values[4]	values[6]	119	1			T234	9		T249	46		T235	9
auto[1]	values[4]	values[7]	366	1			T103	77		T152	9		T317	11
auto[1]	values[5]	values[0]	51	1			T52	12		T234	12		T342	4
auto[1]	values[5]	values[1]	139	1			T52	62		T152	4		T271	10
auto[1]	values[5]	values[2]	178	1			T95	11		T70	10		T117	11
auto[1]	values[5]	values[3]	267	1			T46	11		T65	10		T103	10
auto[1]	values[5]	values[4]	198	1			T103	13		T317	48		T343	2
auto[1]	values[5]	values[5]	123	1			T70	94		T103	3		T235	10
auto[1]	values[5]	values[6]	206	1			T65	7		T52	9		T184	4
auto[1]	values[5]	values[7]	83	1			T195	8		T205	14		T234	11
auto[1]	values[6]	values[0]	338	1			T11	10		T267	14		T71	8
auto[1]	values[6]	values[1]	44	1			T52	4		T233	8		T78	5
auto[1]	values[6]	values[2]	97	1			T65	7		T68	4		T43	13
auto[1]	values[6]	values[3]	116	1			T51	54		T248	7		T249	9
auto[1]	values[6]	values[4]	161	1			T70	9		T236	10		T184	16
auto[1]	values[6]	values[5]	118	1			T46	14		T228	18		T270	13
auto[1]	values[6]	values[6]	128	1			T71	18		T202	9		T287	11
auto[1]	values[6]	values[7]	133	1			T71	6		T280	20		T103	14
auto[1]	values[7]	values[0]	231	1			T65	11		T117	6		T103	11
auto[1]	values[7]	values[1]	147	1			T17	8		T344	10		T228	8
auto[1]	values[7]	values[2]	118	1			T69	7		T70	13		T317	11
auto[1]	values[7]	values[3]	103	1			T65	8		T234	14		T271	8
auto[1]	values[7]	values[4]	588	1			T103	254		T271	10		T78	25
auto[1]	values[7]	values[5]	136	1			T69	13		T248	20		T43	9
auto[1]	values[7]	values[6]	160	1			T103	29		T202	10		T243	9
auto[1]	values[7]	values[7]	153	1			T65	11		T51	5		T70	44