Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17697

1

T6

10

T9

16

T16

2

auto[1]

12218

1

T10

2

T18

12

T55

3

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3388	1			T6	10		T18	12		T65	18
values[1]	4304	1			T9	16		T10	2		T106	6
values[2]	3878	1			T17	22		T19	4		T88	8
values[3]	3451	1			T110	8		T175	2		T67	31
values[4]	3569	1			T16	2		T60	55		T61	10
values[5]	3632	1			T39	14		T62	23		T67	20
values[6]	4251	1			T56	10		T91	10		T92	24
values[7]	3442	1			T20	86		T55	20		T64	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3364	1			T175	2		T90	4		T232	2
values[1]	3632	1			T62	20		T67	48		T237	2
values[2]	3410	1			T16	2		T183	4		T121	28
values[3]	4520	1			T18	12		T20	86		T88	8
values[4]	3605	1			T10	2		T56	10		T92	24
values[5]	3392	1			T6	10		T9	16		T62	56
values[6]	3874	1			T55	20		T61	10		T110	8
values[7]	4118	1			T17	22		T19	4		T39	14

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	130	1			T184	10		T200	24		T313	8
auto[0]	values[0]	values[1]	269	1			T237	2		T193	12		T184	15
auto[0]	values[0]	values[2]	294	1			T36	9		T178	13		T176	11
auto[0]	values[0]	values[3]	355	1			T69	41		T207	12		T255	13
auto[0]	values[0]	values[4]	150	1			T65	18		T182	4		T113	9
auto[0]	values[0]	values[5]	310	1			T6	10		T109	6		T150	22
auto[0]	values[0]	values[6]	288	1			T179	10		T180	11		T324	12
auto[0]	values[0]	values[7]	165	1			T325	18		T200	8		T326	12
auto[0]	values[1]	values[0]	268	1			T69	27		T236	4		T180	10
auto[0]	values[1]	values[1]	287	1			T67	39		T150	15		T178	12
auto[0]	values[1]	values[2]	455	1			T172	10		T48	21		T214	9
auto[0]	values[1]	values[3]	432	1			T234	20		T200	6		T97	11
auto[0]	values[1]	values[4]	345	1			T63	12		T48	49		T244	4
auto[0]	values[1]	values[5]	243	1			T9	16		T62	26		T180	12
auto[0]	values[1]	values[6]	304	1			T191	4		T216	14		T327	20
auto[0]	values[1]	values[7]	489	1			T106	6		T216	13		T185	21
auto[0]	values[2]	values[0]	326	1			T48	24		T178	17		T205	18
auto[0]	values[2]	values[1]	314	1			T150	7		T227	4		T200	10
auto[0]	values[2]	values[2]	176	1			T121	28		T233	6		T243	14
auto[0]	values[2]	values[3]	193	1			T88	8		T179	16		T207	12
auto[0]	values[2]	values[4]	154	1			T48	14		T239	20		T207	9
auto[0]	values[2]	values[5]	292	1			T36	14		T150	17		T216	8
auto[0]	values[2]	values[6]	304	1			T63	14		T246	8		T176	8
auto[0]	values[2]	values[7]	348	1			T17	22		T19	4		T48	11
auto[0]	values[3]	values[0]	168	1			T175	2		T185	10		T220	13
auto[0]	values[3]	values[1]	323	1			T176	15		T180	16		T229	12
auto[0]	values[3]	values[2]	259	1			T328	8		T180	16		T220	10
auto[0]	values[3]	values[3]	367	1			T36	15		T329	8		T208	16
auto[0]	values[3]	values[4]	225	1			T67	9		T178	21		T176	27
auto[0]	values[3]	values[5]	159	1			T69	8		T113	13		T216	27
auto[0]	values[3]	values[6]	281	1			T110	8		T180	12		T97	38
auto[0]	values[3]	values[7]	276	1			T48	11		T178	18		T69	13
auto[0]	values[4]	values[0]	198	1			T200	12		T218	11		T230	11
auto[0]	values[4]	values[1]	151	1			T36	8		T180	4		T97	10
auto[0]	values[4]	values[2]	211	1			T16	2		T178	21		T330	18
auto[0]	values[4]	values[3]	294	1			T150	15		T69	28		T252	9
auto[0]	values[4]	values[4]	459	1			T209	4		T235	20		T224	4
auto[0]	values[4]	values[5]	303	1			T36	8		T331	24		T219	15
auto[0]	values[4]	values[6]	192	1			T97	13		T167	12		T275	7
auto[0]	values[4]	values[7]	282	1			T60	55		T57	24		T67	16
auto[0]	values[5]	values[0]	178	1			T150	10		T69	8		T180	9
auto[0]	values[5]	values[1]	326	1			T69	15		T314	2		T216	15
auto[0]	values[5]	values[2]	235	1			T36	74		T204	6		T208	12
auto[0]	values[5]	values[3]	352	1			T179	13		T180	14		T332	6
auto[0]	values[5]	values[4]	242	1			T195	14		T199	8		T207	17
auto[0]	values[5]	values[5]	214	1			T62	10		T180	13		T201	16
auto[0]	values[5]	values[6]	422	1			T67	13		T219	12		T229	11
auto[0]	values[5]	values[7]	330	1			T39	14		T36	26		T192	13
auto[0]	values[6]	values[0]	352	1			T90	4		T232	2		T67	7
auto[0]	values[6]	values[1]	183	1			T62	14		T184	16		T180	14
auto[0]	values[6]	values[2]	246	1			T63	10		T177	12		T333	8
auto[0]	values[6]	values[3]	197	1			T91	10		T62	41		T150	14
auto[0]	values[6]	values[4]	299	1			T92	24		T180	11		T216	17
auto[0]	values[6]	values[5]	222	1			T184	15		T207	10		T250	11
auto[0]	values[6]	values[6]	319	1			T334	24		T219	18		T185	13
auto[0]	values[6]	values[7]	389	1			T63	12		T113	8		T184	100
auto[0]	values[7]	values[0]	320	1			T113	9		T335	16		T216	11
auto[0]	values[7]	values[1]	250	1			T36	15		T69	40		T221	4
auto[0]	values[7]	values[2]	202	1			T183	4		T212	6		T69	24
auto[0]	values[7]	values[3]	457	1			T20	86		T64	8		T36	17
auto[0]	values[7]	values[4]	202	1			T113	17		T219	8		T218	13
auto[0]	values[7]	values[5]	226	1			T242	2		T178	6		T176	10
auto[0]	values[7]	values[6]	266	1			T55	17		T194	2		T36	15
auto[0]	values[7]	values[7]	229	1			T166	9		T200	13		T306	15
auto[1]	values[0]	values[0]	103	1			T184	23		T200	16		T336	8
auto[1]	values[0]	values[1]	179	1			T184	7		T216	7		T219	4
auto[1]	values[0]	values[2]	229	1			T36	11		T178	7		T176	21
auto[1]	values[0]	values[3]	255	1			T18	12		T69	8		T207	8
auto[1]	values[0]	values[4]	166	1			T113	11		T184	10		T252	23
auto[1]	values[0]	values[5]	208	1			T59	10		T150	2		T166	10
auto[1]	values[0]	values[6]	136	1			T179	10		T180	9		T240	12
auto[1]	values[0]	values[7]	151	1			T200	12		T337	8		T274	7
auto[1]	values[1]	values[0]	156	1			T69	5		T180	10		T319	10
auto[1]	values[1]	values[1]	192	1			T67	9		T150	5		T178	11
auto[1]	values[1]	values[2]	118	1			T172	10		T48	5		T214	11
auto[1]	values[1]	values[3]	226	1			T200	14		T97	9		T185	8
auto[1]	values[1]	values[4]	267	1			T10	2		T63	8		T48	13
auto[1]	values[1]	values[5]	115	1			T62	7		T180	8		T200	10
auto[1]	values[1]	values[6]	227	1			T216	6		T240	9		T167	8
auto[1]	values[1]	values[7]	180	1			T216	7		T185	19		T206	7
auto[1]	values[2]	values[0]	224	1			T48	5		T178	7		T113	6
auto[1]	values[2]	values[1]	198	1			T150	47		T200	10		T255	5
auto[1]	values[2]	values[2]	136	1			T229	8		T267	9		T264	44
auto[1]	values[2]	values[3]	177	1			T179	4		T207	8		T240	36
auto[1]	values[2]	values[4]	142	1			T48	11		T207	11		T252	5
auto[1]	values[2]	values[5]	229	1			T36	6		T150	9		T216	12
auto[1]	values[2]	values[6]	304	1			T63	7		T176	38		T113	3
auto[1]	values[2]	values[7]	361	1			T48	15		T280	44		T254	7
auto[1]	values[3]	values[0]	117	1			T185	10		T220	7		T202	6
auto[1]	values[3]	values[1]	146	1			T176	5		T180	4		T229	8
auto[1]	values[3]	values[2]	235	1			T189	20		T180	4		T220	10
auto[1]	values[3]	values[3]	175	1			T36	5		T208	5		T206	12
auto[1]	values[3]	values[4]	219	1			T67	22		T178	10		T176	5
auto[1]	values[3]	values[5]	121	1			T69	12		T113	7		T216	13
auto[1]	values[3]	values[6]	110	1			T180	8		T97	8		T240	4
auto[1]	values[3]	values[7]	270	1			T48	39		T178	4		T69	7
auto[1]	values[4]	values[0]	128	1			T68	16		T200	8		T218	9
auto[1]	values[4]	values[1]	199	1			T36	12		T180	16		T97	20
auto[1]	values[4]	values[2]	125	1			T178	4		T338	20		T265	16
auto[1]	values[4]	values[3]	307	1			T150	13		T69	35		T252	11
auto[1]	values[4]	values[4]	253	1			T179	10		T113	10		T219	13
auto[1]	values[4]	values[5]	205	1			T36	12		T219	7		T248	11
auto[1]	values[4]	values[6]	113	1			T61	10		T97	8		T167	8
auto[1]	values[4]	values[7]	149	1			T67	7		T257	16		T215	10
auto[1]	values[5]	values[0]	143	1			T150	22		T69	23		T180	11
auto[1]	values[5]	values[1]	159	1			T69	5		T223	2		T216	5
auto[1]	values[5]	values[2]	110	1			T36	11		T208	8		T269	16
auto[1]	values[5]	values[3]	269	1			T179	7		T180	6		T339	7
auto[1]	values[5]	values[4]	127	1			T207	5		T208	11		T213	11
auto[1]	values[5]	values[5]	132	1			T62	13		T180	7		T255	12
auto[1]	values[5]	values[6]	195	1			T67	7		T228	14		T219	10
auto[1]	values[5]	values[7]	198	1			T36	6		T192	10		T166	8
auto[1]	values[6]	values[0]	361	1			T67	21		T198	30		T180	6
auto[1]	values[6]	values[1]	213	1			T62	6		T226	16		T184	4
auto[1]	values[6]	values[2]	277	1			T63	19		T69	17		T179	9
auto[1]	values[6]	values[3]	278	1			T62	14		T58	16		T150	39
auto[1]	values[6]	values[4]	174	1			T56	10		T180	9		T216	3
auto[1]	values[6]	values[5]	248	1			T184	5		T207	10		T250	9
auto[1]	values[6]	values[6]	305	1			T219	7		T185	7		T339	7
auto[1]	values[6]	values[7]	188	1			T63	22		T66	10		T113	12
auto[1]	values[7]	values[0]	192	1			T113	11		T216	9		T206	10
auto[1]	values[7]	values[1]	243	1			T36	30		T69	7		T184	6
auto[1]	values[7]	values[2]	102	1			T69	8		T250	7		T214	3
auto[1]	values[7]	values[3]	186	1			T36	9		T166	10		T200	11
auto[1]	values[7]	values[4]	181	1			T113	23		T219	12		T218	7
auto[1]	values[7]	values[5]	165	1			T178	14		T176	10		T252	8
auto[1]	values[7]	values[6]	108	1			T55	3		T36	5		T245	2
auto[1]	values[7]	values[7]	113	1			T166	12		T200	7		T306	5