Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	333	1			T56	4		T46	1		T272	6
auto[ReadAddrCrossIntoMailbox]	224	1			T15	2		T272	4		T66	1
auto[ReadAddrCrossOutOfMailbox]	253	1			T15	2		T46	3		T65	1
auto[ReadAddrCrossAllMailbox]	143	1			T46	2		T272	4		T37	1
auto[ReadAddrOutsideMailbox]	2757	1			T11	4		T14	6		T15	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1826

1

T11

2

T14

3

T15

5

auto[1]

1884

1

T11

2

T14

3

T15

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	625	1			T11	2		T56	2		T61	2
read_ops[0x0b]	633	1			T14	2		T15	4		T17	4
read_ops[0x3b]	657	1			T14	2		T15	2		T18	2
read_ops[0x6b]	590	1			T11	2		T46	1		T209	2
read_ops[0xbb]	628	1			T14	2		T18	2		T76	2
read_ops[0xeb]	577	1			T15	4		T46	4		T209	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T56	1		T69	1		T52	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T56	1		T95	1		T65	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T72	2		T43	1		T202	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T72	1		T205	1		T103	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T51	2		T279	2		T71	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T46	1		T51	1		T279	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T233	1		T228	1		T249	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T69	1		T71	1		T228	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	219	1			T11	1		T61	1		T76	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	237	1			T11	1		T61	1		T76	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T272	2		T52	2		T230	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T272	2		T65	1		T71	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T15	1		T279	2		T71	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T15	1		T65	1		T279	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T15	1		T279	1		T52	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T15	1		T46	2		T51	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T272	2		T95	1		T117	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T272	2		T152	1		T317	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	242	1			T14	1		T17	2		T57	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	211	1			T14	1		T17	2		T57	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T56	1		T272	1		T71	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T56	1		T272	1		T347	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T272	2		T71	1		T103	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T272	2		T69	1		T51	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	15	1			T72	1		T117	1		T256	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T65	1		T202	1		T234	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T282	1		T279	1		T71	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T282	1		T279	1		T71	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	244	1			T14	1		T15	1		T18	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	244	1			T14	1		T15	1		T18	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T266	1		T51	3		T71	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T266	1		T100	1		T71	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T66	1		T319	1		T286	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T319	1		T103	1		T248	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	14	1			T319	1		T205	1		T228	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T71	4		T319	1		T117	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T52	1		T319	1		T152	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T46	1		T69	1		T319	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	220	1			T11	1		T209	1		T201	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	222	1			T11	1		T209	1		T201	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T65	1		T71	2		T291	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T51	1		T72	1		T291	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T65	1		T69	1		T291	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	9	1			T72	1		T291	1		T152	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T103	1		T348	1		T228	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T248	1		T348	1		T234	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	7	1			T37	1		T71	1		T184	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	7	1			T162	1		T349	1		T350	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	238	1			T14	1		T18	1		T76	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	252	1			T14	1		T18	1		T76	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T46	1		T51	2		T325	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	18	1			T52	1		T325	1		T184	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T65	1		T291	1		T228	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	12	1			T51	1		T117	1		T291	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T69	1		T51	1		T100	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T72	1		T117	1		T248	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T46	1		T248	1		T234	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	9	1			T117	1		T234	1		T271	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	198	1			T15	2		T46	1		T209	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	230	1			T15	2		T46	1		T209	1