Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	438	1			T39	8		T106	6		T91	2
auto[ReadAddrCrossIntoMailbox]	271	1			T121	6		T62	1		T63	1
auto[ReadAddrCrossOutOfMailbox]	354	1			T88	4		T62	1		T63	1
auto[ReadAddrCrossAllMailbox]	235	1			T55	1		T88	2		T121	10
auto[ReadAddrOutsideMailbox]	3732	1			T16	2		T17	4		T18	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2460

1

T16

1

T17

2

T18

2

auto[1]

2570

1

T16

1

T17

2

T18

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	846	1			T18	2		T55	1		T88	2
read_ops[0x0b]	876	1			T55	1		T65	2		T175	2
read_ops[0x3b]	791	1			T16	2		T106	4		T65	2
read_ops[0x6b]	864	1			T17	4		T20	2		T91	2
read_ops[0xbb]	852	1			T39	6		T88	2		T121	6
read_ops[0xeb]	801	1			T18	2		T20	2		T39	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T235	1		T178	1		T176	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T235	1		T48	1		T69	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T67	1		T150	1		T178	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T340	1		T255	1		T185	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T176	1		T179	1		T180	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T62	1		T179	1		T192	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T340	2		T216	1		T273	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	30	1			T48	1		T178	3		T113	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	284	1			T18	1		T55	1		T88	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	336	1			T18	1		T88	1		T90	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T235	1		T221	1		T184	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T235	1		T150	1		T221	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T121	2		T113	1		T180	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T121	2		T63	1		T36	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T67	1		T178	1		T198	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T67	1		T178	1		T166	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T121	1		T216	1		T247	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T55	1		T121	1		T63	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	325	1			T65	1		T175	1		T121	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	333	1			T65	1		T175	1		T121	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T106	2		T121	1		T176	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T106	2		T121	1		T178	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T121	1		T62	1		T69	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T121	1		T178	1		T179	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T67	1		T36	1		T176	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T180	1		T255	1		T252	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T63	1		T48	1		T113	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T178	2		T176	1		T219	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	298	1			T16	1		T65	1		T121	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	279	1			T16	1		T65	1		T121	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T91	1		T178	1		T179	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T91	1		T69	1		T113	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T48	1		T166	1		T234	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T234	1		T229	1		T341	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T67	1		T178	1		T69	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T63	1		T67	1		T179	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T121	1		T48	2		T178	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T121	1		T36	1		T150	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	348	1			T17	2		T20	1		T65	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	309	1			T17	2		T20	1		T65	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	53	1			T39	3		T121	2		T113	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T39	3		T121	2		T48	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	11	1			T219	1		T220	1		T280	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T69	1		T166	1		T97	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T88	1		T48	1		T69	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T88	1		T113	1		T340	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T121	1		T178	1		T69	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T121	1		T67	1		T113	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	285	1			T62	1		T246	1		T212	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	330	1			T63	1		T246	1		T212	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T39	1		T106	1		T121	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T39	1		T106	1		T121	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T67	1		T48	1		T69	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T48	1		T280	1		T303	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T88	1		T48	1		T178	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T88	1		T69	1		T176	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T88	1		T121	2		T36	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T88	1		T121	2		T63	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	296	1			T18	1		T20	1		T55	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	309	1			T18	1		T20	1		T64	1