Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2755	1			T227	2		T65	20		T328	10
values[1]	2566	1			T62	2		T226	2		T272	22
values[2]	2851	1			T17	8		T112	10		T59	18
values[3]	2811	1			T14	18		T15	10		T57	6
values[4]	4088	1			T12	22		T61	27		T201	14
values[5]	2689	1			T11	10		T18	6		T116	2
values[6]	2944	1			T56	8		T60	8		T76	12
values[7]	3036	1			T16	4		T22	10		T58	18

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3710	1			T57	6		T58	18		T46	26
values[1]	2594	1			T61	27		T201	14		T95	20
values[2]	2882	1			T12	22		T17	8		T116	2
values[3]	2940	1			T14	18		T18	6		T55	10
values[4]	2664	1			T63	4		T112	10		T251	6
values[5]	2830	1			T11	10		T15	10		T22	10
values[6]	3161	1			T16	4		T76	12		T226	2
values[7]	2959	1			T60	8		T209	8		T267	14

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23204

1

T11

8

T12

22

T14

18

auto[1]

536

1

T11

2

T66

2

T95

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	556	1			T227	2		T328	10		T43	34
auto[0]	values[0]	values[1]	357	1			T65	20		T268	10		T234	19
auto[0]	values[0]	values[2]	183	1			T307	14		T351	4		T78	20
auto[0]	values[0]	values[3]	252	1			T348	10		T233	20		T296	62
auto[0]	values[0]	values[4]	467	1			T43	20		T296	21		T232	19
auto[0]	values[0]	values[5]	259	1			T264	2		T152	26		T349	4
auto[0]	values[0]	values[6]	365	1			T103	70		T202	20		T292	20
auto[0]	values[0]	values[7]	260	1			T103	20		T231	6		T184	19
auto[0]	values[1]	values[0]	421	1			T347	4		T248	28		T43	29
auto[0]	values[1]	values[1]	289	1			T250	139		T249	20		T352	2
auto[0]	values[1]	values[2]	370	1			T272	22		T51	18		T71	93
auto[0]	values[1]	values[3]	248	1			T62	2		T115	8		T276	8
auto[0]	values[1]	values[4]	233	1			T95	18		T353	4		T248	18
auto[0]	values[1]	values[5]	305	1			T260	4		T72	92		T236	8
auto[0]	values[1]	values[6]	242	1			T226	2		T69	15		T291	16
auto[0]	values[1]	values[7]	390	1			T255	18		T69	20		T70	20
auto[0]	values[2]	values[0]	610	1			T259	8		T204	16		T301	10
auto[0]	values[2]	values[1]	389	1			T202	23		T354	12		T233	20
auto[0]	values[2]	values[2]	343	1			T17	8		T210	12		T95	37
auto[0]	values[2]	values[3]	237	1			T59	18		T266	12		T287	69
auto[0]	values[2]	values[4]	338	1			T112	10		T65	26		T71	20
auto[0]	values[2]	values[5]	170	1			T247	2		T344	10		T355	4
auto[0]	values[2]	values[6]	343	1			T65	28		T51	20		T71	68
auto[0]	values[2]	values[7]	355	1			T244	8		T72	20		T103	20
auto[0]	values[3]	values[0]	443	1			T57	6		T117	20		T184	27
auto[0]	values[3]	values[1]	414	1			T65	30		T152	20		T249	54
auto[0]	values[3]	values[2]	282	1			T245	20		T51	57		T52	17
auto[0]	values[3]	values[3]	278	1			T14	18		T312	2		T68	2
auto[0]	values[3]	values[4]	295	1			T305	4		T70	20		T52	20
auto[0]	values[3]	values[5]	326	1			T15	10		T88	18		T184	20
auto[0]	values[3]	values[6]	282	1			T203	6		T64	10		T71	42
auto[0]	values[3]	values[7]	428	1			T51	20		T71	19		T117	20
auto[0]	values[4]	values[0]	785	1			T66	44		T37	20		T311	2
auto[0]	values[4]	values[1]	314	1			T61	27		T201	14		T195	8
auto[0]	values[4]	values[2]	509	1			T12	22		T65	18		T69	20
auto[0]	values[4]	values[3]	651	1			T69	20		T100	20		T284	18
auto[0]	values[4]	values[4]	300	1			T52	19		T202	21		T234	20
auto[0]	values[4]	values[5]	502	1			T66	51		T262	12		T327	10
auto[0]	values[4]	values[6]	557	1			T225	22		T280	12		T248	20
auto[0]	values[4]	values[7]	386	1			T267	14		T356	2		T103	62
auto[0]	values[5]	values[0]	278	1			T46	26		T71	19		T289	23
auto[0]	values[5]	values[1]	258	1			T248	20		T308	14		T184	25
auto[0]	values[5]	values[2]	306	1			T116	2		T70	48		T72	20
auto[0]	values[5]	values[3]	317	1			T18	6		T55	10		T96	12
auto[0]	values[5]	values[4]	439	1			T63	4		T52	70		T43	20
auto[0]	values[5]	values[5]	367	1			T11	8		T46	20		T278	14
auto[0]	values[5]	values[6]	450	1			T67	24		T37	39		T321	6
auto[0]	values[5]	values[7]	218	1			T103	38		T43	20		T202	21
auto[0]	values[6]	values[0]	274	1			T69	19		T357	6		T309	22
auto[0]	values[6]	values[1]	266	1			T309	26		T228	20		T358	2
auto[0]	values[6]	values[2]	345	1			T56	8		T51	38		T234	48
auto[0]	values[6]	values[3]	353	1			T287	35		T78	20		T359	12
auto[0]	values[6]	values[4]	280	1			T251	6		T275	8		T117	20
auto[0]	values[6]	values[5]	370	1			T52	62		T233	39		T152	94
auto[0]	values[6]	values[6]	373	1			T76	12		T277	20		T113	12
auto[0]	values[6]	values[7]	609	1			T60	8		T69	18		T319	6
auto[0]	values[7]	values[0]	255	1			T58	18		T314	8		T256	20
auto[0]	values[7]	values[1]	260	1			T95	20		T71	66		T72	64
auto[0]	values[7]	values[2]	485	1			T279	14		T184	20		T234	23
auto[0]	values[7]	values[3]	536	1			T306	4		T282	18		T65	18
auto[0]	values[7]	values[4]	255	1			T360	12		T152	18		T361	8
auto[0]	values[7]	values[5]	471	1			T22	10		T323	4		T51	62
auto[0]	values[7]	values[6]	475	1			T16	4		T65	20		T52	20
auto[0]	values[7]	values[7]	230	1			T209	8		T65	21		T274	20
auto[1]	values[0]	values[0]	13	1			T43	1		T152	1		T317	1
auto[1]	values[0]	values[1]	3	1			T234	1		T249	2		-	-
auto[1]	values[0]	values[2]	5	1			T362	1		T187	2		T363	1
auto[1]	values[0]	values[3]	5	1			T296	2		T165	2		T364	1
auto[1]	values[0]	values[4]	13	1			T232	1		T252	3		T365	4
auto[1]	values[0]	values[5]	8	1			T152	2		T366	1		T367	2
auto[1]	values[0]	values[6]	2	1			T152	2		-	-		-	-
auto[1]	values[0]	values[7]	7	1			T184	1		T234	2		T336	1
auto[1]	values[1]	values[0]	12	1			T248	2		T43	2		T317	3
auto[1]	values[1]	values[1]	5	1			T368	2		T238	2		T258	1
auto[1]	values[1]	values[2]	11	1			T51	2		T71	2		T72	1
auto[1]	values[1]	values[3]	7	1			T232	1		T339	2		T239	1
auto[1]	values[1]	values[4]	7	1			T95	2		T248	2		T162	1
auto[1]	values[1]	values[5]	13	1			T72	7		T236	2		T369	1
auto[1]	values[1]	values[6]	8	1			T69	5		T370	1		T371	2
auto[1]	values[1]	values[7]	5	1			T252	1		T372	1		T165	2
auto[1]	values[2]	values[0]	11	1			T205	2		T289	2		T233	1
auto[1]	values[2]	values[1]	14	1			T332	4		T158	4		T249	1
auto[1]	values[2]	values[2]	8	1			T103	2		T270	3		T339	1
auto[1]	values[2]	values[3]	5	1			T287	1		T152	1		T167	3
auto[1]	values[2]	values[4]	7	1			T365	5		T331	2		-	-
auto[1]	values[2]	values[5]	4	1			T373	2		T364	2		-	-
auto[1]	values[2]	values[6]	6	1			T65	1		T374	2		T165	2
auto[1]	values[2]	values[7]	11	1			T256	2		T302	1		T336	1
auto[1]	values[3]	values[0]	11	1			T184	1		T317	2		T162	1
auto[1]	values[3]	values[1]	4	1			T65	1		T249	1		T241	1
auto[1]	values[3]	values[2]	6	1			T52	3		T234	1		T249	1
auto[1]	values[3]	values[3]	15	1			T68	2		T271	5		T375	2
auto[1]	values[3]	values[4]	6	1			T228	1		T170	3		T376	2
auto[1]	values[3]	values[5]	10	1			T249	2		T342	1		T377	3
auto[1]	values[3]	values[6]	6	1			T64	2		T71	1		T239	1
auto[1]	values[3]	values[7]	5	1			T71	1		T256	1		T238	2
auto[1]	values[4]	values[0]	17	1			T66	2		T71	1		T52	2
auto[1]	values[4]	values[1]	6	1			T378	3		T331	2		T377	1
auto[1]	values[4]	values[2]	7	1			T65	2		T70	1		T375	1
auto[1]	values[4]	values[3]	16	1			T152	3		T78	1		T339	2
auto[1]	values[4]	values[4]	4	1			T52	1		T202	1		T256	2
auto[1]	values[4]	values[5]	4	1			T249	1		T238	1		T370	1
auto[1]	values[4]	values[6]	18	1			T280	8		T248	1		T235	1
auto[1]	values[4]	values[7]	12	1			T228	2		T249	1		T336	2
auto[1]	values[5]	values[0]	11	1			T71	1		T289	1		T232	3
auto[1]	values[5]	values[1]	7	1			T234	1		T379	2		T167	1
auto[1]	values[5]	values[2]	4	1			T70	1		T377	2		T79	1
auto[1]	values[5]	values[3]	8	1			T51	2		T184	2		T375	2
auto[1]	values[5]	values[4]	7	1			T52	1		T228	2		T270	3
auto[1]	values[5]	values[5]	8	1			T11	2		T380	2		T374	2
auto[1]	values[5]	values[6]	5	1			T235	1		T378	1		T379	1
auto[1]	values[5]	values[7]	6	1			T103	3		T202	1		T162	1
auto[1]	values[6]	values[0]	9	1			T69	1		T233	2		T381	6
auto[1]	values[6]	values[1]	2	1			T241	1		T382	1		-	-
auto[1]	values[6]	values[2]	9	1			T234	2		T335	1		T339	1
auto[1]	values[6]	values[3]	2	1			T287	1		T370	1		-	-
auto[1]	values[6]	values[4]	4	1			T232	2		T271	1		T377	1
auto[1]	values[6]	values[5]	7	1			T233	1		T341	2		T269	2
auto[1]	values[6]	values[6]	14	1			T65	1		T51	2		T152	2
auto[1]	values[6]	values[7]	27	1			T69	2		T103	8		T296	2
auto[1]	values[7]	values[0]	4	1			T383	4		-	-		-	-
auto[1]	values[7]	values[1]	6	1			T71	3		T234	1		T384	1
auto[1]	values[7]	values[2]	9	1			T234	1		T241	3		T385	1
auto[1]	values[7]	values[3]	10	1			T65	2		T70	6		T103	1
auto[1]	values[7]	values[4]	9	1			T152	2		T386	2		T168	1
auto[1]	values[7]	values[5]	6	1			T235	2		T387	1		T388	3
auto[1]	values[7]	values[6]	15	1			T202	1		T249	1		T340	4
auto[1]	values[7]	values[7]	10	1			T335	2		T389	1		T263	2