Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.32	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	1	127	99.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	1	127	99.22	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3930	1			T17	22		T63	21		T182	4
values[1]	3888	1			T6	10		T10	2		T106	6
values[2]	3726	1			T9	16		T65	18		T61	10
values[3]	3901	1			T39	14		T88	8		T91	10
values[4]	3388	1			T20	86		T92	24		T67	23
values[5]	3845	1			T18	12		T55	20		T56	10
values[6]	3685	1			T16	2		T183	4		T110	8
values[7]	3552	1			T19	4		T64	8		T90	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4288	1			T17	22		T110	8		T121	28
values[1]	3633	1			T6	10		T56	10		T60	55
values[2]	4115	1			T55	20		T65	18		T57	24
values[3]	3583	1			T19	4		T62	33		T182	4
values[4]	3670	1			T39	14		T64	8		T175	2
values[5]	3443	1			T9	16		T10	2		T16	2
values[6]	3665	1			T106	6		T61	10		T63	21
values[7]	3518	1			T88	8		T92	24		T90	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29133

1

T6

10

T9

16

T16

2

auto[1]

782

1

T10

2

T56

2

T62

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	1	127	99.22	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[7]]	[values[5]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	547	1			T17	22		T184	22		T185	20
auto[0]	values[0]	values[1]	753	1			T67	27		T36	20		T150	20
auto[0]	values[0]	values[2]	631	1			T178	31		T68	14		T69	31
auto[0]	values[0]	values[3]	276	1			T182	4		T36	20		T48	28
auto[0]	values[0]	values[4]	391	1			T179	18		T186	22		T187	4
auto[0]	values[0]	values[5]	366	1			T58	14		T69	60		T188	6
auto[0]	values[0]	values[6]	509	1			T63	21		T189	20		T190	16
auto[0]	values[0]	values[7]	336	1			T191	4		T192	22		T193	12
auto[0]	values[1]	values[0]	527	1			T36	45		T176	44		T180	38
auto[0]	values[1]	values[1]	490	1			T6	10		T194	2		T59	10
auto[0]	values[1]	values[2]	531	1			T57	24		T195	14		T48	20
auto[0]	values[1]	values[3]	264	1			T196	20		T197	20		T74	45
auto[0]	values[1]	values[4]	545	1			T63	28		T198	38		T113	20
auto[0]	values[1]	values[5]	596	1			T199	8		T69	34		T200	19
auto[0]	values[1]	values[6]	379	1			T106	6		T201	16		T202	22
auto[0]	values[1]	values[7]	469	1			T113	20		T184	20		T203	14
auto[0]	values[2]	values[0]	604	1			T62	23		T66	8		T48	25
auto[0]	values[2]	values[1]	339	1			T62	18		T67	29		T113	18
auto[0]	values[2]	values[2]	390	1			T65	18		T179	18		T113	20
auto[0]	values[2]	values[3]	507	1			T204	6		T184	31		T180	19
auto[0]	values[2]	values[4]	351	1			T205	18		T69	20		T206	20
auto[0]	values[2]	values[5]	563	1			T9	16		T48	40		T207	41
auto[0]	values[2]	values[6]	323	1			T61	10		T178	22		T208	21
auto[0]	values[2]	values[7]	558	1			T62	31		T63	20		T209	4
auto[0]	values[3]	values[0]	499	1			T210	10		T166	45		T200	18
auto[0]	values[3]	values[1]	431	1			T91	10		T150	31		T200	20
auto[0]	values[3]	values[2]	577	1			T67	20		T177	12		T150	26
auto[0]	values[3]	values[3]	560	1			T62	33		T48	50		T211	4
auto[0]	values[3]	values[4]	501	1			T39	14		T175	2		T212	6
auto[0]	values[3]	values[5]	466	1			T176	20		T184	31		T180	17
auto[0]	values[3]	values[6]	374	1			T213	42		T214	19		T215	20
auto[0]	values[3]	values[7]	393	1			T88	8		T216	20		T217	4
auto[0]	values[4]	values[0]	339	1			T166	26		T200	20		T218	20
auto[0]	values[4]	values[1]	492	1			T67	22		T36	20		T113	20
auto[0]	values[4]	values[2]	451	1			T180	38		T219	18		T97	20
auto[0]	values[4]	values[3]	413	1			T178	19		T206	20		T220	18
auto[0]	values[4]	values[4]	416	1			T221	4		T113	18		T222	21
auto[0]	values[4]	values[5]	303	1			T20	86		T146	8		T223	2
auto[0]	values[4]	values[6]	506	1			T224	4		T69	25		T225	2
auto[0]	values[4]	values[7]	360	1			T92	24		T226	16		T200	20
auto[0]	values[5]	values[0]	421	1			T150	53		T216	14		T219	20
auto[0]	values[5]	values[1]	566	1			T56	8		T60	55		T227	4
auto[0]	values[5]	values[2]	629	1			T55	20		T63	34		T150	22
auto[0]	values[5]	values[3]	355	1			T172	20		T36	26		T228	14
auto[0]	values[5]	values[4]	439	1			T69	29		T180	19		T229	17
auto[0]	values[5]	values[5]	352	1			T18	12		T36	85		T178	23
auto[0]	values[5]	values[6]	529	1			T214	21		T230	112		T231	20
auto[0]	values[5]	values[7]	445	1			T232	2		T48	25		T97	24
auto[0]	values[6]	values[0]	741	1			T110	8		T121	28		T36	26
auto[0]	values[6]	values[1]	249	1			T178	22		T233	6		T97	20
auto[0]	values[6]	values[2]	264	1			T113	20		T234	20		T180	19
auto[0]	values[6]	values[3]	489	1			T179	19		T207	22		T213	20
auto[0]	values[6]	values[4]	467	1			T176	29		T179	20		T180	19
auto[0]	values[6]	values[5]	395	1			T16	2		T183	4		T235	20
auto[0]	values[6]	values[6]	472	1			T109	6		T48	26		T69	63
auto[0]	values[6]	values[7]	526	1			T36	20		T176	20		T236	4
auto[0]	values[7]	values[0]	517	1			T237	2		T238	12		T216	20
auto[0]	values[7]	values[1]	215	1			T239	20		T240	34		T241	18
auto[0]	values[7]	values[2]	532	1			T62	20		T67	47		T242	2
auto[0]	values[7]	values[3]	622	1			T19	4		T36	20		T178	24
auto[0]	values[7]	values[4]	456	1			T64	8		T150	28		T243	14
auto[0]	values[7]	values[5]	298	1			T244	4		T200	20		T245	2
auto[0]	values[7]	values[6]	478	1			T36	18		T184	20		T185	20
auto[0]	values[7]	values[7]	350	1			T90	4		T246	8		T219	20
auto[1]	values[0]	values[0]	9	1			T208	1		T213	1		T247	1
auto[1]	values[0]	values[1]	20	1			T67	1		T248	2		T249	1
auto[1]	values[0]	values[2]	24	1			T68	2		T69	1		T216	2
auto[1]	values[0]	values[3]	6	1			T48	1		T250	2		T251	3
auto[1]	values[0]	values[4]	18	1			T179	2		T252	2		T253	1
auto[1]	values[0]	values[5]	15	1			T58	2		T69	3		T254	4
auto[1]	values[0]	values[6]	16	1			T185	1		T248	1		T250	5
auto[1]	values[0]	values[7]	13	1			T192	1		T200	2		T97	4
auto[1]	values[1]	values[0]	17	1			T176	2		T180	2		T255	2
auto[1]	values[1]	values[1]	9	1			T207	1		T253	1		T256	3
auto[1]	values[1]	values[2]	7	1			T198	1		T248	1		T257	2
auto[1]	values[1]	values[3]	4	1			T258	2		T259	1		T260	1
auto[1]	values[1]	values[4]	18	1			T63	1		T198	2		T184	4
auto[1]	values[1]	values[5]	23	1			T10	2		T200	1		T254	1
auto[1]	values[1]	values[6]	3	1			T202	1		T43	1		T261	1
auto[1]	values[1]	values[7]	6	1			T220	1		T230	1		T253	3
auto[1]	values[2]	values[0]	11	1			T66	2		T262	1		T263	1
auto[1]	values[2]	values[1]	14	1			T62	2		T67	2		T113	2
auto[1]	values[2]	values[2]	15	1			T179	2		T264	1		T74	1
auto[1]	values[2]	values[3]	17	1			T184	1		T180	1		T97	2
auto[1]	values[2]	values[4]	3	1			T213	3		-	-		-	-
auto[1]	values[2]	values[5]	13	1			T48	2		T265	2		T266	3
auto[1]	values[2]	values[6]	6	1			T178	2		T267	1		T268	1
auto[1]	values[2]	values[7]	12	1			T62	4		T219	2		T269	2
auto[1]	values[3]	values[0]	17	1			T200	2		T219	2		T229	1
auto[1]	values[3]	values[1]	5	1			T150	1		T270	1		T271	2
auto[1]	values[3]	values[2]	17	1			T184	2		T250	1		T262	1
auto[1]	values[3]	values[3]	15	1			T184	3		T97	3		T267	1
auto[1]	values[3]	values[4]	14	1			T69	1		T266	2		T272	1
auto[1]	values[3]	values[5]	15	1			T184	2		T180	3		T208	1
auto[1]	values[3]	values[6]	10	1			T214	1		T268	1		T256	1
auto[1]	values[3]	values[7]	7	1			T254	2		T74	1		T42	1
auto[1]	values[4]	values[0]	11	1			T166	2		T220	2		T167	3
auto[1]	values[4]	values[1]	16	1			T67	1		T185	1		T208	3
auto[1]	values[4]	values[2]	20	1			T180	2		T219	4		T202	2
auto[1]	values[4]	values[3]	13	1			T178	1		T220	2		T74	1
auto[1]	values[4]	values[4]	13	1			T113	2		T240	1		T169	1
auto[1]	values[4]	values[5]	11	1			T273	1		T262	2		T42	4
auto[1]	values[4]	values[6]	16	1			T69	2		T229	3		T274	2
auto[1]	values[4]	values[7]	8	1			T253	2		T274	1		T272	3
auto[1]	values[5]	values[0]	14	1			T216	6		T97	1		T275	1
auto[1]	values[5]	values[1]	17	1			T56	2		T180	3		T220	2
auto[1]	values[5]	values[2]	12	1			T150	2		T69	1		T216	1
auto[1]	values[5]	values[3]	12	1			T36	6		T252	1		T215	1
auto[1]	values[5]	values[4]	11	1			T180	1		T229	3		T231	2
auto[1]	values[5]	values[5]	15	1			T200	2		T202	1		T213	1
auto[1]	values[5]	values[6]	14	1			T230	3		T267	1		T264	4
auto[1]	values[5]	values[7]	14	1			T48	1		T97	1		T206	1
auto[1]	values[6]	values[0]	9	1			T69	2		T215	1		T74	1
auto[1]	values[6]	values[1]	6	1			T208	1		T267	3		T251	1
auto[1]	values[6]	values[2]	9	1			T180	1		T254	2		T74	1
auto[1]	values[6]	values[3]	12	1			T179	1		T276	1		T262	2
auto[1]	values[6]	values[4]	15	1			T176	3		T180	1		T185	2
auto[1]	values[6]	values[5]	12	1			T220	1		T277	4		T274	1
auto[1]	values[6]	values[6]	12	1			T69	4		T166	1		T200	1
auto[1]	values[6]	values[7]	7	1			T216	1		T185	4		T214	1
auto[1]	values[7]	values[0]	5	1			T278	1		T268	1		T42	1
auto[1]	values[7]	values[1]	11	1			T240	3		T262	2		T279	3
auto[1]	values[7]	values[2]	6	1			T67	1		T97	1		T208	2
auto[1]	values[7]	values[3]	18	1			T178	1		T179	1		T248	1
auto[1]	values[7]	values[4]	12	1			T166	1		T264	3		T263	1
auto[1]	values[7]	values[6]	18	1			T36	2		T202	1		T213	1
auto[1]	values[7]	values[7]	14	1			T220	1		T280	1		T268	1