Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	766	1			T24	10		T35	7		T38	14
all_values[1]	766	1			T24	10		T35	7		T38	14
all_values[2]	766	1			T24	10		T35	7		T38	14
all_values[3]	766	1			T24	10		T35	7		T38	14
all_values[4]	766	1			T24	10		T35	7		T38	14
all_values[5]	766	1			T24	10		T35	7		T38	14
all_values[6]	766	1			T24	10		T35	7		T38	14
all_values[7]	766	1			T24	10		T35	7		T38	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3231

1

T24

58

T35

28

T38

62

auto[1]

2897

1

T24

22

T35

28

T38

50

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2470

1

T24

24

T35

25

T38

59

auto[1]

3658

1

T24

56

T35

31

T38

53

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3516

1

T24

42

T35

32

T38

78

auto[1]

2612

1

T24

38

T35

24

T38

34

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	159	1			T24	1		T35	1		T38	6
all_values[0]	auto[0]	auto[0]	auto[1]	69	1			T24	3		T38	1		T199	3
all_values[0]	auto[0]	auto[1]	auto[0]	128	1			T35	3		T38	2		T100	1
all_values[0]	auto[0]	auto[1]	auto[1]	73	1			T24	4		T35	1		T38	2
all_values[0]	auto[1]	auto[0]	auto[1]	173	1			T24	2		T35	1		T38	2
all_values[0]	auto[1]	auto[1]	auto[1]	164	1			T35	1		T38	1		T39	2
all_values[1]	auto[0]	auto[0]	auto[0]	150	1			T24	1		T35	2		T38	3
all_values[1]	auto[0]	auto[0]	auto[1]	64	1			T24	1		T38	3		T39	2
all_values[1]	auto[0]	auto[1]	auto[0]	144	1			T24	1		T35	1		T183	1
all_values[1]	auto[0]	auto[1]	auto[1]	80	1			T24	2		T38	1		T183	2
all_values[1]	auto[1]	auto[0]	auto[1]	183	1			T24	5		T35	3		T38	2
all_values[1]	auto[1]	auto[1]	auto[1]	145	1			T35	1		T38	5		T183	3
all_values[2]	auto[0]	auto[0]	auto[0]	148	1			T38	8		T183	4		T200	11
all_values[2]	auto[0]	auto[0]	auto[1]	89	1			T24	3		T38	1		T39	1
all_values[2]	auto[0]	auto[1]	auto[0]	135	1			T35	1		T38	2		T100	2
all_values[2]	auto[0]	auto[1]	auto[1]	56	1			T39	1		T183	2		T100	2
all_values[2]	auto[1]	auto[0]	auto[1]	190	1			T24	6		T35	4		T38	3
all_values[2]	auto[1]	auto[1]	auto[1]	148	1			T24	1		T35	2		T39	1
all_values[3]	auto[0]	auto[0]	auto[0]	139	1			T24	5		T38	5		T39	1
all_values[3]	auto[0]	auto[0]	auto[1]	77	1			T183	2		T100	2		T200	2
all_values[3]	auto[0]	auto[1]	auto[0]	134	1			T35	1		T38	2		T39	2
all_values[3]	auto[0]	auto[1]	auto[1]	79	1			T24	1		T35	2		T38	4
all_values[3]	auto[1]	auto[0]	auto[1]	170	1			T24	3		T35	3		T38	1
all_values[3]	auto[1]	auto[1]	auto[1]	167	1			T24	1		T35	1		T38	2
all_values[4]	auto[0]	auto[0]	auto[0]	137	1			T24	4		T38	3		T39	1
all_values[4]	auto[0]	auto[0]	auto[1]	78	1			T35	2		T38	2		T100	1
all_values[4]	auto[0]	auto[1]	auto[0]	134	1			T24	1		T35	2		T38	2
all_values[4]	auto[0]	auto[1]	auto[1]	88	1			T24	1		T35	1		T38	1
all_values[4]	auto[1]	auto[0]	auto[1]	161	1			T24	2		T38	2		T39	1
all_values[4]	auto[1]	auto[1]	auto[1]	168	1			T24	2		T35	2		T38	4
all_values[5]	auto[0]	auto[0]	auto[0]	257	1			T24	3		T35	2		T38	3
all_values[5]	auto[0]	auto[1]	auto[0]	179	1			T35	2		T38	5		T39	4
all_values[5]	auto[1]	auto[0]	auto[1]	197	1			T24	6		T35	2		T38	4
all_values[5]	auto[1]	auto[1]	auto[1]	133	1			T24	1		T35	1		T38	2
all_values[6]	auto[0]	auto[0]	auto[0]	170	1			T24	3		T35	4		T38	3
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T24	2		T38	1		T183	1
all_values[6]	auto[0]	auto[1]	auto[0]	127	1			T35	3		T38	9		T183	2
all_values[6]	auto[0]	auto[1]	auto[1]	83	1			T39	1		T183	2		T100	1
all_values[6]	auto[1]	auto[0]	auto[1]	148	1			T24	3		T183	6		T200	3
all_values[6]	auto[1]	auto[1]	auto[1]	164	1			T24	2		T38	1		T39	3
all_values[7]	auto[0]	auto[0]	auto[0]	173	1			T24	2		T35	2		T38	3
all_values[7]	auto[0]	auto[0]	auto[1]	65	1			T24	1		T38	2		T39	1
all_values[7]	auto[0]	auto[1]	auto[0]	156	1			T24	3		T35	1		T38	3
all_values[7]	auto[0]	auto[1]	auto[1]	71	1			T35	1		T38	1		T183	3
all_values[7]	auto[1]	auto[0]	auto[1]	160	1			T24	2		T35	2		T38	4
all_values[7]	auto[1]	auto[1]	auto[1]	141	1			T24	2		T35	1		T38	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal