Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	736	1			T22	14		T23	18		T33	4
all_values[1]	736	1			T22	14		T23	18		T33	4
all_values[2]	736	1			T22	14		T23	18		T33	4
all_values[3]	736	1			T22	14		T23	18		T33	4
all_values[4]	736	1			T22	14		T23	18		T33	4
all_values[5]	736	1			T22	14		T23	18		T33	4
all_values[6]	736	1			T22	14		T23	18		T33	4
all_values[7]	736	1			T22	14		T23	18		T33	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3079

1

T22

62

T23

69

T33

21

auto[1]

2809

1

T22

50

T23

75

T33

11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2345

1

T22

49

T23

61

T33

14

auto[1]

3543

1

T22

63

T23

83

T33

18

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3386

1

T22

65

T23

86

T33

19

auto[1]

2502

1

T22

47

T23

58

T33

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	126	1			T22	5		T23	4		T37	2
all_values[0]	auto[0]	auto[0]	auto[1]	78	1			T22	3		T23	1		T33	1
all_values[0]	auto[0]	auto[1]	auto[0]	134	1			T22	3		T23	3		T33	1
all_values[0]	auto[0]	auto[1]	auto[1]	89	1			T22	1		T23	2		T36	1
all_values[0]	auto[1]	auto[0]	auto[1]	171	1			T22	1		T23	3		T33	2
all_values[0]	auto[1]	auto[1]	auto[1]	138	1			T22	1		T23	5		T37	1
all_values[1]	auto[0]	auto[0]	auto[0]	146	1			T22	1		T23	3		T36	1
all_values[1]	auto[0]	auto[0]	auto[1]	79	1			T22	1		T23	4		T33	1
all_values[1]	auto[0]	auto[1]	auto[0]	133	1			T22	6		T23	2		T36	3
all_values[1]	auto[0]	auto[1]	auto[1]	56	1			T37	2		T173	2		T174	1
all_values[1]	auto[1]	auto[0]	auto[1]	184	1			T22	2		T23	5		T33	3
all_values[1]	auto[1]	auto[1]	auto[1]	138	1			T22	4		T23	4		T37	1
all_values[2]	auto[0]	auto[0]	auto[0]	133	1			T22	2		T23	1		T173	6
all_values[2]	auto[0]	auto[0]	auto[1]	72	1			T23	4		T37	3		T173	2
all_values[2]	auto[0]	auto[1]	auto[0]	135	1			T22	5		T23	5		T33	3
all_values[2]	auto[0]	auto[1]	auto[1]	78	1			T22	2		T23	2		T36	1
all_values[2]	auto[1]	auto[0]	auto[1]	166	1			T23	2		T33	1		T36	1
all_values[2]	auto[1]	auto[1]	auto[1]	152	1			T22	5		T23	4		T36	2
all_values[3]	auto[0]	auto[0]	auto[0]	133	1			T22	6		T23	5		T33	1
all_values[3]	auto[0]	auto[0]	auto[1]	94	1			T22	1		T33	1		T37	2
all_values[3]	auto[0]	auto[1]	auto[0]	150	1			T22	1		T33	1		T37	7
all_values[3]	auto[0]	auto[1]	auto[1]	59	1			T22	1		T23	2		T174	1
all_values[3]	auto[1]	auto[0]	auto[1]	158	1			T22	3		T23	7		T33	1
all_values[3]	auto[1]	auto[1]	auto[1]	142	1			T22	2		T23	4		T36	1
all_values[4]	auto[0]	auto[0]	auto[0]	159	1			T22	3		T23	3		T33	1
all_values[4]	auto[0]	auto[0]	auto[1]	67	1			T22	2		T37	3		T173	1
all_values[4]	auto[0]	auto[1]	auto[0]	143	1			T22	2		T23	5		T36	1
all_values[4]	auto[0]	auto[1]	auto[1]	71	1			T22	1		T23	6		T33	1
all_values[4]	auto[1]	auto[0]	auto[1]	148	1			T22	6		T23	1		T33	1
all_values[4]	auto[1]	auto[1]	auto[1]	148	1			T23	3		T33	1		T36	1
all_values[5]	auto[0]	auto[0]	auto[0]	224	1			T22	3		T23	5		T33	2
all_values[5]	auto[0]	auto[1]	auto[0]	176	1			T22	2		T23	7		T33	1
all_values[5]	auto[1]	auto[0]	auto[1]	181	1			T22	8		T23	2		T36	1
all_values[5]	auto[1]	auto[1]	auto[1]	155	1			T22	1		T23	4		T33	1
all_values[6]	auto[0]	auto[0]	auto[0]	133	1			T23	2		T33	2		T37	2
all_values[6]	auto[0]	auto[0]	auto[1]	69	1			T23	1		T37	2		T174	1
all_values[6]	auto[0]	auto[1]	auto[0]	136	1			T22	3		T23	7		T37	3
all_values[6]	auto[0]	auto[1]	auto[1]	84	1			T22	2		T23	2		T33	1
all_values[6]	auto[1]	auto[0]	auto[1]	152	1			T22	2		T23	4		T36	2
all_values[6]	auto[1]	auto[1]	auto[1]	162	1			T22	7		T23	2		T33	1
all_values[7]	auto[0]	auto[0]	auto[0]	154	1			T22	7		T23	4		T33	2
all_values[7]	auto[0]	auto[0]	auto[1]	78	1			T22	2		T23	1		T37	1
all_values[7]	auto[0]	auto[1]	auto[0]	130	1			T23	5		T36	1		T173	4
all_values[7]	auto[0]	auto[1]	auto[1]	67	1			T37	3		T173	2		T174	1
all_values[7]	auto[1]	auto[0]	auto[1]	174	1			T22	4		T23	7		T33	2
all_values[7]	auto[1]	auto[1]	auto[1]	133	1			T22	1		T23	1		T36	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal