Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1776

1

T4

8

T5

2

T13

1

auto[1]

1763

1

T4

6

T27

2

T28

9

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1890

1

T5

2

T13

1

T30

4

auto[1]

1649

1

T4

14

T27

4

T28

15

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2823

1

T4

14

T13

1

T27

4

auto[1]

716

1

T5

2

T30

1

T34

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	689	1			T4	2		T27	1		T28	2
valid[1]	724	1			T4	4		T5	2		T28	2
valid[2]	713	1			T4	1		T27	2		T28	4
valid[3]	725	1			T4	2		T27	1		T28	3
valid[4]	688	1			T4	5		T13	1		T28	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	116	1			T30	1		T74	1		T75	1
auto[0]	auto[0]	valid[0]	auto[1]	149	1			T4	1		T27	1		T28	1
auto[0]	auto[0]	valid[1]	auto[0]	133	1			T30	1		T75	1		T404	1
auto[0]	auto[0]	valid[1]	auto[1]	165	1			T4	3		T29	2		T33	2
auto[0]	auto[0]	valid[2]	auto[0]	102	1			T74	1		T75	1		T401	1
auto[0]	auto[0]	valid[2]	auto[1]	172	1			T4	1		T27	1		T28	1
auto[0]	auto[0]	valid[3]	auto[0]	128	1			T53	1		T74	3		T403	1
auto[0]	auto[0]	valid[3]	auto[1]	172	1			T28	1		T29	1		T32	7
auto[0]	auto[0]	valid[4]	auto[0]	109	1			T13	1		T53	1		T75	2
auto[0]	auto[0]	valid[4]	auto[1]	178	1			T4	3		T28	3		T29	3
auto[0]	auto[1]	valid[0]	auto[0]	111	1			T75	1		T401	1		T109	1
auto[0]	auto[1]	valid[0]	auto[1]	171	1			T4	1		T28	1		T29	1
auto[0]	auto[1]	valid[1]	auto[0]	118	1			T75	3		T403	2		T404	1
auto[0]	auto[1]	valid[1]	auto[1]	163	1			T4	1		T28	2		T29	1
auto[0]	auto[1]	valid[2]	auto[0]	128	1			T75	2		T403	1		T94	4
auto[0]	auto[1]	valid[2]	auto[1]	165	1			T27	1		T28	3		T29	4
auto[0]	auto[1]	valid[3]	auto[0]	128	1			T46	1		T74	1		T403	2
auto[0]	auto[1]	valid[3]	auto[1]	155	1			T4	2		T27	1		T28	2
auto[0]	auto[1]	valid[4]	auto[0]	101	1			T30	1		T74	1		T75	1
auto[0]	auto[1]	valid[4]	auto[1]	159	1			T4	2		T28	1		T29	2
auto[1]	auto[0]	valid[0]	auto[0]	77	1			T34	1		T75	1		T404	1
auto[1]	auto[0]	valid[1]	auto[0]	76	1			T5	2		T46	1		T74	1
auto[1]	auto[0]	valid[2]	auto[0]	70	1			T74	2		T75	1		T39	1
auto[1]	auto[0]	valid[3]	auto[0]	63	1			T75	1		T401	1		T39	1
auto[1]	auto[0]	valid[4]	auto[0]	66	1			T90	1		T400	1		T94	3
auto[1]	auto[1]	valid[0]	auto[0]	65	1			T75	1		T404	1		T90	1
auto[1]	auto[1]	valid[1]	auto[0]	69	1			T75	1		T404	1		T95	2
auto[1]	auto[1]	valid[2]	auto[0]	76	1			T46	1		T74	2		T75	2
auto[1]	auto[1]	valid[3]	auto[0]	79	1			T30	1		T74	1		T75	1
auto[1]	auto[1]	valid[4]	auto[0]	75	1			T74	1		T75	1		T404	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal