Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1620

1

T3

8

T13

1

T26

4

auto[1]

1745

1

T3

6

T13

2

T26

6

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1632

1

T30

2

T32

11

T45

11

auto[1]

1733

1

T3

14

T13

3

T26

10

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2738

1

T3

14

T13

3

T26

10

auto[1]

627

1

T32

2

T45

6

T50

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	684	1			T26	2		T28	4		T22	2
valid[1]	663	1			T3	2		T26	5		T28	1
valid[2]	670	1			T3	2		T13	2		T26	1
valid[3]	689	1			T3	7		T26	1		T31	11
valid[4]	659	1			T3	3		T13	1		T26	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	97	1			T32	2		T45	1		T50	2
auto[0]	auto[0]	valid[0]	auto[1]	148	1			T26	1		T28	1		T22	1
auto[0]	auto[0]	valid[1]	auto[0]	91	1			T32	2		T70	1		T62	1
auto[0]	auto[0]	valid[1]	auto[1]	162	1			T26	2		T28	1		T22	2
auto[0]	auto[0]	valid[2]	auto[0]	86	1			T32	1		T71	2		T51	2
auto[0]	auto[0]	valid[2]	auto[1]	170	1			T3	2		T13	1		T31	4
auto[0]	auto[0]	valid[3]	auto[0]	118	1			T45	2		T62	1		T51	2
auto[0]	auto[0]	valid[3]	auto[1]	175	1			T3	4		T26	1		T31	6
auto[0]	auto[0]	valid[4]	auto[0]	98	1			T30	1		T32	3		T51	2
auto[0]	auto[0]	valid[4]	auto[1]	167	1			T3	2		T31	4		T32	1
auto[0]	auto[1]	valid[0]	auto[0]	124	1			T30	1		T71	1		T62	1
auto[0]	auto[1]	valid[0]	auto[1]	193	1			T26	1		T28	3		T22	1
auto[0]	auto[1]	valid[1]	auto[0]	94	1			T32	1		T45	1		T50	4
auto[0]	auto[1]	valid[1]	auto[1]	180	1			T3	2		T26	3		T31	4
auto[0]	auto[1]	valid[2]	auto[0]	99	1			T50	1		T62	1		T356	1
auto[0]	auto[1]	valid[2]	auto[1]	174	1			T13	1		T26	1		T31	3
auto[0]	auto[1]	valid[3]	auto[0]	101	1			T36	1		T69	1		T355	1
auto[0]	auto[1]	valid[3]	auto[1]	185	1			T3	3		T31	5		T32	1
auto[0]	auto[1]	valid[4]	auto[0]	97	1			T45	1		T50	1		T363	2
auto[0]	auto[1]	valid[4]	auto[1]	179	1			T3	1		T13	1		T26	1
auto[1]	auto[0]	valid[0]	auto[0]	61	1			T45	2		T104	1		T172	1
auto[1]	auto[0]	valid[1]	auto[0]	57	1			T63	2		T36	1		T357	1
auto[1]	auto[0]	valid[2]	auto[0]	71	1			T45	1		T71	1		T62	1
auto[1]	auto[0]	valid[3]	auto[0]	56	1			T32	1		T45	1		T36	1
auto[1]	auto[0]	valid[4]	auto[0]	63	1			T45	1		T51	1		T36	2
auto[1]	auto[1]	valid[0]	auto[0]	61	1			T50	1		T62	1		T51	1
auto[1]	auto[1]	valid[1]	auto[0]	79	1			T32	1		T172	1		T350	1
auto[1]	auto[1]	valid[2]	auto[0]	70	1			T45	1		T63	1		T363	1
auto[1]	auto[1]	valid[3]	auto[0]	54	1			T63	1		T172	1		T357	1
auto[1]	auto[1]	valid[4]	auto[0]	55	1			T36	2		T95	1		T178	4

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal