Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42269

1

T5

8

T14

1

T29

6

auto[1]

18917

1

T3

14

T13

61

T26

199

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45646

1

T3

14

T5

5

T13

61

auto[1]

15540

1

T5

3

T29

3

T22

61

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	31665	1			T3	14		T5	1		T13	30
others[1]	5149	1			T5	3		T13	5		T26	14
others[2]	5121	1			T5	2		T13	10		T26	16
others[3]	5767	1			T5	1		T13	7		T26	11
interest[1]	3324	1			T13	1		T26	10		T29	1
interest[4]	20631	1			T3	14		T13	21		T26	66
interest[64]	10160	1			T5	1		T13	8		T14	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	13753	1			T5	1		T29	3		T22	39
auto[0]	auto[0]	others[1]	2318	1			T5	2		T22	11		T30	3
auto[0]	auto[0]	others[2]	2235	1			T5	1		T22	6		T30	3
auto[0]	auto[0]	others[3]	2533	1			T5	1		T22	3		T30	8
auto[0]	auto[0]	interest[1]	1443	1			T22	6		T30	2		T32	6
auto[0]	auto[0]	interest[4]	8926	1			T29	1		T22	26		T30	16
auto[0]	auto[0]	interest[64]	4447	1			T14	1		T22	14		T30	5
auto[0]	auto[1]	others[0]	9879	1			T3	14		T13	30		T26	110
auto[0]	auto[1]	others[1]	1534	1			T13	5		T26	14		T22	6
auto[0]	auto[1]	others[2]	1551	1			T13	10		T26	16		T22	7
auto[0]	auto[1]	others[3]	1789	1			T13	7		T26	11		T22	5
auto[0]	auto[1]	interest[1]	1028	1			T13	1		T26	10		T22	3
auto[0]	auto[1]	interest[4]	6501	1			T3	14		T13	21		T26	66
auto[0]	auto[1]	interest[64]	3136	1			T13	8		T26	38		T22	6
auto[1]	auto[0]	others[0]	8033	1			T29	1		T22	30		T30	16
auto[1]	auto[0]	others[1]	1297	1			T5	1		T29	1		T22	5
auto[1]	auto[0]	others[2]	1335	1			T5	1		T22	5		T30	4
auto[1]	auto[0]	others[3]	1445	1			T22	7		T30	3		T32	8
auto[1]	auto[0]	interest[1]	853	1			T29	1		T22	3		T30	2
auto[1]	auto[0]	interest[4]	5204	1			T29	1		T22	18		T30	11
auto[1]	auto[0]	interest[64]	2577	1			T5	1		T22	11		T30	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal