Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48373

1

T5

9

T13

3

T31

1

auto[1]

17589

1

T4

14

T27

4

T28

233

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48032

1

T4

14

T5

2

T13

1

auto[1]

17930

1

T5

7

T13

2

T31

1

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33871	1			T4	14		T5	5		T13	2
others[1]	5542	1			T28	15		T29	24		T30	15
others[2]	5560	1			T5	2		T28	22		T29	28
others[3]	6262	1			T5	1		T28	19		T29	14
interest[1]	3721	1			T5	1		T28	17		T29	9
interest[4]	22162	1			T4	14		T5	4		T13	1
interest[64]	11006	1			T13	1		T28	40		T29	37

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15517	1			T5	1		T30	30		T34	14
auto[0]	auto[0]	others[1]	2585	1			T30	11		T34	8		T48	1
auto[0]	auto[0]	others[2]	2604	1			T30	6		T34	8		T46	6
auto[0]	auto[0]	others[3]	2916	1			T30	8		T34	5		T46	7
auto[0]	auto[0]	interest[1]	1766	1			T5	1		T30	2		T34	1
auto[0]	auto[0]	interest[4]	10140	1			T30	16		T34	9		T48	1
auto[0]	auto[0]	interest[64]	5055	1			T13	1		T30	12		T34	6
auto[0]	auto[1]	others[0]	9187	1			T4	14		T27	4		T28	120
auto[0]	auto[1]	others[1]	1439	1			T28	15		T29	24		T30	3
auto[0]	auto[1]	others[2]	1477	1			T28	22		T29	28		T30	5
auto[0]	auto[1]	others[3]	1636	1			T28	19		T29	14		T30	4
auto[0]	auto[1]	interest[1]	937	1			T28	17		T29	9		T30	1
auto[0]	auto[1]	interest[4]	6063	1			T4	14		T27	4		T28	78
auto[0]	auto[1]	interest[64]	2913	1			T28	40		T29	37		T30	8
auto[1]	auto[0]	others[0]	9167	1			T5	4		T13	2		T31	1
auto[1]	auto[0]	others[1]	1518	1			T30	1		T34	2		T48	1
auto[1]	auto[0]	others[2]	1479	1			T5	2		T30	6		T34	2
auto[1]	auto[0]	others[3]	1710	1			T5	1		T30	4		T46	7
auto[1]	auto[0]	interest[1]	1018	1			T30	3		T34	2		T46	2
auto[1]	auto[0]	interest[4]	5959	1			T5	4		T13	1		T30	13
auto[1]	auto[0]	interest[64]	3038	1			T30	10		T34	3		T46	13

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal