Unified Coverage Report :: Cond split page

Go back

 LINE       19544
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T12,T14,T29

 LINE       19544
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T45,T60,T34

 LINE       19544
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T14,T45,T55

 LINE       19544
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T12,T14,T55

 LINE       19544
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T12,T116,T55

 LINE       19544
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T13,T55,T32

 LINE       19544
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T16,T45,T60

 LINE       19544
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T3,T14,T16

 LINE       19544
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T13,T14,T116

 LINE       19544
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T12,T14,T16

 LINE       19544
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T3,T45,T55

 LINE       19544
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T12,T16,T55

 LINE       19544
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T13,T14,T55

 LINE       19544
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T14,T116,T55

 LINE       19544
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T12,T13,T14

 LINE       19544
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T14,T55,T57

 LINE       19544
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T12,T116,T55

 LINE       19544
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T45,T116,T55

 LINE       19544
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T12,T14,T29

 LINE       19544
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T14,T16,T60

 LINE       19544
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T11,T12
1	1	Covered	T12,T14,T116

 LINE       19544
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T12,T14,T55

 LINE       19544
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T12,T14,T116

 LINE       19544
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T13,T14,T57

 LINE       19544
 SUB-EXPRESSION (addr_hit[43] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T12,T116,T29

 LINE       19544
 SUB-EXPRESSION (addr_hit[44] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T16,T116,T55

 LINE       19544
 SUB-EXPRESSION (addr_hit[45] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T12,T55,T91

 LINE       19544
 SUB-EXPRESSION (addr_hit[46] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T14,T116,T60

 LINE       19544
 SUB-EXPRESSION (addr_hit[47] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T12,T14,T57

 LINE       19544
 SUB-EXPRESSION (addr_hit[48] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T12,T55,T91

 LINE       19544
 SUB-EXPRESSION (addr_hit[49] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T14,T116,T60

 LINE       19544
 SUB-EXPRESSION (addr_hit[50] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T12,T14,T60

 LINE       19544
 SUB-EXPRESSION (addr_hit[51] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T12,T16,T45

 LINE       19544
 SUB-EXPRESSION (addr_hit[52] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T16,T116,T57

 LINE       19544
 SUB-EXPRESSION (addr_hit[53] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T12,T14,T16

 LINE       19544
 SUB-EXPRESSION (addr_hit[54] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T11,T12,T14
1	1	Covered	T14,T16,T55

 LINE       19544
 SUB-EXPRESSION (addr_hit[55] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T12,T16,T55
1	1	Covered	T12,T29,T57

 LINE       19544
 SUB-EXPRESSION (addr_hit[56] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T12,T16,T55
1	1	Covered	T14,T16,T116

 LINE       19544
 SUB-EXPRESSION (addr_hit[57] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T12,T60,T92
1	1	Covered	T116,T57,T60

 LINE       19544
 SUB-EXPRESSION (addr_hit[58] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T12,T60,T34
1	1	Covered	T13,T116,T57

 LINE       19544
 SUB-EXPRESSION (addr_hit[59] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T34,T59,T125
1	1	Covered	T6,T14,T16

 LINE       19544
 SUB-EXPRESSION (addr_hit[60] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T4,T5,T10
1	1	Covered	T12,T13,T55

 LINE       19544
 SUB-EXPRESSION (addr_hit[61] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T5,T13,T14
1	1	Covered	T16,T116,T91

 LINE       19544
 SUB-EXPRESSION (addr_hit[62] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T14,T27
1	1	Covered	T14,T60,T34

 LINE       19544
 SUB-EXPRESSION (addr_hit[63] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T4,T27,T28
1	1	Covered	T16,T57,T91

 LINE       19544
 SUB-EXPRESSION (addr_hit[64] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T27,T28
1	1	Covered	T12,T14,T16

 LINE       19544
 SUB-EXPRESSION (addr_hit[65] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T28,T29,T30
1	1	Covered	T45,T55,T60

 LINE       19544
 SUB-EXPRESSION (addr_hit[66] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T28,T29,T30
1	1	Covered	T13,T14,T16

 LINE       19544
 SUB-EXPRESSION (addr_hit[67] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T28,T116,T29
1	1	Covered	T12,T14,T116

 LINE       19544
 SUB-EXPRESSION (addr_hit[68] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T28,T29,T30
1	1	Covered	T14,T60,T34

 LINE       19544
 SUB-EXPRESSION (addr_hit[69] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T16,T28,T29
1	1	Covered	T3,T60,T34

 LINE       19544
 SUB-EXPRESSION (addr_hit[70] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T12,T14,T28
1	1	Covered	T12,T14,T60

 LINE       19544
 SUB-EXPRESSION (addr_hit[71] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T5,T13,T30
1	1	Covered	T5,T12,T13

 LINE       19544
 SUB-EXPRESSION (addr_hit[72] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T5,T12,T13
1	1	Covered	T16,T91,T46

 LINE       19621
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T118,T121,T126
1	1	1	Covered	T5,T13,T21

 LINE       19636
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T57,T24,T34
1	1	0	Covered	T118,T119,T121
1	1	1	Covered	T24,T35,T38

 LINE       19653
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T14,T29,T57
1	1	0	Covered	T118,T119,T126
1	1	1	Covered	T24,T35,T38

 LINE       19670
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T10
1	0	1	Covered	T6,T14,T16
1	1	0	Covered	T121,T126,T127
1	1	1	Covered	T6,T41,T98

 LINE       19673
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T14
1	1	0	Covered	T119,T126,T128
1	1	1	Covered	T11,T12,T14

 LINE       19680
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T15
1	1	0	Covered	T119,T121,T126
1	1	1	Covered	T11,T15,T16

 LINE       19687
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T7,T12
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T20

 LINE       19688
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T3,T12,T14
1	1	0	Covered	T118,T119,T126
1	1	1	Covered	T12,T14,T15

 LINE       19697
 EXPRESSION (addr_hit[8] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T12,T14
1	1	0	Not Covered
1	1	1	Covered	T12,T60,T92

 LINE       19698
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T14
1	1	0	Covered	T119,T126,T129
1	1	1	Covered	T11,T12,T14

 LINE       19701
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T12,T14
1	1	0	Not Covered
1	1	1	Covered	T11,T12,T14

 LINE       19702
 EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T9,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T11,T12,T14

 LINE       19703
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T9,T11,T12
1	1	0	Covered	T119,T121,T126
1	1	1	Covered	T12,T14,T15

 LINE       19710
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T3,T11,T12
1	1	0	Covered	T118,T119,T121
1	1	1	Covered	T11,T12,T14

 LINE       19715
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T14
1	1	0	Covered	T119,T126,T129
1	1	1	Covered	T11,T12,T14

 LINE       19720
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T12,T14,T15
1	1	0	Covered	T121,T126,T129
1	1	1	Covered	T12,T14,T15

 LINE       19723
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T14
1	1	0	Covered	T118,T119,T121
1	1	1	Covered	T11,T12,T14

 LINE       19726
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T12,T61
1	1	0	Not Covered
1	1	1	Covered	T61,T58,T46

 LINE       19727
 EXPRESSION (addr_hit[18] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T57,T32,T61
1	1	0	Not Covered
1	1	1	Covered	T61,T58,T46

 LINE       19728
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T14
1	1	0	Covered	T119,T126,T129
1	1	1	Covered	T11,T12,T14

 LINE       19793
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T14
1	1	0	Covered	T119,T121,T129
1	1	1	Covered	T11,T12,T14

 LINE       19858
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T14
1	1	0	Covered	T127,T130,T131
1	1	1	Covered	T11,T12,T14

 LINE       19923
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T14
1	1	0	Covered	T119,T121,T126
1	1	1	Covered	T11,T12,T14

 LINE       19988
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T14
1	1	0	Covered	T119,T126,T129
1	1	1	Covered	T11,T12,T14

 LINE       20053
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T13
1	1	0	Covered	T118,T119,T121
1	1	1	Covered	T11,T12,T14

 LINE       20118
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T14
1	1	0	Covered	T119,T121,T129
1	1	1	Covered	T11,T12,T14

 LINE       20183
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T3,T11,T12
1	1	0	Covered	T119,T126,T129
1	1	1	Covered	T11,T12,T14

 LINE       20248
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T13
1	1	0	Covered	T118,T119,T121
1	1	1	Covered	T11,T12,T14

 LINE       20251
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T14
1	1	0	Covered	T118,T119,T121
1	1	1	Covered	T11,T12,T14

 LINE       20254
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T3,T11,T12
1	1	0	Covered	T126,T129,T127
1	1	1	Covered	T11,T12,T14

 LINE       20257
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T14
1	1	0	Covered	T119,T121,T129
1	1	1	Covered	T11,T12,T14

 LINE       20260
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T13
1	1	0	Covered	T126,T132,T130
1	1	1	Covered	T11,T12,T14

 LINE       20287
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T14
1	1	0	Covered	T118,T119,T121
1	1	1	Covered	T11,T12,T14

 LINE       20314
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T13
1	1	0	Covered	T121,T126,T129
1	1	1	Covered	T11,T12,T14

 LINE       20341
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T14
1	1	0	Covered	T119,T126,T129
1	1	1	Covered	T11,T12,T14

 LINE       20368
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T14
1	1	0	Covered	T119,T126,T129
1	1	1	Covered	T11,T12,T14

 LINE       20395
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T14
1	1	0	Covered	T119,T121,T132
1	1	1	Covered	T11,T12,T14

 LINE       20422
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T14
1	1	0	Covered	T119,T126,T129
1	1	1	Covered	T11,T12,T14

 LINE       20449
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T14
1	1	0	Covered	T119,T126,T129
1	1	1	Covered	T11,T12,T14

 LINE       20476
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T3,T11,T12
1	1	0	Covered	T118,T119,T121
1	1	1	Covered	T11,T12,T14

 LINE       20503
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T14
1	1	0	Covered	T118,T121,T126
1	1	1	Covered	T11,T12,T14

 LINE       20530
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T11,T12,T14
1	1	0	Covered	T119,T121,T126
1	1	1	Covered	T11,T12,T14