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72 always_ff @(posedge clk_i or negedge rst_ni) begin
73 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
74 1/1 err_q <= '0;
Tests: T1 T2 T3
75 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
76 1/1 err_q <= 1'b1;
Tests: T9 T19 T25
77 end
MISSING_ELSE
78 end
79
80 // integrity error output is permanent and should be used for alert generation
81 // register errors are transactional
82 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T2 T3
83
84 // outgoing integrity generation
85 tlul_pkg::tl_d2h_t tl_o_pre;
86 tlul_rsp_intg_gen #(
87 .EnableRspIntgGen(1),
88 .EnableDataIntgGen(1)
89 ) u_rsp_intg_gen (
90 .tl_i(tl_o_pre),
91 .tl_o(tl_o)
92 );
93
94 tlul_pkg::tl_h2d_t tl_socket_h2d [3];
95 tlul_pkg::tl_d2h_t tl_socket_d2h [3];
96
97 logic [1:0] reg_steer;
98
99 // socket_1n connection
100 1/1 assign tl_reg_h2d = tl_socket_h2d[2];
Tests: T1 T2 T3
101 1/1 assign tl_socket_d2h[2] = tl_reg_d2h;
Tests: T1 T2 T3
102
103 1/1 assign tl_win_o[0] = tl_socket_h2d[0];
Tests: T1 T2 T3
104 1/1 assign tl_socket_d2h[0] = tl_win_i[0];
Tests: T1 T2 T3
105 1/1 assign tl_win_o[1] = tl_socket_h2d[1];
Tests: T1 T2 T3
106 1/1 assign tl_socket_d2h[1] = tl_win_i[1];
Tests: T1 T2 T3
107
108 // Create Socket_1n
109 tlul_socket_1n #(
110 .N (3),
111 .HReqPass (1'b1),
112 .HRspPass (1'b1),
113 .DReqPass ({3{1'b1}}),
114 .DRspPass ({3{1'b1}}),
115 .HReqDepth (4'h0),
116 .HRspDepth (4'h0),
117 .DReqDepth ({3{4'h0}}),
118 .DRspDepth ({3{4'h0}}),
119 .ExplicitErrs (1'b0)
120 ) u_socket (
121 .clk_i (clk_i),
122 .rst_ni (rst_ni),
123 .tl_h_i (tl_i),
124 .tl_h_o (tl_o_pre),
125 .tl_d_o (tl_socket_h2d),
126 .tl_d_i (tl_socket_d2h),
127 .dev_select_i (reg_steer)
128 );
129
130 // Create steering logic
131 always_comb begin
132 1/1 reg_steer =
Tests: T1 T2 T3
133 tl_i.a_address[AW-1:0] inside {[4096:7487]} ? 2'd0 :
134 tl_i.a_address[AW-1:0] inside {[7680:8127]} ? 2'd1 :
135 // Default set to register
136 2'd2;
137
138 // Override this in case of an integrity error
139 1/1 if (intg_err) begin
Tests: T1 T2 T3
140 1/1 reg_steer = 2'd2;
Tests: T122 T123 T124
141 end
MISSING_ELSE
142 end
143
144 tlul_adapter_reg #(
145 .RegAw(AW),
146 .RegDw(DW),
147 .EnableDataIntgGen(0)
148 ) u_reg_if (
149 .clk_i (clk_i),
150 .rst_ni (rst_ni),
151
152 .tl_i (tl_reg_h2d),
153 .tl_o (tl_reg_d2h),
154
155 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
156 .intg_error_o(),
157
158 .we_o (reg_we),
159 .re_o (reg_re),
160 .addr_o (reg_addr),
161 .wdata_o (reg_wdata),
162 .be_o (reg_be),
163 .busy_i (reg_busy),
164 .rdata_i (reg_rdata),
165 .error_i (reg_error)
166 );
167
168 // cdc oversampling signals
169
170 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T1 T2 T3
171 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T1 T2 T4
172
173 // Define SW related signals
174 // Format: <reg>_<field>_{wd|we|qs}
175 // or <reg>_{wd|we|qs} if field == 1 or 0
176 logic intr_state_we;
177 logic intr_state_upload_cmdfifo_not_empty_qs;
178 logic intr_state_upload_cmdfifo_not_empty_wd;
179 logic intr_state_upload_payload_not_empty_qs;
180 logic intr_state_upload_payload_not_empty_wd;
181 logic intr_state_upload_payload_overflow_qs;
182 logic intr_state_upload_payload_overflow_wd;
183 logic intr_state_readbuf_watermark_qs;
184 logic intr_state_readbuf_watermark_wd;
185 logic intr_state_readbuf_flip_qs;
186 logic intr_state_readbuf_flip_wd;
187 logic intr_state_tpm_header_not_empty_qs;
188 logic intr_state_tpm_rdfifo_cmd_end_qs;
189 logic intr_state_tpm_rdfifo_cmd_end_wd;
190 logic intr_state_tpm_rdfifo_drop_qs;
191 logic intr_state_tpm_rdfifo_drop_wd;
192 logic intr_enable_we;
193 logic intr_enable_upload_cmdfifo_not_empty_qs;
194 logic intr_enable_upload_cmdfifo_not_empty_wd;
195 logic intr_enable_upload_payload_not_empty_qs;
196 logic intr_enable_upload_payload_not_empty_wd;
197 logic intr_enable_upload_payload_overflow_qs;
198 logic intr_enable_upload_payload_overflow_wd;
199 logic intr_enable_readbuf_watermark_qs;
200 logic intr_enable_readbuf_watermark_wd;
201 logic intr_enable_readbuf_flip_qs;
202 logic intr_enable_readbuf_flip_wd;
203 logic intr_enable_tpm_header_not_empty_qs;
204 logic intr_enable_tpm_header_not_empty_wd;
205 logic intr_enable_tpm_rdfifo_cmd_end_qs;
206 logic intr_enable_tpm_rdfifo_cmd_end_wd;
207 logic intr_enable_tpm_rdfifo_drop_qs;
208 logic intr_enable_tpm_rdfifo_drop_wd;
209 logic intr_test_we;
210 logic intr_test_upload_cmdfifo_not_empty_wd;
211 logic intr_test_upload_payload_not_empty_wd;
212 logic intr_test_upload_payload_overflow_wd;
213 logic intr_test_readbuf_watermark_wd;
214 logic intr_test_readbuf_flip_wd;
215 logic intr_test_tpm_header_not_empty_wd;
216 logic intr_test_tpm_rdfifo_cmd_end_wd;
217 logic intr_test_tpm_rdfifo_drop_wd;
218 logic alert_test_we;
219 logic alert_test_wd;
220 logic control_we;
221 logic control_flash_status_fifo_clr_qs;
222 logic control_flash_status_fifo_clr_wd;
223 logic control_flash_read_buffer_clr_qs;
224 logic control_flash_read_buffer_clr_wd;
225 logic [1:0] control_mode_qs;
226 logic [1:0] control_mode_wd;
227 logic cfg_we;
228 logic cfg_tx_order_qs;
229 logic cfg_tx_order_wd;
230 logic cfg_rx_order_qs;
231 logic cfg_rx_order_wd;
232 logic cfg_mailbox_en_qs;
233 logic cfg_mailbox_en_wd;
234 logic status_re;
235 logic status_csb_qs;
236 logic status_tpm_csb_qs;
237 logic intercept_en_we;
238 logic intercept_en_status_qs;
239 logic intercept_en_status_wd;
240 logic intercept_en_jedec_qs;
241 logic intercept_en_jedec_wd;
242 logic intercept_en_sfdp_qs;
243 logic intercept_en_sfdp_wd;
244 logic intercept_en_mbx_qs;
245 logic intercept_en_mbx_wd;
246 logic addr_mode_re;
247 logic addr_mode_we;
248 logic addr_mode_addr_4b_en_qs;
249 logic addr_mode_addr_4b_en_wd;
250 logic addr_mode_pending_qs;
251 logic last_read_addr_re;
252 logic [31:0] last_read_addr_qs;
253 logic flash_status_re;
254 logic flash_status_we;
255 logic flash_status_busy_qs;
256 logic flash_status_busy_wd;
257 logic flash_status_wel_qs;
258 logic flash_status_wel_wd;
259 logic [21:0] flash_status_status_qs;
260 logic [21:0] flash_status_status_wd;
261 logic jedec_cc_we;
262 logic [7:0] jedec_cc_cc_qs;
263 logic [7:0] jedec_cc_cc_wd;
264 logic [7:0] jedec_cc_num_cc_qs;
265 logic [7:0] jedec_cc_num_cc_wd;
266 logic jedec_id_we;
267 logic [15:0] jedec_id_id_qs;
268 logic [15:0] jedec_id_id_wd;
269 logic [7:0] jedec_id_mf_qs;
270 logic [7:0] jedec_id_mf_wd;
271 logic read_threshold_we;
272 logic [9:0] read_threshold_qs;
273 logic [9:0] read_threshold_wd;
274 logic mailbox_addr_we;
275 logic [31:0] mailbox_addr_qs;
276 logic [31:0] mailbox_addr_wd;
277 logic [4:0] upload_status_cmdfifo_depth_qs;
278 logic upload_status_cmdfifo_notempty_qs;
279 logic [4:0] upload_status_addrfifo_depth_qs;
280 logic upload_status_addrfifo_notempty_qs;
281 logic [8:0] upload_status2_payload_depth_qs;
282 logic [7:0] upload_status2_payload_start_idx_qs;
283 logic upload_cmdfifo_re;
284 logic [7:0] upload_cmdfifo_data_qs;
285 logic upload_cmdfifo_busy_qs;
286 logic upload_cmdfifo_wel_qs;
287 logic upload_cmdfifo_addr4b_mode_qs;
288 logic upload_addrfifo_re;
289 logic [31:0] upload_addrfifo_qs;
290 logic cmd_filter_0_we;
291 logic cmd_filter_0_filter_0_qs;
292 logic cmd_filter_0_filter_0_wd;
293 logic cmd_filter_0_filter_1_qs;
294 logic cmd_filter_0_filter_1_wd;
295 logic cmd_filter_0_filter_2_qs;
296 logic cmd_filter_0_filter_2_wd;
297 logic cmd_filter_0_filter_3_qs;
298 logic cmd_filter_0_filter_3_wd;
299 logic cmd_filter_0_filter_4_qs;
300 logic cmd_filter_0_filter_4_wd;
301 logic cmd_filter_0_filter_5_qs;
302 logic cmd_filter_0_filter_5_wd;
303 logic cmd_filter_0_filter_6_qs;
304 logic cmd_filter_0_filter_6_wd;
305 logic cmd_filter_0_filter_7_qs;
306 logic cmd_filter_0_filter_7_wd;
307 logic cmd_filter_0_filter_8_qs;
308 logic cmd_filter_0_filter_8_wd;
309 logic cmd_filter_0_filter_9_qs;
310 logic cmd_filter_0_filter_9_wd;
311 logic cmd_filter_0_filter_10_qs;
312 logic cmd_filter_0_filter_10_wd;
313 logic cmd_filter_0_filter_11_qs;
314 logic cmd_filter_0_filter_11_wd;
315 logic cmd_filter_0_filter_12_qs;
316 logic cmd_filter_0_filter_12_wd;
317 logic cmd_filter_0_filter_13_qs;
318 logic cmd_filter_0_filter_13_wd;
319 logic cmd_filter_0_filter_14_qs;
320 logic cmd_filter_0_filter_14_wd;
321 logic cmd_filter_0_filter_15_qs;
322 logic cmd_filter_0_filter_15_wd;
323 logic cmd_filter_0_filter_16_qs;
324 logic cmd_filter_0_filter_16_wd;
325 logic cmd_filter_0_filter_17_qs;
326 logic cmd_filter_0_filter_17_wd;
327 logic cmd_filter_0_filter_18_qs;
328 logic cmd_filter_0_filter_18_wd;
329 logic cmd_filter_0_filter_19_qs;
330 logic cmd_filter_0_filter_19_wd;
331 logic cmd_filter_0_filter_20_qs;
332 logic cmd_filter_0_filter_20_wd;
333 logic cmd_filter_0_filter_21_qs;
334 logic cmd_filter_0_filter_21_wd;
335 logic cmd_filter_0_filter_22_qs;
336 logic cmd_filter_0_filter_22_wd;
337 logic cmd_filter_0_filter_23_qs;
338 logic cmd_filter_0_filter_23_wd;
339 logic cmd_filter_0_filter_24_qs;
340 logic cmd_filter_0_filter_24_wd;
341 logic cmd_filter_0_filter_25_qs;
342 logic cmd_filter_0_filter_25_wd;
343 logic cmd_filter_0_filter_26_qs;
344 logic cmd_filter_0_filter_26_wd;
345 logic cmd_filter_0_filter_27_qs;
346 logic cmd_filter_0_filter_27_wd;
347 logic cmd_filter_0_filter_28_qs;
348 logic cmd_filter_0_filter_28_wd;
349 logic cmd_filter_0_filter_29_qs;
350 logic cmd_filter_0_filter_29_wd;
351 logic cmd_filter_0_filter_30_qs;
352 logic cmd_filter_0_filter_30_wd;
353 logic cmd_filter_0_filter_31_qs;
354 logic cmd_filter_0_filter_31_wd;
355 logic cmd_filter_1_we;
356 logic cmd_filter_1_filter_32_qs;
357 logic cmd_filter_1_filter_32_wd;
358 logic cmd_filter_1_filter_33_qs;
359 logic cmd_filter_1_filter_33_wd;
360 logic cmd_filter_1_filter_34_qs;
361 logic cmd_filter_1_filter_34_wd;
362 logic cmd_filter_1_filter_35_qs;
363 logic cmd_filter_1_filter_35_wd;
364 logic cmd_filter_1_filter_36_qs;
365 logic cmd_filter_1_filter_36_wd;
366 logic cmd_filter_1_filter_37_qs;
367 logic cmd_filter_1_filter_37_wd;
368 logic cmd_filter_1_filter_38_qs;
369 logic cmd_filter_1_filter_38_wd;
370 logic cmd_filter_1_filter_39_qs;
371 logic cmd_filter_1_filter_39_wd;
372 logic cmd_filter_1_filter_40_qs;
373 logic cmd_filter_1_filter_40_wd;
374 logic cmd_filter_1_filter_41_qs;
375 logic cmd_filter_1_filter_41_wd;
376 logic cmd_filter_1_filter_42_qs;
377 logic cmd_filter_1_filter_42_wd;
378 logic cmd_filter_1_filter_43_qs;
379 logic cmd_filter_1_filter_43_wd;
380 logic cmd_filter_1_filter_44_qs;
381 logic cmd_filter_1_filter_44_wd;
382 logic cmd_filter_1_filter_45_qs;
383 logic cmd_filter_1_filter_45_wd;
384 logic cmd_filter_1_filter_46_qs;
385 logic cmd_filter_1_filter_46_wd;
386 logic cmd_filter_1_filter_47_qs;
387 logic cmd_filter_1_filter_47_wd;
388 logic cmd_filter_1_filter_48_qs;
389 logic cmd_filter_1_filter_48_wd;
390 logic cmd_filter_1_filter_49_qs;
391 logic cmd_filter_1_filter_49_wd;
392 logic cmd_filter_1_filter_50_qs;
393 logic cmd_filter_1_filter_50_wd;
394 logic cmd_filter_1_filter_51_qs;
395 logic cmd_filter_1_filter_51_wd;
396 logic cmd_filter_1_filter_52_qs;
397 logic cmd_filter_1_filter_52_wd;
398 logic cmd_filter_1_filter_53_qs;
399 logic cmd_filter_1_filter_53_wd;
400 logic cmd_filter_1_filter_54_qs;
401 logic cmd_filter_1_filter_54_wd;
402 logic cmd_filter_1_filter_55_qs;
403 logic cmd_filter_1_filter_55_wd;
404 logic cmd_filter_1_filter_56_qs;
405 logic cmd_filter_1_filter_56_wd;
406 logic cmd_filter_1_filter_57_qs;
407 logic cmd_filter_1_filter_57_wd;
408 logic cmd_filter_1_filter_58_qs;
409 logic cmd_filter_1_filter_58_wd;
410 logic cmd_filter_1_filter_59_qs;
411 logic cmd_filter_1_filter_59_wd;
412 logic cmd_filter_1_filter_60_qs;
413 logic cmd_filter_1_filter_60_wd;
414 logic cmd_filter_1_filter_61_qs;
415 logic cmd_filter_1_filter_61_wd;
416 logic cmd_filter_1_filter_62_qs;
417 logic cmd_filter_1_filter_62_wd;
418 logic cmd_filter_1_filter_63_qs;
419 logic cmd_filter_1_filter_63_wd;
420 logic cmd_filter_2_we;
421 logic cmd_filter_2_filter_64_qs;
422 logic cmd_filter_2_filter_64_wd;
423 logic cmd_filter_2_filter_65_qs;
424 logic cmd_filter_2_filter_65_wd;
425 logic cmd_filter_2_filter_66_qs;
426 logic cmd_filter_2_filter_66_wd;
427 logic cmd_filter_2_filter_67_qs;
428 logic cmd_filter_2_filter_67_wd;
429 logic cmd_filter_2_filter_68_qs;
430 logic cmd_filter_2_filter_68_wd;
431 logic cmd_filter_2_filter_69_qs;
432 logic cmd_filter_2_filter_69_wd;
433 logic cmd_filter_2_filter_70_qs;
434 logic cmd_filter_2_filter_70_wd;
435 logic cmd_filter_2_filter_71_qs;
436 logic cmd_filter_2_filter_71_wd;
437 logic cmd_filter_2_filter_72_qs;
438 logic cmd_filter_2_filter_72_wd;
439 logic cmd_filter_2_filter_73_qs;
440 logic cmd_filter_2_filter_73_wd;
441 logic cmd_filter_2_filter_74_qs;
442 logic cmd_filter_2_filter_74_wd;
443 logic cmd_filter_2_filter_75_qs;
444 logic cmd_filter_2_filter_75_wd;
445 logic cmd_filter_2_filter_76_qs;
446 logic cmd_filter_2_filter_76_wd;
447 logic cmd_filter_2_filter_77_qs;
448 logic cmd_filter_2_filter_77_wd;
449 logic cmd_filter_2_filter_78_qs;
450 logic cmd_filter_2_filter_78_wd;
451 logic cmd_filter_2_filter_79_qs;
452 logic cmd_filter_2_filter_79_wd;
453 logic cmd_filter_2_filter_80_qs;
454 logic cmd_filter_2_filter_80_wd;
455 logic cmd_filter_2_filter_81_qs;
456 logic cmd_filter_2_filter_81_wd;
457 logic cmd_filter_2_filter_82_qs;
458 logic cmd_filter_2_filter_82_wd;
459 logic cmd_filter_2_filter_83_qs;
460 logic cmd_filter_2_filter_83_wd;
461 logic cmd_filter_2_filter_84_qs;
462 logic cmd_filter_2_filter_84_wd;
463 logic cmd_filter_2_filter_85_qs;
464 logic cmd_filter_2_filter_85_wd;
465 logic cmd_filter_2_filter_86_qs;
466 logic cmd_filter_2_filter_86_wd;
467 logic cmd_filter_2_filter_87_qs;
468 logic cmd_filter_2_filter_87_wd;
469 logic cmd_filter_2_filter_88_qs;
470 logic cmd_filter_2_filter_88_wd;
471 logic cmd_filter_2_filter_89_qs;
472 logic cmd_filter_2_filter_89_wd;
473 logic cmd_filter_2_filter_90_qs;
474 logic cmd_filter_2_filter_90_wd;
475 logic cmd_filter_2_filter_91_qs;
476 logic cmd_filter_2_filter_91_wd;
477 logic cmd_filter_2_filter_92_qs;
478 logic cmd_filter_2_filter_92_wd;
479 logic cmd_filter_2_filter_93_qs;
480 logic cmd_filter_2_filter_93_wd;
481 logic cmd_filter_2_filter_94_qs;
482 logic cmd_filter_2_filter_94_wd;
483 logic cmd_filter_2_filter_95_qs;
484 logic cmd_filter_2_filter_95_wd;
485 logic cmd_filter_3_we;
486 logic cmd_filter_3_filter_96_qs;
487 logic cmd_filter_3_filter_96_wd;
488 logic cmd_filter_3_filter_97_qs;
489 logic cmd_filter_3_filter_97_wd;
490 logic cmd_filter_3_filter_98_qs;
491 logic cmd_filter_3_filter_98_wd;
492 logic cmd_filter_3_filter_99_qs;
493 logic cmd_filter_3_filter_99_wd;
494 logic cmd_filter_3_filter_100_qs;
495 logic cmd_filter_3_filter_100_wd;
496 logic cmd_filter_3_filter_101_qs;
497 logic cmd_filter_3_filter_101_wd;
498 logic cmd_filter_3_filter_102_qs;
499 logic cmd_filter_3_filter_102_wd;
500 logic cmd_filter_3_filter_103_qs;
501 logic cmd_filter_3_filter_103_wd;
502 logic cmd_filter_3_filter_104_qs;
503 logic cmd_filter_3_filter_104_wd;
504 logic cmd_filter_3_filter_105_qs;
505 logic cmd_filter_3_filter_105_wd;
506 logic cmd_filter_3_filter_106_qs;
507 logic cmd_filter_3_filter_106_wd;
508 logic cmd_filter_3_filter_107_qs;
509 logic cmd_filter_3_filter_107_wd;
510 logic cmd_filter_3_filter_108_qs;
511 logic cmd_filter_3_filter_108_wd;
512 logic cmd_filter_3_filter_109_qs;
513 logic cmd_filter_3_filter_109_wd;
514 logic cmd_filter_3_filter_110_qs;
515 logic cmd_filter_3_filter_110_wd;
516 logic cmd_filter_3_filter_111_qs;
517 logic cmd_filter_3_filter_111_wd;
518 logic cmd_filter_3_filter_112_qs;
519 logic cmd_filter_3_filter_112_wd;
520 logic cmd_filter_3_filter_113_qs;
521 logic cmd_filter_3_filter_113_wd;
522 logic cmd_filter_3_filter_114_qs;
523 logic cmd_filter_3_filter_114_wd;
524 logic cmd_filter_3_filter_115_qs;
525 logic cmd_filter_3_filter_115_wd;
526 logic cmd_filter_3_filter_116_qs;
527 logic cmd_filter_3_filter_116_wd;
528 logic cmd_filter_3_filter_117_qs;
529 logic cmd_filter_3_filter_117_wd;
530 logic cmd_filter_3_filter_118_qs;
531 logic cmd_filter_3_filter_118_wd;
532 logic cmd_filter_3_filter_119_qs;
533 logic cmd_filter_3_filter_119_wd;
534 logic cmd_filter_3_filter_120_qs;
535 logic cmd_filter_3_filter_120_wd;
536 logic cmd_filter_3_filter_121_qs;
537 logic cmd_filter_3_filter_121_wd;
538 logic cmd_filter_3_filter_122_qs;
539 logic cmd_filter_3_filter_122_wd;
540 logic cmd_filter_3_filter_123_qs;
541 logic cmd_filter_3_filter_123_wd;
542 logic cmd_filter_3_filter_124_qs;
543 logic cmd_filter_3_filter_124_wd;
544 logic cmd_filter_3_filter_125_qs;
545 logic cmd_filter_3_filter_125_wd;
546 logic cmd_filter_3_filter_126_qs;
547 logic cmd_filter_3_filter_126_wd;
548 logic cmd_filter_3_filter_127_qs;
549 logic cmd_filter_3_filter_127_wd;
550 logic cmd_filter_4_we;
551 logic cmd_filter_4_filter_128_qs;
552 logic cmd_filter_4_filter_128_wd;
553 logic cmd_filter_4_filter_129_qs;
554 logic cmd_filter_4_filter_129_wd;
555 logic cmd_filter_4_filter_130_qs;
556 logic cmd_filter_4_filter_130_wd;
557 logic cmd_filter_4_filter_131_qs;
558 logic cmd_filter_4_filter_131_wd;
559 logic cmd_filter_4_filter_132_qs;
560 logic cmd_filter_4_filter_132_wd;
561 logic cmd_filter_4_filter_133_qs;
562 logic cmd_filter_4_filter_133_wd;
563 logic cmd_filter_4_filter_134_qs;
564 logic cmd_filter_4_filter_134_wd;
565 logic cmd_filter_4_filter_135_qs;
566 logic cmd_filter_4_filter_135_wd;
567 logic cmd_filter_4_filter_136_qs;
568 logic cmd_filter_4_filter_136_wd;
569 logic cmd_filter_4_filter_137_qs;
570 logic cmd_filter_4_filter_137_wd;
571 logic cmd_filter_4_filter_138_qs;
572 logic cmd_filter_4_filter_138_wd;
573 logic cmd_filter_4_filter_139_qs;
574 logic cmd_filter_4_filter_139_wd;
575 logic cmd_filter_4_filter_140_qs;
576 logic cmd_filter_4_filter_140_wd;
577 logic cmd_filter_4_filter_141_qs;
578 logic cmd_filter_4_filter_141_wd;
579 logic cmd_filter_4_filter_142_qs;
580 logic cmd_filter_4_filter_142_wd;
581 logic cmd_filter_4_filter_143_qs;
582 logic cmd_filter_4_filter_143_wd;
583 logic cmd_filter_4_filter_144_qs;
584 logic cmd_filter_4_filter_144_wd;
585 logic cmd_filter_4_filter_145_qs;
586 logic cmd_filter_4_filter_145_wd;
587 logic cmd_filter_4_filter_146_qs;
588 logic cmd_filter_4_filter_146_wd;
589 logic cmd_filter_4_filter_147_qs;
590 logic cmd_filter_4_filter_147_wd;
591 logic cmd_filter_4_filter_148_qs;
592 logic cmd_filter_4_filter_148_wd;
593 logic cmd_filter_4_filter_149_qs;
594 logic cmd_filter_4_filter_149_wd;
595 logic cmd_filter_4_filter_150_qs;
596 logic cmd_filter_4_filter_150_wd;
597 logic cmd_filter_4_filter_151_qs;
598 logic cmd_filter_4_filter_151_wd;
599 logic cmd_filter_4_filter_152_qs;
600 logic cmd_filter_4_filter_152_wd;
601 logic cmd_filter_4_filter_153_qs;
602 logic cmd_filter_4_filter_153_wd;
603 logic cmd_filter_4_filter_154_qs;
604 logic cmd_filter_4_filter_154_wd;
605 logic cmd_filter_4_filter_155_qs;
606 logic cmd_filter_4_filter_155_wd;
607 logic cmd_filter_4_filter_156_qs;
608 logic cmd_filter_4_filter_156_wd;
609 logic cmd_filter_4_filter_157_qs;
610 logic cmd_filter_4_filter_157_wd;
611 logic cmd_filter_4_filter_158_qs;
612 logic cmd_filter_4_filter_158_wd;
613 logic cmd_filter_4_filter_159_qs;
614 logic cmd_filter_4_filter_159_wd;
615 logic cmd_filter_5_we;
616 logic cmd_filter_5_filter_160_qs;
617 logic cmd_filter_5_filter_160_wd;
618 logic cmd_filter_5_filter_161_qs;
619 logic cmd_filter_5_filter_161_wd;
620 logic cmd_filter_5_filter_162_qs;
621 logic cmd_filter_5_filter_162_wd;
622 logic cmd_filter_5_filter_163_qs;
623 logic cmd_filter_5_filter_163_wd;
624 logic cmd_filter_5_filter_164_qs;
625 logic cmd_filter_5_filter_164_wd;
626 logic cmd_filter_5_filter_165_qs;
627 logic cmd_filter_5_filter_165_wd;
628 logic cmd_filter_5_filter_166_qs;
629 logic cmd_filter_5_filter_166_wd;
630 logic cmd_filter_5_filter_167_qs;
631 logic cmd_filter_5_filter_167_wd;
632 logic cmd_filter_5_filter_168_qs;
633 logic cmd_filter_5_filter_168_wd;
634 logic cmd_filter_5_filter_169_qs;
635 logic cmd_filter_5_filter_169_wd;
636 logic cmd_filter_5_filter_170_qs;
637 logic cmd_filter_5_filter_170_wd;
638 logic cmd_filter_5_filter_171_qs;
639 logic cmd_filter_5_filter_171_wd;
640 logic cmd_filter_5_filter_172_qs;
641 logic cmd_filter_5_filter_172_wd;
642 logic cmd_filter_5_filter_173_qs;
643 logic cmd_filter_5_filter_173_wd;
644 logic cmd_filter_5_filter_174_qs;
645 logic cmd_filter_5_filter_174_wd;
646 logic cmd_filter_5_filter_175_qs;
647 logic cmd_filter_5_filter_175_wd;
648 logic cmd_filter_5_filter_176_qs;
649 logic cmd_filter_5_filter_176_wd;
650 logic cmd_filter_5_filter_177_qs;
651 logic cmd_filter_5_filter_177_wd;
652 logic cmd_filter_5_filter_178_qs;
653 logic cmd_filter_5_filter_178_wd;
654 logic cmd_filter_5_filter_179_qs;
655 logic cmd_filter_5_filter_179_wd;
656 logic cmd_filter_5_filter_180_qs;
657 logic cmd_filter_5_filter_180_wd;
658 logic cmd_filter_5_filter_181_qs;
659 logic cmd_filter_5_filter_181_wd;
660 logic cmd_filter_5_filter_182_qs;
661 logic cmd_filter_5_filter_182_wd;
662 logic cmd_filter_5_filter_183_qs;
663 logic cmd_filter_5_filter_183_wd;
664 logic cmd_filter_5_filter_184_qs;
665 logic cmd_filter_5_filter_184_wd;
666 logic cmd_filter_5_filter_185_qs;
667 logic cmd_filter_5_filter_185_wd;
668 logic cmd_filter_5_filter_186_qs;
669 logic cmd_filter_5_filter_186_wd;
670 logic cmd_filter_5_filter_187_qs;
671 logic cmd_filter_5_filter_187_wd;
672 logic cmd_filter_5_filter_188_qs;
673 logic cmd_filter_5_filter_188_wd;
674 logic cmd_filter_5_filter_189_qs;
675 logic cmd_filter_5_filter_189_wd;
676 logic cmd_filter_5_filter_190_qs;
677 logic cmd_filter_5_filter_190_wd;
678 logic cmd_filter_5_filter_191_qs;
679 logic cmd_filter_5_filter_191_wd;
680 logic cmd_filter_6_we;
681 logic cmd_filter_6_filter_192_qs;
682 logic cmd_filter_6_filter_192_wd;
683 logic cmd_filter_6_filter_193_qs;
684 logic cmd_filter_6_filter_193_wd;
685 logic cmd_filter_6_filter_194_qs;
686 logic cmd_filter_6_filter_194_wd;
687 logic cmd_filter_6_filter_195_qs;
688 logic cmd_filter_6_filter_195_wd;
689 logic cmd_filter_6_filter_196_qs;
690 logic cmd_filter_6_filter_196_wd;
691 logic cmd_filter_6_filter_197_qs;
692 logic cmd_filter_6_filter_197_wd;
693 logic cmd_filter_6_filter_198_qs;
694 logic cmd_filter_6_filter_198_wd;
695 logic cmd_filter_6_filter_199_qs;
696 logic cmd_filter_6_filter_199_wd;
697 logic cmd_filter_6_filter_200_qs;
698 logic cmd_filter_6_filter_200_wd;
699 logic cmd_filter_6_filter_201_qs;
700 logic cmd_filter_6_filter_201_wd;
701 logic cmd_filter_6_filter_202_qs;
702 logic cmd_filter_6_filter_202_wd;
703 logic cmd_filter_6_filter_203_qs;
704 logic cmd_filter_6_filter_203_wd;
705 logic cmd_filter_6_filter_204_qs;
706 logic cmd_filter_6_filter_204_wd;
707 logic cmd_filter_6_filter_205_qs;
708 logic cmd_filter_6_filter_205_wd;
709 logic cmd_filter_6_filter_206_qs;
710 logic cmd_filter_6_filter_206_wd;
711 logic cmd_filter_6_filter_207_qs;
712 logic cmd_filter_6_filter_207_wd;
713 logic cmd_filter_6_filter_208_qs;
714 logic cmd_filter_6_filter_208_wd;
715 logic cmd_filter_6_filter_209_qs;
716 logic cmd_filter_6_filter_209_wd;
717 logic cmd_filter_6_filter_210_qs;
718 logic cmd_filter_6_filter_210_wd;
719 logic cmd_filter_6_filter_211_qs;
720 logic cmd_filter_6_filter_211_wd;
721 logic cmd_filter_6_filter_212_qs;
722 logic cmd_filter_6_filter_212_wd;
723 logic cmd_filter_6_filter_213_qs;
724 logic cmd_filter_6_filter_213_wd;
725 logic cmd_filter_6_filter_214_qs;
726 logic cmd_filter_6_filter_214_wd;
727 logic cmd_filter_6_filter_215_qs;
728 logic cmd_filter_6_filter_215_wd;
729 logic cmd_filter_6_filter_216_qs;
730 logic cmd_filter_6_filter_216_wd;
731 logic cmd_filter_6_filter_217_qs;
732 logic cmd_filter_6_filter_217_wd;
733 logic cmd_filter_6_filter_218_qs;
734 logic cmd_filter_6_filter_218_wd;
735 logic cmd_filter_6_filter_219_qs;
736 logic cmd_filter_6_filter_219_wd;
737 logic cmd_filter_6_filter_220_qs;
738 logic cmd_filter_6_filter_220_wd;
739 logic cmd_filter_6_filter_221_qs;
740 logic cmd_filter_6_filter_221_wd;
741 logic cmd_filter_6_filter_222_qs;
742 logic cmd_filter_6_filter_222_wd;
743 logic cmd_filter_6_filter_223_qs;
744 logic cmd_filter_6_filter_223_wd;
745 logic cmd_filter_7_we;
746 logic cmd_filter_7_filter_224_qs;
747 logic cmd_filter_7_filter_224_wd;
748 logic cmd_filter_7_filter_225_qs;
749 logic cmd_filter_7_filter_225_wd;
750 logic cmd_filter_7_filter_226_qs;
751 logic cmd_filter_7_filter_226_wd;
752 logic cmd_filter_7_filter_227_qs;
753 logic cmd_filter_7_filter_227_wd;
754 logic cmd_filter_7_filter_228_qs;
755 logic cmd_filter_7_filter_228_wd;
756 logic cmd_filter_7_filter_229_qs;
757 logic cmd_filter_7_filter_229_wd;
758 logic cmd_filter_7_filter_230_qs;
759 logic cmd_filter_7_filter_230_wd;
760 logic cmd_filter_7_filter_231_qs;
761 logic cmd_filter_7_filter_231_wd;
762 logic cmd_filter_7_filter_232_qs;
763 logic cmd_filter_7_filter_232_wd;
764 logic cmd_filter_7_filter_233_qs;
765 logic cmd_filter_7_filter_233_wd;
766 logic cmd_filter_7_filter_234_qs;
767 logic cmd_filter_7_filter_234_wd;
768 logic cmd_filter_7_filter_235_qs;
769 logic cmd_filter_7_filter_235_wd;
770 logic cmd_filter_7_filter_236_qs;
771 logic cmd_filter_7_filter_236_wd;
772 logic cmd_filter_7_filter_237_qs;
773 logic cmd_filter_7_filter_237_wd;
774 logic cmd_filter_7_filter_238_qs;
775 logic cmd_filter_7_filter_238_wd;
776 logic cmd_filter_7_filter_239_qs;
777 logic cmd_filter_7_filter_239_wd;
778 logic cmd_filter_7_filter_240_qs;
779 logic cmd_filter_7_filter_240_wd;
780 logic cmd_filter_7_filter_241_qs;
781 logic cmd_filter_7_filter_241_wd;
782 logic cmd_filter_7_filter_242_qs;
783 logic cmd_filter_7_filter_242_wd;
784 logic cmd_filter_7_filter_243_qs;
785 logic cmd_filter_7_filter_243_wd;
786 logic cmd_filter_7_filter_244_qs;
787 logic cmd_filter_7_filter_244_wd;
788 logic cmd_filter_7_filter_245_qs;
789 logic cmd_filter_7_filter_245_wd;
790 logic cmd_filter_7_filter_246_qs;
791 logic cmd_filter_7_filter_246_wd;
792 logic cmd_filter_7_filter_247_qs;
793 logic cmd_filter_7_filter_247_wd;
794 logic cmd_filter_7_filter_248_qs;
795 logic cmd_filter_7_filter_248_wd;
796 logic cmd_filter_7_filter_249_qs;
797 logic cmd_filter_7_filter_249_wd;
798 logic cmd_filter_7_filter_250_qs;
799 logic cmd_filter_7_filter_250_wd;
800 logic cmd_filter_7_filter_251_qs;
801 logic cmd_filter_7_filter_251_wd;
802 logic cmd_filter_7_filter_252_qs;
803 logic cmd_filter_7_filter_252_wd;
804 logic cmd_filter_7_filter_253_qs;
805 logic cmd_filter_7_filter_253_wd;
806 logic cmd_filter_7_filter_254_qs;
807 logic cmd_filter_7_filter_254_wd;
808 logic cmd_filter_7_filter_255_qs;
809 logic cmd_filter_7_filter_255_wd;
810 logic addr_swap_mask_we;
811 logic [31:0] addr_swap_mask_qs;
812 logic [31:0] addr_swap_mask_wd;
813 logic addr_swap_data_we;
814 logic [31:0] addr_swap_data_qs;
815 logic [31:0] addr_swap_data_wd;
816 logic payload_swap_mask_we;
817 logic [31:0] payload_swap_mask_qs;
818 logic [31:0] payload_swap_mask_wd;
819 logic payload_swap_data_we;
820 logic [31:0] payload_swap_data_qs;
821 logic [31:0] payload_swap_data_wd;
822 logic cmd_info_0_we;
823 logic [7:0] cmd_info_0_opcode_0_qs;
824 logic [7:0] cmd_info_0_opcode_0_wd;
825 logic [1:0] cmd_info_0_addr_mode_0_qs;
826 logic [1:0] cmd_info_0_addr_mode_0_wd;
827 logic cmd_info_0_addr_swap_en_0_qs;
828 logic cmd_info_0_addr_swap_en_0_wd;
829 logic cmd_info_0_mbyte_en_0_qs;
830 logic cmd_info_0_mbyte_en_0_wd;
831 logic [2:0] cmd_info_0_dummy_size_0_qs;
832 logic [2:0] cmd_info_0_dummy_size_0_wd;
833 logic cmd_info_0_dummy_en_0_qs;
834 logic cmd_info_0_dummy_en_0_wd;
835 logic [3:0] cmd_info_0_payload_en_0_qs;
836 logic [3:0] cmd_info_0_payload_en_0_wd;
837 logic cmd_info_0_payload_dir_0_qs;
838 logic cmd_info_0_payload_dir_0_wd;
839 logic cmd_info_0_payload_swap_en_0_qs;
840 logic cmd_info_0_payload_swap_en_0_wd;
841 logic [1:0] cmd_info_0_read_pipeline_mode_0_qs;
842 logic [1:0] cmd_info_0_read_pipeline_mode_0_wd;
843 logic cmd_info_0_upload_0_qs;
844 logic cmd_info_0_upload_0_wd;
845 logic cmd_info_0_busy_0_qs;
846 logic cmd_info_0_busy_0_wd;
847 logic cmd_info_0_valid_0_qs;
848 logic cmd_info_0_valid_0_wd;
849 logic cmd_info_1_we;
850 logic [7:0] cmd_info_1_opcode_1_qs;
851 logic [7:0] cmd_info_1_opcode_1_wd;
852 logic [1:0] cmd_info_1_addr_mode_1_qs;
853 logic [1:0] cmd_info_1_addr_mode_1_wd;
854 logic cmd_info_1_addr_swap_en_1_qs;
855 logic cmd_info_1_addr_swap_en_1_wd;
856 logic cmd_info_1_mbyte_en_1_qs;
857 logic cmd_info_1_mbyte_en_1_wd;
858 logic [2:0] cmd_info_1_dummy_size_1_qs;
859 logic [2:0] cmd_info_1_dummy_size_1_wd;
860 logic cmd_info_1_dummy_en_1_qs;
861 logic cmd_info_1_dummy_en_1_wd;
862 logic [3:0] cmd_info_1_payload_en_1_qs;
863 logic [3:0] cmd_info_1_payload_en_1_wd;
864 logic cmd_info_1_payload_dir_1_qs;
865 logic cmd_info_1_payload_dir_1_wd;
866 logic cmd_info_1_payload_swap_en_1_qs;
867 logic cmd_info_1_payload_swap_en_1_wd;
868 logic [1:0] cmd_info_1_read_pipeline_mode_1_qs;
869 logic [1:0] cmd_info_1_read_pipeline_mode_1_wd;
870 logic cmd_info_1_upload_1_qs;
871 logic cmd_info_1_upload_1_wd;
872 logic cmd_info_1_busy_1_qs;
873 logic cmd_info_1_busy_1_wd;
874 logic cmd_info_1_valid_1_qs;
875 logic cmd_info_1_valid_1_wd;
876 logic cmd_info_2_we;
877 logic [7:0] cmd_info_2_opcode_2_qs;
878 logic [7:0] cmd_info_2_opcode_2_wd;
879 logic [1:0] cmd_info_2_addr_mode_2_qs;
880 logic [1:0] cmd_info_2_addr_mode_2_wd;
881 logic cmd_info_2_addr_swap_en_2_qs;
882 logic cmd_info_2_addr_swap_en_2_wd;
883 logic cmd_info_2_mbyte_en_2_qs;
884 logic cmd_info_2_mbyte_en_2_wd;
885 logic [2:0] cmd_info_2_dummy_size_2_qs;
886 logic [2:0] cmd_info_2_dummy_size_2_wd;
887 logic cmd_info_2_dummy_en_2_qs;
888 logic cmd_info_2_dummy_en_2_wd;
889 logic [3:0] cmd_info_2_payload_en_2_qs;
890 logic [3:0] cmd_info_2_payload_en_2_wd;
891 logic cmd_info_2_payload_dir_2_qs;
892 logic cmd_info_2_payload_dir_2_wd;
893 logic cmd_info_2_payload_swap_en_2_qs;
894 logic cmd_info_2_payload_swap_en_2_wd;
895 logic [1:0] cmd_info_2_read_pipeline_mode_2_qs;
896 logic [1:0] cmd_info_2_read_pipeline_mode_2_wd;
897 logic cmd_info_2_upload_2_qs;
898 logic cmd_info_2_upload_2_wd;
899 logic cmd_info_2_busy_2_qs;
900 logic cmd_info_2_busy_2_wd;
901 logic cmd_info_2_valid_2_qs;
902 logic cmd_info_2_valid_2_wd;
903 logic cmd_info_3_we;
904 logic [7:0] cmd_info_3_opcode_3_qs;
905 logic [7:0] cmd_info_3_opcode_3_wd;
906 logic [1:0] cmd_info_3_addr_mode_3_qs;
907 logic [1:0] cmd_info_3_addr_mode_3_wd;
908 logic cmd_info_3_addr_swap_en_3_qs;
909 logic cmd_info_3_addr_swap_en_3_wd;
910 logic cmd_info_3_mbyte_en_3_qs;
911 logic cmd_info_3_mbyte_en_3_wd;
912 logic [2:0] cmd_info_3_dummy_size_3_qs;
913 logic [2:0] cmd_info_3_dummy_size_3_wd;
914 logic cmd_info_3_dummy_en_3_qs;
915 logic cmd_info_3_dummy_en_3_wd;
916 logic [3:0] cmd_info_3_payload_en_3_qs;
917 logic [3:0] cmd_info_3_payload_en_3_wd;
918 logic cmd_info_3_payload_dir_3_qs;
919 logic cmd_info_3_payload_dir_3_wd;
920 logic cmd_info_3_payload_swap_en_3_qs;
921 logic cmd_info_3_payload_swap_en_3_wd;
922 logic [1:0] cmd_info_3_read_pipeline_mode_3_qs;
923 logic [1:0] cmd_info_3_read_pipeline_mode_3_wd;
924 logic cmd_info_3_upload_3_qs;
925 logic cmd_info_3_upload_3_wd;
926 logic cmd_info_3_busy_3_qs;
927 logic cmd_info_3_busy_3_wd;
928 logic cmd_info_3_valid_3_qs;
929 logic cmd_info_3_valid_3_wd;
930 logic cmd_info_4_we;
931 logic [7:0] cmd_info_4_opcode_4_qs;
932 logic [7:0] cmd_info_4_opcode_4_wd;
933 logic [1:0] cmd_info_4_addr_mode_4_qs;
934 logic [1:0] cmd_info_4_addr_mode_4_wd;
935 logic cmd_info_4_addr_swap_en_4_qs;
936 logic cmd_info_4_addr_swap_en_4_wd;
937 logic cmd_info_4_mbyte_en_4_qs;
938 logic cmd_info_4_mbyte_en_4_wd;
939 logic [2:0] cmd_info_4_dummy_size_4_qs;
940 logic [2:0] cmd_info_4_dummy_size_4_wd;
941 logic cmd_info_4_dummy_en_4_qs;
942 logic cmd_info_4_dummy_en_4_wd;
943 logic [3:0] cmd_info_4_payload_en_4_qs;
944 logic [3:0] cmd_info_4_payload_en_4_wd;
945 logic cmd_info_4_payload_dir_4_qs;
946 logic cmd_info_4_payload_dir_4_wd;
947 logic cmd_info_4_payload_swap_en_4_qs;
948 logic cmd_info_4_payload_swap_en_4_wd;
949 logic [1:0] cmd_info_4_read_pipeline_mode_4_qs;
950 logic [1:0] cmd_info_4_read_pipeline_mode_4_wd;
951 logic cmd_info_4_upload_4_qs;
952 logic cmd_info_4_upload_4_wd;
953 logic cmd_info_4_busy_4_qs;
954 logic cmd_info_4_busy_4_wd;
955 logic cmd_info_4_valid_4_qs;
956 logic cmd_info_4_valid_4_wd;
957 logic cmd_info_5_we;
958 logic [7:0] cmd_info_5_opcode_5_qs;
959 logic [7:0] cmd_info_5_opcode_5_wd;
960 logic [1:0] cmd_info_5_addr_mode_5_qs;
961 logic [1:0] cmd_info_5_addr_mode_5_wd;
962 logic cmd_info_5_addr_swap_en_5_qs;
963 logic cmd_info_5_addr_swap_en_5_wd;
964 logic cmd_info_5_mbyte_en_5_qs;
965 logic cmd_info_5_mbyte_en_5_wd;
966 logic [2:0] cmd_info_5_dummy_size_5_qs;
967 logic [2:0] cmd_info_5_dummy_size_5_wd;
968 logic cmd_info_5_dummy_en_5_qs;
969 logic cmd_info_5_dummy_en_5_wd;
970 logic [3:0] cmd_info_5_payload_en_5_qs;
971 logic [3:0] cmd_info_5_payload_en_5_wd;
972 logic cmd_info_5_payload_dir_5_qs;
973 logic cmd_info_5_payload_dir_5_wd;
974 logic cmd_info_5_payload_swap_en_5_qs;
975 logic cmd_info_5_payload_swap_en_5_wd;
976 logic [1:0] cmd_info_5_read_pipeline_mode_5_qs;
977 logic [1:0] cmd_info_5_read_pipeline_mode_5_wd;
978 logic cmd_info_5_upload_5_qs;
979 logic cmd_info_5_upload_5_wd;
980 logic cmd_info_5_busy_5_qs;
981 logic cmd_info_5_busy_5_wd;
982 logic cmd_info_5_valid_5_qs;
983 logic cmd_info_5_valid_5_wd;
984 logic cmd_info_6_we;
985 logic [7:0] cmd_info_6_opcode_6_qs;
986 logic [7:0] cmd_info_6_opcode_6_wd;
987 logic [1:0] cmd_info_6_addr_mode_6_qs;
988 logic [1:0] cmd_info_6_addr_mode_6_wd;
989 logic cmd_info_6_addr_swap_en_6_qs;
990 logic cmd_info_6_addr_swap_en_6_wd;
991 logic cmd_info_6_mbyte_en_6_qs;
992 logic cmd_info_6_mbyte_en_6_wd;
993 logic [2:0] cmd_info_6_dummy_size_6_qs;
994 logic [2:0] cmd_info_6_dummy_size_6_wd;
995 logic cmd_info_6_dummy_en_6_qs;
996 logic cmd_info_6_dummy_en_6_wd;
997 logic [3:0] cmd_info_6_payload_en_6_qs;
998 logic [3:0] cmd_info_6_payload_en_6_wd;
999 logic cmd_info_6_payload_dir_6_qs;
1000 logic cmd_info_6_payload_dir_6_wd;
1001 logic cmd_info_6_payload_swap_en_6_qs;
1002 logic cmd_info_6_payload_swap_en_6_wd;
1003 logic [1:0] cmd_info_6_read_pipeline_mode_6_qs;
1004 logic [1:0] cmd_info_6_read_pipeline_mode_6_wd;
1005 logic cmd_info_6_upload_6_qs;
1006 logic cmd_info_6_upload_6_wd;
1007 logic cmd_info_6_busy_6_qs;
1008 logic cmd_info_6_busy_6_wd;
1009 logic cmd_info_6_valid_6_qs;
1010 logic cmd_info_6_valid_6_wd;
1011 logic cmd_info_7_we;
1012 logic [7:0] cmd_info_7_opcode_7_qs;
1013 logic [7:0] cmd_info_7_opcode_7_wd;
1014 logic [1:0] cmd_info_7_addr_mode_7_qs;
1015 logic [1:0] cmd_info_7_addr_mode_7_wd;
1016 logic cmd_info_7_addr_swap_en_7_qs;
1017 logic cmd_info_7_addr_swap_en_7_wd;
1018 logic cmd_info_7_mbyte_en_7_qs;
1019 logic cmd_info_7_mbyte_en_7_wd;
1020 logic [2:0] cmd_info_7_dummy_size_7_qs;
1021 logic [2:0] cmd_info_7_dummy_size_7_wd;
1022 logic cmd_info_7_dummy_en_7_qs;
1023 logic cmd_info_7_dummy_en_7_wd;
1024 logic [3:0] cmd_info_7_payload_en_7_qs;
1025 logic [3:0] cmd_info_7_payload_en_7_wd;
1026 logic cmd_info_7_payload_dir_7_qs;
1027 logic cmd_info_7_payload_dir_7_wd;
1028 logic cmd_info_7_payload_swap_en_7_qs;
1029 logic cmd_info_7_payload_swap_en_7_wd;
1030 logic [1:0] cmd_info_7_read_pipeline_mode_7_qs;
1031 logic [1:0] cmd_info_7_read_pipeline_mode_7_wd;
1032 logic cmd_info_7_upload_7_qs;
1033 logic cmd_info_7_upload_7_wd;
1034 logic cmd_info_7_busy_7_qs;
1035 logic cmd_info_7_busy_7_wd;
1036 logic cmd_info_7_valid_7_qs;
1037 logic cmd_info_7_valid_7_wd;
1038 logic cmd_info_8_we;
1039 logic [7:0] cmd_info_8_opcode_8_qs;
1040 logic [7:0] cmd_info_8_opcode_8_wd;
1041 logic [1:0] cmd_info_8_addr_mode_8_qs;
1042 logic [1:0] cmd_info_8_addr_mode_8_wd;
1043 logic cmd_info_8_addr_swap_en_8_qs;
1044 logic cmd_info_8_addr_swap_en_8_wd;
1045 logic cmd_info_8_mbyte_en_8_qs;
1046 logic cmd_info_8_mbyte_en_8_wd;
1047 logic [2:0] cmd_info_8_dummy_size_8_qs;
1048 logic [2:0] cmd_info_8_dummy_size_8_wd;
1049 logic cmd_info_8_dummy_en_8_qs;
1050 logic cmd_info_8_dummy_en_8_wd;
1051 logic [3:0] cmd_info_8_payload_en_8_qs;
1052 logic [3:0] cmd_info_8_payload_en_8_wd;
1053 logic cmd_info_8_payload_dir_8_qs;
1054 logic cmd_info_8_payload_dir_8_wd;
1055 logic cmd_info_8_payload_swap_en_8_qs;
1056 logic cmd_info_8_payload_swap_en_8_wd;
1057 logic [1:0] cmd_info_8_read_pipeline_mode_8_qs;
1058 logic [1:0] cmd_info_8_read_pipeline_mode_8_wd;
1059 logic cmd_info_8_upload_8_qs;
1060 logic cmd_info_8_upload_8_wd;
1061 logic cmd_info_8_busy_8_qs;
1062 logic cmd_info_8_busy_8_wd;
1063 logic cmd_info_8_valid_8_qs;
1064 logic cmd_info_8_valid_8_wd;
1065 logic cmd_info_9_we;
1066 logic [7:0] cmd_info_9_opcode_9_qs;
1067 logic [7:0] cmd_info_9_opcode_9_wd;
1068 logic [1:0] cmd_info_9_addr_mode_9_qs;
1069 logic [1:0] cmd_info_9_addr_mode_9_wd;
1070 logic cmd_info_9_addr_swap_en_9_qs;
1071 logic cmd_info_9_addr_swap_en_9_wd;
1072 logic cmd_info_9_mbyte_en_9_qs;
1073 logic cmd_info_9_mbyte_en_9_wd;
1074 logic [2:0] cmd_info_9_dummy_size_9_qs;
1075 logic [2:0] cmd_info_9_dummy_size_9_wd;
1076 logic cmd_info_9_dummy_en_9_qs;
1077 logic cmd_info_9_dummy_en_9_wd;
1078 logic [3:0] cmd_info_9_payload_en_9_qs;
1079 logic [3:0] cmd_info_9_payload_en_9_wd;
1080 logic cmd_info_9_payload_dir_9_qs;
1081 logic cmd_info_9_payload_dir_9_wd;
1082 logic cmd_info_9_payload_swap_en_9_qs;
1083 logic cmd_info_9_payload_swap_en_9_wd;
1084 logic [1:0] cmd_info_9_read_pipeline_mode_9_qs;
1085 logic [1:0] cmd_info_9_read_pipeline_mode_9_wd;
1086 logic cmd_info_9_upload_9_qs;
1087 logic cmd_info_9_upload_9_wd;
1088 logic cmd_info_9_busy_9_qs;
1089 logic cmd_info_9_busy_9_wd;
1090 logic cmd_info_9_valid_9_qs;
1091 logic cmd_info_9_valid_9_wd;
1092 logic cmd_info_10_we;
1093 logic [7:0] cmd_info_10_opcode_10_qs;
1094 logic [7:0] cmd_info_10_opcode_10_wd;
1095 logic [1:0] cmd_info_10_addr_mode_10_qs;
1096 logic [1:0] cmd_info_10_addr_mode_10_wd;
1097 logic cmd_info_10_addr_swap_en_10_qs;
1098 logic cmd_info_10_addr_swap_en_10_wd;
1099 logic cmd_info_10_mbyte_en_10_qs;
1100 logic cmd_info_10_mbyte_en_10_wd;
1101 logic [2:0] cmd_info_10_dummy_size_10_qs;
1102 logic [2:0] cmd_info_10_dummy_size_10_wd;
1103 logic cmd_info_10_dummy_en_10_qs;
1104 logic cmd_info_10_dummy_en_10_wd;
1105 logic [3:0] cmd_info_10_payload_en_10_qs;
1106 logic [3:0] cmd_info_10_payload_en_10_wd;
1107 logic cmd_info_10_payload_dir_10_qs;
1108 logic cmd_info_10_payload_dir_10_wd;
1109 logic cmd_info_10_payload_swap_en_10_qs;
1110 logic cmd_info_10_payload_swap_en_10_wd;
1111 logic [1:0] cmd_info_10_read_pipeline_mode_10_qs;
1112 logic [1:0] cmd_info_10_read_pipeline_mode_10_wd;
1113 logic cmd_info_10_upload_10_qs;
1114 logic cmd_info_10_upload_10_wd;
1115 logic cmd_info_10_busy_10_qs;
1116 logic cmd_info_10_busy_10_wd;
1117 logic cmd_info_10_valid_10_qs;
1118 logic cmd_info_10_valid_10_wd;
1119 logic cmd_info_11_we;
1120 logic [7:0] cmd_info_11_opcode_11_qs;
1121 logic [7:0] cmd_info_11_opcode_11_wd;
1122 logic [1:0] cmd_info_11_addr_mode_11_qs;
1123 logic [1:0] cmd_info_11_addr_mode_11_wd;
1124 logic cmd_info_11_addr_swap_en_11_qs;
1125 logic cmd_info_11_addr_swap_en_11_wd;
1126 logic cmd_info_11_mbyte_en_11_qs;
1127 logic cmd_info_11_mbyte_en_11_wd;
1128 logic [2:0] cmd_info_11_dummy_size_11_qs;
1129 logic [2:0] cmd_info_11_dummy_size_11_wd;
1130 logic cmd_info_11_dummy_en_11_qs;
1131 logic cmd_info_11_dummy_en_11_wd;
1132 logic [3:0] cmd_info_11_payload_en_11_qs;
1133 logic [3:0] cmd_info_11_payload_en_11_wd;
1134 logic cmd_info_11_payload_dir_11_qs;
1135 logic cmd_info_11_payload_dir_11_wd;
1136 logic cmd_info_11_payload_swap_en_11_qs;
1137 logic cmd_info_11_payload_swap_en_11_wd;
1138 logic [1:0] cmd_info_11_read_pipeline_mode_11_qs;
1139 logic [1:0] cmd_info_11_read_pipeline_mode_11_wd;
1140 logic cmd_info_11_upload_11_qs;
1141 logic cmd_info_11_upload_11_wd;
1142 logic cmd_info_11_busy_11_qs;
1143 logic cmd_info_11_busy_11_wd;
1144 logic cmd_info_11_valid_11_qs;
1145 logic cmd_info_11_valid_11_wd;
1146 logic cmd_info_12_we;
1147 logic [7:0] cmd_info_12_opcode_12_qs;
1148 logic [7:0] cmd_info_12_opcode_12_wd;
1149 logic [1:0] cmd_info_12_addr_mode_12_qs;
1150 logic [1:0] cmd_info_12_addr_mode_12_wd;
1151 logic cmd_info_12_addr_swap_en_12_qs;
1152 logic cmd_info_12_addr_swap_en_12_wd;
1153 logic cmd_info_12_mbyte_en_12_qs;
1154 logic cmd_info_12_mbyte_en_12_wd;
1155 logic [2:0] cmd_info_12_dummy_size_12_qs;
1156 logic [2:0] cmd_info_12_dummy_size_12_wd;
1157 logic cmd_info_12_dummy_en_12_qs;
1158 logic cmd_info_12_dummy_en_12_wd;
1159 logic [3:0] cmd_info_12_payload_en_12_qs;
1160 logic [3:0] cmd_info_12_payload_en_12_wd;
1161 logic cmd_info_12_payload_dir_12_qs;
1162 logic cmd_info_12_payload_dir_12_wd;
1163 logic cmd_info_12_payload_swap_en_12_qs;
1164 logic cmd_info_12_payload_swap_en_12_wd;
1165 logic [1:0] cmd_info_12_read_pipeline_mode_12_qs;
1166 logic [1:0] cmd_info_12_read_pipeline_mode_12_wd;
1167 logic cmd_info_12_upload_12_qs;
1168 logic cmd_info_12_upload_12_wd;
1169 logic cmd_info_12_busy_12_qs;
1170 logic cmd_info_12_busy_12_wd;
1171 logic cmd_info_12_valid_12_qs;
1172 logic cmd_info_12_valid_12_wd;
1173 logic cmd_info_13_we;
1174 logic [7:0] cmd_info_13_opcode_13_qs;
1175 logic [7:0] cmd_info_13_opcode_13_wd;
1176 logic [1:0] cmd_info_13_addr_mode_13_qs;
1177 logic [1:0] cmd_info_13_addr_mode_13_wd;
1178 logic cmd_info_13_addr_swap_en_13_qs;
1179 logic cmd_info_13_addr_swap_en_13_wd;
1180 logic cmd_info_13_mbyte_en_13_qs;
1181 logic cmd_info_13_mbyte_en_13_wd;
1182 logic [2:0] cmd_info_13_dummy_size_13_qs;
1183 logic [2:0] cmd_info_13_dummy_size_13_wd;
1184 logic cmd_info_13_dummy_en_13_qs;
1185 logic cmd_info_13_dummy_en_13_wd;
1186 logic [3:0] cmd_info_13_payload_en_13_qs;
1187 logic [3:0] cmd_info_13_payload_en_13_wd;
1188 logic cmd_info_13_payload_dir_13_qs;
1189 logic cmd_info_13_payload_dir_13_wd;
1190 logic cmd_info_13_payload_swap_en_13_qs;
1191 logic cmd_info_13_payload_swap_en_13_wd;
1192 logic [1:0] cmd_info_13_read_pipeline_mode_13_qs;
1193 logic [1:0] cmd_info_13_read_pipeline_mode_13_wd;
1194 logic cmd_info_13_upload_13_qs;
1195 logic cmd_info_13_upload_13_wd;
1196 logic cmd_info_13_busy_13_qs;
1197 logic cmd_info_13_busy_13_wd;
1198 logic cmd_info_13_valid_13_qs;
1199 logic cmd_info_13_valid_13_wd;
1200 logic cmd_info_14_we;
1201 logic [7:0] cmd_info_14_opcode_14_qs;
1202 logic [7:0] cmd_info_14_opcode_14_wd;
1203 logic [1:0] cmd_info_14_addr_mode_14_qs;
1204 logic [1:0] cmd_info_14_addr_mode_14_wd;
1205 logic cmd_info_14_addr_swap_en_14_qs;
1206 logic cmd_info_14_addr_swap_en_14_wd;
1207 logic cmd_info_14_mbyte_en_14_qs;
1208 logic cmd_info_14_mbyte_en_14_wd;
1209 logic [2:0] cmd_info_14_dummy_size_14_qs;
1210 logic [2:0] cmd_info_14_dummy_size_14_wd;
1211 logic cmd_info_14_dummy_en_14_qs;
1212 logic cmd_info_14_dummy_en_14_wd;
1213 logic [3:0] cmd_info_14_payload_en_14_qs;
1214 logic [3:0] cmd_info_14_payload_en_14_wd;
1215 logic cmd_info_14_payload_dir_14_qs;
1216 logic cmd_info_14_payload_dir_14_wd;
1217 logic cmd_info_14_payload_swap_en_14_qs;
1218 logic cmd_info_14_payload_swap_en_14_wd;
1219 logic [1:0] cmd_info_14_read_pipeline_mode_14_qs;
1220 logic [1:0] cmd_info_14_read_pipeline_mode_14_wd;
1221 logic cmd_info_14_upload_14_qs;
1222 logic cmd_info_14_upload_14_wd;
1223 logic cmd_info_14_busy_14_qs;
1224 logic cmd_info_14_busy_14_wd;
1225 logic cmd_info_14_valid_14_qs;
1226 logic cmd_info_14_valid_14_wd;
1227 logic cmd_info_15_we;
1228 logic [7:0] cmd_info_15_opcode_15_qs;
1229 logic [7:0] cmd_info_15_opcode_15_wd;
1230 logic [1:0] cmd_info_15_addr_mode_15_qs;
1231 logic [1:0] cmd_info_15_addr_mode_15_wd;
1232 logic cmd_info_15_addr_swap_en_15_qs;
1233 logic cmd_info_15_addr_swap_en_15_wd;
1234 logic cmd_info_15_mbyte_en_15_qs;
1235 logic cmd_info_15_mbyte_en_15_wd;
1236 logic [2:0] cmd_info_15_dummy_size_15_qs;
1237 logic [2:0] cmd_info_15_dummy_size_15_wd;
1238 logic cmd_info_15_dummy_en_15_qs;
1239 logic cmd_info_15_dummy_en_15_wd;
1240 logic [3:0] cmd_info_15_payload_en_15_qs;
1241 logic [3:0] cmd_info_15_payload_en_15_wd;
1242 logic cmd_info_15_payload_dir_15_qs;
1243 logic cmd_info_15_payload_dir_15_wd;
1244 logic cmd_info_15_payload_swap_en_15_qs;
1245 logic cmd_info_15_payload_swap_en_15_wd;
1246 logic [1:0] cmd_info_15_read_pipeline_mode_15_qs;
1247 logic [1:0] cmd_info_15_read_pipeline_mode_15_wd;
1248 logic cmd_info_15_upload_15_qs;
1249 logic cmd_info_15_upload_15_wd;
1250 logic cmd_info_15_busy_15_qs;
1251 logic cmd_info_15_busy_15_wd;
1252 logic cmd_info_15_valid_15_qs;
1253 logic cmd_info_15_valid_15_wd;
1254 logic cmd_info_16_we;
1255 logic [7:0] cmd_info_16_opcode_16_qs;
1256 logic [7:0] cmd_info_16_opcode_16_wd;
1257 logic [1:0] cmd_info_16_addr_mode_16_qs;
1258 logic [1:0] cmd_info_16_addr_mode_16_wd;
1259 logic cmd_info_16_addr_swap_en_16_qs;
1260 logic cmd_info_16_addr_swap_en_16_wd;
1261 logic cmd_info_16_mbyte_en_16_qs;
1262 logic cmd_info_16_mbyte_en_16_wd;
1263 logic [2:0] cmd_info_16_dummy_size_16_qs;
1264 logic [2:0] cmd_info_16_dummy_size_16_wd;
1265 logic cmd_info_16_dummy_en_16_qs;
1266 logic cmd_info_16_dummy_en_16_wd;
1267 logic [3:0] cmd_info_16_payload_en_16_qs;
1268 logic [3:0] cmd_info_16_payload_en_16_wd;
1269 logic cmd_info_16_payload_dir_16_qs;
1270 logic cmd_info_16_payload_dir_16_wd;
1271 logic cmd_info_16_payload_swap_en_16_qs;
1272 logic cmd_info_16_payload_swap_en_16_wd;
1273 logic [1:0] cmd_info_16_read_pipeline_mode_16_qs;
1274 logic [1:0] cmd_info_16_read_pipeline_mode_16_wd;
1275 logic cmd_info_16_upload_16_qs;
1276 logic cmd_info_16_upload_16_wd;
1277 logic cmd_info_16_busy_16_qs;
1278 logic cmd_info_16_busy_16_wd;
1279 logic cmd_info_16_valid_16_qs;
1280 logic cmd_info_16_valid_16_wd;
1281 logic cmd_info_17_we;
1282 logic [7:0] cmd_info_17_opcode_17_qs;
1283 logic [7:0] cmd_info_17_opcode_17_wd;
1284 logic [1:0] cmd_info_17_addr_mode_17_qs;
1285 logic [1:0] cmd_info_17_addr_mode_17_wd;
1286 logic cmd_info_17_addr_swap_en_17_qs;
1287 logic cmd_info_17_addr_swap_en_17_wd;
1288 logic cmd_info_17_mbyte_en_17_qs;
1289 logic cmd_info_17_mbyte_en_17_wd;
1290 logic [2:0] cmd_info_17_dummy_size_17_qs;
1291 logic [2:0] cmd_info_17_dummy_size_17_wd;
1292 logic cmd_info_17_dummy_en_17_qs;
1293 logic cmd_info_17_dummy_en_17_wd;
1294 logic [3:0] cmd_info_17_payload_en_17_qs;
1295 logic [3:0] cmd_info_17_payload_en_17_wd;
1296 logic cmd_info_17_payload_dir_17_qs;
1297 logic cmd_info_17_payload_dir_17_wd;
1298 logic cmd_info_17_payload_swap_en_17_qs;
1299 logic cmd_info_17_payload_swap_en_17_wd;
1300 logic [1:0] cmd_info_17_read_pipeline_mode_17_qs;
1301 logic [1:0] cmd_info_17_read_pipeline_mode_17_wd;
1302 logic cmd_info_17_upload_17_qs;
1303 logic cmd_info_17_upload_17_wd;
1304 logic cmd_info_17_busy_17_qs;
1305 logic cmd_info_17_busy_17_wd;
1306 logic cmd_info_17_valid_17_qs;
1307 logic cmd_info_17_valid_17_wd;
1308 logic cmd_info_18_we;
1309 logic [7:0] cmd_info_18_opcode_18_qs;
1310 logic [7:0] cmd_info_18_opcode_18_wd;
1311 logic [1:0] cmd_info_18_addr_mode_18_qs;
1312 logic [1:0] cmd_info_18_addr_mode_18_wd;
1313 logic cmd_info_18_addr_swap_en_18_qs;
1314 logic cmd_info_18_addr_swap_en_18_wd;
1315 logic cmd_info_18_mbyte_en_18_qs;
1316 logic cmd_info_18_mbyte_en_18_wd;
1317 logic [2:0] cmd_info_18_dummy_size_18_qs;
1318 logic [2:0] cmd_info_18_dummy_size_18_wd;
1319 logic cmd_info_18_dummy_en_18_qs;
1320 logic cmd_info_18_dummy_en_18_wd;
1321 logic [3:0] cmd_info_18_payload_en_18_qs;
1322 logic [3:0] cmd_info_18_payload_en_18_wd;
1323 logic cmd_info_18_payload_dir_18_qs;
1324 logic cmd_info_18_payload_dir_18_wd;
1325 logic cmd_info_18_payload_swap_en_18_qs;
1326 logic cmd_info_18_payload_swap_en_18_wd;
1327 logic [1:0] cmd_info_18_read_pipeline_mode_18_qs;
1328 logic [1:0] cmd_info_18_read_pipeline_mode_18_wd;
1329 logic cmd_info_18_upload_18_qs;
1330 logic cmd_info_18_upload_18_wd;
1331 logic cmd_info_18_busy_18_qs;
1332 logic cmd_info_18_busy_18_wd;
1333 logic cmd_info_18_valid_18_qs;
1334 logic cmd_info_18_valid_18_wd;
1335 logic cmd_info_19_we;
1336 logic [7:0] cmd_info_19_opcode_19_qs;
1337 logic [7:0] cmd_info_19_opcode_19_wd;
1338 logic [1:0] cmd_info_19_addr_mode_19_qs;
1339 logic [1:0] cmd_info_19_addr_mode_19_wd;
1340 logic cmd_info_19_addr_swap_en_19_qs;
1341 logic cmd_info_19_addr_swap_en_19_wd;
1342 logic cmd_info_19_mbyte_en_19_qs;
1343 logic cmd_info_19_mbyte_en_19_wd;
1344 logic [2:0] cmd_info_19_dummy_size_19_qs;
1345 logic [2:0] cmd_info_19_dummy_size_19_wd;
1346 logic cmd_info_19_dummy_en_19_qs;
1347 logic cmd_info_19_dummy_en_19_wd;
1348 logic [3:0] cmd_info_19_payload_en_19_qs;
1349 logic [3:0] cmd_info_19_payload_en_19_wd;
1350 logic cmd_info_19_payload_dir_19_qs;
1351 logic cmd_info_19_payload_dir_19_wd;
1352 logic cmd_info_19_payload_swap_en_19_qs;
1353 logic cmd_info_19_payload_swap_en_19_wd;
1354 logic [1:0] cmd_info_19_read_pipeline_mode_19_qs;
1355 logic [1:0] cmd_info_19_read_pipeline_mode_19_wd;
1356 logic cmd_info_19_upload_19_qs;
1357 logic cmd_info_19_upload_19_wd;
1358 logic cmd_info_19_busy_19_qs;
1359 logic cmd_info_19_busy_19_wd;
1360 logic cmd_info_19_valid_19_qs;
1361 logic cmd_info_19_valid_19_wd;
1362 logic cmd_info_20_we;
1363 logic [7:0] cmd_info_20_opcode_20_qs;
1364 logic [7:0] cmd_info_20_opcode_20_wd;
1365 logic [1:0] cmd_info_20_addr_mode_20_qs;
1366 logic [1:0] cmd_info_20_addr_mode_20_wd;
1367 logic cmd_info_20_addr_swap_en_20_qs;
1368 logic cmd_info_20_addr_swap_en_20_wd;
1369 logic cmd_info_20_mbyte_en_20_qs;
1370 logic cmd_info_20_mbyte_en_20_wd;
1371 logic [2:0] cmd_info_20_dummy_size_20_qs;
1372 logic [2:0] cmd_info_20_dummy_size_20_wd;
1373 logic cmd_info_20_dummy_en_20_qs;
1374 logic cmd_info_20_dummy_en_20_wd;
1375 logic [3:0] cmd_info_20_payload_en_20_qs;
1376 logic [3:0] cmd_info_20_payload_en_20_wd;
1377 logic cmd_info_20_payload_dir_20_qs;
1378 logic cmd_info_20_payload_dir_20_wd;
1379 logic cmd_info_20_payload_swap_en_20_qs;
1380 logic cmd_info_20_payload_swap_en_20_wd;
1381 logic [1:0] cmd_info_20_read_pipeline_mode_20_qs;
1382 logic [1:0] cmd_info_20_read_pipeline_mode_20_wd;
1383 logic cmd_info_20_upload_20_qs;
1384 logic cmd_info_20_upload_20_wd;
1385 logic cmd_info_20_busy_20_qs;
1386 logic cmd_info_20_busy_20_wd;
1387 logic cmd_info_20_valid_20_qs;
1388 logic cmd_info_20_valid_20_wd;
1389 logic cmd_info_21_we;
1390 logic [7:0] cmd_info_21_opcode_21_qs;
1391 logic [7:0] cmd_info_21_opcode_21_wd;
1392 logic [1:0] cmd_info_21_addr_mode_21_qs;
1393 logic [1:0] cmd_info_21_addr_mode_21_wd;
1394 logic cmd_info_21_addr_swap_en_21_qs;
1395 logic cmd_info_21_addr_swap_en_21_wd;
1396 logic cmd_info_21_mbyte_en_21_qs;
1397 logic cmd_info_21_mbyte_en_21_wd;
1398 logic [2:0] cmd_info_21_dummy_size_21_qs;
1399 logic [2:0] cmd_info_21_dummy_size_21_wd;
1400 logic cmd_info_21_dummy_en_21_qs;
1401 logic cmd_info_21_dummy_en_21_wd;
1402 logic [3:0] cmd_info_21_payload_en_21_qs;
1403 logic [3:0] cmd_info_21_payload_en_21_wd;
1404 logic cmd_info_21_payload_dir_21_qs;
1405 logic cmd_info_21_payload_dir_21_wd;
1406 logic cmd_info_21_payload_swap_en_21_qs;
1407 logic cmd_info_21_payload_swap_en_21_wd;
1408 logic [1:0] cmd_info_21_read_pipeline_mode_21_qs;
1409 logic [1:0] cmd_info_21_read_pipeline_mode_21_wd;
1410 logic cmd_info_21_upload_21_qs;
1411 logic cmd_info_21_upload_21_wd;
1412 logic cmd_info_21_busy_21_qs;
1413 logic cmd_info_21_busy_21_wd;
1414 logic cmd_info_21_valid_21_qs;
1415 logic cmd_info_21_valid_21_wd;
1416 logic cmd_info_22_we;
1417 logic [7:0] cmd_info_22_opcode_22_qs;
1418 logic [7:0] cmd_info_22_opcode_22_wd;
1419 logic [1:0] cmd_info_22_addr_mode_22_qs;
1420 logic [1:0] cmd_info_22_addr_mode_22_wd;
1421 logic cmd_info_22_addr_swap_en_22_qs;
1422 logic cmd_info_22_addr_swap_en_22_wd;
1423 logic cmd_info_22_mbyte_en_22_qs;
1424 logic cmd_info_22_mbyte_en_22_wd;
1425 logic [2:0] cmd_info_22_dummy_size_22_qs;
1426 logic [2:0] cmd_info_22_dummy_size_22_wd;
1427 logic cmd_info_22_dummy_en_22_qs;
1428 logic cmd_info_22_dummy_en_22_wd;
1429 logic [3:0] cmd_info_22_payload_en_22_qs;
1430 logic [3:0] cmd_info_22_payload_en_22_wd;
1431 logic cmd_info_22_payload_dir_22_qs;
1432 logic cmd_info_22_payload_dir_22_wd;
1433 logic cmd_info_22_payload_swap_en_22_qs;
1434 logic cmd_info_22_payload_swap_en_22_wd;
1435 logic [1:0] cmd_info_22_read_pipeline_mode_22_qs;
1436 logic [1:0] cmd_info_22_read_pipeline_mode_22_wd;
1437 logic cmd_info_22_upload_22_qs;
1438 logic cmd_info_22_upload_22_wd;
1439 logic cmd_info_22_busy_22_qs;
1440 logic cmd_info_22_busy_22_wd;
1441 logic cmd_info_22_valid_22_qs;
1442 logic cmd_info_22_valid_22_wd;
1443 logic cmd_info_23_we;
1444 logic [7:0] cmd_info_23_opcode_23_qs;
1445 logic [7:0] cmd_info_23_opcode_23_wd;
1446 logic [1:0] cmd_info_23_addr_mode_23_qs;
1447 logic [1:0] cmd_info_23_addr_mode_23_wd;
1448 logic cmd_info_23_addr_swap_en_23_qs;
1449 logic cmd_info_23_addr_swap_en_23_wd;
1450 logic cmd_info_23_mbyte_en_23_qs;
1451 logic cmd_info_23_mbyte_en_23_wd;
1452 logic [2:0] cmd_info_23_dummy_size_23_qs;
1453 logic [2:0] cmd_info_23_dummy_size_23_wd;
1454 logic cmd_info_23_dummy_en_23_qs;
1455 logic cmd_info_23_dummy_en_23_wd;
1456 logic [3:0] cmd_info_23_payload_en_23_qs;
1457 logic [3:0] cmd_info_23_payload_en_23_wd;
1458 logic cmd_info_23_payload_dir_23_qs;
1459 logic cmd_info_23_payload_dir_23_wd;
1460 logic cmd_info_23_payload_swap_en_23_qs;
1461 logic cmd_info_23_payload_swap_en_23_wd;
1462 logic [1:0] cmd_info_23_read_pipeline_mode_23_qs;
1463 logic [1:0] cmd_info_23_read_pipeline_mode_23_wd;
1464 logic cmd_info_23_upload_23_qs;
1465 logic cmd_info_23_upload_23_wd;
1466 logic cmd_info_23_busy_23_qs;
1467 logic cmd_info_23_busy_23_wd;
1468 logic cmd_info_23_valid_23_qs;
1469 logic cmd_info_23_valid_23_wd;
1470 logic cmd_info_en4b_we;
1471 logic [7:0] cmd_info_en4b_opcode_qs;
1472 logic [7:0] cmd_info_en4b_opcode_wd;
1473 logic cmd_info_en4b_valid_qs;
1474 logic cmd_info_en4b_valid_wd;
1475 logic cmd_info_ex4b_we;
1476 logic [7:0] cmd_info_ex4b_opcode_qs;
1477 logic [7:0] cmd_info_ex4b_opcode_wd;
1478 logic cmd_info_ex4b_valid_qs;
1479 logic cmd_info_ex4b_valid_wd;
1480 logic cmd_info_wren_we;
1481 logic [7:0] cmd_info_wren_opcode_qs;
1482 logic [7:0] cmd_info_wren_opcode_wd;
1483 logic cmd_info_wren_valid_qs;
1484 logic cmd_info_wren_valid_wd;
1485 logic cmd_info_wrdi_we;
1486 logic [7:0] cmd_info_wrdi_opcode_qs;
1487 logic [7:0] cmd_info_wrdi_opcode_wd;
1488 logic cmd_info_wrdi_valid_qs;
1489 logic cmd_info_wrdi_valid_wd;
1490 logic [7:0] tpm_cap_rev_qs;
1491 logic tpm_cap_locality_qs;
1492 logic [2:0] tpm_cap_max_wr_size_qs;
1493 logic [2:0] tpm_cap_max_rd_size_qs;
1494 logic tpm_cfg_we;
1495 logic tpm_cfg_en_qs;
1496 logic tpm_cfg_en_wd;
1497 logic tpm_cfg_tpm_mode_qs;
1498 logic tpm_cfg_tpm_mode_wd;
1499 logic tpm_cfg_hw_reg_dis_qs;
1500 logic tpm_cfg_hw_reg_dis_wd;
1501 logic tpm_cfg_tpm_reg_chk_dis_qs;
1502 logic tpm_cfg_tpm_reg_chk_dis_wd;
1503 logic tpm_cfg_invalid_locality_qs;
1504 logic tpm_cfg_invalid_locality_wd;
1505 logic tpm_status_re;
1506 logic tpm_status_we;
1507 logic tpm_status_cmdaddr_notempty_qs;
1508 logic tpm_status_wrfifo_pending_qs;
1509 logic tpm_status_wrfifo_pending_wd;
1510 logic tpm_status_rdfifo_aborted_qs;
1511 logic tpm_access_0_we;
1512 logic [7:0] tpm_access_0_access_0_qs;
1513 logic [7:0] tpm_access_0_access_0_wd;
1514 logic [7:0] tpm_access_0_access_1_qs;
1515 logic [7:0] tpm_access_0_access_1_wd;
1516 logic [7:0] tpm_access_0_access_2_qs;
1517 logic [7:0] tpm_access_0_access_2_wd;
1518 logic [7:0] tpm_access_0_access_3_qs;
1519 logic [7:0] tpm_access_0_access_3_wd;
1520 logic tpm_access_1_we;
1521 logic [7:0] tpm_access_1_qs;
1522 logic [7:0] tpm_access_1_wd;
1523 logic tpm_sts_we;
1524 logic [31:0] tpm_sts_qs;
1525 logic [31:0] tpm_sts_wd;
1526 logic tpm_intf_capability_we;
1527 logic [31:0] tpm_intf_capability_qs;
1528 logic [31:0] tpm_intf_capability_wd;
1529 logic tpm_int_enable_we;
1530 logic [31:0] tpm_int_enable_qs;
1531 logic [31:0] tpm_int_enable_wd;
1532 logic tpm_int_vector_we;
1533 logic [7:0] tpm_int_vector_qs;
1534 logic [7:0] tpm_int_vector_wd;
1535 logic tpm_int_status_we;
1536 logic [31:0] tpm_int_status_qs;
1537 logic [31:0] tpm_int_status_wd;
1538 logic tpm_did_vid_we;
1539 logic [15:0] tpm_did_vid_vid_qs;
1540 logic [15:0] tpm_did_vid_vid_wd;
1541 logic [15:0] tpm_did_vid_did_qs;
1542 logic [15:0] tpm_did_vid_did_wd;
1543 logic tpm_rid_we;
1544 logic [7:0] tpm_rid_qs;
1545 logic [7:0] tpm_rid_wd;
1546 logic tpm_cmd_addr_re;
1547 logic [23:0] tpm_cmd_addr_addr_qs;
1548 logic [7:0] tpm_cmd_addr_cmd_qs;
1549 logic tpm_read_fifo_we;
1550 logic [31:0] tpm_read_fifo_wd;
1551
1552 // Register instances
1553 // R[intr_state]: V(False)
1554 // F[upload_cmdfifo_not_empty]: 0:0
1555 prim_subreg #(
1556 .DW (1),
1557 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1558 .RESVAL (1'h0),
1559 .Mubi (1'b0)
1560 ) u_intr_state_upload_cmdfifo_not_empty (
1561 .clk_i (clk_i),
1562 .rst_ni (rst_ni),
1563
1564 // from register interface
1565 .we (intr_state_we),
1566 .wd (intr_state_upload_cmdfifo_not_empty_wd),
1567
1568 // from internal hardware
1569 .de (hw2reg.intr_state.upload_cmdfifo_not_empty.de),
1570 .d (hw2reg.intr_state.upload_cmdfifo_not_empty.d),
1571
1572 // to internal hardware
1573 .qe (),
1574 .q (reg2hw.intr_state.upload_cmdfifo_not_empty.q),
1575 .ds (),
1576
1577 // to register interface (read)
1578 .qs (intr_state_upload_cmdfifo_not_empty_qs)
1579 );
1580
1581 // F[upload_payload_not_empty]: 1:1
1582 prim_subreg #(
1583 .DW (1),
1584 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1585 .RESVAL (1'h0),
1586 .Mubi (1'b0)
1587 ) u_intr_state_upload_payload_not_empty (
1588 .clk_i (clk_i),
1589 .rst_ni (rst_ni),
1590
1591 // from register interface
1592 .we (intr_state_we),
1593 .wd (intr_state_upload_payload_not_empty_wd),
1594
1595 // from internal hardware
1596 .de (hw2reg.intr_state.upload_payload_not_empty.de),
1597 .d (hw2reg.intr_state.upload_payload_not_empty.d),
1598
1599 // to internal hardware
1600 .qe (),
1601 .q (reg2hw.intr_state.upload_payload_not_empty.q),
1602 .ds (),
1603
1604 // to register interface (read)
1605 .qs (intr_state_upload_payload_not_empty_qs)
1606 );
1607
1608 // F[upload_payload_overflow]: 2:2
1609 prim_subreg #(
1610 .DW (1),
1611 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1612 .RESVAL (1'h0),
1613 .Mubi (1'b0)
1614 ) u_intr_state_upload_payload_overflow (
1615 .clk_i (clk_i),
1616 .rst_ni (rst_ni),
1617
1618 // from register interface
1619 .we (intr_state_we),
1620 .wd (intr_state_upload_payload_overflow_wd),
1621
1622 // from internal hardware
1623 .de (hw2reg.intr_state.upload_payload_overflow.de),
1624 .d (hw2reg.intr_state.upload_payload_overflow.d),
1625
1626 // to internal hardware
1627 .qe (),
1628 .q (reg2hw.intr_state.upload_payload_overflow.q),
1629 .ds (),
1630
1631 // to register interface (read)
1632 .qs (intr_state_upload_payload_overflow_qs)
1633 );
1634
1635 // F[readbuf_watermark]: 3:3
1636 prim_subreg #(
1637 .DW (1),
1638 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1639 .RESVAL (1'h0),
1640 .Mubi (1'b0)
1641 ) u_intr_state_readbuf_watermark (
1642 .clk_i (clk_i),
1643 .rst_ni (rst_ni),
1644
1645 // from register interface
1646 .we (intr_state_we),
1647 .wd (intr_state_readbuf_watermark_wd),
1648
1649 // from internal hardware
1650 .de (hw2reg.intr_state.readbuf_watermark.de),
1651 .d (hw2reg.intr_state.readbuf_watermark.d),
1652
1653 // to internal hardware
1654 .qe (),
1655 .q (reg2hw.intr_state.readbuf_watermark.q),
1656 .ds (),
1657
1658 // to register interface (read)
1659 .qs (intr_state_readbuf_watermark_qs)
1660 );
1661
1662 // F[readbuf_flip]: 4:4
1663 prim_subreg #(
1664 .DW (1),
1665 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1666 .RESVAL (1'h0),
1667 .Mubi (1'b0)
1668 ) u_intr_state_readbuf_flip (
1669 .clk_i (clk_i),
1670 .rst_ni (rst_ni),
1671
1672 // from register interface
1673 .we (intr_state_we),
1674 .wd (intr_state_readbuf_flip_wd),
1675
1676 // from internal hardware
1677 .de (hw2reg.intr_state.readbuf_flip.de),
1678 .d (hw2reg.intr_state.readbuf_flip.d),
1679
1680 // to internal hardware
1681 .qe (),
1682 .q (reg2hw.intr_state.readbuf_flip.q),
1683 .ds (),
1684
1685 // to register interface (read)
1686 .qs (intr_state_readbuf_flip_qs)
1687 );
1688
1689 // F[tpm_header_not_empty]: 5:5
1690 prim_subreg #(
1691 .DW (1),
1692 .SwAccess(prim_subreg_pkg::SwAccessRO),
1693 .RESVAL (1'h0),
1694 .Mubi (1'b0)
1695 ) u_intr_state_tpm_header_not_empty (
1696 .clk_i (clk_i),
1697 .rst_ni (rst_ni),
1698
1699 // from register interface
1700 .we (1'b0),
1701 .wd ('0),
1702
1703 // from internal hardware
1704 .de (hw2reg.intr_state.tpm_header_not_empty.de),
1705 .d (hw2reg.intr_state.tpm_header_not_empty.d),
1706
1707 // to internal hardware
1708 .qe (),
1709 .q (reg2hw.intr_state.tpm_header_not_empty.q),
1710 .ds (),
1711
1712 // to register interface (read)
1713 .qs (intr_state_tpm_header_not_empty_qs)
1714 );
1715
1716 // F[tpm_rdfifo_cmd_end]: 6:6
1717 prim_subreg #(
1718 .DW (1),
1719 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1720 .RESVAL (1'h0),
1721 .Mubi (1'b0)
1722 ) u_intr_state_tpm_rdfifo_cmd_end (
1723 .clk_i (clk_i),
1724 .rst_ni (rst_ni),
1725
1726 // from register interface
1727 .we (intr_state_we),
1728 .wd (intr_state_tpm_rdfifo_cmd_end_wd),
1729
1730 // from internal hardware
1731 .de (hw2reg.intr_state.tpm_rdfifo_cmd_end.de),
1732 .d (hw2reg.intr_state.tpm_rdfifo_cmd_end.d),
1733
1734 // to internal hardware
1735 .qe (),
1736 .q (reg2hw.intr_state.tpm_rdfifo_cmd_end.q),
1737 .ds (),
1738
1739 // to register interface (read)
1740 .qs (intr_state_tpm_rdfifo_cmd_end_qs)
1741 );
1742
1743 // F[tpm_rdfifo_drop]: 7:7
1744 prim_subreg #(
1745 .DW (1),
1746 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1747 .RESVAL (1'h0),
1748 .Mubi (1'b0)
1749 ) u_intr_state_tpm_rdfifo_drop (
1750 .clk_i (clk_i),
1751 .rst_ni (rst_ni),
1752
1753 // from register interface
1754 .we (intr_state_we),
1755 .wd (intr_state_tpm_rdfifo_drop_wd),
1756
1757 // from internal hardware
1758 .de (hw2reg.intr_state.tpm_rdfifo_drop.de),
1759 .d (hw2reg.intr_state.tpm_rdfifo_drop.d),
1760
1761 // to internal hardware
1762 .qe (),
1763 .q (reg2hw.intr_state.tpm_rdfifo_drop.q),
1764 .ds (),
1765
1766 // to register interface (read)
1767 .qs (intr_state_tpm_rdfifo_drop_qs)
1768 );
1769
1770
1771 // R[intr_enable]: V(False)
1772 // F[upload_cmdfifo_not_empty]: 0:0
1773 prim_subreg #(
1774 .DW (1),
1775 .SwAccess(prim_subreg_pkg::SwAccessRW),
1776 .RESVAL (1'h0),
1777 .Mubi (1'b0)
1778 ) u_intr_enable_upload_cmdfifo_not_empty (
1779 .clk_i (clk_i),
1780 .rst_ni (rst_ni),
1781
1782 // from register interface
1783 .we (intr_enable_we),
1784 .wd (intr_enable_upload_cmdfifo_not_empty_wd),
1785
1786 // from internal hardware
1787 .de (1'b0),
1788 .d ('0),
1789
1790 // to internal hardware
1791 .qe (),
1792 .q (reg2hw.intr_enable.upload_cmdfifo_not_empty.q),
1793 .ds (),
1794
1795 // to register interface (read)
1796 .qs (intr_enable_upload_cmdfifo_not_empty_qs)
1797 );
1798
1799 // F[upload_payload_not_empty]: 1:1
1800 prim_subreg #(
1801 .DW (1),
1802 .SwAccess(prim_subreg_pkg::SwAccessRW),
1803 .RESVAL (1'h0),
1804 .Mubi (1'b0)
1805 ) u_intr_enable_upload_payload_not_empty (
1806 .clk_i (clk_i),
1807 .rst_ni (rst_ni),
1808
1809 // from register interface
1810 .we (intr_enable_we),
1811 .wd (intr_enable_upload_payload_not_empty_wd),
1812
1813 // from internal hardware
1814 .de (1'b0),
1815 .d ('0),
1816
1817 // to internal hardware
1818 .qe (),
1819 .q (reg2hw.intr_enable.upload_payload_not_empty.q),
1820 .ds (),
1821
1822 // to register interface (read)
1823 .qs (intr_enable_upload_payload_not_empty_qs)
1824 );
1825
1826 // F[upload_payload_overflow]: 2:2
1827 prim_subreg #(
1828 .DW (1),
1829 .SwAccess(prim_subreg_pkg::SwAccessRW),
1830 .RESVAL (1'h0),
1831 .Mubi (1'b0)
1832 ) u_intr_enable_upload_payload_overflow (
1833 .clk_i (clk_i),
1834 .rst_ni (rst_ni),
1835
1836 // from register interface
1837 .we (intr_enable_we),
1838 .wd (intr_enable_upload_payload_overflow_wd),
1839
1840 // from internal hardware
1841 .de (1'b0),
1842 .d ('0),
1843
1844 // to internal hardware
1845 .qe (),
1846 .q (reg2hw.intr_enable.upload_payload_overflow.q),
1847 .ds (),
1848
1849 // to register interface (read)
1850 .qs (intr_enable_upload_payload_overflow_qs)
1851 );
1852
1853 // F[readbuf_watermark]: 3:3
1854 prim_subreg #(
1855 .DW (1),
1856 .SwAccess(prim_subreg_pkg::SwAccessRW),
1857 .RESVAL (1'h0),
1858 .Mubi (1'b0)
1859 ) u_intr_enable_readbuf_watermark (
1860 .clk_i (clk_i),
1861 .rst_ni (rst_ni),
1862
1863 // from register interface
1864 .we (intr_enable_we),
1865 .wd (intr_enable_readbuf_watermark_wd),
1866
1867 // from internal hardware
1868 .de (1'b0),
1869 .d ('0),
1870
1871 // to internal hardware
1872 .qe (),
1873 .q (reg2hw.intr_enable.readbuf_watermark.q),
1874 .ds (),
1875
1876 // to register interface (read)
1877 .qs (intr_enable_readbuf_watermark_qs)
1878 );
1879
1880 // F[readbuf_flip]: 4:4
1881 prim_subreg #(
1882 .DW (1),
1883 .SwAccess(prim_subreg_pkg::SwAccessRW),
1884 .RESVAL (1'h0),
1885 .Mubi (1'b0)
1886 ) u_intr_enable_readbuf_flip (
1887 .clk_i (clk_i),
1888 .rst_ni (rst_ni),
1889
1890 // from register interface
1891 .we (intr_enable_we),
1892 .wd (intr_enable_readbuf_flip_wd),
1893
1894 // from internal hardware
1895 .de (1'b0),
1896 .d ('0),
1897
1898 // to internal hardware
1899 .qe (),
1900 .q (reg2hw.intr_enable.readbuf_flip.q),
1901 .ds (),
1902
1903 // to register interface (read)
1904 .qs (intr_enable_readbuf_flip_qs)
1905 );
1906
1907 // F[tpm_header_not_empty]: 5:5
1908 prim_subreg #(
1909 .DW (1),
1910 .SwAccess(prim_subreg_pkg::SwAccessRW),
1911 .RESVAL (1'h0),
1912 .Mubi (1'b0)
1913 ) u_intr_enable_tpm_header_not_empty (
1914 .clk_i (clk_i),
1915 .rst_ni (rst_ni),
1916
1917 // from register interface
1918 .we (intr_enable_we),
1919 .wd (intr_enable_tpm_header_not_empty_wd),
1920
1921 // from internal hardware
1922 .de (1'b0),
1923 .d ('0),
1924
1925 // to internal hardware
1926 .qe (),
1927 .q (reg2hw.intr_enable.tpm_header_not_empty.q),
1928 .ds (),
1929
1930 // to register interface (read)
1931 .qs (intr_enable_tpm_header_not_empty_qs)
1932 );
1933
1934 // F[tpm_rdfifo_cmd_end]: 6:6
1935 prim_subreg #(
1936 .DW (1),
1937 .SwAccess(prim_subreg_pkg::SwAccessRW),
1938 .RESVAL (1'h0),
1939 .Mubi (1'b0)
1940 ) u_intr_enable_tpm_rdfifo_cmd_end (
1941 .clk_i (clk_i),
1942 .rst_ni (rst_ni),
1943
1944 // from register interface
1945 .we (intr_enable_we),
1946 .wd (intr_enable_tpm_rdfifo_cmd_end_wd),
1947
1948 // from internal hardware
1949 .de (1'b0),
1950 .d ('0),
1951
1952 // to internal hardware
1953 .qe (),
1954 .q (reg2hw.intr_enable.tpm_rdfifo_cmd_end.q),
1955 .ds (),
1956
1957 // to register interface (read)
1958 .qs (intr_enable_tpm_rdfifo_cmd_end_qs)
1959 );
1960
1961 // F[tpm_rdfifo_drop]: 7:7
1962 prim_subreg #(
1963 .DW (1),
1964 .SwAccess(prim_subreg_pkg::SwAccessRW),
1965 .RESVAL (1'h0),
1966 .Mubi (1'b0)
1967 ) u_intr_enable_tpm_rdfifo_drop (
1968 .clk_i (clk_i),
1969 .rst_ni (rst_ni),
1970
1971 // from register interface
1972 .we (intr_enable_we),
1973 .wd (intr_enable_tpm_rdfifo_drop_wd),
1974
1975 // from internal hardware
1976 .de (1'b0),
1977 .d ('0),
1978
1979 // to internal hardware
1980 .qe (),
1981 .q (reg2hw.intr_enable.tpm_rdfifo_drop.q),
1982 .ds (),
1983
1984 // to register interface (read)
1985 .qs (intr_enable_tpm_rdfifo_drop_qs)
1986 );
1987
1988
1989 // R[intr_test]: V(True)
1990 logic intr_test_qe;
1991 logic [7:0] intr_test_flds_we;
1992 1/1 assign intr_test_qe = &intr_test_flds_we;
Tests: T24 T35 T38
1993 // F[upload_cmdfifo_not_empty]: 0:0
1994 prim_subreg_ext #(
1995 .DW (1)
1996 ) u_intr_test_upload_cmdfifo_not_empty (
1997 .re (1'b0),
1998 .we (intr_test_we),
1999 .wd (intr_test_upload_cmdfifo_not_empty_wd),
2000 .d ('0),
2001 .qre (),
2002 .qe (intr_test_flds_we[0]),
2003 .q (reg2hw.intr_test.upload_cmdfifo_not_empty.q),
2004 .ds (),
2005 .qs ()
2006 );
2007 1/1 assign reg2hw.intr_test.upload_cmdfifo_not_empty.qe = intr_test_qe;
Tests: T24 T35 T38
2008
2009 // F[upload_payload_not_empty]: 1:1
2010 prim_subreg_ext #(
2011 .DW (1)
2012 ) u_intr_test_upload_payload_not_empty (
2013 .re (1'b0),
2014 .we (intr_test_we),
2015 .wd (intr_test_upload_payload_not_empty_wd),
2016 .d ('0),
2017 .qre (),
2018 .qe (intr_test_flds_we[1]),
2019 .q (reg2hw.intr_test.upload_payload_not_empty.q),
2020 .ds (),
2021 .qs ()
2022 );
2023 1/1 assign reg2hw.intr_test.upload_payload_not_empty.qe = intr_test_qe;
Tests: T24 T35 T38
2024
2025 // F[upload_payload_overflow]: 2:2
2026 prim_subreg_ext #(
2027 .DW (1)
2028 ) u_intr_test_upload_payload_overflow (
2029 .re (1'b0),
2030 .we (intr_test_we),
2031 .wd (intr_test_upload_payload_overflow_wd),
2032 .d ('0),
2033 .qre (),
2034 .qe (intr_test_flds_we[2]),
2035 .q (reg2hw.intr_test.upload_payload_overflow.q),
2036 .ds (),
2037 .qs ()
2038 );
2039 1/1 assign reg2hw.intr_test.upload_payload_overflow.qe = intr_test_qe;
Tests: T24 T35 T38
2040
2041 // F[readbuf_watermark]: 3:3
2042 prim_subreg_ext #(
2043 .DW (1)
2044 ) u_intr_test_readbuf_watermark (
2045 .re (1'b0),
2046 .we (intr_test_we),
2047 .wd (intr_test_readbuf_watermark_wd),
2048 .d ('0),
2049 .qre (),
2050 .qe (intr_test_flds_we[3]),
2051 .q (reg2hw.intr_test.readbuf_watermark.q),
2052 .ds (),
2053 .qs ()
2054 );
2055 1/1 assign reg2hw.intr_test.readbuf_watermark.qe = intr_test_qe;
Tests: T24 T35 T38
2056
2057 // F[readbuf_flip]: 4:4
2058 prim_subreg_ext #(
2059 .DW (1)
2060 ) u_intr_test_readbuf_flip (
2061 .re (1'b0),
2062 .we (intr_test_we),
2063 .wd (intr_test_readbuf_flip_wd),
2064 .d ('0),
2065 .qre (),
2066 .qe (intr_test_flds_we[4]),
2067 .q (reg2hw.intr_test.readbuf_flip.q),
2068 .ds (),
2069 .qs ()
2070 );
2071 1/1 assign reg2hw.intr_test.readbuf_flip.qe = intr_test_qe;
Tests: T24 T35 T38
2072
2073 // F[tpm_header_not_empty]: 5:5
2074 prim_subreg_ext #(
2075 .DW (1)
2076 ) u_intr_test_tpm_header_not_empty (
2077 .re (1'b0),
2078 .we (intr_test_we),
2079 .wd (intr_test_tpm_header_not_empty_wd),
2080 .d ('0),
2081 .qre (),
2082 .qe (intr_test_flds_we[5]),
2083 .q (reg2hw.intr_test.tpm_header_not_empty.q),
2084 .ds (),
2085 .qs ()
2086 );
2087 1/1 assign reg2hw.intr_test.tpm_header_not_empty.qe = intr_test_qe;
Tests: T24 T35 T38
2088
2089 // F[tpm_rdfifo_cmd_end]: 6:6
2090 prim_subreg_ext #(
2091 .DW (1)
2092 ) u_intr_test_tpm_rdfifo_cmd_end (
2093 .re (1'b0),
2094 .we (intr_test_we),
2095 .wd (intr_test_tpm_rdfifo_cmd_end_wd),
2096 .d ('0),
2097 .qre (),
2098 .qe (intr_test_flds_we[6]),
2099 .q (reg2hw.intr_test.tpm_rdfifo_cmd_end.q),
2100 .ds (),
2101 .qs ()
2102 );
2103 1/1 assign reg2hw.intr_test.tpm_rdfifo_cmd_end.qe = intr_test_qe;
Tests: T24 T35 T38
2104
2105 // F[tpm_rdfifo_drop]: 7:7
2106 prim_subreg_ext #(
2107 .DW (1)
2108 ) u_intr_test_tpm_rdfifo_drop (
2109 .re (1'b0),
2110 .we (intr_test_we),
2111 .wd (intr_test_tpm_rdfifo_drop_wd),
2112 .d ('0),
2113 .qre (),
2114 .qe (intr_test_flds_we[7]),
2115 .q (reg2hw.intr_test.tpm_rdfifo_drop.q),
2116 .ds (),
2117 .qs ()
2118 );
2119 1/1 assign reg2hw.intr_test.tpm_rdfifo_drop.qe = intr_test_qe;
Tests: T24 T35 T38
2120
2121
2122 // R[alert_test]: V(True)
2123 logic alert_test_qe;
2124 logic [0:0] alert_test_flds_we;
2125 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T6 T41 T98
2126 prim_subreg_ext #(
2127 .DW (1)
2128 ) u_alert_test (
2129 .re (1'b0),
2130 .we (alert_test_we),
2131 .wd (alert_test_wd),
2132 .d ('0),
2133 .qre (),
2134 .qe (alert_test_flds_we[0]),
2135 .q (reg2hw.alert_test.q),
2136 .ds (),
2137 .qs ()
2138 );
2139 1/1 assign reg2hw.alert_test.qe = alert_test_qe;
Tests: T6 T41 T98
2140
2141
2142 // R[control]: V(False)
2143 // F[flash_status_fifo_clr]: 0:0
2144 prim_subreg #(
2145 .DW (1),
2146 .SwAccess(prim_subreg_pkg::SwAccessW1S),
2147 .RESVAL (1'h0),
2148 .Mubi (1'b0)
2149 ) u_control_flash_status_fifo_clr (
2150 .clk_i (clk_i),
2151 .rst_ni (rst_ni),
2152
2153 // from register interface
2154 .we (control_we),
2155 .wd (control_flash_status_fifo_clr_wd),
2156
2157 // from internal hardware
2158 .de (hw2reg.control.flash_status_fifo_clr.de),
2159 .d (hw2reg.control.flash_status_fifo_clr.d),
2160
2161 // to internal hardware
2162 .qe (),
2163 .q (reg2hw.control.flash_status_fifo_clr.q),
2164 .ds (),
2165
2166 // to register interface (read)
2167 .qs (control_flash_status_fifo_clr_qs)
2168 );
2169
2170 // F[flash_read_buffer_clr]: 1:1
2171 prim_subreg #(
2172 .DW (1),
2173 .SwAccess(prim_subreg_pkg::SwAccessW1S),
2174 .RESVAL (1'h0),
2175 .Mubi (1'b0)
2176 ) u_control_flash_read_buffer_clr (
2177 .clk_i (clk_i),
2178 .rst_ni (rst_ni),
2179
2180 // from register interface
2181 .we (control_we),
2182 .wd (control_flash_read_buffer_clr_wd),
2183
2184 // from internal hardware
2185 .de (hw2reg.control.flash_read_buffer_clr.de),
2186 .d (hw2reg.control.flash_read_buffer_clr.d),
2187
2188 // to internal hardware
2189 .qe (),
2190 .q (reg2hw.control.flash_read_buffer_clr.q),
2191 .ds (),
2192
2193 // to register interface (read)
2194 .qs (control_flash_read_buffer_clr_qs)
2195 );
2196
2197 // F[mode]: 5:4
2198 prim_subreg #(
2199 .DW (2),
2200 .SwAccess(prim_subreg_pkg::SwAccessRW),
2201 .RESVAL (2'h1),
2202 .Mubi (1'b0)
2203 ) u_control_mode (
2204 .clk_i (clk_i),
2205 .rst_ni (rst_ni),
2206
2207 // from register interface
2208 .we (control_we),
2209 .wd (control_mode_wd),
2210
2211 // from internal hardware
2212 .de (1'b0),
2213 .d ('0),
2214
2215 // to internal hardware
2216 .qe (),
2217 .q (reg2hw.control.mode.q),
2218 .ds (),
2219
2220 // to register interface (read)
2221 .qs (control_mode_qs)
2222 );
2223
2224
2225 // R[cfg]: V(False)
2226 // F[tx_order]: 2:2
2227 prim_subreg #(
2228 .DW (1),
2229 .SwAccess(prim_subreg_pkg::SwAccessRW),
2230 .RESVAL (1'h0),
2231 .Mubi (1'b0)
2232 ) u_cfg_tx_order (
2233 .clk_i (clk_i),
2234 .rst_ni (rst_ni),
2235
2236 // from register interface
2237 .we (cfg_we),
2238 .wd (cfg_tx_order_wd),
2239
2240 // from internal hardware
2241 .de (1'b0),
2242 .d ('0),
2243
2244 // to internal hardware
2245 .qe (),
2246 .q (reg2hw.cfg.tx_order.q),
2247 .ds (),
2248
2249 // to register interface (read)
2250 .qs (cfg_tx_order_qs)
2251 );
2252
2253 // F[rx_order]: 3:3
2254 prim_subreg #(
2255 .DW (1),
2256 .SwAccess(prim_subreg_pkg::SwAccessRW),
2257 .RESVAL (1'h0),
2258 .Mubi (1'b0)
2259 ) u_cfg_rx_order (
2260 .clk_i (clk_i),
2261 .rst_ni (rst_ni),
2262
2263 // from register interface
2264 .we (cfg_we),
2265 .wd (cfg_rx_order_wd),
2266
2267 // from internal hardware
2268 .de (1'b0),
2269 .d ('0),
2270
2271 // to internal hardware
2272 .qe (),
2273 .q (reg2hw.cfg.rx_order.q),
2274 .ds (),
2275
2276 // to register interface (read)
2277 .qs (cfg_rx_order_qs)
2278 );
2279
2280 // F[mailbox_en]: 24:24
2281 prim_subreg #(
2282 .DW (1),
2283 .SwAccess(prim_subreg_pkg::SwAccessRW),
2284 .RESVAL (1'h0),
2285 .Mubi (1'b0)
2286 ) u_cfg_mailbox_en (
2287 .clk_i (clk_i),
2288 .rst_ni (rst_ni),
2289
2290 // from register interface
2291 .we (cfg_we),
2292 .wd (cfg_mailbox_en_wd),
2293
2294 // from internal hardware
2295 .de (1'b0),
2296 .d ('0),
2297
2298 // to internal hardware
2299 .qe (),
2300 .q (reg2hw.cfg.mailbox_en.q),
2301 .ds (),
2302
2303 // to register interface (read)
2304 .qs (cfg_mailbox_en_qs)
2305 );
2306
2307
2308 // R[status]: V(True)
2309 // F[csb]: 5:5
2310 prim_subreg_ext #(
2311 .DW (1)
2312 ) u_status_csb (
2313 .re (status_re),
2314 .we (1'b0),
2315 .wd ('0),
2316 .d (hw2reg.status.csb.d),
2317 .qre (),
2318 .qe (),
2319 .q (),
2320 .ds (),
2321 .qs (status_csb_qs)
2322 );
2323
2324 // F[tpm_csb]: 6:6
2325 prim_subreg_ext #(
2326 .DW (1)
2327 ) u_status_tpm_csb (
2328 .re (status_re),
2329 .we (1'b0),
2330 .wd ('0),
2331 .d (hw2reg.status.tpm_csb.d),
2332 .qre (),
2333 .qe (),
2334 .q (),
2335 .ds (),
2336 .qs (status_tpm_csb_qs)
2337 );
2338
2339
2340 // R[intercept_en]: V(False)
2341 // F[status]: 0:0
2342 prim_subreg #(
2343 .DW (1),
2344 .SwAccess(prim_subreg_pkg::SwAccessRW),
2345 .RESVAL (1'h0),
2346 .Mubi (1'b0)
2347 ) u_intercept_en_status (
2348 .clk_i (clk_i),
2349 .rst_ni (rst_ni),
2350
2351 // from register interface
2352 .we (intercept_en_we),
2353 .wd (intercept_en_status_wd),
2354
2355 // from internal hardware
2356 .de (1'b0),
2357 .d ('0),
2358
2359 // to internal hardware
2360 .qe (),
2361 .q (reg2hw.intercept_en.status.q),
2362 .ds (),
2363
2364 // to register interface (read)
2365 .qs (intercept_en_status_qs)
2366 );
2367
2368 // F[jedec]: 1:1
2369 prim_subreg #(
2370 .DW (1),
2371 .SwAccess(prim_subreg_pkg::SwAccessRW),
2372 .RESVAL (1'h0),
2373 .Mubi (1'b0)
2374 ) u_intercept_en_jedec (
2375 .clk_i (clk_i),
2376 .rst_ni (rst_ni),
2377
2378 // from register interface
2379 .we (intercept_en_we),
2380 .wd (intercept_en_jedec_wd),
2381
2382 // from internal hardware
2383 .de (1'b0),
2384 .d ('0),
2385
2386 // to internal hardware
2387 .qe (),
2388 .q (reg2hw.intercept_en.jedec.q),
2389 .ds (),
2390
2391 // to register interface (read)
2392 .qs (intercept_en_jedec_qs)
2393 );
2394
2395 // F[sfdp]: 2:2
2396 prim_subreg #(
2397 .DW (1),
2398 .SwAccess(prim_subreg_pkg::SwAccessRW),
2399 .RESVAL (1'h0),
2400 .Mubi (1'b0)
2401 ) u_intercept_en_sfdp (
2402 .clk_i (clk_i),
2403 .rst_ni (rst_ni),
2404
2405 // from register interface
2406 .we (intercept_en_we),
2407 .wd (intercept_en_sfdp_wd),
2408
2409 // from internal hardware
2410 .de (1'b0),
2411 .d ('0),
2412
2413 // to internal hardware
2414 .qe (),
2415 .q (reg2hw.intercept_en.sfdp.q),
2416 .ds (),
2417
2418 // to register interface (read)
2419 .qs (intercept_en_sfdp_qs)
2420 );
2421
2422 // F[mbx]: 3:3
2423 prim_subreg #(
2424 .DW (1),
2425 .SwAccess(prim_subreg_pkg::SwAccessRW),
2426 .RESVAL (1'h0),
2427 .Mubi (1'b0)
2428 ) u_intercept_en_mbx (
2429 .clk_i (clk_i),
2430 .rst_ni (rst_ni),
2431
2432 // from register interface
2433 .we (intercept_en_we),
2434 .wd (intercept_en_mbx_wd),
2435
2436 // from internal hardware
2437 .de (1'b0),
2438 .d ('0),
2439
2440 // to internal hardware
2441 .qe (),
2442 .q (reg2hw.intercept_en.mbx.q),
2443 .ds (),
2444
2445 // to register interface (read)
2446 .qs (intercept_en_mbx_qs)
2447 );
2448
2449
2450 // R[addr_mode]: V(True)
2451 logic addr_mode_qe;
2452 logic [1:0] addr_mode_flds_we;
2453 // This ignores QEs that are set to constant 0 due to read-only fields.
2454 logic unused_addr_mode_flds_we;
2455 unreachable assign unused_addr_mode_flds_we = ^(addr_mode_flds_we & 2'h2);
2456 1/1 assign addr_mode_qe = &(addr_mode_flds_we | 2'h2);
Tests: T11 T12 T14
2457 // F[addr_4b_en]: 0:0
2458 prim_subreg_ext #(
2459 .DW (1)
2460 ) u_addr_mode_addr_4b_en (
2461 .re (addr_mode_re),
2462 .we (addr_mode_we),
2463 .wd (addr_mode_addr_4b_en_wd),
2464 .d (hw2reg.addr_mode.addr_4b_en.d),
2465 .qre (),
2466 .qe (addr_mode_flds_we[0]),
2467 .q (reg2hw.addr_mode.addr_4b_en.q),
2468 .ds (),
2469 .qs (addr_mode_addr_4b_en_qs)
2470 );
2471 1/1 assign reg2hw.addr_mode.addr_4b_en.qe = addr_mode_qe;
Tests: T11 T12 T14
2472
2473 // F[pending]: 31:31
2474 prim_subreg_ext #(
2475 .DW (1)
2476 ) u_addr_mode_pending (
2477 .re (addr_mode_re),
2478 .we (1'b0),
2479 .wd ('0),
2480 .d (hw2reg.addr_mode.pending.d),
2481 .qre (),
2482 .qe (addr_mode_flds_we[1]),
2483 .q (),
2484 .ds (),
2485 .qs (addr_mode_pending_qs)
2486 );
2487
2488
2489 // R[last_read_addr]: V(True)
2490 prim_subreg_ext #(
2491 .DW (32)
2492 ) u_last_read_addr (
2493 .re (last_read_addr_re),
2494 .we (1'b0),
2495 .wd ('0),
2496 .d (hw2reg.last_read_addr.d),
2497 .qre (),
2498 .qe (),
2499 .q (),
2500 .ds (),
2501 .qs (last_read_addr_qs)
2502 );
2503
2504
2505 // R[flash_status]: V(True)
2506 logic flash_status_qe;
2507 logic [2:0] flash_status_flds_we;
2508 1/1 assign flash_status_qe = &flash_status_flds_we;
Tests: T12 T14 T15
2509 // F[busy]: 0:0
2510 prim_subreg_ext #(
2511 .DW (1)
2512 ) u_flash_status_busy (
2513 .re (flash_status_re),
2514 .we (flash_status_we),
2515 .wd (flash_status_busy_wd),
2516 .d (hw2reg.flash_status.busy.d),
2517 .qre (),
2518 .qe (flash_status_flds_we[0]),
2519 .q (reg2hw.flash_status.busy.q),
2520 .ds (),
2521 .qs (flash_status_busy_qs)
2522 );
2523 1/1 assign reg2hw.flash_status.busy.qe = flash_status_qe;
Tests: T12 T14 T15
2524
2525 // F[wel]: 1:1
2526 prim_subreg_ext #(
2527 .DW (1)
2528 ) u_flash_status_wel (
2529 .re (flash_status_re),
2530 .we (flash_status_we),
2531 .wd (flash_status_wel_wd),
2532 .d (hw2reg.flash_status.wel.d),
2533 .qre (),
2534 .qe (flash_status_flds_we[1]),
2535 .q (reg2hw.flash_status.wel.q),
2536 .ds (),
2537 .qs (flash_status_wel_qs)
2538 );
2539 1/1 assign reg2hw.flash_status.wel.qe = flash_status_qe;
Tests: T12 T14 T15
2540
2541 // F[status]: 23:2
2542 prim_subreg_ext #(
2543 .DW (22)
2544 ) u_flash_status_status (
2545 .re (flash_status_re),
2546 .we (flash_status_we),
2547 .wd (flash_status_status_wd),
2548 .d (hw2reg.flash_status.status.d),
2549 .qre (),
2550 .qe (flash_status_flds_we[2]),
2551 .q (reg2hw.flash_status.status.q),
2552 .ds (),
2553 .qs (flash_status_status_qs)
2554 );
2555 1/1 assign reg2hw.flash_status.status.qe = flash_status_qe;
Tests: T12 T14 T15
2556
2557
2558 // R[jedec_cc]: V(False)
2559 // F[cc]: 7:0
2560 prim_subreg #(
2561 .DW (8),
2562 .SwAccess(prim_subreg_pkg::SwAccessRW),
2563 .RESVAL (8'h7f),
2564 .Mubi (1'b0)
2565 ) u_jedec_cc_cc (
2566 .clk_i (clk_i),
2567 .rst_ni (rst_ni),
2568
2569 // from register interface
2570 .we (jedec_cc_we),
2571 .wd (jedec_cc_cc_wd),
2572
2573 // from internal hardware
2574 .de (1'b0),
2575 .d ('0),
2576
2577 // to internal hardware
2578 .qe (),
2579 .q (reg2hw.jedec_cc.cc.q),
2580 .ds (),
2581
2582 // to register interface (read)
2583 .qs (jedec_cc_cc_qs)
2584 );
2585
2586 // F[num_cc]: 15:8
2587 prim_subreg #(
2588 .DW (8),
2589 .SwAccess(prim_subreg_pkg::SwAccessRW),
2590 .RESVAL (8'h0),
2591 .Mubi (1'b0)
2592 ) u_jedec_cc_num_cc (
2593 .clk_i (clk_i),
2594 .rst_ni (rst_ni),
2595
2596 // from register interface
2597 .we (jedec_cc_we),
2598 .wd (jedec_cc_num_cc_wd),
2599
2600 // from internal hardware
2601 .de (1'b0),
2602 .d ('0),
2603
2604 // to internal hardware
2605 .qe (),
2606 .q (reg2hw.jedec_cc.num_cc.q),
2607 .ds (),
2608
2609 // to register interface (read)
2610 .qs (jedec_cc_num_cc_qs)
2611 );
2612
2613
2614 // R[jedec_id]: V(False)
2615 // F[id]: 15:0
2616 prim_subreg #(
2617 .DW (16),
2618 .SwAccess(prim_subreg_pkg::SwAccessRW),
2619 .RESVAL (16'h0),
2620 .Mubi (1'b0)
2621 ) u_jedec_id_id (
2622 .clk_i (clk_i),
2623 .rst_ni (rst_ni),
2624
2625 // from register interface
2626 .we (jedec_id_we),
2627 .wd (jedec_id_id_wd),
2628
2629 // from internal hardware
2630 .de (1'b0),
2631 .d ('0),
2632
2633 // to internal hardware
2634 .qe (),
2635 .q (reg2hw.jedec_id.id.q),
2636 .ds (),
2637
2638 // to register interface (read)
2639 .qs (jedec_id_id_qs)
2640 );
2641
2642 // F[mf]: 23:16
2643 prim_subreg #(
2644 .DW (8),
2645 .SwAccess(prim_subreg_pkg::SwAccessRW),
2646 .RESVAL (8'h0),
2647 .Mubi (1'b0)
2648 ) u_jedec_id_mf (
2649 .clk_i (clk_i),
2650 .rst_ni (rst_ni),
2651
2652 // from register interface
2653 .we (jedec_id_we),
2654 .wd (jedec_id_mf_wd),
2655
2656 // from internal hardware
2657 .de (1'b0),
2658 .d ('0),
2659
2660 // to internal hardware
2661 .qe (),
2662 .q (reg2hw.jedec_id.mf.q),
2663 .ds (),
2664
2665 // to register interface (read)
2666 .qs (jedec_id_mf_qs)
2667 );
2668
2669
2670 // R[read_threshold]: V(False)
2671 prim_subreg #(
2672 .DW (10),
2673 .SwAccess(prim_subreg_pkg::SwAccessRW),
2674 .RESVAL (10'h0),
2675 .Mubi (1'b0)
2676 ) u_read_threshold (
2677 .clk_i (clk_i),
2678 .rst_ni (rst_ni),
2679
2680 // from register interface
2681 .we (read_threshold_we),
2682 .wd (read_threshold_wd),
2683
2684 // from internal hardware
2685 .de (1'b0),
2686 .d ('0),
2687
2688 // to internal hardware
2689 .qe (),
2690 .q (reg2hw.read_threshold.q),
2691 .ds (),
2692
2693 // to register interface (read)
2694 .qs (read_threshold_qs)
2695 );
2696
2697
2698 // R[mailbox_addr]: V(False)
2699 prim_subreg #(
2700 .DW (32),
2701 .SwAccess(prim_subreg_pkg::SwAccessRW),
2702 .RESVAL (32'h0),
2703 .Mubi (1'b0)
2704 ) u_mailbox_addr (
2705 .clk_i (clk_i),
2706 .rst_ni (rst_ni),
2707
2708 // from register interface
2709 .we (mailbox_addr_we),
2710 .wd (mailbox_addr_wd),
2711
2712 // from internal hardware
2713 .de (1'b0),
2714 .d ('0),
2715
2716 // to internal hardware
2717 .qe (),
2718 .q (reg2hw.mailbox_addr.q),
2719 .ds (),
2720
2721 // to register interface (read)
2722 .qs (mailbox_addr_qs)
2723 );
2724
2725
2726 // R[upload_status]: V(False)
2727 // F[cmdfifo_depth]: 4:0
2728 prim_subreg #(
2729 .DW (5),
2730 .SwAccess(prim_subreg_pkg::SwAccessRO),
2731 .RESVAL (5'h0),
2732 .Mubi (1'b0)
2733 ) u_upload_status_cmdfifo_depth (
2734 .clk_i (clk_i),
2735 .rst_ni (rst_ni),
2736
2737 // from register interface
2738 .we (1'b0),
2739 .wd ('0),
2740
2741 // from internal hardware
2742 .de (hw2reg.upload_status.cmdfifo_depth.de),
2743 .d (hw2reg.upload_status.cmdfifo_depth.d),
2744
2745 // to internal hardware
2746 .qe (),
2747 .q (),
2748 .ds (),
2749
2750 // to register interface (read)
2751 .qs (upload_status_cmdfifo_depth_qs)
2752 );
2753
2754 // F[cmdfifo_notempty]: 7:7
2755 prim_subreg #(
2756 .DW (1),
2757 .SwAccess(prim_subreg_pkg::SwAccessRO),
2758 .RESVAL (1'h0),
2759 .Mubi (1'b0)
2760 ) u_upload_status_cmdfifo_notempty (
2761 .clk_i (clk_i),
2762 .rst_ni (rst_ni),
2763
2764 // from register interface
2765 .we (1'b0),
2766 .wd ('0),
2767
2768 // from internal hardware
2769 .de (hw2reg.upload_status.cmdfifo_notempty.de),
2770 .d (hw2reg.upload_status.cmdfifo_notempty.d),
2771
2772 // to internal hardware
2773 .qe (),
2774 .q (),
2775 .ds (),
2776
2777 // to register interface (read)
2778 .qs (upload_status_cmdfifo_notempty_qs)
2779 );
2780
2781 // F[addrfifo_depth]: 12:8
2782 prim_subreg #(
2783 .DW (5),
2784 .SwAccess(prim_subreg_pkg::SwAccessRO),
2785 .RESVAL (5'h0),
2786 .Mubi (1'b0)
2787 ) u_upload_status_addrfifo_depth (
2788 .clk_i (clk_i),
2789 .rst_ni (rst_ni),
2790
2791 // from register interface
2792 .we (1'b0),
2793 .wd ('0),
2794
2795 // from internal hardware
2796 .de (hw2reg.upload_status.addrfifo_depth.de),
2797 .d (hw2reg.upload_status.addrfifo_depth.d),
2798
2799 // to internal hardware
2800 .qe (),
2801 .q (),
2802 .ds (),
2803
2804 // to register interface (read)
2805 .qs (upload_status_addrfifo_depth_qs)
2806 );
2807
2808 // F[addrfifo_notempty]: 15:15
2809 prim_subreg #(
2810 .DW (1),
2811 .SwAccess(prim_subreg_pkg::SwAccessRO),
2812 .RESVAL (1'h0),
2813 .Mubi (1'b0)
2814 ) u_upload_status_addrfifo_notempty (
2815 .clk_i (clk_i),
2816 .rst_ni (rst_ni),
2817
2818 // from register interface
2819 .we (1'b0),
2820 .wd ('0),
2821
2822 // from internal hardware
2823 .de (hw2reg.upload_status.addrfifo_notempty.de),
2824 .d (hw2reg.upload_status.addrfifo_notempty.d),
2825
2826 // to internal hardware
2827 .qe (),
2828 .q (),
2829 .ds (),
2830
2831 // to register interface (read)
2832 .qs (upload_status_addrfifo_notempty_qs)
2833 );
2834
2835
2836 // R[upload_status2]: V(False)
2837 // F[payload_depth]: 8:0
2838 prim_subreg #(
2839 .DW (9),
2840 .SwAccess(prim_subreg_pkg::SwAccessRO),
2841 .RESVAL (9'h0),
2842 .Mubi (1'b0)
2843 ) u_upload_status2_payload_depth (
2844 .clk_i (clk_i),
2845 .rst_ni (rst_ni),
2846
2847 // from register interface
2848 .we (1'b0),
2849 .wd ('0),
2850
2851 // from internal hardware
2852 .de (hw2reg.upload_status2.payload_depth.de),
2853 .d (hw2reg.upload_status2.payload_depth.d),
2854
2855 // to internal hardware
2856 .qe (),
2857 .q (),
2858 .ds (),
2859
2860 // to register interface (read)
2861 .qs (upload_status2_payload_depth_qs)
2862 );
2863
2864 // F[payload_start_idx]: 23:16
2865 prim_subreg #(
2866 .DW (8),
2867 .SwAccess(prim_subreg_pkg::SwAccessRO),
2868 .RESVAL (8'h0),
2869 .Mubi (1'b0)
2870 ) u_upload_status2_payload_start_idx (
2871 .clk_i (clk_i),
2872 .rst_ni (rst_ni),
2873
2874 // from register interface
2875 .we (1'b0),
2876 .wd ('0),
2877
2878 // from internal hardware
2879 .de (hw2reg.upload_status2.payload_start_idx.de),
2880 .d (hw2reg.upload_status2.payload_start_idx.d),
2881
2882 // to internal hardware
2883 .qe (),
2884 .q (),
2885 .ds (),
2886
2887 // to register interface (read)
2888 .qs (upload_status2_payload_start_idx_qs)
2889 );
2890
2891
2892 // R[upload_cmdfifo]: V(True)
2893 // F[data]: 7:0
2894 prim_subreg_ext #(
2895 .DW (8)
2896 ) u_upload_cmdfifo_data (
2897 .re (upload_cmdfifo_re),
2898 .we (1'b0),
2899 .wd ('0),
2900 .d (hw2reg.upload_cmdfifo.data.d),
2901 .qre (reg2hw.upload_cmdfifo.data.re),
2902 .qe (),
2903 .q (reg2hw.upload_cmdfifo.data.q),
2904 .ds (),
2905 .qs (upload_cmdfifo_data_qs)
2906 );
2907
2908 // F[busy]: 13:13
2909 prim_subreg_ext #(
2910 .DW (1)
2911 ) u_upload_cmdfifo_busy (
2912 .re (upload_cmdfifo_re),
2913 .we (1'b0),
2914 .wd ('0),
2915 .d (hw2reg.upload_cmdfifo.busy.d),
2916 .qre (reg2hw.upload_cmdfifo.busy.re),
2917 .qe (),
2918 .q (reg2hw.upload_cmdfifo.busy.q),
2919 .ds (),
2920 .qs (upload_cmdfifo_busy_qs)
2921 );
2922
2923 // F[wel]: 14:14
2924 prim_subreg_ext #(
2925 .DW (1)
2926 ) u_upload_cmdfifo_wel (
2927 .re (upload_cmdfifo_re),
2928 .we (1'b0),
2929 .wd ('0),
2930 .d (hw2reg.upload_cmdfifo.wel.d),
2931 .qre (reg2hw.upload_cmdfifo.wel.re),
2932 .qe (),
2933 .q (reg2hw.upload_cmdfifo.wel.q),
2934 .ds (),
2935 .qs (upload_cmdfifo_wel_qs)
2936 );
2937
2938 // F[addr4b_mode]: 15:15
2939 prim_subreg_ext #(
2940 .DW (1)
2941 ) u_upload_cmdfifo_addr4b_mode (
2942 .re (upload_cmdfifo_re),
2943 .we (1'b0),
2944 .wd ('0),
2945 .d (hw2reg.upload_cmdfifo.addr4b_mode.d),
2946 .qre (reg2hw.upload_cmdfifo.addr4b_mode.re),
2947 .qe (),
2948 .q (reg2hw.upload_cmdfifo.addr4b_mode.q),
2949 .ds (),
2950 .qs (upload_cmdfifo_addr4b_mode_qs)
2951 );
2952
2953
2954 // R[upload_addrfifo]: V(True)
2955 prim_subreg_ext #(
2956 .DW (32)
2957 ) u_upload_addrfifo (
2958 .re (upload_addrfifo_re),
2959 .we (1'b0),
2960 .wd ('0),
2961 .d (hw2reg.upload_addrfifo.d),
2962 .qre (reg2hw.upload_addrfifo.re),
2963 .qe (),
2964 .q (reg2hw.upload_addrfifo.q),
2965 .ds (),
2966 .qs (upload_addrfifo_qs)
2967 );
2968
2969
2970 // Subregister 0 of Multireg cmd_filter
2971 // R[cmd_filter_0]: V(False)
2972 // F[filter_0]: 0:0
2973 prim_subreg #(
2974 .DW (1),
2975 .SwAccess(prim_subreg_pkg::SwAccessRW),
2976 .RESVAL (1'h0),
2977 .Mubi (1'b0)
2978 ) u_cmd_filter_0_filter_0 (
2979 .clk_i (clk_i),
2980 .rst_ni (rst_ni),
2981
2982 // from register interface
2983 .we (cmd_filter_0_we),
2984 .wd (cmd_filter_0_filter_0_wd),
2985
2986 // from internal hardware
2987 .de (1'b0),
2988 .d ('0),
2989
2990 // to internal hardware
2991 .qe (),
2992 .q (reg2hw.cmd_filter[0].q),
2993 .ds (),
2994
2995 // to register interface (read)
2996 .qs (cmd_filter_0_filter_0_qs)
2997 );
2998
2999 // F[filter_1]: 1:1
3000 prim_subreg #(
3001 .DW (1),
3002 .SwAccess(prim_subreg_pkg::SwAccessRW),
3003 .RESVAL (1'h0),
3004 .Mubi (1'b0)
3005 ) u_cmd_filter_0_filter_1 (
3006 .clk_i (clk_i),
3007 .rst_ni (rst_ni),
3008
3009 // from register interface
3010 .we (cmd_filter_0_we),
3011 .wd (cmd_filter_0_filter_1_wd),
3012
3013 // from internal hardware
3014 .de (1'b0),
3015 .d ('0),
3016
3017 // to internal hardware
3018 .qe (),
3019 .q (reg2hw.cmd_filter[1].q),
3020 .ds (),
3021
3022 // to register interface (read)
3023 .qs (cmd_filter_0_filter_1_qs)
3024 );
3025
3026 // F[filter_2]: 2:2
3027 prim_subreg #(
3028 .DW (1),
3029 .SwAccess(prim_subreg_pkg::SwAccessRW),
3030 .RESVAL (1'h0),
3031 .Mubi (1'b0)
3032 ) u_cmd_filter_0_filter_2 (
3033 .clk_i (clk_i),
3034 .rst_ni (rst_ni),
3035
3036 // from register interface
3037 .we (cmd_filter_0_we),
3038 .wd (cmd_filter_0_filter_2_wd),
3039
3040 // from internal hardware
3041 .de (1'b0),
3042 .d ('0),
3043
3044 // to internal hardware
3045 .qe (),
3046 .q (reg2hw.cmd_filter[2].q),
3047 .ds (),
3048
3049 // to register interface (read)
3050 .qs (cmd_filter_0_filter_2_qs)
3051 );
3052
3053 // F[filter_3]: 3:3
3054 prim_subreg #(
3055 .DW (1),
3056 .SwAccess(prim_subreg_pkg::SwAccessRW),
3057 .RESVAL (1'h0),
3058 .Mubi (1'b0)
3059 ) u_cmd_filter_0_filter_3 (
3060 .clk_i (clk_i),
3061 .rst_ni (rst_ni),
3062
3063 // from register interface
3064 .we (cmd_filter_0_we),
3065 .wd (cmd_filter_0_filter_3_wd),
3066
3067 // from internal hardware
3068 .de (1'b0),
3069 .d ('0),
3070
3071 // to internal hardware
3072 .qe (),
3073 .q (reg2hw.cmd_filter[3].q),
3074 .ds (),
3075
3076 // to register interface (read)
3077 .qs (cmd_filter_0_filter_3_qs)
3078 );
3079
3080 // F[filter_4]: 4:4
3081 prim_subreg #(
3082 .DW (1),
3083 .SwAccess(prim_subreg_pkg::SwAccessRW),
3084 .RESVAL (1'h0),
3085 .Mubi (1'b0)
3086 ) u_cmd_filter_0_filter_4 (
3087 .clk_i (clk_i),
3088 .rst_ni (rst_ni),
3089
3090 // from register interface
3091 .we (cmd_filter_0_we),
3092 .wd (cmd_filter_0_filter_4_wd),
3093
3094 // from internal hardware
3095 .de (1'b0),
3096 .d ('0),
3097
3098 // to internal hardware
3099 .qe (),
3100 .q (reg2hw.cmd_filter[4].q),
3101 .ds (),
3102
3103 // to register interface (read)
3104 .qs (cmd_filter_0_filter_4_qs)
3105 );
3106
3107 // F[filter_5]: 5:5
3108 prim_subreg #(
3109 .DW (1),
3110 .SwAccess(prim_subreg_pkg::SwAccessRW),
3111 .RESVAL (1'h0),
3112 .Mubi (1'b0)
3113 ) u_cmd_filter_0_filter_5 (
3114 .clk_i (clk_i),
3115 .rst_ni (rst_ni),
3116
3117 // from register interface
3118 .we (cmd_filter_0_we),
3119 .wd (cmd_filter_0_filter_5_wd),
3120
3121 // from internal hardware
3122 .de (1'b0),
3123 .d ('0),
3124
3125 // to internal hardware
3126 .qe (),
3127 .q (reg2hw.cmd_filter[5].q),
3128 .ds (),
3129
3130 // to register interface (read)
3131 .qs (cmd_filter_0_filter_5_qs)
3132 );
3133
3134 // F[filter_6]: 6:6
3135 prim_subreg #(
3136 .DW (1),
3137 .SwAccess(prim_subreg_pkg::SwAccessRW),
3138 .RESVAL (1'h0),
3139 .Mubi (1'b0)
3140 ) u_cmd_filter_0_filter_6 (
3141 .clk_i (clk_i),
3142 .rst_ni (rst_ni),
3143
3144 // from register interface
3145 .we (cmd_filter_0_we),
3146 .wd (cmd_filter_0_filter_6_wd),
3147
3148 // from internal hardware
3149 .de (1'b0),
3150 .d ('0),
3151
3152 // to internal hardware
3153 .qe (),
3154 .q (reg2hw.cmd_filter[6].q),
3155 .ds (),
3156
3157 // to register interface (read)
3158 .qs (cmd_filter_0_filter_6_qs)
3159 );
3160
3161 // F[filter_7]: 7:7
3162 prim_subreg #(
3163 .DW (1),
3164 .SwAccess(prim_subreg_pkg::SwAccessRW),
3165 .RESVAL (1'h0),
3166 .Mubi (1'b0)
3167 ) u_cmd_filter_0_filter_7 (
3168 .clk_i (clk_i),
3169 .rst_ni (rst_ni),
3170
3171 // from register interface
3172 .we (cmd_filter_0_we),
3173 .wd (cmd_filter_0_filter_7_wd),
3174
3175 // from internal hardware
3176 .de (1'b0),
3177 .d ('0),
3178
3179 // to internal hardware
3180 .qe (),
3181 .q (reg2hw.cmd_filter[7].q),
3182 .ds (),
3183
3184 // to register interface (read)
3185 .qs (cmd_filter_0_filter_7_qs)
3186 );
3187
3188 // F[filter_8]: 8:8
3189 prim_subreg #(
3190 .DW (1),
3191 .SwAccess(prim_subreg_pkg::SwAccessRW),
3192 .RESVAL (1'h0),
3193 .Mubi (1'b0)
3194 ) u_cmd_filter_0_filter_8 (
3195 .clk_i (clk_i),
3196 .rst_ni (rst_ni),
3197
3198 // from register interface
3199 .we (cmd_filter_0_we),
3200 .wd (cmd_filter_0_filter_8_wd),
3201
3202 // from internal hardware
3203 .de (1'b0),
3204 .d ('0),
3205
3206 // to internal hardware
3207 .qe (),
3208 .q (reg2hw.cmd_filter[8].q),
3209 .ds (),
3210
3211 // to register interface (read)
3212 .qs (cmd_filter_0_filter_8_qs)
3213 );
3214
3215 // F[filter_9]: 9:9
3216 prim_subreg #(
3217 .DW (1),
3218 .SwAccess(prim_subreg_pkg::SwAccessRW),
3219 .RESVAL (1'h0),
3220 .Mubi (1'b0)
3221 ) u_cmd_filter_0_filter_9 (
3222 .clk_i (clk_i),
3223 .rst_ni (rst_ni),
3224
3225 // from register interface
3226 .we (cmd_filter_0_we),
3227 .wd (cmd_filter_0_filter_9_wd),
3228
3229 // from internal hardware
3230 .de (1'b0),
3231 .d ('0),
3232
3233 // to internal hardware
3234 .qe (),
3235 .q (reg2hw.cmd_filter[9].q),
3236 .ds (),
3237
3238 // to register interface (read)
3239 .qs (cmd_filter_0_filter_9_qs)
3240 );
3241
3242 // F[filter_10]: 10:10
3243 prim_subreg #(
3244 .DW (1),
3245 .SwAccess(prim_subreg_pkg::SwAccessRW),
3246 .RESVAL (1'h0),
3247 .Mubi (1'b0)
3248 ) u_cmd_filter_0_filter_10 (
3249 .clk_i (clk_i),
3250 .rst_ni (rst_ni),
3251
3252 // from register interface
3253 .we (cmd_filter_0_we),
3254 .wd (cmd_filter_0_filter_10_wd),
3255
3256 // from internal hardware
3257 .de (1'b0),
3258 .d ('0),
3259
3260 // to internal hardware
3261 .qe (),
3262 .q (reg2hw.cmd_filter[10].q),
3263 .ds (),
3264
3265 // to register interface (read)
3266 .qs (cmd_filter_0_filter_10_qs)
3267 );
3268
3269 // F[filter_11]: 11:11
3270 prim_subreg #(
3271 .DW (1),
3272 .SwAccess(prim_subreg_pkg::SwAccessRW),
3273 .RESVAL (1'h0),
3274 .Mubi (1'b0)
3275 ) u_cmd_filter_0_filter_11 (
3276 .clk_i (clk_i),
3277 .rst_ni (rst_ni),
3278
3279 // from register interface
3280 .we (cmd_filter_0_we),
3281 .wd (cmd_filter_0_filter_11_wd),
3282
3283 // from internal hardware
3284 .de (1'b0),
3285 .d ('0),
3286
3287 // to internal hardware
3288 .qe (),
3289 .q (reg2hw.cmd_filter[11].q),
3290 .ds (),
3291
3292 // to register interface (read)
3293 .qs (cmd_filter_0_filter_11_qs)
3294 );
3295
3296 // F[filter_12]: 12:12
3297 prim_subreg #(
3298 .DW (1),
3299 .SwAccess(prim_subreg_pkg::SwAccessRW),
3300 .RESVAL (1'h0),
3301 .Mubi (1'b0)
3302 ) u_cmd_filter_0_filter_12 (
3303 .clk_i (clk_i),
3304 .rst_ni (rst_ni),
3305
3306 // from register interface
3307 .we (cmd_filter_0_we),
3308 .wd (cmd_filter_0_filter_12_wd),
3309
3310 // from internal hardware
3311 .de (1'b0),
3312 .d ('0),
3313
3314 // to internal hardware
3315 .qe (),
3316 .q (reg2hw.cmd_filter[12].q),
3317 .ds (),
3318
3319 // to register interface (read)
3320 .qs (cmd_filter_0_filter_12_qs)
3321 );
3322
3323 // F[filter_13]: 13:13
3324 prim_subreg #(
3325 .DW (1),
3326 .SwAccess(prim_subreg_pkg::SwAccessRW),
3327 .RESVAL (1'h0),
3328 .Mubi (1'b0)
3329 ) u_cmd_filter_0_filter_13 (
3330 .clk_i (clk_i),
3331 .rst_ni (rst_ni),
3332
3333 // from register interface
3334 .we (cmd_filter_0_we),
3335 .wd (cmd_filter_0_filter_13_wd),
3336
3337 // from internal hardware
3338 .de (1'b0),
3339 .d ('0),
3340
3341 // to internal hardware
3342 .qe (),
3343 .q (reg2hw.cmd_filter[13].q),
3344 .ds (),
3345
3346 // to register interface (read)
3347 .qs (cmd_filter_0_filter_13_qs)
3348 );
3349
3350 // F[filter_14]: 14:14
3351 prim_subreg #(
3352 .DW (1),
3353 .SwAccess(prim_subreg_pkg::SwAccessRW),
3354 .RESVAL (1'h0),
3355 .Mubi (1'b0)
3356 ) u_cmd_filter_0_filter_14 (
3357 .clk_i (clk_i),
3358 .rst_ni (rst_ni),
3359
3360 // from register interface
3361 .we (cmd_filter_0_we),
3362 .wd (cmd_filter_0_filter_14_wd),
3363
3364 // from internal hardware
3365 .de (1'b0),
3366 .d ('0),
3367
3368 // to internal hardware
3369 .qe (),
3370 .q (reg2hw.cmd_filter[14].q),
3371 .ds (),
3372
3373 // to register interface (read)
3374 .qs (cmd_filter_0_filter_14_qs)
3375 );
3376
3377 // F[filter_15]: 15:15
3378 prim_subreg #(
3379 .DW (1),
3380 .SwAccess(prim_subreg_pkg::SwAccessRW),
3381 .RESVAL (1'h0),
3382 .Mubi (1'b0)
3383 ) u_cmd_filter_0_filter_15 (
3384 .clk_i (clk_i),
3385 .rst_ni (rst_ni),
3386
3387 // from register interface
3388 .we (cmd_filter_0_we),
3389 .wd (cmd_filter_0_filter_15_wd),
3390
3391 // from internal hardware
3392 .de (1'b0),
3393 .d ('0),
3394
3395 // to internal hardware
3396 .qe (),
3397 .q (reg2hw.cmd_filter[15].q),
3398 .ds (),
3399
3400 // to register interface (read)
3401 .qs (cmd_filter_0_filter_15_qs)
3402 );
3403
3404 // F[filter_16]: 16:16
3405 prim_subreg #(
3406 .DW (1),
3407 .SwAccess(prim_subreg_pkg::SwAccessRW),
3408 .RESVAL (1'h0),
3409 .Mubi (1'b0)
3410 ) u_cmd_filter_0_filter_16 (
3411 .clk_i (clk_i),
3412 .rst_ni (rst_ni),
3413
3414 // from register interface
3415 .we (cmd_filter_0_we),
3416 .wd (cmd_filter_0_filter_16_wd),
3417
3418 // from internal hardware
3419 .de (1'b0),
3420 .d ('0),
3421
3422 // to internal hardware
3423 .qe (),
3424 .q (reg2hw.cmd_filter[16].q),
3425 .ds (),
3426
3427 // to register interface (read)
3428 .qs (cmd_filter_0_filter_16_qs)
3429 );
3430
3431 // F[filter_17]: 17:17
3432 prim_subreg #(
3433 .DW (1),
3434 .SwAccess(prim_subreg_pkg::SwAccessRW),
3435 .RESVAL (1'h0),
3436 .Mubi (1'b0)
3437 ) u_cmd_filter_0_filter_17 (
3438 .clk_i (clk_i),
3439 .rst_ni (rst_ni),
3440
3441 // from register interface
3442 .we (cmd_filter_0_we),
3443 .wd (cmd_filter_0_filter_17_wd),
3444
3445 // from internal hardware
3446 .de (1'b0),
3447 .d ('0),
3448
3449 // to internal hardware
3450 .qe (),
3451 .q (reg2hw.cmd_filter[17].q),
3452 .ds (),
3453
3454 // to register interface (read)
3455 .qs (cmd_filter_0_filter_17_qs)
3456 );
3457
3458 // F[filter_18]: 18:18
3459 prim_subreg #(
3460 .DW (1),
3461 .SwAccess(prim_subreg_pkg::SwAccessRW),
3462 .RESVAL (1'h0),
3463 .Mubi (1'b0)
3464 ) u_cmd_filter_0_filter_18 (
3465 .clk_i (clk_i),
3466 .rst_ni (rst_ni),
3467
3468 // from register interface
3469 .we (cmd_filter_0_we),
3470 .wd (cmd_filter_0_filter_18_wd),
3471
3472 // from internal hardware
3473 .de (1'b0),
3474 .d ('0),
3475
3476 // to internal hardware
3477 .qe (),
3478 .q (reg2hw.cmd_filter[18].q),
3479 .ds (),
3480
3481 // to register interface (read)
3482 .qs (cmd_filter_0_filter_18_qs)
3483 );
3484
3485 // F[filter_19]: 19:19
3486 prim_subreg #(
3487 .DW (1),
3488 .SwAccess(prim_subreg_pkg::SwAccessRW),
3489 .RESVAL (1'h0),
3490 .Mubi (1'b0)
3491 ) u_cmd_filter_0_filter_19 (
3492 .clk_i (clk_i),
3493 .rst_ni (rst_ni),
3494
3495 // from register interface
3496 .we (cmd_filter_0_we),
3497 .wd (cmd_filter_0_filter_19_wd),
3498
3499 // from internal hardware
3500 .de (1'b0),
3501 .d ('0),
3502
3503 // to internal hardware
3504 .qe (),
3505 .q (reg2hw.cmd_filter[19].q),
3506 .ds (),
3507
3508 // to register interface (read)
3509 .qs (cmd_filter_0_filter_19_qs)
3510 );
3511
3512 // F[filter_20]: 20:20
3513 prim_subreg #(
3514 .DW (1),
3515 .SwAccess(prim_subreg_pkg::SwAccessRW),
3516 .RESVAL (1'h0),
3517 .Mubi (1'b0)
3518 ) u_cmd_filter_0_filter_20 (
3519 .clk_i (clk_i),
3520 .rst_ni (rst_ni),
3521
3522 // from register interface
3523 .we (cmd_filter_0_we),
3524 .wd (cmd_filter_0_filter_20_wd),
3525
3526 // from internal hardware
3527 .de (1'b0),
3528 .d ('0),
3529
3530 // to internal hardware
3531 .qe (),
3532 .q (reg2hw.cmd_filter[20].q),
3533 .ds (),
3534
3535 // to register interface (read)
3536 .qs (cmd_filter_0_filter_20_qs)
3537 );
3538
3539 // F[filter_21]: 21:21
3540 prim_subreg #(
3541 .DW (1),
3542 .SwAccess(prim_subreg_pkg::SwAccessRW),
3543 .RESVAL (1'h0),
3544 .Mubi (1'b0)
3545 ) u_cmd_filter_0_filter_21 (
3546 .clk_i (clk_i),
3547 .rst_ni (rst_ni),
3548
3549 // from register interface
3550 .we (cmd_filter_0_we),
3551 .wd (cmd_filter_0_filter_21_wd),
3552
3553 // from internal hardware
3554 .de (1'b0),
3555 .d ('0),
3556
3557 // to internal hardware
3558 .qe (),
3559 .q (reg2hw.cmd_filter[21].q),
3560 .ds (),
3561
3562 // to register interface (read)
3563 .qs (cmd_filter_0_filter_21_qs)
3564 );
3565
3566 // F[filter_22]: 22:22
3567 prim_subreg #(
3568 .DW (1),
3569 .SwAccess(prim_subreg_pkg::SwAccessRW),
3570 .RESVAL (1'h0),
3571 .Mubi (1'b0)
3572 ) u_cmd_filter_0_filter_22 (
3573 .clk_i (clk_i),
3574 .rst_ni (rst_ni),
3575
3576 // from register interface
3577 .we (cmd_filter_0_we),
3578 .wd (cmd_filter_0_filter_22_wd),
3579
3580 // from internal hardware
3581 .de (1'b0),
3582 .d ('0),
3583
3584 // to internal hardware
3585 .qe (),
3586 .q (reg2hw.cmd_filter[22].q),
3587 .ds (),
3588
3589 // to register interface (read)
3590 .qs (cmd_filter_0_filter_22_qs)
3591 );
3592
3593 // F[filter_23]: 23:23
3594 prim_subreg #(
3595 .DW (1),
3596 .SwAccess(prim_subreg_pkg::SwAccessRW),
3597 .RESVAL (1'h0),
3598 .Mubi (1'b0)
3599 ) u_cmd_filter_0_filter_23 (
3600 .clk_i (clk_i),
3601 .rst_ni (rst_ni),
3602
3603 // from register interface
3604 .we (cmd_filter_0_we),
3605 .wd (cmd_filter_0_filter_23_wd),
3606
3607 // from internal hardware
3608 .de (1'b0),
3609 .d ('0),
3610
3611 // to internal hardware
3612 .qe (),
3613 .q (reg2hw.cmd_filter[23].q),
3614 .ds (),
3615
3616 // to register interface (read)
3617 .qs (cmd_filter_0_filter_23_qs)
3618 );
3619
3620 // F[filter_24]: 24:24
3621 prim_subreg #(
3622 .DW (1),
3623 .SwAccess(prim_subreg_pkg::SwAccessRW),
3624 .RESVAL (1'h0),
3625 .Mubi (1'b0)
3626 ) u_cmd_filter_0_filter_24 (
3627 .clk_i (clk_i),
3628 .rst_ni (rst_ni),
3629
3630 // from register interface
3631 .we (cmd_filter_0_we),
3632 .wd (cmd_filter_0_filter_24_wd),
3633
3634 // from internal hardware
3635 .de (1'b0),
3636 .d ('0),
3637
3638 // to internal hardware
3639 .qe (),
3640 .q (reg2hw.cmd_filter[24].q),
3641 .ds (),
3642
3643 // to register interface (read)
3644 .qs (cmd_filter_0_filter_24_qs)
3645 );
3646
3647 // F[filter_25]: 25:25
3648 prim_subreg #(
3649 .DW (1),
3650 .SwAccess(prim_subreg_pkg::SwAccessRW),
3651 .RESVAL (1'h0),
3652 .Mubi (1'b0)
3653 ) u_cmd_filter_0_filter_25 (
3654 .clk_i (clk_i),
3655 .rst_ni (rst_ni),
3656
3657 // from register interface
3658 .we (cmd_filter_0_we),
3659 .wd (cmd_filter_0_filter_25_wd),
3660
3661 // from internal hardware
3662 .de (1'b0),
3663 .d ('0),
3664
3665 // to internal hardware
3666 .qe (),
3667 .q (reg2hw.cmd_filter[25].q),
3668 .ds (),
3669
3670 // to register interface (read)
3671 .qs (cmd_filter_0_filter_25_qs)
3672 );
3673
3674 // F[filter_26]: 26:26
3675 prim_subreg #(
3676 .DW (1),
3677 .SwAccess(prim_subreg_pkg::SwAccessRW),
3678 .RESVAL (1'h0),
3679 .Mubi (1'b0)
3680 ) u_cmd_filter_0_filter_26 (
3681 .clk_i (clk_i),
3682 .rst_ni (rst_ni),
3683
3684 // from register interface
3685 .we (cmd_filter_0_we),
3686 .wd (cmd_filter_0_filter_26_wd),
3687
3688 // from internal hardware
3689 .de (1'b0),
3690 .d ('0),
3691
3692 // to internal hardware
3693 .qe (),
3694 .q (reg2hw.cmd_filter[26].q),
3695 .ds (),
3696
3697 // to register interface (read)
3698 .qs (cmd_filter_0_filter_26_qs)
3699 );
3700
3701 // F[filter_27]: 27:27
3702 prim_subreg #(
3703 .DW (1),
3704 .SwAccess(prim_subreg_pkg::SwAccessRW),
3705 .RESVAL (1'h0),
3706 .Mubi (1'b0)
3707 ) u_cmd_filter_0_filter_27 (
3708 .clk_i (clk_i),
3709 .rst_ni (rst_ni),
3710
3711 // from register interface
3712 .we (cmd_filter_0_we),
3713 .wd (cmd_filter_0_filter_27_wd),
3714
3715 // from internal hardware
3716 .de (1'b0),
3717 .d ('0),
3718
3719 // to internal hardware
3720 .qe (),
3721 .q (reg2hw.cmd_filter[27].q),
3722 .ds (),
3723
3724 // to register interface (read)
3725 .qs (cmd_filter_0_filter_27_qs)
3726 );
3727
3728 // F[filter_28]: 28:28
3729 prim_subreg #(
3730 .DW (1),
3731 .SwAccess(prim_subreg_pkg::SwAccessRW),
3732 .RESVAL (1'h0),
3733 .Mubi (1'b0)
3734 ) u_cmd_filter_0_filter_28 (
3735 .clk_i (clk_i),
3736 .rst_ni (rst_ni),
3737
3738 // from register interface
3739 .we (cmd_filter_0_we),
3740 .wd (cmd_filter_0_filter_28_wd),
3741
3742 // from internal hardware
3743 .de (1'b0),
3744 .d ('0),
3745
3746 // to internal hardware
3747 .qe (),
3748 .q (reg2hw.cmd_filter[28].q),
3749 .ds (),
3750
3751 // to register interface (read)
3752 .qs (cmd_filter_0_filter_28_qs)
3753 );
3754
3755 // F[filter_29]: 29:29
3756 prim_subreg #(
3757 .DW (1),
3758 .SwAccess(prim_subreg_pkg::SwAccessRW),
3759 .RESVAL (1'h0),
3760 .Mubi (1'b0)
3761 ) u_cmd_filter_0_filter_29 (
3762 .clk_i (clk_i),
3763 .rst_ni (rst_ni),
3764
3765 // from register interface
3766 .we (cmd_filter_0_we),
3767 .wd (cmd_filter_0_filter_29_wd),
3768
3769 // from internal hardware
3770 .de (1'b0),
3771 .d ('0),
3772
3773 // to internal hardware
3774 .qe (),
3775 .q (reg2hw.cmd_filter[29].q),
3776 .ds (),
3777
3778 // to register interface (read)
3779 .qs (cmd_filter_0_filter_29_qs)
3780 );
3781
3782 // F[filter_30]: 30:30
3783 prim_subreg #(
3784 .DW (1),
3785 .SwAccess(prim_subreg_pkg::SwAccessRW),
3786 .RESVAL (1'h0),
3787 .Mubi (1'b0)
3788 ) u_cmd_filter_0_filter_30 (
3789 .clk_i (clk_i),
3790 .rst_ni (rst_ni),
3791
3792 // from register interface
3793 .we (cmd_filter_0_we),
3794 .wd (cmd_filter_0_filter_30_wd),
3795
3796 // from internal hardware
3797 .de (1'b0),
3798 .d ('0),
3799
3800 // to internal hardware
3801 .qe (),
3802 .q (reg2hw.cmd_filter[30].q),
3803 .ds (),
3804
3805 // to register interface (read)
3806 .qs (cmd_filter_0_filter_30_qs)
3807 );
3808
3809 // F[filter_31]: 31:31
3810 prim_subreg #(
3811 .DW (1),
3812 .SwAccess(prim_subreg_pkg::SwAccessRW),
3813 .RESVAL (1'h0),
3814 .Mubi (1'b0)
3815 ) u_cmd_filter_0_filter_31 (
3816 .clk_i (clk_i),
3817 .rst_ni (rst_ni),
3818
3819 // from register interface
3820 .we (cmd_filter_0_we),
3821 .wd (cmd_filter_0_filter_31_wd),
3822
3823 // from internal hardware
3824 .de (1'b0),
3825 .d ('0),
3826
3827 // to internal hardware
3828 .qe (),
3829 .q (reg2hw.cmd_filter[31].q),
3830 .ds (),
3831
3832 // to register interface (read)
3833 .qs (cmd_filter_0_filter_31_qs)
3834 );
3835
3836
3837 // Subregister 1 of Multireg cmd_filter
3838 // R[cmd_filter_1]: V(False)
3839 // F[filter_32]: 0:0
3840 prim_subreg #(
3841 .DW (1),
3842 .SwAccess(prim_subreg_pkg::SwAccessRW),
3843 .RESVAL (1'h0),
3844 .Mubi (1'b0)
3845 ) u_cmd_filter_1_filter_32 (
3846 .clk_i (clk_i),
3847 .rst_ni (rst_ni),
3848
3849 // from register interface
3850 .we (cmd_filter_1_we),
3851 .wd (cmd_filter_1_filter_32_wd),
3852
3853 // from internal hardware
3854 .de (1'b0),
3855 .d ('0),
3856
3857 // to internal hardware
3858 .qe (),
3859 .q (reg2hw.cmd_filter[32].q),
3860 .ds (),
3861
3862 // to register interface (read)
3863 .qs (cmd_filter_1_filter_32_qs)
3864 );
3865
3866 // F[filter_33]: 1:1
3867 prim_subreg #(
3868 .DW (1),
3869 .SwAccess(prim_subreg_pkg::SwAccessRW),
3870 .RESVAL (1'h0),
3871 .Mubi (1'b0)
3872 ) u_cmd_filter_1_filter_33 (
3873 .clk_i (clk_i),
3874 .rst_ni (rst_ni),
3875
3876 // from register interface
3877 .we (cmd_filter_1_we),
3878 .wd (cmd_filter_1_filter_33_wd),
3879
3880 // from internal hardware
3881 .de (1'b0),
3882 .d ('0),
3883
3884 // to internal hardware
3885 .qe (),
3886 .q (reg2hw.cmd_filter[33].q),
3887 .ds (),
3888
3889 // to register interface (read)
3890 .qs (cmd_filter_1_filter_33_qs)
3891 );
3892
3893 // F[filter_34]: 2:2
3894 prim_subreg #(
3895 .DW (1),
3896 .SwAccess(prim_subreg_pkg::SwAccessRW),
3897 .RESVAL (1'h0),
3898 .Mubi (1'b0)
3899 ) u_cmd_filter_1_filter_34 (
3900 .clk_i (clk_i),
3901 .rst_ni (rst_ni),
3902
3903 // from register interface
3904 .we (cmd_filter_1_we),
3905 .wd (cmd_filter_1_filter_34_wd),
3906
3907 // from internal hardware
3908 .de (1'b0),
3909 .d ('0),
3910
3911 // to internal hardware
3912 .qe (),
3913 .q (reg2hw.cmd_filter[34].q),
3914 .ds (),
3915
3916 // to register interface (read)
3917 .qs (cmd_filter_1_filter_34_qs)
3918 );
3919
3920 // F[filter_35]: 3:3
3921 prim_subreg #(
3922 .DW (1),
3923 .SwAccess(prim_subreg_pkg::SwAccessRW),
3924 .RESVAL (1'h0),
3925 .Mubi (1'b0)
3926 ) u_cmd_filter_1_filter_35 (
3927 .clk_i (clk_i),
3928 .rst_ni (rst_ni),
3929
3930 // from register interface
3931 .we (cmd_filter_1_we),
3932 .wd (cmd_filter_1_filter_35_wd),
3933
3934 // from internal hardware
3935 .de (1'b0),
3936 .d ('0),
3937
3938 // to internal hardware
3939 .qe (),
3940 .q (reg2hw.cmd_filter[35].q),
3941 .ds (),
3942
3943 // to register interface (read)
3944 .qs (cmd_filter_1_filter_35_qs)
3945 );
3946
3947 // F[filter_36]: 4:4
3948 prim_subreg #(
3949 .DW (1),
3950 .SwAccess(prim_subreg_pkg::SwAccessRW),
3951 .RESVAL (1'h0),
3952 .Mubi (1'b0)
3953 ) u_cmd_filter_1_filter_36 (
3954 .clk_i (clk_i),
3955 .rst_ni (rst_ni),
3956
3957 // from register interface
3958 .we (cmd_filter_1_we),
3959 .wd (cmd_filter_1_filter_36_wd),
3960
3961 // from internal hardware
3962 .de (1'b0),
3963 .d ('0),
3964
3965 // to internal hardware
3966 .qe (),
3967 .q (reg2hw.cmd_filter[36].q),
3968 .ds (),
3969
3970 // to register interface (read)
3971 .qs (cmd_filter_1_filter_36_qs)
3972 );
3973
3974 // F[filter_37]: 5:5
3975 prim_subreg #(
3976 .DW (1),
3977 .SwAccess(prim_subreg_pkg::SwAccessRW),
3978 .RESVAL (1'h0),
3979 .Mubi (1'b0)
3980 ) u_cmd_filter_1_filter_37 (
3981 .clk_i (clk_i),
3982 .rst_ni (rst_ni),
3983
3984 // from register interface
3985 .we (cmd_filter_1_we),
3986 .wd (cmd_filter_1_filter_37_wd),
3987
3988 // from internal hardware
3989 .de (1'b0),
3990 .d ('0),
3991
3992 // to internal hardware
3993 .qe (),
3994 .q (reg2hw.cmd_filter[37].q),
3995 .ds (),
3996
3997 // to register interface (read)
3998 .qs (cmd_filter_1_filter_37_qs)
3999 );
4000
4001 // F[filter_38]: 6:6
4002 prim_subreg #(
4003 .DW (1),
4004 .SwAccess(prim_subreg_pkg::SwAccessRW),
4005 .RESVAL (1'h0),
4006 .Mubi (1'b0)
4007 ) u_cmd_filter_1_filter_38 (
4008 .clk_i (clk_i),
4009 .rst_ni (rst_ni),
4010
4011 // from register interface
4012 .we (cmd_filter_1_we),
4013 .wd (cmd_filter_1_filter_38_wd),
4014
4015 // from internal hardware
4016 .de (1'b0),
4017 .d ('0),
4018
4019 // to internal hardware
4020 .qe (),
4021 .q (reg2hw.cmd_filter[38].q),
4022 .ds (),
4023
4024 // to register interface (read)
4025 .qs (cmd_filter_1_filter_38_qs)
4026 );
4027
4028 // F[filter_39]: 7:7
4029 prim_subreg #(
4030 .DW (1),
4031 .SwAccess(prim_subreg_pkg::SwAccessRW),
4032 .RESVAL (1'h0),
4033 .Mubi (1'b0)
4034 ) u_cmd_filter_1_filter_39 (
4035 .clk_i (clk_i),
4036 .rst_ni (rst_ni),
4037
4038 // from register interface
4039 .we (cmd_filter_1_we),
4040 .wd (cmd_filter_1_filter_39_wd),
4041
4042 // from internal hardware
4043 .de (1'b0),
4044 .d ('0),
4045
4046 // to internal hardware
4047 .qe (),
4048 .q (reg2hw.cmd_filter[39].q),
4049 .ds (),
4050
4051 // to register interface (read)
4052 .qs (cmd_filter_1_filter_39_qs)
4053 );
4054
4055 // F[filter_40]: 8:8
4056 prim_subreg #(
4057 .DW (1),
4058 .SwAccess(prim_subreg_pkg::SwAccessRW),
4059 .RESVAL (1'h0),
4060 .Mubi (1'b0)
4061 ) u_cmd_filter_1_filter_40 (
4062 .clk_i (clk_i),
4063 .rst_ni (rst_ni),
4064
4065 // from register interface
4066 .we (cmd_filter_1_we),
4067 .wd (cmd_filter_1_filter_40_wd),
4068
4069 // from internal hardware
4070 .de (1'b0),
4071 .d ('0),
4072
4073 // to internal hardware
4074 .qe (),
4075 .q (reg2hw.cmd_filter[40].q),
4076 .ds (),
4077
4078 // to register interface (read)
4079 .qs (cmd_filter_1_filter_40_qs)
4080 );
4081
4082 // F[filter_41]: 9:9
4083 prim_subreg #(
4084 .DW (1),
4085 .SwAccess(prim_subreg_pkg::SwAccessRW),
4086 .RESVAL (1'h0),
4087 .Mubi (1'b0)
4088 ) u_cmd_filter_1_filter_41 (
4089 .clk_i (clk_i),
4090 .rst_ni (rst_ni),
4091
4092 // from register interface
4093 .we (cmd_filter_1_we),
4094 .wd (cmd_filter_1_filter_41_wd),
4095
4096 // from internal hardware
4097 .de (1'b0),
4098 .d ('0),
4099
4100 // to internal hardware
4101 .qe (),
4102 .q (reg2hw.cmd_filter[41].q),
4103 .ds (),
4104
4105 // to register interface (read)
4106 .qs (cmd_filter_1_filter_41_qs)
4107 );
4108
4109 // F[filter_42]: 10:10
4110 prim_subreg #(
4111 .DW (1),
4112 .SwAccess(prim_subreg_pkg::SwAccessRW),
4113 .RESVAL (1'h0),
4114 .Mubi (1'b0)
4115 ) u_cmd_filter_1_filter_42 (
4116 .clk_i (clk_i),
4117 .rst_ni (rst_ni),
4118
4119 // from register interface
4120 .we (cmd_filter_1_we),
4121 .wd (cmd_filter_1_filter_42_wd),
4122
4123 // from internal hardware
4124 .de (1'b0),
4125 .d ('0),
4126
4127 // to internal hardware
4128 .qe (),
4129 .q (reg2hw.cmd_filter[42].q),
4130 .ds (),
4131
4132 // to register interface (read)
4133 .qs (cmd_filter_1_filter_42_qs)
4134 );
4135
4136 // F[filter_43]: 11:11
4137 prim_subreg #(
4138 .DW (1),
4139 .SwAccess(prim_subreg_pkg::SwAccessRW),
4140 .RESVAL (1'h0),
4141 .Mubi (1'b0)
4142 ) u_cmd_filter_1_filter_43 (
4143 .clk_i (clk_i),
4144 .rst_ni (rst_ni),
4145
4146 // from register interface
4147 .we (cmd_filter_1_we),
4148 .wd (cmd_filter_1_filter_43_wd),
4149
4150 // from internal hardware
4151 .de (1'b0),
4152 .d ('0),
4153
4154 // to internal hardware
4155 .qe (),
4156 .q (reg2hw.cmd_filter[43].q),
4157 .ds (),
4158
4159 // to register interface (read)
4160 .qs (cmd_filter_1_filter_43_qs)
4161 );
4162
4163 // F[filter_44]: 12:12
4164 prim_subreg #(
4165 .DW (1),
4166 .SwAccess(prim_subreg_pkg::SwAccessRW),
4167 .RESVAL (1'h0),
4168 .Mubi (1'b0)
4169 ) u_cmd_filter_1_filter_44 (
4170 .clk_i (clk_i),
4171 .rst_ni (rst_ni),
4172
4173 // from register interface
4174 .we (cmd_filter_1_we),
4175 .wd (cmd_filter_1_filter_44_wd),
4176
4177 // from internal hardware
4178 .de (1'b0),
4179 .d ('0),
4180
4181 // to internal hardware
4182 .qe (),
4183 .q (reg2hw.cmd_filter[44].q),
4184 .ds (),
4185
4186 // to register interface (read)
4187 .qs (cmd_filter_1_filter_44_qs)
4188 );
4189
4190 // F[filter_45]: 13:13
4191 prim_subreg #(
4192 .DW (1),
4193 .SwAccess(prim_subreg_pkg::SwAccessRW),
4194 .RESVAL (1'h0),
4195 .Mubi (1'b0)
4196 ) u_cmd_filter_1_filter_45 (
4197 .clk_i (clk_i),
4198 .rst_ni (rst_ni),
4199
4200 // from register interface
4201 .we (cmd_filter_1_we),
4202 .wd (cmd_filter_1_filter_45_wd),
4203
4204 // from internal hardware
4205 .de (1'b0),
4206 .d ('0),
4207
4208 // to internal hardware
4209 .qe (),
4210 .q (reg2hw.cmd_filter[45].q),
4211 .ds (),
4212
4213 // to register interface (read)
4214 .qs (cmd_filter_1_filter_45_qs)
4215 );
4216
4217 // F[filter_46]: 14:14
4218 prim_subreg #(
4219 .DW (1),
4220 .SwAccess(prim_subreg_pkg::SwAccessRW),
4221 .RESVAL (1'h0),
4222 .Mubi (1'b0)
4223 ) u_cmd_filter_1_filter_46 (
4224 .clk_i (clk_i),
4225 .rst_ni (rst_ni),
4226
4227 // from register interface
4228 .we (cmd_filter_1_we),
4229 .wd (cmd_filter_1_filter_46_wd),
4230
4231 // from internal hardware
4232 .de (1'b0),
4233 .d ('0),
4234
4235 // to internal hardware
4236 .qe (),
4237 .q (reg2hw.cmd_filter[46].q),
4238 .ds (),
4239
4240 // to register interface (read)
4241 .qs (cmd_filter_1_filter_46_qs)
4242 );
4243
4244 // F[filter_47]: 15:15
4245 prim_subreg #(
4246 .DW (1),
4247 .SwAccess(prim_subreg_pkg::SwAccessRW),
4248 .RESVAL (1'h0),
4249 .Mubi (1'b0)
4250 ) u_cmd_filter_1_filter_47 (
4251 .clk_i (clk_i),
4252 .rst_ni (rst_ni),
4253
4254 // from register interface
4255 .we (cmd_filter_1_we),
4256 .wd (cmd_filter_1_filter_47_wd),
4257
4258 // from internal hardware
4259 .de (1'b0),
4260 .d ('0),
4261
4262 // to internal hardware
4263 .qe (),
4264 .q (reg2hw.cmd_filter[47].q),
4265 .ds (),
4266
4267 // to register interface (read)
4268 .qs (cmd_filter_1_filter_47_qs)
4269 );
4270
4271 // F[filter_48]: 16:16
4272 prim_subreg #(
4273 .DW (1),
4274 .SwAccess(prim_subreg_pkg::SwAccessRW),
4275 .RESVAL (1'h0),
4276 .Mubi (1'b0)
4277 ) u_cmd_filter_1_filter_48 (
4278 .clk_i (clk_i),
4279 .rst_ni (rst_ni),
4280
4281 // from register interface
4282 .we (cmd_filter_1_we),
4283 .wd (cmd_filter_1_filter_48_wd),
4284
4285 // from internal hardware
4286 .de (1'b0),
4287 .d ('0),
4288
4289 // to internal hardware
4290 .qe (),
4291 .q (reg2hw.cmd_filter[48].q),
4292 .ds (),
4293
4294 // to register interface (read)
4295 .qs (cmd_filter_1_filter_48_qs)
4296 );
4297
4298 // F[filter_49]: 17:17
4299 prim_subreg #(
4300 .DW (1),
4301 .SwAccess(prim_subreg_pkg::SwAccessRW),
4302 .RESVAL (1'h0),
4303 .Mubi (1'b0)
4304 ) u_cmd_filter_1_filter_49 (
4305 .clk_i (clk_i),
4306 .rst_ni (rst_ni),
4307
4308 // from register interface
4309 .we (cmd_filter_1_we),
4310 .wd (cmd_filter_1_filter_49_wd),
4311
4312 // from internal hardware
4313 .de (1'b0),
4314 .d ('0),
4315
4316 // to internal hardware
4317 .qe (),
4318 .q (reg2hw.cmd_filter[49].q),
4319 .ds (),
4320
4321 // to register interface (read)
4322 .qs (cmd_filter_1_filter_49_qs)
4323 );
4324
4325 // F[filter_50]: 18:18
4326 prim_subreg #(
4327 .DW (1),
4328 .SwAccess(prim_subreg_pkg::SwAccessRW),
4329 .RESVAL (1'h0),
4330 .Mubi (1'b0)
4331 ) u_cmd_filter_1_filter_50 (
4332 .clk_i (clk_i),
4333 .rst_ni (rst_ni),
4334
4335 // from register interface
4336 .we (cmd_filter_1_we),
4337 .wd (cmd_filter_1_filter_50_wd),
4338
4339 // from internal hardware
4340 .de (1'b0),
4341 .d ('0),
4342
4343 // to internal hardware
4344 .qe (),
4345 .q (reg2hw.cmd_filter[50].q),
4346 .ds (),
4347
4348 // to register interface (read)
4349 .qs (cmd_filter_1_filter_50_qs)
4350 );
4351
4352 // F[filter_51]: 19:19
4353 prim_subreg #(
4354 .DW (1),
4355 .SwAccess(prim_subreg_pkg::SwAccessRW),
4356 .RESVAL (1'h0),
4357 .Mubi (1'b0)
4358 ) u_cmd_filter_1_filter_51 (
4359 .clk_i (clk_i),
4360 .rst_ni (rst_ni),
4361
4362 // from register interface
4363 .we (cmd_filter_1_we),
4364 .wd (cmd_filter_1_filter_51_wd),
4365
4366 // from internal hardware
4367 .de (1'b0),
4368 .d ('0),
4369
4370 // to internal hardware
4371 .qe (),
4372 .q (reg2hw.cmd_filter[51].q),
4373 .ds (),
4374
4375 // to register interface (read)
4376 .qs (cmd_filter_1_filter_51_qs)
4377 );
4378
4379 // F[filter_52]: 20:20
4380 prim_subreg #(
4381 .DW (1),
4382 .SwAccess(prim_subreg_pkg::SwAccessRW),
4383 .RESVAL (1'h0),
4384 .Mubi (1'b0)
4385 ) u_cmd_filter_1_filter_52 (
4386 .clk_i (clk_i),
4387 .rst_ni (rst_ni),
4388
4389 // from register interface
4390 .we (cmd_filter_1_we),
4391 .wd (cmd_filter_1_filter_52_wd),
4392
4393 // from internal hardware
4394 .de (1'b0),
4395 .d ('0),
4396
4397 // to internal hardware
4398 .qe (),
4399 .q (reg2hw.cmd_filter[52].q),
4400 .ds (),
4401
4402 // to register interface (read)
4403 .qs (cmd_filter_1_filter_52_qs)
4404 );
4405
4406 // F[filter_53]: 21:21
4407 prim_subreg #(
4408 .DW (1),
4409 .SwAccess(prim_subreg_pkg::SwAccessRW),
4410 .RESVAL (1'h0),
4411 .Mubi (1'b0)
4412 ) u_cmd_filter_1_filter_53 (
4413 .clk_i (clk_i),
4414 .rst_ni (rst_ni),
4415
4416 // from register interface
4417 .we (cmd_filter_1_we),
4418 .wd (cmd_filter_1_filter_53_wd),
4419
4420 // from internal hardware
4421 .de (1'b0),
4422 .d ('0),
4423
4424 // to internal hardware
4425 .qe (),
4426 .q (reg2hw.cmd_filter[53].q),
4427 .ds (),
4428
4429 // to register interface (read)
4430 .qs (cmd_filter_1_filter_53_qs)
4431 );
4432
4433 // F[filter_54]: 22:22
4434 prim_subreg #(
4435 .DW (1),
4436 .SwAccess(prim_subreg_pkg::SwAccessRW),
4437 .RESVAL (1'h0),
4438 .Mubi (1'b0)
4439 ) u_cmd_filter_1_filter_54 (
4440 .clk_i (clk_i),
4441 .rst_ni (rst_ni),
4442
4443 // from register interface
4444 .we (cmd_filter_1_we),
4445 .wd (cmd_filter_1_filter_54_wd),
4446
4447 // from internal hardware
4448 .de (1'b0),
4449 .d ('0),
4450
4451 // to internal hardware
4452 .qe (),
4453 .q (reg2hw.cmd_filter[54].q),
4454 .ds (),
4455
4456 // to register interface (read)
4457 .qs (cmd_filter_1_filter_54_qs)
4458 );
4459
4460 // F[filter_55]: 23:23
4461 prim_subreg #(
4462 .DW (1),
4463 .SwAccess(prim_subreg_pkg::SwAccessRW),
4464 .RESVAL (1'h0),
4465 .Mubi (1'b0)
4466 ) u_cmd_filter_1_filter_55 (
4467 .clk_i (clk_i),
4468 .rst_ni (rst_ni),
4469
4470 // from register interface
4471 .we (cmd_filter_1_we),
4472 .wd (cmd_filter_1_filter_55_wd),
4473
4474 // from internal hardware
4475 .de (1'b0),
4476 .d ('0),
4477
4478 // to internal hardware
4479 .qe (),
4480 .q (reg2hw.cmd_filter[55].q),
4481 .ds (),
4482
4483 // to register interface (read)
4484 .qs (cmd_filter_1_filter_55_qs)
4485 );
4486
4487 // F[filter_56]: 24:24
4488 prim_subreg #(
4489 .DW (1),
4490 .SwAccess(prim_subreg_pkg::SwAccessRW),
4491 .RESVAL (1'h0),
4492 .Mubi (1'b0)
4493 ) u_cmd_filter_1_filter_56 (
4494 .clk_i (clk_i),
4495 .rst_ni (rst_ni),
4496
4497 // from register interface
4498 .we (cmd_filter_1_we),
4499 .wd (cmd_filter_1_filter_56_wd),
4500
4501 // from internal hardware
4502 .de (1'b0),
4503 .d ('0),
4504
4505 // to internal hardware
4506 .qe (),
4507 .q (reg2hw.cmd_filter[56].q),
4508 .ds (),
4509
4510 // to register interface (read)
4511 .qs (cmd_filter_1_filter_56_qs)
4512 );
4513
4514 // F[filter_57]: 25:25
4515 prim_subreg #(
4516 .DW (1),
4517 .SwAccess(prim_subreg_pkg::SwAccessRW),
4518 .RESVAL (1'h0),
4519 .Mubi (1'b0)
4520 ) u_cmd_filter_1_filter_57 (
4521 .clk_i (clk_i),
4522 .rst_ni (rst_ni),
4523
4524 // from register interface
4525 .we (cmd_filter_1_we),
4526 .wd (cmd_filter_1_filter_57_wd),
4527
4528 // from internal hardware
4529 .de (1'b0),
4530 .d ('0),
4531
4532 // to internal hardware
4533 .qe (),
4534 .q (reg2hw.cmd_filter[57].q),
4535 .ds (),
4536
4537 // to register interface (read)
4538 .qs (cmd_filter_1_filter_57_qs)
4539 );
4540
4541 // F[filter_58]: 26:26
4542 prim_subreg #(
4543 .DW (1),
4544 .SwAccess(prim_subreg_pkg::SwAccessRW),
4545 .RESVAL (1'h0),
4546 .Mubi (1'b0)
4547 ) u_cmd_filter_1_filter_58 (
4548 .clk_i (clk_i),
4549 .rst_ni (rst_ni),
4550
4551 // from register interface
4552 .we (cmd_filter_1_we),
4553 .wd (cmd_filter_1_filter_58_wd),
4554
4555 // from internal hardware
4556 .de (1'b0),
4557 .d ('0),
4558
4559 // to internal hardware
4560 .qe (),
4561 .q (reg2hw.cmd_filter[58].q),
4562 .ds (),
4563
4564 // to register interface (read)
4565 .qs (cmd_filter_1_filter_58_qs)
4566 );
4567
4568 // F[filter_59]: 27:27
4569 prim_subreg #(
4570 .DW (1),
4571 .SwAccess(prim_subreg_pkg::SwAccessRW),
4572 .RESVAL (1'h0),
4573 .Mubi (1'b0)
4574 ) u_cmd_filter_1_filter_59 (
4575 .clk_i (clk_i),
4576 .rst_ni (rst_ni),
4577
4578 // from register interface
4579 .we (cmd_filter_1_we),
4580 .wd (cmd_filter_1_filter_59_wd),
4581
4582 // from internal hardware
4583 .de (1'b0),
4584 .d ('0),
4585
4586 // to internal hardware
4587 .qe (),
4588 .q (reg2hw.cmd_filter[59].q),
4589 .ds (),
4590
4591 // to register interface (read)
4592 .qs (cmd_filter_1_filter_59_qs)
4593 );
4594
4595 // F[filter_60]: 28:28
4596 prim_subreg #(
4597 .DW (1),
4598 .SwAccess(prim_subreg_pkg::SwAccessRW),
4599 .RESVAL (1'h0),
4600 .Mubi (1'b0)
4601 ) u_cmd_filter_1_filter_60 (
4602 .clk_i (clk_i),
4603 .rst_ni (rst_ni),
4604
4605 // from register interface
4606 .we (cmd_filter_1_we),
4607 .wd (cmd_filter_1_filter_60_wd),
4608
4609 // from internal hardware
4610 .de (1'b0),
4611 .d ('0),
4612
4613 // to internal hardware
4614 .qe (),
4615 .q (reg2hw.cmd_filter[60].q),
4616 .ds (),
4617
4618 // to register interface (read)
4619 .qs (cmd_filter_1_filter_60_qs)
4620 );
4621
4622 // F[filter_61]: 29:29
4623 prim_subreg #(
4624 .DW (1),
4625 .SwAccess(prim_subreg_pkg::SwAccessRW),
4626 .RESVAL (1'h0),
4627 .Mubi (1'b0)
4628 ) u_cmd_filter_1_filter_61 (
4629 .clk_i (clk_i),
4630 .rst_ni (rst_ni),
4631
4632 // from register interface
4633 .we (cmd_filter_1_we),
4634 .wd (cmd_filter_1_filter_61_wd),
4635
4636 // from internal hardware
4637 .de (1'b0),
4638 .d ('0),
4639
4640 // to internal hardware
4641 .qe (),
4642 .q (reg2hw.cmd_filter[61].q),
4643 .ds (),
4644
4645 // to register interface (read)
4646 .qs (cmd_filter_1_filter_61_qs)
4647 );
4648
4649 // F[filter_62]: 30:30
4650 prim_subreg #(
4651 .DW (1),
4652 .SwAccess(prim_subreg_pkg::SwAccessRW),
4653 .RESVAL (1'h0),
4654 .Mubi (1'b0)
4655 ) u_cmd_filter_1_filter_62 (
4656 .clk_i (clk_i),
4657 .rst_ni (rst_ni),
4658
4659 // from register interface
4660 .we (cmd_filter_1_we),
4661 .wd (cmd_filter_1_filter_62_wd),
4662
4663 // from internal hardware
4664 .de (1'b0),
4665 .d ('0),
4666
4667 // to internal hardware
4668 .qe (),
4669 .q (reg2hw.cmd_filter[62].q),
4670 .ds (),
4671
4672 // to register interface (read)
4673 .qs (cmd_filter_1_filter_62_qs)
4674 );
4675
4676 // F[filter_63]: 31:31
4677 prim_subreg #(
4678 .DW (1),
4679 .SwAccess(prim_subreg_pkg::SwAccessRW),
4680 .RESVAL (1'h0),
4681 .Mubi (1'b0)
4682 ) u_cmd_filter_1_filter_63 (
4683 .clk_i (clk_i),
4684 .rst_ni (rst_ni),
4685
4686 // from register interface
4687 .we (cmd_filter_1_we),
4688 .wd (cmd_filter_1_filter_63_wd),
4689
4690 // from internal hardware
4691 .de (1'b0),
4692 .d ('0),
4693
4694 // to internal hardware
4695 .qe (),
4696 .q (reg2hw.cmd_filter[63].q),
4697 .ds (),
4698
4699 // to register interface (read)
4700 .qs (cmd_filter_1_filter_63_qs)
4701 );
4702
4703
4704 // Subregister 2 of Multireg cmd_filter
4705 // R[cmd_filter_2]: V(False)
4706 // F[filter_64]: 0:0
4707 prim_subreg #(
4708 .DW (1),
4709 .SwAccess(prim_subreg_pkg::SwAccessRW),
4710 .RESVAL (1'h0),
4711 .Mubi (1'b0)
4712 ) u_cmd_filter_2_filter_64 (
4713 .clk_i (clk_i),
4714 .rst_ni (rst_ni),
4715
4716 // from register interface
4717 .we (cmd_filter_2_we),
4718 .wd (cmd_filter_2_filter_64_wd),
4719
4720 // from internal hardware
4721 .de (1'b0),
4722 .d ('0),
4723
4724 // to internal hardware
4725 .qe (),
4726 .q (reg2hw.cmd_filter[64].q),
4727 .ds (),
4728
4729 // to register interface (read)
4730 .qs (cmd_filter_2_filter_64_qs)
4731 );
4732
4733 // F[filter_65]: 1:1
4734 prim_subreg #(
4735 .DW (1),
4736 .SwAccess(prim_subreg_pkg::SwAccessRW),
4737 .RESVAL (1'h0),
4738 .Mubi (1'b0)
4739 ) u_cmd_filter_2_filter_65 (
4740 .clk_i (clk_i),
4741 .rst_ni (rst_ni),
4742
4743 // from register interface
4744 .we (cmd_filter_2_we),
4745 .wd (cmd_filter_2_filter_65_wd),
4746
4747 // from internal hardware
4748 .de (1'b0),
4749 .d ('0),
4750
4751 // to internal hardware
4752 .qe (),
4753 .q (reg2hw.cmd_filter[65].q),
4754 .ds (),
4755
4756 // to register interface (read)
4757 .qs (cmd_filter_2_filter_65_qs)
4758 );
4759
4760 // F[filter_66]: 2:2
4761 prim_subreg #(
4762 .DW (1),
4763 .SwAccess(prim_subreg_pkg::SwAccessRW),
4764 .RESVAL (1'h0),
4765 .Mubi (1'b0)
4766 ) u_cmd_filter_2_filter_66 (
4767 .clk_i (clk_i),
4768 .rst_ni (rst_ni),
4769
4770 // from register interface
4771 .we (cmd_filter_2_we),
4772 .wd (cmd_filter_2_filter_66_wd),
4773
4774 // from internal hardware
4775 .de (1'b0),
4776 .d ('0),
4777
4778 // to internal hardware
4779 .qe (),
4780 .q (reg2hw.cmd_filter[66].q),
4781 .ds (),
4782
4783 // to register interface (read)
4784 .qs (cmd_filter_2_filter_66_qs)
4785 );
4786
4787 // F[filter_67]: 3:3
4788 prim_subreg #(
4789 .DW (1),
4790 .SwAccess(prim_subreg_pkg::SwAccessRW),
4791 .RESVAL (1'h0),
4792 .Mubi (1'b0)
4793 ) u_cmd_filter_2_filter_67 (
4794 .clk_i (clk_i),
4795 .rst_ni (rst_ni),
4796
4797 // from register interface
4798 .we (cmd_filter_2_we),
4799 .wd (cmd_filter_2_filter_67_wd),
4800
4801 // from internal hardware
4802 .de (1'b0),
4803 .d ('0),
4804
4805 // to internal hardware
4806 .qe (),
4807 .q (reg2hw.cmd_filter[67].q),
4808 .ds (),
4809
4810 // to register interface (read)
4811 .qs (cmd_filter_2_filter_67_qs)
4812 );
4813
4814 // F[filter_68]: 4:4
4815 prim_subreg #(
4816 .DW (1),
4817 .SwAccess(prim_subreg_pkg::SwAccessRW),
4818 .RESVAL (1'h0),
4819 .Mubi (1'b0)
4820 ) u_cmd_filter_2_filter_68 (
4821 .clk_i (clk_i),
4822 .rst_ni (rst_ni),
4823
4824 // from register interface
4825 .we (cmd_filter_2_we),
4826 .wd (cmd_filter_2_filter_68_wd),
4827
4828 // from internal hardware
4829 .de (1'b0),
4830 .d ('0),
4831
4832 // to internal hardware
4833 .qe (),
4834 .q (reg2hw.cmd_filter[68].q),
4835 .ds (),
4836
4837 // to register interface (read)
4838 .qs (cmd_filter_2_filter_68_qs)
4839 );
4840
4841 // F[filter_69]: 5:5
4842 prim_subreg #(
4843 .DW (1),
4844 .SwAccess(prim_subreg_pkg::SwAccessRW),
4845 .RESVAL (1'h0),
4846 .Mubi (1'b0)
4847 ) u_cmd_filter_2_filter_69 (
4848 .clk_i (clk_i),
4849 .rst_ni (rst_ni),
4850
4851 // from register interface
4852 .we (cmd_filter_2_we),
4853 .wd (cmd_filter_2_filter_69_wd),
4854
4855 // from internal hardware
4856 .de (1'b0),
4857 .d ('0),
4858
4859 // to internal hardware
4860 .qe (),
4861 .q (reg2hw.cmd_filter[69].q),
4862 .ds (),
4863
4864 // to register interface (read)
4865 .qs (cmd_filter_2_filter_69_qs)
4866 );
4867
4868 // F[filter_70]: 6:6
4869 prim_subreg #(
4870 .DW (1),
4871 .SwAccess(prim_subreg_pkg::SwAccessRW),
4872 .RESVAL (1'h0),
4873 .Mubi (1'b0)
4874 ) u_cmd_filter_2_filter_70 (
4875 .clk_i (clk_i),
4876 .rst_ni (rst_ni),
4877
4878 // from register interface
4879 .we (cmd_filter_2_we),
4880 .wd (cmd_filter_2_filter_70_wd),
4881
4882 // from internal hardware
4883 .de (1'b0),
4884 .d ('0),
4885
4886 // to internal hardware
4887 .qe (),
4888 .q (reg2hw.cmd_filter[70].q),
4889 .ds (),
4890
4891 // to register interface (read)
4892 .qs (cmd_filter_2_filter_70_qs)
4893 );
4894
4895 // F[filter_71]: 7:7
4896 prim_subreg #(
4897 .DW (1),
4898 .SwAccess(prim_subreg_pkg::SwAccessRW),
4899 .RESVAL (1'h0),
4900 .Mubi (1'b0)
4901 ) u_cmd_filter_2_filter_71 (
4902 .clk_i (clk_i),
4903 .rst_ni (rst_ni),
4904
4905 // from register interface
4906 .we (cmd_filter_2_we),
4907 .wd (cmd_filter_2_filter_71_wd),
4908
4909 // from internal hardware
4910 .de (1'b0),
4911 .d ('0),
4912
4913 // to internal hardware
4914 .qe (),
4915 .q (reg2hw.cmd_filter[71].q),
4916 .ds (),
4917
4918 // to register interface (read)
4919 .qs (cmd_filter_2_filter_71_qs)
4920 );
4921
4922 // F[filter_72]: 8:8
4923 prim_subreg #(
4924 .DW (1),
4925 .SwAccess(prim_subreg_pkg::SwAccessRW),
4926 .RESVAL (1'h0),
4927 .Mubi (1'b0)
4928 ) u_cmd_filter_2_filter_72 (
4929 .clk_i (clk_i),
4930 .rst_ni (rst_ni),
4931
4932 // from register interface
4933 .we (cmd_filter_2_we),
4934 .wd (cmd_filter_2_filter_72_wd),
4935
4936 // from internal hardware
4937 .de (1'b0),
4938 .d ('0),
4939
4940 // to internal hardware
4941 .qe (),
4942 .q (reg2hw.cmd_filter[72].q),
4943 .ds (),
4944
4945 // to register interface (read)
4946 .qs (cmd_filter_2_filter_72_qs)
4947 );
4948
4949 // F[filter_73]: 9:9
4950 prim_subreg #(
4951 .DW (1),
4952 .SwAccess(prim_subreg_pkg::SwAccessRW),
4953 .RESVAL (1'h0),
4954 .Mubi (1'b0)
4955 ) u_cmd_filter_2_filter_73 (
4956 .clk_i (clk_i),
4957 .rst_ni (rst_ni),
4958
4959 // from register interface
4960 .we (cmd_filter_2_we),
4961 .wd (cmd_filter_2_filter_73_wd),
4962
4963 // from internal hardware
4964 .de (1'b0),
4965 .d ('0),
4966
4967 // to internal hardware
4968 .qe (),
4969 .q (reg2hw.cmd_filter[73].q),
4970 .ds (),
4971
4972 // to register interface (read)
4973 .qs (cmd_filter_2_filter_73_qs)
4974 );
4975
4976 // F[filter_74]: 10:10
4977 prim_subreg #(
4978 .DW (1),
4979 .SwAccess(prim_subreg_pkg::SwAccessRW),
4980 .RESVAL (1'h0),
4981 .Mubi (1'b0)
4982 ) u_cmd_filter_2_filter_74 (
4983 .clk_i (clk_i),
4984 .rst_ni (rst_ni),
4985
4986 // from register interface
4987 .we (cmd_filter_2_we),
4988 .wd (cmd_filter_2_filter_74_wd),
4989
4990 // from internal hardware
4991 .de (1'b0),
4992 .d ('0),
4993
4994 // to internal hardware
4995 .qe (),
4996 .q (reg2hw.cmd_filter[74].q),
4997 .ds (),
4998
4999 // to register interface (read)
5000 .qs (cmd_filter_2_filter_74_qs)
5001 );
5002
5003 // F[filter_75]: 11:11
5004 prim_subreg #(
5005 .DW (1),
5006 .SwAccess(prim_subreg_pkg::SwAccessRW),
5007 .RESVAL (1'h0),
5008 .Mubi (1'b0)
5009 ) u_cmd_filter_2_filter_75 (
5010 .clk_i (clk_i),
5011 .rst_ni (rst_ni),
5012
5013 // from register interface
5014 .we (cmd_filter_2_we),
5015 .wd (cmd_filter_2_filter_75_wd),
5016
5017 // from internal hardware
5018 .de (1'b0),
5019 .d ('0),
5020
5021 // to internal hardware
5022 .qe (),
5023 .q (reg2hw.cmd_filter[75].q),
5024 .ds (),
5025
5026 // to register interface (read)
5027 .qs (cmd_filter_2_filter_75_qs)
5028 );
5029
5030 // F[filter_76]: 12:12
5031 prim_subreg #(
5032 .DW (1),
5033 .SwAccess(prim_subreg_pkg::SwAccessRW),
5034 .RESVAL (1'h0),
5035 .Mubi (1'b0)
5036 ) u_cmd_filter_2_filter_76 (
5037 .clk_i (clk_i),
5038 .rst_ni (rst_ni),
5039
5040 // from register interface
5041 .we (cmd_filter_2_we),
5042 .wd (cmd_filter_2_filter_76_wd),
5043
5044 // from internal hardware
5045 .de (1'b0),
5046 .d ('0),
5047
5048 // to internal hardware
5049 .qe (),
5050 .q (reg2hw.cmd_filter[76].q),
5051 .ds (),
5052
5053 // to register interface (read)
5054 .qs (cmd_filter_2_filter_76_qs)
5055 );
5056
5057 // F[filter_77]: 13:13
5058 prim_subreg #(
5059 .DW (1),
5060 .SwAccess(prim_subreg_pkg::SwAccessRW),
5061 .RESVAL (1'h0),
5062 .Mubi (1'b0)
5063 ) u_cmd_filter_2_filter_77 (
5064 .clk_i (clk_i),
5065 .rst_ni (rst_ni),
5066
5067 // from register interface
5068 .we (cmd_filter_2_we),
5069 .wd (cmd_filter_2_filter_77_wd),
5070
5071 // from internal hardware
5072 .de (1'b0),
5073 .d ('0),
5074
5075 // to internal hardware
5076 .qe (),
5077 .q (reg2hw.cmd_filter[77].q),
5078 .ds (),
5079
5080 // to register interface (read)
5081 .qs (cmd_filter_2_filter_77_qs)
5082 );
5083
5084 // F[filter_78]: 14:14
5085 prim_subreg #(
5086 .DW (1),
5087 .SwAccess(prim_subreg_pkg::SwAccessRW),
5088 .RESVAL (1'h0),
5089 .Mubi (1'b0)
5090 ) u_cmd_filter_2_filter_78 (
5091 .clk_i (clk_i),
5092 .rst_ni (rst_ni),
5093
5094 // from register interface
5095 .we (cmd_filter_2_we),
5096 .wd (cmd_filter_2_filter_78_wd),
5097
5098 // from internal hardware
5099 .de (1'b0),
5100 .d ('0),
5101
5102 // to internal hardware
5103 .qe (),
5104 .q (reg2hw.cmd_filter[78].q),
5105 .ds (),
5106
5107 // to register interface (read)
5108 .qs (cmd_filter_2_filter_78_qs)
5109 );
5110
5111 // F[filter_79]: 15:15
5112 prim_subreg #(
5113 .DW (1),
5114 .SwAccess(prim_subreg_pkg::SwAccessRW),
5115 .RESVAL (1'h0),
5116 .Mubi (1'b0)
5117 ) u_cmd_filter_2_filter_79 (
5118 .clk_i (clk_i),
5119 .rst_ni (rst_ni),
5120
5121 // from register interface
5122 .we (cmd_filter_2_we),
5123 .wd (cmd_filter_2_filter_79_wd),
5124
5125 // from internal hardware
5126 .de (1'b0),
5127 .d ('0),
5128
5129 // to internal hardware
5130 .qe (),
5131 .q (reg2hw.cmd_filter[79].q),
5132 .ds (),
5133
5134 // to register interface (read)
5135 .qs (cmd_filter_2_filter_79_qs)
5136 );
5137
5138 // F[filter_80]: 16:16
5139 prim_subreg #(
5140 .DW (1),
5141 .SwAccess(prim_subreg_pkg::SwAccessRW),
5142 .RESVAL (1'h0),
5143 .Mubi (1'b0)
5144 ) u_cmd_filter_2_filter_80 (
5145 .clk_i (clk_i),
5146 .rst_ni (rst_ni),
5147
5148 // from register interface
5149 .we (cmd_filter_2_we),
5150 .wd (cmd_filter_2_filter_80_wd),
5151
5152 // from internal hardware
5153 .de (1'b0),
5154 .d ('0),
5155
5156 // to internal hardware
5157 .qe (),
5158 .q (reg2hw.cmd_filter[80].q),
5159 .ds (),
5160
5161 // to register interface (read)
5162 .qs (cmd_filter_2_filter_80_qs)
5163 );
5164
5165 // F[filter_81]: 17:17
5166 prim_subreg #(
5167 .DW (1),
5168 .SwAccess(prim_subreg_pkg::SwAccessRW),
5169 .RESVAL (1'h0),
5170 .Mubi (1'b0)
5171 ) u_cmd_filter_2_filter_81 (
5172 .clk_i (clk_i),
5173 .rst_ni (rst_ni),
5174
5175 // from register interface
5176 .we (cmd_filter_2_we),
5177 .wd (cmd_filter_2_filter_81_wd),
5178
5179 // from internal hardware
5180 .de (1'b0),
5181 .d ('0),
5182
5183 // to internal hardware
5184 .qe (),
5185 .q (reg2hw.cmd_filter[81].q),
5186 .ds (),
5187
5188 // to register interface (read)
5189 .qs (cmd_filter_2_filter_81_qs)
5190 );
5191
5192 // F[filter_82]: 18:18
5193 prim_subreg #(
5194 .DW (1),
5195 .SwAccess(prim_subreg_pkg::SwAccessRW),
5196 .RESVAL (1'h0),
5197 .Mubi (1'b0)
5198 ) u_cmd_filter_2_filter_82 (
5199 .clk_i (clk_i),
5200 .rst_ni (rst_ni),
5201
5202 // from register interface
5203 .we (cmd_filter_2_we),
5204 .wd (cmd_filter_2_filter_82_wd),
5205
5206 // from internal hardware
5207 .de (1'b0),
5208 .d ('0),
5209
5210 // to internal hardware
5211 .qe (),
5212 .q (reg2hw.cmd_filter[82].q),
5213 .ds (),
5214
5215 // to register interface (read)
5216 .qs (cmd_filter_2_filter_82_qs)
5217 );
5218
5219 // F[filter_83]: 19:19
5220 prim_subreg #(
5221 .DW (1),
5222 .SwAccess(prim_subreg_pkg::SwAccessRW),
5223 .RESVAL (1'h0),
5224 .Mubi (1'b0)
5225 ) u_cmd_filter_2_filter_83 (
5226 .clk_i (clk_i),
5227 .rst_ni (rst_ni),
5228
5229 // from register interface
5230 .we (cmd_filter_2_we),
5231 .wd (cmd_filter_2_filter_83_wd),
5232
5233 // from internal hardware
5234 .de (1'b0),
5235 .d ('0),
5236
5237 // to internal hardware
5238 .qe (),
5239 .q (reg2hw.cmd_filter[83].q),
5240 .ds (),
5241
5242 // to register interface (read)
5243 .qs (cmd_filter_2_filter_83_qs)
5244 );
5245
5246 // F[filter_84]: 20:20
5247 prim_subreg #(
5248 .DW (1),
5249 .SwAccess(prim_subreg_pkg::SwAccessRW),
5250 .RESVAL (1'h0),
5251 .Mubi (1'b0)
5252 ) u_cmd_filter_2_filter_84 (
5253 .clk_i (clk_i),
5254 .rst_ni (rst_ni),
5255
5256 // from register interface
5257 .we (cmd_filter_2_we),
5258 .wd (cmd_filter_2_filter_84_wd),
5259
5260 // from internal hardware
5261 .de (1'b0),
5262 .d ('0),
5263
5264 // to internal hardware
5265 .qe (),
5266 .q (reg2hw.cmd_filter[84].q),
5267 .ds (),
5268
5269 // to register interface (read)
5270 .qs (cmd_filter_2_filter_84_qs)
5271 );
5272
5273 // F[filter_85]: 21:21
5274 prim_subreg #(
5275 .DW (1),
5276 .SwAccess(prim_subreg_pkg::SwAccessRW),
5277 .RESVAL (1'h0),
5278 .Mubi (1'b0)
5279 ) u_cmd_filter_2_filter_85 (
5280 .clk_i (clk_i),
5281 .rst_ni (rst_ni),
5282
5283 // from register interface
5284 .we (cmd_filter_2_we),
5285 .wd (cmd_filter_2_filter_85_wd),
5286
5287 // from internal hardware
5288 .de (1'b0),
5289 .d ('0),
5290
5291 // to internal hardware
5292 .qe (),
5293 .q (reg2hw.cmd_filter[85].q),
5294 .ds (),
5295
5296 // to register interface (read)
5297 .qs (cmd_filter_2_filter_85_qs)
5298 );
5299
5300 // F[filter_86]: 22:22
5301 prim_subreg #(
5302 .DW (1),
5303 .SwAccess(prim_subreg_pkg::SwAccessRW),
5304 .RESVAL (1'h0),
5305 .Mubi (1'b0)
5306 ) u_cmd_filter_2_filter_86 (
5307 .clk_i (clk_i),
5308 .rst_ni (rst_ni),
5309
5310 // from register interface
5311 .we (cmd_filter_2_we),
5312 .wd (cmd_filter_2_filter_86_wd),
5313
5314 // from internal hardware
5315 .de (1'b0),
5316 .d ('0),
5317
5318 // to internal hardware
5319 .qe (),
5320 .q (reg2hw.cmd_filter[86].q),
5321 .ds (),
5322
5323 // to register interface (read)
5324 .qs (cmd_filter_2_filter_86_qs)
5325 );
5326
5327 // F[filter_87]: 23:23
5328 prim_subreg #(
5329 .DW (1),
5330 .SwAccess(prim_subreg_pkg::SwAccessRW),
5331 .RESVAL (1'h0),
5332 .Mubi (1'b0)
5333 ) u_cmd_filter_2_filter_87 (
5334 .clk_i (clk_i),
5335 .rst_ni (rst_ni),
5336
5337 // from register interface
5338 .we (cmd_filter_2_we),
5339 .wd (cmd_filter_2_filter_87_wd),
5340
5341 // from internal hardware
5342 .de (1'b0),
5343 .d ('0),
5344
5345 // to internal hardware
5346 .qe (),
5347 .q (reg2hw.cmd_filter[87].q),
5348 .ds (),
5349
5350 // to register interface (read)
5351 .qs (cmd_filter_2_filter_87_qs)
5352 );
5353
5354 // F[filter_88]: 24:24
5355 prim_subreg #(
5356 .DW (1),
5357 .SwAccess(prim_subreg_pkg::SwAccessRW),
5358 .RESVAL (1'h0),
5359 .Mubi (1'b0)
5360 ) u_cmd_filter_2_filter_88 (
5361 .clk_i (clk_i),
5362 .rst_ni (rst_ni),
5363
5364 // from register interface
5365 .we (cmd_filter_2_we),
5366 .wd (cmd_filter_2_filter_88_wd),
5367
5368 // from internal hardware
5369 .de (1'b0),
5370 .d ('0),
5371
5372 // to internal hardware
5373 .qe (),
5374 .q (reg2hw.cmd_filter[88].q),
5375 .ds (),
5376
5377 // to register interface (read)
5378 .qs (cmd_filter_2_filter_88_qs)
5379 );
5380
5381 // F[filter_89]: 25:25
5382 prim_subreg #(
5383 .DW (1),
5384 .SwAccess(prim_subreg_pkg::SwAccessRW),
5385 .RESVAL (1'h0),
5386 .Mubi (1'b0)
5387 ) u_cmd_filter_2_filter_89 (
5388 .clk_i (clk_i),
5389 .rst_ni (rst_ni),
5390
5391 // from register interface
5392 .we (cmd_filter_2_we),
5393 .wd (cmd_filter_2_filter_89_wd),
5394
5395 // from internal hardware
5396 .de (1'b0),
5397 .d ('0),
5398
5399 // to internal hardware
5400 .qe (),
5401 .q (reg2hw.cmd_filter[89].q),
5402 .ds (),
5403
5404 // to register interface (read)
5405 .qs (cmd_filter_2_filter_89_qs)
5406 );
5407
5408 // F[filter_90]: 26:26
5409 prim_subreg #(
5410 .DW (1),
5411 .SwAccess(prim_subreg_pkg::SwAccessRW),
5412 .RESVAL (1'h0),
5413 .Mubi (1'b0)
5414 ) u_cmd_filter_2_filter_90 (
5415 .clk_i (clk_i),
5416 .rst_ni (rst_ni),
5417
5418 // from register interface
5419 .we (cmd_filter_2_we),
5420 .wd (cmd_filter_2_filter_90_wd),
5421
5422 // from internal hardware
5423 .de (1'b0),
5424 .d ('0),
5425
5426 // to internal hardware
5427 .qe (),
5428 .q (reg2hw.cmd_filter[90].q),
5429 .ds (),
5430
5431 // to register interface (read)
5432 .qs (cmd_filter_2_filter_90_qs)
5433 );
5434
5435 // F[filter_91]: 27:27
5436 prim_subreg #(
5437 .DW (1),
5438 .SwAccess(prim_subreg_pkg::SwAccessRW),
5439 .RESVAL (1'h0),
5440 .Mubi (1'b0)
5441 ) u_cmd_filter_2_filter_91 (
5442 .clk_i (clk_i),
5443 .rst_ni (rst_ni),
5444
5445 // from register interface
5446 .we (cmd_filter_2_we),
5447 .wd (cmd_filter_2_filter_91_wd),
5448
5449 // from internal hardware
5450 .de (1'b0),
5451 .d ('0),
5452
5453 // to internal hardware
5454 .qe (),
5455 .q (reg2hw.cmd_filter[91].q),
5456 .ds (),
5457
5458 // to register interface (read)
5459 .qs (cmd_filter_2_filter_91_qs)
5460 );
5461
5462 // F[filter_92]: 28:28
5463 prim_subreg #(
5464 .DW (1),
5465 .SwAccess(prim_subreg_pkg::SwAccessRW),
5466 .RESVAL (1'h0),
5467 .Mubi (1'b0)
5468 ) u_cmd_filter_2_filter_92 (
5469 .clk_i (clk_i),
5470 .rst_ni (rst_ni),
5471
5472 // from register interface
5473 .we (cmd_filter_2_we),
5474 .wd (cmd_filter_2_filter_92_wd),
5475
5476 // from internal hardware
5477 .de (1'b0),
5478 .d ('0),
5479
5480 // to internal hardware
5481 .qe (),
5482 .q (reg2hw.cmd_filter[92].q),
5483 .ds (),
5484
5485 // to register interface (read)
5486 .qs (cmd_filter_2_filter_92_qs)
5487 );
5488
5489 // F[filter_93]: 29:29
5490 prim_subreg #(
5491 .DW (1),
5492 .SwAccess(prim_subreg_pkg::SwAccessRW),
5493 .RESVAL (1'h0),
5494 .Mubi (1'b0)
5495 ) u_cmd_filter_2_filter_93 (
5496 .clk_i (clk_i),
5497 .rst_ni (rst_ni),
5498
5499 // from register interface
5500 .we (cmd_filter_2_we),
5501 .wd (cmd_filter_2_filter_93_wd),
5502
5503 // from internal hardware
5504 .de (1'b0),
5505 .d ('0),
5506
5507 // to internal hardware
5508 .qe (),
5509 .q (reg2hw.cmd_filter[93].q),
5510 .ds (),
5511
5512 // to register interface (read)
5513 .qs (cmd_filter_2_filter_93_qs)
5514 );
5515
5516 // F[filter_94]: 30:30
5517 prim_subreg #(
5518 .DW (1),
5519 .SwAccess(prim_subreg_pkg::SwAccessRW),
5520 .RESVAL (1'h0),
5521 .Mubi (1'b0)
5522 ) u_cmd_filter_2_filter_94 (
5523 .clk_i (clk_i),
5524 .rst_ni (rst_ni),
5525
5526 // from register interface
5527 .we (cmd_filter_2_we),
5528 .wd (cmd_filter_2_filter_94_wd),
5529
5530 // from internal hardware
5531 .de (1'b0),
5532 .d ('0),
5533
5534 // to internal hardware
5535 .qe (),
5536 .q (reg2hw.cmd_filter[94].q),
5537 .ds (),
5538
5539 // to register interface (read)
5540 .qs (cmd_filter_2_filter_94_qs)
5541 );
5542
5543 // F[filter_95]: 31:31
5544 prim_subreg #(
5545 .DW (1),
5546 .SwAccess(prim_subreg_pkg::SwAccessRW),
5547 .RESVAL (1'h0),
5548 .Mubi (1'b0)
5549 ) u_cmd_filter_2_filter_95 (
5550 .clk_i (clk_i),
5551 .rst_ni (rst_ni),
5552
5553 // from register interface
5554 .we (cmd_filter_2_we),
5555 .wd (cmd_filter_2_filter_95_wd),
5556
5557 // from internal hardware
5558 .de (1'b0),
5559 .d ('0),
5560
5561 // to internal hardware
5562 .qe (),
5563 .q (reg2hw.cmd_filter[95].q),
5564 .ds (),
5565
5566 // to register interface (read)
5567 .qs (cmd_filter_2_filter_95_qs)
5568 );
5569
5570
5571 // Subregister 3 of Multireg cmd_filter
5572 // R[cmd_filter_3]: V(False)
5573 // F[filter_96]: 0:0
5574 prim_subreg #(
5575 .DW (1),
5576 .SwAccess(prim_subreg_pkg::SwAccessRW),
5577 .RESVAL (1'h0),
5578 .Mubi (1'b0)
5579 ) u_cmd_filter_3_filter_96 (
5580 .clk_i (clk_i),
5581 .rst_ni (rst_ni),
5582
5583 // from register interface
5584 .we (cmd_filter_3_we),
5585 .wd (cmd_filter_3_filter_96_wd),
5586
5587 // from internal hardware
5588 .de (1'b0),
5589 .d ('0),
5590
5591 // to internal hardware
5592 .qe (),
5593 .q (reg2hw.cmd_filter[96].q),
5594 .ds (),
5595
5596 // to register interface (read)
5597 .qs (cmd_filter_3_filter_96_qs)
5598 );
5599
5600 // F[filter_97]: 1:1
5601 prim_subreg #(
5602 .DW (1),
5603 .SwAccess(prim_subreg_pkg::SwAccessRW),
5604 .RESVAL (1'h0),
5605 .Mubi (1'b0)
5606 ) u_cmd_filter_3_filter_97 (
5607 .clk_i (clk_i),
5608 .rst_ni (rst_ni),
5609
5610 // from register interface
5611 .we (cmd_filter_3_we),
5612 .wd (cmd_filter_3_filter_97_wd),
5613
5614 // from internal hardware
5615 .de (1'b0),
5616 .d ('0),
5617
5618 // to internal hardware
5619 .qe (),
5620 .q (reg2hw.cmd_filter[97].q),
5621 .ds (),
5622
5623 // to register interface (read)
5624 .qs (cmd_filter_3_filter_97_qs)
5625 );
5626
5627 // F[filter_98]: 2:2
5628 prim_subreg #(
5629 .DW (1),
5630 .SwAccess(prim_subreg_pkg::SwAccessRW),
5631 .RESVAL (1'h0),
5632 .Mubi (1'b0)
5633 ) u_cmd_filter_3_filter_98 (
5634 .clk_i (clk_i),
5635 .rst_ni (rst_ni),
5636
5637 // from register interface
5638 .we (cmd_filter_3_we),
5639 .wd (cmd_filter_3_filter_98_wd),
5640
5641 // from internal hardware
5642 .de (1'b0),
5643 .d ('0),
5644
5645 // to internal hardware
5646 .qe (),
5647 .q (reg2hw.cmd_filter[98].q),
5648 .ds (),
5649
5650 // to register interface (read)
5651 .qs (cmd_filter_3_filter_98_qs)
5652 );
5653
5654 // F[filter_99]: 3:3
5655 prim_subreg #(
5656 .DW (1),
5657 .SwAccess(prim_subreg_pkg::SwAccessRW),
5658 .RESVAL (1'h0),
5659 .Mubi (1'b0)
5660 ) u_cmd_filter_3_filter_99 (
5661 .clk_i (clk_i),
5662 .rst_ni (rst_ni),
5663
5664 // from register interface
5665 .we (cmd_filter_3_we),
5666 .wd (cmd_filter_3_filter_99_wd),
5667
5668 // from internal hardware
5669 .de (1'b0),
5670 .d ('0),
5671
5672 // to internal hardware
5673 .qe (),
5674 .q (reg2hw.cmd_filter[99].q),
5675 .ds (),
5676
5677 // to register interface (read)
5678 .qs (cmd_filter_3_filter_99_qs)
5679 );
5680
5681 // F[filter_100]: 4:4
5682 prim_subreg #(
5683 .DW (1),
5684 .SwAccess(prim_subreg_pkg::SwAccessRW),
5685 .RESVAL (1'h0),
5686 .Mubi (1'b0)
5687 ) u_cmd_filter_3_filter_100 (
5688 .clk_i (clk_i),
5689 .rst_ni (rst_ni),
5690
5691 // from register interface
5692 .we (cmd_filter_3_we),
5693 .wd (cmd_filter_3_filter_100_wd),
5694
5695 // from internal hardware
5696 .de (1'b0),
5697 .d ('0),
5698
5699 // to internal hardware
5700 .qe (),
5701 .q (reg2hw.cmd_filter[100].q),
5702 .ds (),
5703
5704 // to register interface (read)
5705 .qs (cmd_filter_3_filter_100_qs)
5706 );
5707
5708 // F[filter_101]: 5:5
5709 prim_subreg #(
5710 .DW (1),
5711 .SwAccess(prim_subreg_pkg::SwAccessRW),
5712 .RESVAL (1'h0),
5713 .Mubi (1'b0)
5714 ) u_cmd_filter_3_filter_101 (
5715 .clk_i (clk_i),
5716 .rst_ni (rst_ni),
5717
5718 // from register interface
5719 .we (cmd_filter_3_we),
5720 .wd (cmd_filter_3_filter_101_wd),
5721
5722 // from internal hardware
5723 .de (1'b0),
5724 .d ('0),
5725
5726 // to internal hardware
5727 .qe (),
5728 .q (reg2hw.cmd_filter[101].q),
5729 .ds (),
5730
5731 // to register interface (read)
5732 .qs (cmd_filter_3_filter_101_qs)
5733 );
5734
5735 // F[filter_102]: 6:6
5736 prim_subreg #(
5737 .DW (1),
5738 .SwAccess(prim_subreg_pkg::SwAccessRW),
5739 .RESVAL (1'h0),
5740 .Mubi (1'b0)
5741 ) u_cmd_filter_3_filter_102 (
5742 .clk_i (clk_i),
5743 .rst_ni (rst_ni),
5744
5745 // from register interface
5746 .we (cmd_filter_3_we),
5747 .wd (cmd_filter_3_filter_102_wd),
5748
5749 // from internal hardware
5750 .de (1'b0),
5751 .d ('0),
5752
5753 // to internal hardware
5754 .qe (),
5755 .q (reg2hw.cmd_filter[102].q),
5756 .ds (),
5757
5758 // to register interface (read)
5759 .qs (cmd_filter_3_filter_102_qs)
5760 );
5761
5762 // F[filter_103]: 7:7
5763 prim_subreg #(
5764 .DW (1),
5765 .SwAccess(prim_subreg_pkg::SwAccessRW),
5766 .RESVAL (1'h0),
5767 .Mubi (1'b0)
5768 ) u_cmd_filter_3_filter_103 (
5769 .clk_i (clk_i),
5770 .rst_ni (rst_ni),
5771
5772 // from register interface
5773 .we (cmd_filter_3_we),
5774 .wd (cmd_filter_3_filter_103_wd),
5775
5776 // from internal hardware
5777 .de (1'b0),
5778 .d ('0),
5779
5780 // to internal hardware
5781 .qe (),
5782 .q (reg2hw.cmd_filter[103].q),
5783 .ds (),
5784
5785 // to register interface (read)
5786 .qs (cmd_filter_3_filter_103_qs)
5787 );
5788
5789 // F[filter_104]: 8:8
5790 prim_subreg #(
5791 .DW (1),
5792 .SwAccess(prim_subreg_pkg::SwAccessRW),
5793 .RESVAL (1'h0),
5794 .Mubi (1'b0)
5795 ) u_cmd_filter_3_filter_104 (
5796 .clk_i (clk_i),
5797 .rst_ni (rst_ni),
5798
5799 // from register interface
5800 .we (cmd_filter_3_we),
5801 .wd (cmd_filter_3_filter_104_wd),
5802
5803 // from internal hardware
5804 .de (1'b0),
5805 .d ('0),
5806
5807 // to internal hardware
5808 .qe (),
5809 .q (reg2hw.cmd_filter[104].q),
5810 .ds (),
5811
5812 // to register interface (read)
5813 .qs (cmd_filter_3_filter_104_qs)
5814 );
5815
5816 // F[filter_105]: 9:9
5817 prim_subreg #(
5818 .DW (1),
5819 .SwAccess(prim_subreg_pkg::SwAccessRW),
5820 .RESVAL (1'h0),
5821 .Mubi (1'b0)
5822 ) u_cmd_filter_3_filter_105 (
5823 .clk_i (clk_i),
5824 .rst_ni (rst_ni),
5825
5826 // from register interface
5827 .we (cmd_filter_3_we),
5828 .wd (cmd_filter_3_filter_105_wd),
5829
5830 // from internal hardware
5831 .de (1'b0),
5832 .d ('0),
5833
5834 // to internal hardware
5835 .qe (),
5836 .q (reg2hw.cmd_filter[105].q),
5837 .ds (),
5838
5839 // to register interface (read)
5840 .qs (cmd_filter_3_filter_105_qs)
5841 );
5842
5843 // F[filter_106]: 10:10
5844 prim_subreg #(
5845 .DW (1),
5846 .SwAccess(prim_subreg_pkg::SwAccessRW),
5847 .RESVAL (1'h0),
5848 .Mubi (1'b0)
5849 ) u_cmd_filter_3_filter_106 (
5850 .clk_i (clk_i),
5851 .rst_ni (rst_ni),
5852
5853 // from register interface
5854 .we (cmd_filter_3_we),
5855 .wd (cmd_filter_3_filter_106_wd),
5856
5857 // from internal hardware
5858 .de (1'b0),
5859 .d ('0),
5860
5861 // to internal hardware
5862 .qe (),
5863 .q (reg2hw.cmd_filter[106].q),
5864 .ds (),
5865
5866 // to register interface (read)
5867 .qs (cmd_filter_3_filter_106_qs)
5868 );
5869
5870 // F[filter_107]: 11:11
5871 prim_subreg #(
5872 .DW (1),
5873 .SwAccess(prim_subreg_pkg::SwAccessRW),
5874 .RESVAL (1'h0),
5875 .Mubi (1'b0)
5876 ) u_cmd_filter_3_filter_107 (
5877 .clk_i (clk_i),
5878 .rst_ni (rst_ni),
5879
5880 // from register interface
5881 .we (cmd_filter_3_we),
5882 .wd (cmd_filter_3_filter_107_wd),
5883
5884 // from internal hardware
5885 .de (1'b0),
5886 .d ('0),
5887
5888 // to internal hardware
5889 .qe (),
5890 .q (reg2hw.cmd_filter[107].q),
5891 .ds (),
5892
5893 // to register interface (read)
5894 .qs (cmd_filter_3_filter_107_qs)
5895 );
5896
5897 // F[filter_108]: 12:12
5898 prim_subreg #(
5899 .DW (1),
5900 .SwAccess(prim_subreg_pkg::SwAccessRW),
5901 .RESVAL (1'h0),
5902 .Mubi (1'b0)
5903 ) u_cmd_filter_3_filter_108 (
5904 .clk_i (clk_i),
5905 .rst_ni (rst_ni),
5906
5907 // from register interface
5908 .we (cmd_filter_3_we),
5909 .wd (cmd_filter_3_filter_108_wd),
5910
5911 // from internal hardware
5912 .de (1'b0),
5913 .d ('0),
5914
5915 // to internal hardware
5916 .qe (),
5917 .q (reg2hw.cmd_filter[108].q),
5918 .ds (),
5919
5920 // to register interface (read)
5921 .qs (cmd_filter_3_filter_108_qs)
5922 );
5923
5924 // F[filter_109]: 13:13
5925 prim_subreg #(
5926 .DW (1),
5927 .SwAccess(prim_subreg_pkg::SwAccessRW),
5928 .RESVAL (1'h0),
5929 .Mubi (1'b0)
5930 ) u_cmd_filter_3_filter_109 (
5931 .clk_i (clk_i),
5932 .rst_ni (rst_ni),
5933
5934 // from register interface
5935 .we (cmd_filter_3_we),
5936 .wd (cmd_filter_3_filter_109_wd),
5937
5938 // from internal hardware
5939 .de (1'b0),
5940 .d ('0),
5941
5942 // to internal hardware
5943 .qe (),
5944 .q (reg2hw.cmd_filter[109].q),
5945 .ds (),
5946
5947 // to register interface (read)
5948 .qs (cmd_filter_3_filter_109_qs)
5949 );
5950
5951 // F[filter_110]: 14:14
5952 prim_subreg #(
5953 .DW (1),
5954 .SwAccess(prim_subreg_pkg::SwAccessRW),
5955 .RESVAL (1'h0),
5956 .Mubi (1'b0)
5957 ) u_cmd_filter_3_filter_110 (
5958 .clk_i (clk_i),
5959 .rst_ni (rst_ni),
5960
5961 // from register interface
5962 .we (cmd_filter_3_we),
5963 .wd (cmd_filter_3_filter_110_wd),
5964
5965 // from internal hardware
5966 .de (1'b0),
5967 .d ('0),
5968
5969 // to internal hardware
5970 .qe (),
5971 .q (reg2hw.cmd_filter[110].q),
5972 .ds (),
5973
5974 // to register interface (read)
5975 .qs (cmd_filter_3_filter_110_qs)
5976 );
5977
5978 // F[filter_111]: 15:15
5979 prim_subreg #(
5980 .DW (1),
5981 .SwAccess(prim_subreg_pkg::SwAccessRW),
5982 .RESVAL (1'h0),
5983 .Mubi (1'b0)
5984 ) u_cmd_filter_3_filter_111 (
5985 .clk_i (clk_i),
5986 .rst_ni (rst_ni),
5987
5988 // from register interface
5989 .we (cmd_filter_3_we),
5990 .wd (cmd_filter_3_filter_111_wd),
5991
5992 // from internal hardware
5993 .de (1'b0),
5994 .d ('0),
5995
5996 // to internal hardware
5997 .qe (),
5998 .q (reg2hw.cmd_filter[111].q),
5999 .ds (),
6000
6001 // to register interface (read)
6002 .qs (cmd_filter_3_filter_111_qs)
6003 );
6004
6005 // F[filter_112]: 16:16
6006 prim_subreg #(
6007 .DW (1),
6008 .SwAccess(prim_subreg_pkg::SwAccessRW),
6009 .RESVAL (1'h0),
6010 .Mubi (1'b0)
6011 ) u_cmd_filter_3_filter_112 (
6012 .clk_i (clk_i),
6013 .rst_ni (rst_ni),
6014
6015 // from register interface
6016 .we (cmd_filter_3_we),
6017 .wd (cmd_filter_3_filter_112_wd),
6018
6019 // from internal hardware
6020 .de (1'b0),
6021 .d ('0),
6022
6023 // to internal hardware
6024 .qe (),
6025 .q (reg2hw.cmd_filter[112].q),
6026 .ds (),
6027
6028 // to register interface (read)
6029 .qs (cmd_filter_3_filter_112_qs)
6030 );
6031
6032 // F[filter_113]: 17:17
6033 prim_subreg #(
6034 .DW (1),
6035 .SwAccess(prim_subreg_pkg::SwAccessRW),
6036 .RESVAL (1'h0),
6037 .Mubi (1'b0)
6038 ) u_cmd_filter_3_filter_113 (
6039 .clk_i (clk_i),
6040 .rst_ni (rst_ni),
6041
6042 // from register interface
6043 .we (cmd_filter_3_we),
6044 .wd (cmd_filter_3_filter_113_wd),
6045
6046 // from internal hardware
6047 .de (1'b0),
6048 .d ('0),
6049
6050 // to internal hardware
6051 .qe (),
6052 .q (reg2hw.cmd_filter[113].q),
6053 .ds (),
6054
6055 // to register interface (read)
6056 .qs (cmd_filter_3_filter_113_qs)
6057 );
6058
6059 // F[filter_114]: 18:18
6060 prim_subreg #(
6061 .DW (1),
6062 .SwAccess(prim_subreg_pkg::SwAccessRW),
6063 .RESVAL (1'h0),
6064 .Mubi (1'b0)
6065 ) u_cmd_filter_3_filter_114 (
6066 .clk_i (clk_i),
6067 .rst_ni (rst_ni),
6068
6069 // from register interface
6070 .we (cmd_filter_3_we),
6071 .wd (cmd_filter_3_filter_114_wd),
6072
6073 // from internal hardware
6074 .de (1'b0),
6075 .d ('0),
6076
6077 // to internal hardware
6078 .qe (),
6079 .q (reg2hw.cmd_filter[114].q),
6080 .ds (),
6081
6082 // to register interface (read)
6083 .qs (cmd_filter_3_filter_114_qs)
6084 );
6085
6086 // F[filter_115]: 19:19
6087 prim_subreg #(
6088 .DW (1),
6089 .SwAccess(prim_subreg_pkg::SwAccessRW),
6090 .RESVAL (1'h0),
6091 .Mubi (1'b0)
6092 ) u_cmd_filter_3_filter_115 (
6093 .clk_i (clk_i),
6094 .rst_ni (rst_ni),
6095
6096 // from register interface
6097 .we (cmd_filter_3_we),
6098 .wd (cmd_filter_3_filter_115_wd),
6099
6100 // from internal hardware
6101 .de (1'b0),
6102 .d ('0),
6103
6104 // to internal hardware
6105 .qe (),
6106 .q (reg2hw.cmd_filter[115].q),
6107 .ds (),
6108
6109 // to register interface (read)
6110 .qs (cmd_filter_3_filter_115_qs)
6111 );
6112
6113 // F[filter_116]: 20:20
6114 prim_subreg #(
6115 .DW (1),
6116 .SwAccess(prim_subreg_pkg::SwAccessRW),
6117 .RESVAL (1'h0),
6118 .Mubi (1'b0)
6119 ) u_cmd_filter_3_filter_116 (
6120 .clk_i (clk_i),
6121 .rst_ni (rst_ni),
6122
6123 // from register interface
6124 .we (cmd_filter_3_we),
6125 .wd (cmd_filter_3_filter_116_wd),
6126
6127 // from internal hardware
6128 .de (1'b0),
6129 .d ('0),
6130
6131 // to internal hardware
6132 .qe (),
6133 .q (reg2hw.cmd_filter[116].q),
6134 .ds (),
6135
6136 // to register interface (read)
6137 .qs (cmd_filter_3_filter_116_qs)
6138 );
6139
6140 // F[filter_117]: 21:21
6141 prim_subreg #(
6142 .DW (1),
6143 .SwAccess(prim_subreg_pkg::SwAccessRW),
6144 .RESVAL (1'h0),
6145 .Mubi (1'b0)
6146 ) u_cmd_filter_3_filter_117 (
6147 .clk_i (clk_i),
6148 .rst_ni (rst_ni),
6149
6150 // from register interface
6151 .we (cmd_filter_3_we),
6152 .wd (cmd_filter_3_filter_117_wd),
6153
6154 // from internal hardware
6155 .de (1'b0),
6156 .d ('0),
6157
6158 // to internal hardware
6159 .qe (),
6160 .q (reg2hw.cmd_filter[117].q),
6161 .ds (),
6162
6163 // to register interface (read)
6164 .qs (cmd_filter_3_filter_117_qs)
6165 );
6166
6167 // F[filter_118]: 22:22
6168 prim_subreg #(
6169 .DW (1),
6170 .SwAccess(prim_subreg_pkg::SwAccessRW),
6171 .RESVAL (1'h0),
6172 .Mubi (1'b0)
6173 ) u_cmd_filter_3_filter_118 (
6174 .clk_i (clk_i),
6175 .rst_ni (rst_ni),
6176
6177 // from register interface
6178 .we (cmd_filter_3_we),
6179 .wd (cmd_filter_3_filter_118_wd),
6180
6181 // from internal hardware
6182 .de (1'b0),
6183 .d ('0),
6184
6185 // to internal hardware
6186 .qe (),
6187 .q (reg2hw.cmd_filter[118].q),
6188 .ds (),
6189
6190 // to register interface (read)
6191 .qs (cmd_filter_3_filter_118_qs)
6192 );
6193
6194 // F[filter_119]: 23:23
6195 prim_subreg #(
6196 .DW (1),
6197 .SwAccess(prim_subreg_pkg::SwAccessRW),
6198 .RESVAL (1'h0),
6199 .Mubi (1'b0)
6200 ) u_cmd_filter_3_filter_119 (
6201 .clk_i (clk_i),
6202 .rst_ni (rst_ni),
6203
6204 // from register interface
6205 .we (cmd_filter_3_we),
6206 .wd (cmd_filter_3_filter_119_wd),
6207
6208 // from internal hardware
6209 .de (1'b0),
6210 .d ('0),
6211
6212 // to internal hardware
6213 .qe (),
6214 .q (reg2hw.cmd_filter[119].q),
6215 .ds (),
6216
6217 // to register interface (read)
6218 .qs (cmd_filter_3_filter_119_qs)
6219 );
6220
6221 // F[filter_120]: 24:24
6222 prim_subreg #(
6223 .DW (1),
6224 .SwAccess(prim_subreg_pkg::SwAccessRW),
6225 .RESVAL (1'h0),
6226 .Mubi (1'b0)
6227 ) u_cmd_filter_3_filter_120 (
6228 .clk_i (clk_i),
6229 .rst_ni (rst_ni),
6230
6231 // from register interface
6232 .we (cmd_filter_3_we),
6233 .wd (cmd_filter_3_filter_120_wd),
6234
6235 // from internal hardware
6236 .de (1'b0),
6237 .d ('0),
6238
6239 // to internal hardware
6240 .qe (),
6241 .q (reg2hw.cmd_filter[120].q),
6242 .ds (),
6243
6244 // to register interface (read)
6245 .qs (cmd_filter_3_filter_120_qs)
6246 );
6247
6248 // F[filter_121]: 25:25
6249 prim_subreg #(
6250 .DW (1),
6251 .SwAccess(prim_subreg_pkg::SwAccessRW),
6252 .RESVAL (1'h0),
6253 .Mubi (1'b0)
6254 ) u_cmd_filter_3_filter_121 (
6255 .clk_i (clk_i),
6256 .rst_ni (rst_ni),
6257
6258 // from register interface
6259 .we (cmd_filter_3_we),
6260 .wd (cmd_filter_3_filter_121_wd),
6261
6262 // from internal hardware
6263 .de (1'b0),
6264 .d ('0),
6265
6266 // to internal hardware
6267 .qe (),
6268 .q (reg2hw.cmd_filter[121].q),
6269 .ds (),
6270
6271 // to register interface (read)
6272 .qs (cmd_filter_3_filter_121_qs)
6273 );
6274
6275 // F[filter_122]: 26:26
6276 prim_subreg #(
6277 .DW (1),
6278 .SwAccess(prim_subreg_pkg::SwAccessRW),
6279 .RESVAL (1'h0),
6280 .Mubi (1'b0)
6281 ) u_cmd_filter_3_filter_122 (
6282 .clk_i (clk_i),
6283 .rst_ni (rst_ni),
6284
6285 // from register interface
6286 .we (cmd_filter_3_we),
6287 .wd (cmd_filter_3_filter_122_wd),
6288
6289 // from internal hardware
6290 .de (1'b0),
6291 .d ('0),
6292
6293 // to internal hardware
6294 .qe (),
6295 .q (reg2hw.cmd_filter[122].q),
6296 .ds (),
6297
6298 // to register interface (read)
6299 .qs (cmd_filter_3_filter_122_qs)
6300 );
6301
6302 // F[filter_123]: 27:27
6303 prim_subreg #(
6304 .DW (1),
6305 .SwAccess(prim_subreg_pkg::SwAccessRW),
6306 .RESVAL (1'h0),
6307 .Mubi (1'b0)
6308 ) u_cmd_filter_3_filter_123 (
6309 .clk_i (clk_i),
6310 .rst_ni (rst_ni),
6311
6312 // from register interface
6313 .we (cmd_filter_3_we),
6314 .wd (cmd_filter_3_filter_123_wd),
6315
6316 // from internal hardware
6317 .de (1'b0),
6318 .d ('0),
6319
6320 // to internal hardware
6321 .qe (),
6322 .q (reg2hw.cmd_filter[123].q),
6323 .ds (),
6324
6325 // to register interface (read)
6326 .qs (cmd_filter_3_filter_123_qs)
6327 );
6328
6329 // F[filter_124]: 28:28
6330 prim_subreg #(
6331 .DW (1),
6332 .SwAccess(prim_subreg_pkg::SwAccessRW),
6333 .RESVAL (1'h0),
6334 .Mubi (1'b0)
6335 ) u_cmd_filter_3_filter_124 (
6336 .clk_i (clk_i),
6337 .rst_ni (rst_ni),
6338
6339 // from register interface
6340 .we (cmd_filter_3_we),
6341 .wd (cmd_filter_3_filter_124_wd),
6342
6343 // from internal hardware
6344 .de (1'b0),
6345 .d ('0),
6346
6347 // to internal hardware
6348 .qe (),
6349 .q (reg2hw.cmd_filter[124].q),
6350 .ds (),
6351
6352 // to register interface (read)
6353 .qs (cmd_filter_3_filter_124_qs)
6354 );
6355
6356 // F[filter_125]: 29:29
6357 prim_subreg #(
6358 .DW (1),
6359 .SwAccess(prim_subreg_pkg::SwAccessRW),
6360 .RESVAL (1'h0),
6361 .Mubi (1'b0)
6362 ) u_cmd_filter_3_filter_125 (
6363 .clk_i (clk_i),
6364 .rst_ni (rst_ni),
6365
6366 // from register interface
6367 .we (cmd_filter_3_we),
6368 .wd (cmd_filter_3_filter_125_wd),
6369
6370 // from internal hardware
6371 .de (1'b0),
6372 .d ('0),
6373
6374 // to internal hardware
6375 .qe (),
6376 .q (reg2hw.cmd_filter[125].q),
6377 .ds (),
6378
6379 // to register interface (read)
6380 .qs (cmd_filter_3_filter_125_qs)
6381 );
6382
6383 // F[filter_126]: 30:30
6384 prim_subreg #(
6385 .DW (1),
6386 .SwAccess(prim_subreg_pkg::SwAccessRW),
6387 .RESVAL (1'h0),
6388 .Mubi (1'b0)
6389 ) u_cmd_filter_3_filter_126 (
6390 .clk_i (clk_i),
6391 .rst_ni (rst_ni),
6392
6393 // from register interface
6394 .we (cmd_filter_3_we),
6395 .wd (cmd_filter_3_filter_126_wd),
6396
6397 // from internal hardware
6398 .de (1'b0),
6399 .d ('0),
6400
6401 // to internal hardware
6402 .qe (),
6403 .q (reg2hw.cmd_filter[126].q),
6404 .ds (),
6405
6406 // to register interface (read)
6407 .qs (cmd_filter_3_filter_126_qs)
6408 );
6409
6410 // F[filter_127]: 31:31
6411 prim_subreg #(
6412 .DW (1),
6413 .SwAccess(prim_subreg_pkg::SwAccessRW),
6414 .RESVAL (1'h0),
6415 .Mubi (1'b0)
6416 ) u_cmd_filter_3_filter_127 (
6417 .clk_i (clk_i),
6418 .rst_ni (rst_ni),
6419
6420 // from register interface
6421 .we (cmd_filter_3_we),
6422 .wd (cmd_filter_3_filter_127_wd),
6423
6424 // from internal hardware
6425 .de (1'b0),
6426 .d ('0),
6427
6428 // to internal hardware
6429 .qe (),
6430 .q (reg2hw.cmd_filter[127].q),
6431 .ds (),
6432
6433 // to register interface (read)
6434 .qs (cmd_filter_3_filter_127_qs)
6435 );
6436
6437
6438 // Subregister 4 of Multireg cmd_filter
6439 // R[cmd_filter_4]: V(False)
6440 // F[filter_128]: 0:0
6441 prim_subreg #(
6442 .DW (1),
6443 .SwAccess(prim_subreg_pkg::SwAccessRW),
6444 .RESVAL (1'h0),
6445 .Mubi (1'b0)
6446 ) u_cmd_filter_4_filter_128 (
6447 .clk_i (clk_i),
6448 .rst_ni (rst_ni),
6449
6450 // from register interface
6451 .we (cmd_filter_4_we),
6452 .wd (cmd_filter_4_filter_128_wd),
6453
6454 // from internal hardware
6455 .de (1'b0),
6456 .d ('0),
6457
6458 // to internal hardware
6459 .qe (),
6460 .q (reg2hw.cmd_filter[128].q),
6461 .ds (),
6462
6463 // to register interface (read)
6464 .qs (cmd_filter_4_filter_128_qs)
6465 );
6466
6467 // F[filter_129]: 1:1
6468 prim_subreg #(
6469 .DW (1),
6470 .SwAccess(prim_subreg_pkg::SwAccessRW),
6471 .RESVAL (1'h0),
6472 .Mubi (1'b0)
6473 ) u_cmd_filter_4_filter_129 (
6474 .clk_i (clk_i),
6475 .rst_ni (rst_ni),
6476
6477 // from register interface
6478 .we (cmd_filter_4_we),
6479 .wd (cmd_filter_4_filter_129_wd),
6480
6481 // from internal hardware
6482 .de (1'b0),
6483 .d ('0),
6484
6485 // to internal hardware
6486 .qe (),
6487 .q (reg2hw.cmd_filter[129].q),
6488 .ds (),
6489
6490 // to register interface (read)
6491 .qs (cmd_filter_4_filter_129_qs)
6492 );
6493
6494 // F[filter_130]: 2:2
6495 prim_subreg #(
6496 .DW (1),
6497 .SwAccess(prim_subreg_pkg::SwAccessRW),
6498 .RESVAL (1'h0),
6499 .Mubi (1'b0)
6500 ) u_cmd_filter_4_filter_130 (
6501 .clk_i (clk_i),
6502 .rst_ni (rst_ni),
6503
6504 // from register interface
6505 .we (cmd_filter_4_we),
6506 .wd (cmd_filter_4_filter_130_wd),
6507
6508 // from internal hardware
6509 .de (1'b0),
6510 .d ('0),
6511
6512 // to internal hardware
6513 .qe (),
6514 .q (reg2hw.cmd_filter[130].q),
6515 .ds (),
6516
6517 // to register interface (read)
6518 .qs (cmd_filter_4_filter_130_qs)
6519 );
6520
6521 // F[filter_131]: 3:3
6522 prim_subreg #(
6523 .DW (1),
6524 .SwAccess(prim_subreg_pkg::SwAccessRW),
6525 .RESVAL (1'h0),
6526 .Mubi (1'b0)
6527 ) u_cmd_filter_4_filter_131 (
6528 .clk_i (clk_i),
6529 .rst_ni (rst_ni),
6530
6531 // from register interface
6532 .we (cmd_filter_4_we),
6533 .wd (cmd_filter_4_filter_131_wd),
6534
6535 // from internal hardware
6536 .de (1'b0),
6537 .d ('0),
6538
6539 // to internal hardware
6540 .qe (),
6541 .q (reg2hw.cmd_filter[131].q),
6542 .ds (),
6543
6544 // to register interface (read)
6545 .qs (cmd_filter_4_filter_131_qs)
6546 );
6547
6548 // F[filter_132]: 4:4
6549 prim_subreg #(
6550 .DW (1),
6551 .SwAccess(prim_subreg_pkg::SwAccessRW),
6552 .RESVAL (1'h0),
6553 .Mubi (1'b0)
6554 ) u_cmd_filter_4_filter_132 (
6555 .clk_i (clk_i),
6556 .rst_ni (rst_ni),
6557
6558 // from register interface
6559 .we (cmd_filter_4_we),
6560 .wd (cmd_filter_4_filter_132_wd),
6561
6562 // from internal hardware
6563 .de (1'b0),
6564 .d ('0),
6565
6566 // to internal hardware
6567 .qe (),
6568 .q (reg2hw.cmd_filter[132].q),
6569 .ds (),
6570
6571 // to register interface (read)
6572 .qs (cmd_filter_4_filter_132_qs)
6573 );
6574
6575 // F[filter_133]: 5:5
6576 prim_subreg #(
6577 .DW (1),
6578 .SwAccess(prim_subreg_pkg::SwAccessRW),
6579 .RESVAL (1'h0),
6580 .Mubi (1'b0)
6581 ) u_cmd_filter_4_filter_133 (
6582 .clk_i (clk_i),
6583 .rst_ni (rst_ni),
6584
6585 // from register interface
6586 .we (cmd_filter_4_we),
6587 .wd (cmd_filter_4_filter_133_wd),
6588
6589 // from internal hardware
6590 .de (1'b0),
6591 .d ('0),
6592
6593 // to internal hardware
6594 .qe (),
6595 .q (reg2hw.cmd_filter[133].q),
6596 .ds (),
6597
6598 // to register interface (read)
6599 .qs (cmd_filter_4_filter_133_qs)
6600 );
6601
6602 // F[filter_134]: 6:6
6603 prim_subreg #(
6604 .DW (1),
6605 .SwAccess(prim_subreg_pkg::SwAccessRW),
6606 .RESVAL (1'h0),
6607 .Mubi (1'b0)
6608 ) u_cmd_filter_4_filter_134 (
6609 .clk_i (clk_i),
6610 .rst_ni (rst_ni),
6611
6612 // from register interface
6613 .we (cmd_filter_4_we),
6614 .wd (cmd_filter_4_filter_134_wd),
6615
6616 // from internal hardware
6617 .de (1'b0),
6618 .d ('0),
6619
6620 // to internal hardware
6621 .qe (),
6622 .q (reg2hw.cmd_filter[134].q),
6623 .ds (),
6624
6625 // to register interface (read)
6626 .qs (cmd_filter_4_filter_134_qs)
6627 );
6628
6629 // F[filter_135]: 7:7
6630 prim_subreg #(
6631 .DW (1),
6632 .SwAccess(prim_subreg_pkg::SwAccessRW),
6633 .RESVAL (1'h0),
6634 .Mubi (1'b0)
6635 ) u_cmd_filter_4_filter_135 (
6636 .clk_i (clk_i),
6637 .rst_ni (rst_ni),
6638
6639 // from register interface
6640 .we (cmd_filter_4_we),
6641 .wd (cmd_filter_4_filter_135_wd),
6642
6643 // from internal hardware
6644 .de (1'b0),
6645 .d ('0),
6646
6647 // to internal hardware
6648 .qe (),
6649 .q (reg2hw.cmd_filter[135].q),
6650 .ds (),
6651
6652 // to register interface (read)
6653 .qs (cmd_filter_4_filter_135_qs)
6654 );
6655
6656 // F[filter_136]: 8:8
6657 prim_subreg #(
6658 .DW (1),
6659 .SwAccess(prim_subreg_pkg::SwAccessRW),
6660 .RESVAL (1'h0),
6661 .Mubi (1'b0)
6662 ) u_cmd_filter_4_filter_136 (
6663 .clk_i (clk_i),
6664 .rst_ni (rst_ni),
6665
6666 // from register interface
6667 .we (cmd_filter_4_we),
6668 .wd (cmd_filter_4_filter_136_wd),
6669
6670 // from internal hardware
6671 .de (1'b0),
6672 .d ('0),
6673
6674 // to internal hardware
6675 .qe (),
6676 .q (reg2hw.cmd_filter[136].q),
6677 .ds (),
6678
6679 // to register interface (read)
6680 .qs (cmd_filter_4_filter_136_qs)
6681 );
6682
6683 // F[filter_137]: 9:9
6684 prim_subreg #(
6685 .DW (1),
6686 .SwAccess(prim_subreg_pkg::SwAccessRW),
6687 .RESVAL (1'h0),
6688 .Mubi (1'b0)
6689 ) u_cmd_filter_4_filter_137 (
6690 .clk_i (clk_i),
6691 .rst_ni (rst_ni),
6692
6693 // from register interface
6694 .we (cmd_filter_4_we),
6695 .wd (cmd_filter_4_filter_137_wd),
6696
6697 // from internal hardware
6698 .de (1'b0),
6699 .d ('0),
6700
6701 // to internal hardware
6702 .qe (),
6703 .q (reg2hw.cmd_filter[137].q),
6704 .ds (),
6705
6706 // to register interface (read)
6707 .qs (cmd_filter_4_filter_137_qs)
6708 );
6709
6710 // F[filter_138]: 10:10
6711 prim_subreg #(
6712 .DW (1),
6713 .SwAccess(prim_subreg_pkg::SwAccessRW),
6714 .RESVAL (1'h0),
6715 .Mubi (1'b0)
6716 ) u_cmd_filter_4_filter_138 (
6717 .clk_i (clk_i),
6718 .rst_ni (rst_ni),
6719
6720 // from register interface
6721 .we (cmd_filter_4_we),
6722 .wd (cmd_filter_4_filter_138_wd),
6723
6724 // from internal hardware
6725 .de (1'b0),
6726 .d ('0),
6727
6728 // to internal hardware
6729 .qe (),
6730 .q (reg2hw.cmd_filter[138].q),
6731 .ds (),
6732
6733 // to register interface (read)
6734 .qs (cmd_filter_4_filter_138_qs)
6735 );
6736
6737 // F[filter_139]: 11:11
6738 prim_subreg #(
6739 .DW (1),
6740 .SwAccess(prim_subreg_pkg::SwAccessRW),
6741 .RESVAL (1'h0),
6742 .Mubi (1'b0)
6743 ) u_cmd_filter_4_filter_139 (
6744 .clk_i (clk_i),
6745 .rst_ni (rst_ni),
6746
6747 // from register interface
6748 .we (cmd_filter_4_we),
6749 .wd (cmd_filter_4_filter_139_wd),
6750
6751 // from internal hardware
6752 .de (1'b0),
6753 .d ('0),
6754
6755 // to internal hardware
6756 .qe (),
6757 .q (reg2hw.cmd_filter[139].q),
6758 .ds (),
6759
6760 // to register interface (read)
6761 .qs (cmd_filter_4_filter_139_qs)
6762 );
6763
6764 // F[filter_140]: 12:12
6765 prim_subreg #(
6766 .DW (1),
6767 .SwAccess(prim_subreg_pkg::SwAccessRW),
6768 .RESVAL (1'h0),
6769 .Mubi (1'b0)
6770 ) u_cmd_filter_4_filter_140 (
6771 .clk_i (clk_i),
6772 .rst_ni (rst_ni),
6773
6774 // from register interface
6775 .we (cmd_filter_4_we),
6776 .wd (cmd_filter_4_filter_140_wd),
6777
6778 // from internal hardware
6779 .de (1'b0),
6780 .d ('0),
6781
6782 // to internal hardware
6783 .qe (),
6784 .q (reg2hw.cmd_filter[140].q),
6785 .ds (),
6786
6787 // to register interface (read)
6788 .qs (cmd_filter_4_filter_140_qs)
6789 );
6790
6791 // F[filter_141]: 13:13
6792 prim_subreg #(
6793 .DW (1),
6794 .SwAccess(prim_subreg_pkg::SwAccessRW),
6795 .RESVAL (1'h0),
6796 .Mubi (1'b0)
6797 ) u_cmd_filter_4_filter_141 (
6798 .clk_i (clk_i),
6799 .rst_ni (rst_ni),
6800
6801 // from register interface
6802 .we (cmd_filter_4_we),
6803 .wd (cmd_filter_4_filter_141_wd),
6804
6805 // from internal hardware
6806 .de (1'b0),
6807 .d ('0),
6808
6809 // to internal hardware
6810 .qe (),
6811 .q (reg2hw.cmd_filter[141].q),
6812 .ds (),
6813
6814 // to register interface (read)
6815 .qs (cmd_filter_4_filter_141_qs)
6816 );
6817
6818 // F[filter_142]: 14:14
6819 prim_subreg #(
6820 .DW (1),
6821 .SwAccess(prim_subreg_pkg::SwAccessRW),
6822 .RESVAL (1'h0),
6823 .Mubi (1'b0)
6824 ) u_cmd_filter_4_filter_142 (
6825 .clk_i (clk_i),
6826 .rst_ni (rst_ni),
6827
6828 // from register interface
6829 .we (cmd_filter_4_we),
6830 .wd (cmd_filter_4_filter_142_wd),
6831
6832 // from internal hardware
6833 .de (1'b0),
6834 .d ('0),
6835
6836 // to internal hardware
6837 .qe (),
6838 .q (reg2hw.cmd_filter[142].q),
6839 .ds (),
6840
6841 // to register interface (read)
6842 .qs (cmd_filter_4_filter_142_qs)
6843 );
6844
6845 // F[filter_143]: 15:15
6846 prim_subreg #(
6847 .DW (1),
6848 .SwAccess(prim_subreg_pkg::SwAccessRW),
6849 .RESVAL (1'h0),
6850 .Mubi (1'b0)
6851 ) u_cmd_filter_4_filter_143 (
6852 .clk_i (clk_i),
6853 .rst_ni (rst_ni),
6854
6855 // from register interface
6856 .we (cmd_filter_4_we),
6857 .wd (cmd_filter_4_filter_143_wd),
6858
6859 // from internal hardware
6860 .de (1'b0),
6861 .d ('0),
6862
6863 // to internal hardware
6864 .qe (),
6865 .q (reg2hw.cmd_filter[143].q),
6866 .ds (),
6867
6868 // to register interface (read)
6869 .qs (cmd_filter_4_filter_143_qs)
6870 );
6871
6872 // F[filter_144]: 16:16
6873 prim_subreg #(
6874 .DW (1),
6875 .SwAccess(prim_subreg_pkg::SwAccessRW),
6876 .RESVAL (1'h0),
6877 .Mubi (1'b0)
6878 ) u_cmd_filter_4_filter_144 (
6879 .clk_i (clk_i),
6880 .rst_ni (rst_ni),
6881
6882 // from register interface
6883 .we (cmd_filter_4_we),
6884 .wd (cmd_filter_4_filter_144_wd),
6885
6886 // from internal hardware
6887 .de (1'b0),
6888 .d ('0),
6889
6890 // to internal hardware
6891 .qe (),
6892 .q (reg2hw.cmd_filter[144].q),
6893 .ds (),
6894
6895 // to register interface (read)
6896 .qs (cmd_filter_4_filter_144_qs)
6897 );
6898
6899 // F[filter_145]: 17:17
6900 prim_subreg #(
6901 .DW (1),
6902 .SwAccess(prim_subreg_pkg::SwAccessRW),
6903 .RESVAL (1'h0),
6904 .Mubi (1'b0)
6905 ) u_cmd_filter_4_filter_145 (
6906 .clk_i (clk_i),
6907 .rst_ni (rst_ni),
6908
6909 // from register interface
6910 .we (cmd_filter_4_we),
6911 .wd (cmd_filter_4_filter_145_wd),
6912
6913 // from internal hardware
6914 .de (1'b0),
6915 .d ('0),
6916
6917 // to internal hardware
6918 .qe (),
6919 .q (reg2hw.cmd_filter[145].q),
6920 .ds (),
6921
6922 // to register interface (read)
6923 .qs (cmd_filter_4_filter_145_qs)
6924 );
6925
6926 // F[filter_146]: 18:18
6927 prim_subreg #(
6928 .DW (1),
6929 .SwAccess(prim_subreg_pkg::SwAccessRW),
6930 .RESVAL (1'h0),
6931 .Mubi (1'b0)
6932 ) u_cmd_filter_4_filter_146 (
6933 .clk_i (clk_i),
6934 .rst_ni (rst_ni),
6935
6936 // from register interface
6937 .we (cmd_filter_4_we),
6938 .wd (cmd_filter_4_filter_146_wd),
6939
6940 // from internal hardware
6941 .de (1'b0),
6942 .d ('0),
6943
6944 // to internal hardware
6945 .qe (),
6946 .q (reg2hw.cmd_filter[146].q),
6947 .ds (),
6948
6949 // to register interface (read)
6950 .qs (cmd_filter_4_filter_146_qs)
6951 );
6952
6953 // F[filter_147]: 19:19
6954 prim_subreg #(
6955 .DW (1),
6956 .SwAccess(prim_subreg_pkg::SwAccessRW),
6957 .RESVAL (1'h0),
6958 .Mubi (1'b0)
6959 ) u_cmd_filter_4_filter_147 (
6960 .clk_i (clk_i),
6961 .rst_ni (rst_ni),
6962
6963 // from register interface
6964 .we (cmd_filter_4_we),
6965 .wd (cmd_filter_4_filter_147_wd),
6966
6967 // from internal hardware
6968 .de (1'b0),
6969 .d ('0),
6970
6971 // to internal hardware
6972 .qe (),
6973 .q (reg2hw.cmd_filter[147].q),
6974 .ds (),
6975
6976 // to register interface (read)
6977 .qs (cmd_filter_4_filter_147_qs)
6978 );
6979
6980 // F[filter_148]: 20:20
6981 prim_subreg #(
6982 .DW (1),
6983 .SwAccess(prim_subreg_pkg::SwAccessRW),
6984 .RESVAL (1'h0),
6985 .Mubi (1'b0)
6986 ) u_cmd_filter_4_filter_148 (
6987 .clk_i (clk_i),
6988 .rst_ni (rst_ni),
6989
6990 // from register interface
6991 .we (cmd_filter_4_we),
6992 .wd (cmd_filter_4_filter_148_wd),
6993
6994 // from internal hardware
6995 .de (1'b0),
6996 .d ('0),
6997
6998 // to internal hardware
6999 .qe (),
7000 .q (reg2hw.cmd_filter[148].q),
7001 .ds (),
7002
7003 // to register interface (read)
7004 .qs (cmd_filter_4_filter_148_qs)
7005 );
7006
7007 // F[filter_149]: 21:21
7008 prim_subreg #(
7009 .DW (1),
7010 .SwAccess(prim_subreg_pkg::SwAccessRW),
7011 .RESVAL (1'h0),
7012 .Mubi (1'b0)
7013 ) u_cmd_filter_4_filter_149 (
7014 .clk_i (clk_i),
7015 .rst_ni (rst_ni),
7016
7017 // from register interface
7018 .we (cmd_filter_4_we),
7019 .wd (cmd_filter_4_filter_149_wd),
7020
7021 // from internal hardware
7022 .de (1'b0),
7023 .d ('0),
7024
7025 // to internal hardware
7026 .qe (),
7027 .q (reg2hw.cmd_filter[149].q),
7028 .ds (),
7029
7030 // to register interface (read)
7031 .qs (cmd_filter_4_filter_149_qs)
7032 );
7033
7034 // F[filter_150]: 22:22
7035 prim_subreg #(
7036 .DW (1),
7037 .SwAccess(prim_subreg_pkg::SwAccessRW),
7038 .RESVAL (1'h0),
7039 .Mubi (1'b0)
7040 ) u_cmd_filter_4_filter_150 (
7041 .clk_i (clk_i),
7042 .rst_ni (rst_ni),
7043
7044 // from register interface
7045 .we (cmd_filter_4_we),
7046 .wd (cmd_filter_4_filter_150_wd),
7047
7048 // from internal hardware
7049 .de (1'b0),
7050 .d ('0),
7051
7052 // to internal hardware
7053 .qe (),
7054 .q (reg2hw.cmd_filter[150].q),
7055 .ds (),
7056
7057 // to register interface (read)
7058 .qs (cmd_filter_4_filter_150_qs)
7059 );
7060
7061 // F[filter_151]: 23:23
7062 prim_subreg #(
7063 .DW (1),
7064 .SwAccess(prim_subreg_pkg::SwAccessRW),
7065 .RESVAL (1'h0),
7066 .Mubi (1'b0)
7067 ) u_cmd_filter_4_filter_151 (
7068 .clk_i (clk_i),
7069 .rst_ni (rst_ni),
7070
7071 // from register interface
7072 .we (cmd_filter_4_we),
7073 .wd (cmd_filter_4_filter_151_wd),
7074
7075 // from internal hardware
7076 .de (1'b0),
7077 .d ('0),
7078
7079 // to internal hardware
7080 .qe (),
7081 .q (reg2hw.cmd_filter[151].q),
7082 .ds (),
7083
7084 // to register interface (read)
7085 .qs (cmd_filter_4_filter_151_qs)
7086 );
7087
7088 // F[filter_152]: 24:24
7089 prim_subreg #(
7090 .DW (1),
7091 .SwAccess(prim_subreg_pkg::SwAccessRW),
7092 .RESVAL (1'h0),
7093 .Mubi (1'b0)
7094 ) u_cmd_filter_4_filter_152 (
7095 .clk_i (clk_i),
7096 .rst_ni (rst_ni),
7097
7098 // from register interface
7099 .we (cmd_filter_4_we),
7100 .wd (cmd_filter_4_filter_152_wd),
7101
7102 // from internal hardware
7103 .de (1'b0),
7104 .d ('0),
7105
7106 // to internal hardware
7107 .qe (),
7108 .q (reg2hw.cmd_filter[152].q),
7109 .ds (),
7110
7111 // to register interface (read)
7112 .qs (cmd_filter_4_filter_152_qs)
7113 );
7114
7115 // F[filter_153]: 25:25
7116 prim_subreg #(
7117 .DW (1),
7118 .SwAccess(prim_subreg_pkg::SwAccessRW),
7119 .RESVAL (1'h0),
7120 .Mubi (1'b0)
7121 ) u_cmd_filter_4_filter_153 (
7122 .clk_i (clk_i),
7123 .rst_ni (rst_ni),
7124
7125 // from register interface
7126 .we (cmd_filter_4_we),
7127 .wd (cmd_filter_4_filter_153_wd),
7128
7129 // from internal hardware
7130 .de (1'b0),
7131 .d ('0),
7132
7133 // to internal hardware
7134 .qe (),
7135 .q (reg2hw.cmd_filter[153].q),
7136 .ds (),
7137
7138 // to register interface (read)
7139 .qs (cmd_filter_4_filter_153_qs)
7140 );
7141
7142 // F[filter_154]: 26:26
7143 prim_subreg #(
7144 .DW (1),
7145 .SwAccess(prim_subreg_pkg::SwAccessRW),
7146 .RESVAL (1'h0),
7147 .Mubi (1'b0)
7148 ) u_cmd_filter_4_filter_154 (
7149 .clk_i (clk_i),
7150 .rst_ni (rst_ni),
7151
7152 // from register interface
7153 .we (cmd_filter_4_we),
7154 .wd (cmd_filter_4_filter_154_wd),
7155
7156 // from internal hardware
7157 .de (1'b0),
7158 .d ('0),
7159
7160 // to internal hardware
7161 .qe (),
7162 .q (reg2hw.cmd_filter[154].q),
7163 .ds (),
7164
7165 // to register interface (read)
7166 .qs (cmd_filter_4_filter_154_qs)
7167 );
7168
7169 // F[filter_155]: 27:27
7170 prim_subreg #(
7171 .DW (1),
7172 .SwAccess(prim_subreg_pkg::SwAccessRW),
7173 .RESVAL (1'h0),
7174 .Mubi (1'b0)
7175 ) u_cmd_filter_4_filter_155 (
7176 .clk_i (clk_i),
7177 .rst_ni (rst_ni),
7178
7179 // from register interface
7180 .we (cmd_filter_4_we),
7181 .wd (cmd_filter_4_filter_155_wd),
7182
7183 // from internal hardware
7184 .de (1'b0),
7185 .d ('0),
7186
7187 // to internal hardware
7188 .qe (),
7189 .q (reg2hw.cmd_filter[155].q),
7190 .ds (),
7191
7192 // to register interface (read)
7193 .qs (cmd_filter_4_filter_155_qs)
7194 );
7195
7196 // F[filter_156]: 28:28
7197 prim_subreg #(
7198 .DW (1),
7199 .SwAccess(prim_subreg_pkg::SwAccessRW),
7200 .RESVAL (1'h0),
7201 .Mubi (1'b0)
7202 ) u_cmd_filter_4_filter_156 (
7203 .clk_i (clk_i),
7204 .rst_ni (rst_ni),
7205
7206 // from register interface
7207 .we (cmd_filter_4_we),
7208 .wd (cmd_filter_4_filter_156_wd),
7209
7210 // from internal hardware
7211 .de (1'b0),
7212 .d ('0),
7213
7214 // to internal hardware
7215 .qe (),
7216 .q (reg2hw.cmd_filter[156].q),
7217 .ds (),
7218
7219 // to register interface (read)
7220 .qs (cmd_filter_4_filter_156_qs)
7221 );
7222
7223 // F[filter_157]: 29:29
7224 prim_subreg #(
7225 .DW (1),
7226 .SwAccess(prim_subreg_pkg::SwAccessRW),
7227 .RESVAL (1'h0),
7228 .Mubi (1'b0)
7229 ) u_cmd_filter_4_filter_157 (
7230 .clk_i (clk_i),
7231 .rst_ni (rst_ni),
7232
7233 // from register interface
7234 .we (cmd_filter_4_we),
7235 .wd (cmd_filter_4_filter_157_wd),
7236
7237 // from internal hardware
7238 .de (1'b0),
7239 .d ('0),
7240
7241 // to internal hardware
7242 .qe (),
7243 .q (reg2hw.cmd_filter[157].q),
7244 .ds (),
7245
7246 // to register interface (read)
7247 .qs (cmd_filter_4_filter_157_qs)
7248 );
7249
7250 // F[filter_158]: 30:30
7251 prim_subreg #(
7252 .DW (1),
7253 .SwAccess(prim_subreg_pkg::SwAccessRW),
7254 .RESVAL (1'h0),
7255 .Mubi (1'b0)
7256 ) u_cmd_filter_4_filter_158 (
7257 .clk_i (clk_i),
7258 .rst_ni (rst_ni),
7259
7260 // from register interface
7261 .we (cmd_filter_4_we),
7262 .wd (cmd_filter_4_filter_158_wd),
7263
7264 // from internal hardware
7265 .de (1'b0),
7266 .d ('0),
7267
7268 // to internal hardware
7269 .qe (),
7270 .q (reg2hw.cmd_filter[158].q),
7271 .ds (),
7272
7273 // to register interface (read)
7274 .qs (cmd_filter_4_filter_158_qs)
7275 );
7276
7277 // F[filter_159]: 31:31
7278 prim_subreg #(
7279 .DW (1),
7280 .SwAccess(prim_subreg_pkg::SwAccessRW),
7281 .RESVAL (1'h0),
7282 .Mubi (1'b0)
7283 ) u_cmd_filter_4_filter_159 (
7284 .clk_i (clk_i),
7285 .rst_ni (rst_ni),
7286
7287 // from register interface
7288 .we (cmd_filter_4_we),
7289 .wd (cmd_filter_4_filter_159_wd),
7290
7291 // from internal hardware
7292 .de (1'b0),
7293 .d ('0),
7294
7295 // to internal hardware
7296 .qe (),
7297 .q (reg2hw.cmd_filter[159].q),
7298 .ds (),
7299
7300 // to register interface (read)
7301 .qs (cmd_filter_4_filter_159_qs)
7302 );
7303
7304
7305 // Subregister 5 of Multireg cmd_filter
7306 // R[cmd_filter_5]: V(False)
7307 // F[filter_160]: 0:0
7308 prim_subreg #(
7309 .DW (1),
7310 .SwAccess(prim_subreg_pkg::SwAccessRW),
7311 .RESVAL (1'h0),
7312 .Mubi (1'b0)
7313 ) u_cmd_filter_5_filter_160 (
7314 .clk_i (clk_i),
7315 .rst_ni (rst_ni),
7316
7317 // from register interface
7318 .we (cmd_filter_5_we),
7319 .wd (cmd_filter_5_filter_160_wd),
7320
7321 // from internal hardware
7322 .de (1'b0),
7323 .d ('0),
7324
7325 // to internal hardware
7326 .qe (),
7327 .q (reg2hw.cmd_filter[160].q),
7328 .ds (),
7329
7330 // to register interface (read)
7331 .qs (cmd_filter_5_filter_160_qs)
7332 );
7333
7334 // F[filter_161]: 1:1
7335 prim_subreg #(
7336 .DW (1),
7337 .SwAccess(prim_subreg_pkg::SwAccessRW),
7338 .RESVAL (1'h0),
7339 .Mubi (1'b0)
7340 ) u_cmd_filter_5_filter_161 (
7341 .clk_i (clk_i),
7342 .rst_ni (rst_ni),
7343
7344 // from register interface
7345 .we (cmd_filter_5_we),
7346 .wd (cmd_filter_5_filter_161_wd),
7347
7348 // from internal hardware
7349 .de (1'b0),
7350 .d ('0),
7351
7352 // to internal hardware
7353 .qe (),
7354 .q (reg2hw.cmd_filter[161].q),
7355 .ds (),
7356
7357 // to register interface (read)
7358 .qs (cmd_filter_5_filter_161_qs)
7359 );
7360
7361 // F[filter_162]: 2:2
7362 prim_subreg #(
7363 .DW (1),
7364 .SwAccess(prim_subreg_pkg::SwAccessRW),
7365 .RESVAL (1'h0),
7366 .Mubi (1'b0)
7367 ) u_cmd_filter_5_filter_162 (
7368 .clk_i (clk_i),
7369 .rst_ni (rst_ni),
7370
7371 // from register interface
7372 .we (cmd_filter_5_we),
7373 .wd (cmd_filter_5_filter_162_wd),
7374
7375 // from internal hardware
7376 .de (1'b0),
7377 .d ('0),
7378
7379 // to internal hardware
7380 .qe (),
7381 .q (reg2hw.cmd_filter[162].q),
7382 .ds (),
7383
7384 // to register interface (read)
7385 .qs (cmd_filter_5_filter_162_qs)
7386 );
7387
7388 // F[filter_163]: 3:3
7389 prim_subreg #(
7390 .DW (1),
7391 .SwAccess(prim_subreg_pkg::SwAccessRW),
7392 .RESVAL (1'h0),
7393 .Mubi (1'b0)
7394 ) u_cmd_filter_5_filter_163 (
7395 .clk_i (clk_i),
7396 .rst_ni (rst_ni),
7397
7398 // from register interface
7399 .we (cmd_filter_5_we),
7400 .wd (cmd_filter_5_filter_163_wd),
7401
7402 // from internal hardware
7403 .de (1'b0),
7404 .d ('0),
7405
7406 // to internal hardware
7407 .qe (),
7408 .q (reg2hw.cmd_filter[163].q),
7409 .ds (),
7410
7411 // to register interface (read)
7412 .qs (cmd_filter_5_filter_163_qs)
7413 );
7414
7415 // F[filter_164]: 4:4
7416 prim_subreg #(
7417 .DW (1),
7418 .SwAccess(prim_subreg_pkg::SwAccessRW),
7419 .RESVAL (1'h0),
7420 .Mubi (1'b0)
7421 ) u_cmd_filter_5_filter_164 (
7422 .clk_i (clk_i),
7423 .rst_ni (rst_ni),
7424
7425 // from register interface
7426 .we (cmd_filter_5_we),
7427 .wd (cmd_filter_5_filter_164_wd),
7428
7429 // from internal hardware
7430 .de (1'b0),
7431 .d ('0),
7432
7433 // to internal hardware
7434 .qe (),
7435 .q (reg2hw.cmd_filter[164].q),
7436 .ds (),
7437
7438 // to register interface (read)
7439 .qs (cmd_filter_5_filter_164_qs)
7440 );
7441
7442 // F[filter_165]: 5:5
7443 prim_subreg #(
7444 .DW (1),
7445 .SwAccess(prim_subreg_pkg::SwAccessRW),
7446 .RESVAL (1'h0),
7447 .Mubi (1'b0)
7448 ) u_cmd_filter_5_filter_165 (
7449 .clk_i (clk_i),
7450 .rst_ni (rst_ni),
7451
7452 // from register interface
7453 .we (cmd_filter_5_we),
7454 .wd (cmd_filter_5_filter_165_wd),
7455
7456 // from internal hardware
7457 .de (1'b0),
7458 .d ('0),
7459
7460 // to internal hardware
7461 .qe (),
7462 .q (reg2hw.cmd_filter[165].q),
7463 .ds (),
7464
7465 // to register interface (read)
7466 .qs (cmd_filter_5_filter_165_qs)
7467 );
7468
7469 // F[filter_166]: 6:6
7470 prim_subreg #(
7471 .DW (1),
7472 .SwAccess(prim_subreg_pkg::SwAccessRW),
7473 .RESVAL (1'h0),
7474 .Mubi (1'b0)
7475 ) u_cmd_filter_5_filter_166 (
7476 .clk_i (clk_i),
7477 .rst_ni (rst_ni),
7478
7479 // from register interface
7480 .we (cmd_filter_5_we),
7481 .wd (cmd_filter_5_filter_166_wd),
7482
7483 // from internal hardware
7484 .de (1'b0),
7485 .d ('0),
7486
7487 // to internal hardware
7488 .qe (),
7489 .q (reg2hw.cmd_filter[166].q),
7490 .ds (),
7491
7492 // to register interface (read)
7493 .qs (cmd_filter_5_filter_166_qs)
7494 );
7495
7496 // F[filter_167]: 7:7
7497 prim_subreg #(
7498 .DW (1),
7499 .SwAccess(prim_subreg_pkg::SwAccessRW),
7500 .RESVAL (1'h0),
7501 .Mubi (1'b0)
7502 ) u_cmd_filter_5_filter_167 (
7503 .clk_i (clk_i),
7504 .rst_ni (rst_ni),
7505
7506 // from register interface
7507 .we (cmd_filter_5_we),
7508 .wd (cmd_filter_5_filter_167_wd),
7509
7510 // from internal hardware
7511 .de (1'b0),
7512 .d ('0),
7513
7514 // to internal hardware
7515 .qe (),
7516 .q (reg2hw.cmd_filter[167].q),
7517 .ds (),
7518
7519 // to register interface (read)
7520 .qs (cmd_filter_5_filter_167_qs)
7521 );
7522
7523 // F[filter_168]: 8:8
7524 prim_subreg #(
7525 .DW (1),
7526 .SwAccess(prim_subreg_pkg::SwAccessRW),
7527 .RESVAL (1'h0),
7528 .Mubi (1'b0)
7529 ) u_cmd_filter_5_filter_168 (
7530 .clk_i (clk_i),
7531 .rst_ni (rst_ni),
7532
7533 // from register interface
7534 .we (cmd_filter_5_we),
7535 .wd (cmd_filter_5_filter_168_wd),
7536
7537 // from internal hardware
7538 .de (1'b0),
7539 .d ('0),
7540
7541 // to internal hardware
7542 .qe (),
7543 .q (reg2hw.cmd_filter[168].q),
7544 .ds (),
7545
7546 // to register interface (read)
7547 .qs (cmd_filter_5_filter_168_qs)
7548 );
7549
7550 // F[filter_169]: 9:9
7551 prim_subreg #(
7552 .DW (1),
7553 .SwAccess(prim_subreg_pkg::SwAccessRW),
7554 .RESVAL (1'h0),
7555 .Mubi (1'b0)
7556 ) u_cmd_filter_5_filter_169 (
7557 .clk_i (clk_i),
7558 .rst_ni (rst_ni),
7559
7560 // from register interface
7561 .we (cmd_filter_5_we),
7562 .wd (cmd_filter_5_filter_169_wd),
7563
7564 // from internal hardware
7565 .de (1'b0),
7566 .d ('0),
7567
7568 // to internal hardware
7569 .qe (),
7570 .q (reg2hw.cmd_filter[169].q),
7571 .ds (),
7572
7573 // to register interface (read)
7574 .qs (cmd_filter_5_filter_169_qs)
7575 );
7576
7577 // F[filter_170]: 10:10
7578 prim_subreg #(
7579 .DW (1),
7580 .SwAccess(prim_subreg_pkg::SwAccessRW),
7581 .RESVAL (1'h0),
7582 .Mubi (1'b0)
7583 ) u_cmd_filter_5_filter_170 (
7584 .clk_i (clk_i),
7585 .rst_ni (rst_ni),
7586
7587 // from register interface
7588 .we (cmd_filter_5_we),
7589 .wd (cmd_filter_5_filter_170_wd),
7590
7591 // from internal hardware
7592 .de (1'b0),
7593 .d ('0),
7594
7595 // to internal hardware
7596 .qe (),
7597 .q (reg2hw.cmd_filter[170].q),
7598 .ds (),
7599
7600 // to register interface (read)
7601 .qs (cmd_filter_5_filter_170_qs)
7602 );
7603
7604 // F[filter_171]: 11:11
7605 prim_subreg #(
7606 .DW (1),
7607 .SwAccess(prim_subreg_pkg::SwAccessRW),
7608 .RESVAL (1'h0),
7609 .Mubi (1'b0)
7610 ) u_cmd_filter_5_filter_171 (
7611 .clk_i (clk_i),
7612 .rst_ni (rst_ni),
7613
7614 // from register interface
7615 .we (cmd_filter_5_we),
7616 .wd (cmd_filter_5_filter_171_wd),
7617
7618 // from internal hardware
7619 .de (1'b0),
7620 .d ('0),
7621
7622 // to internal hardware
7623 .qe (),
7624 .q (reg2hw.cmd_filter[171].q),
7625 .ds (),
7626
7627 // to register interface (read)
7628 .qs (cmd_filter_5_filter_171_qs)
7629 );
7630
7631 // F[filter_172]: 12:12
7632 prim_subreg #(
7633 .DW (1),
7634 .SwAccess(prim_subreg_pkg::SwAccessRW),
7635 .RESVAL (1'h0),
7636 .Mubi (1'b0)
7637 ) u_cmd_filter_5_filter_172 (
7638 .clk_i (clk_i),
7639 .rst_ni (rst_ni),
7640
7641 // from register interface
7642 .we (cmd_filter_5_we),
7643 .wd (cmd_filter_5_filter_172_wd),
7644
7645 // from internal hardware
7646 .de (1'b0),
7647 .d ('0),
7648
7649 // to internal hardware
7650 .qe (),
7651 .q (reg2hw.cmd_filter[172].q),
7652 .ds (),
7653
7654 // to register interface (read)
7655 .qs (cmd_filter_5_filter_172_qs)
7656 );
7657
7658 // F[filter_173]: 13:13
7659 prim_subreg #(
7660 .DW (1),
7661 .SwAccess(prim_subreg_pkg::SwAccessRW),
7662 .RESVAL (1'h0),
7663 .Mubi (1'b0)
7664 ) u_cmd_filter_5_filter_173 (
7665 .clk_i (clk_i),
7666 .rst_ni (rst_ni),
7667
7668 // from register interface
7669 .we (cmd_filter_5_we),
7670 .wd (cmd_filter_5_filter_173_wd),
7671
7672 // from internal hardware
7673 .de (1'b0),
7674 .d ('0),
7675
7676 // to internal hardware
7677 .qe (),
7678 .q (reg2hw.cmd_filter[173].q),
7679 .ds (),
7680
7681 // to register interface (read)
7682 .qs (cmd_filter_5_filter_173_qs)
7683 );
7684
7685 // F[filter_174]: 14:14
7686 prim_subreg #(
7687 .DW (1),
7688 .SwAccess(prim_subreg_pkg::SwAccessRW),
7689 .RESVAL (1'h0),
7690 .Mubi (1'b0)
7691 ) u_cmd_filter_5_filter_174 (
7692 .clk_i (clk_i),
7693 .rst_ni (rst_ni),
7694
7695 // from register interface
7696 .we (cmd_filter_5_we),
7697 .wd (cmd_filter_5_filter_174_wd),
7698
7699 // from internal hardware
7700 .de (1'b0),
7701 .d ('0),
7702
7703 // to internal hardware
7704 .qe (),
7705 .q (reg2hw.cmd_filter[174].q),
7706 .ds (),
7707
7708 // to register interface (read)
7709 .qs (cmd_filter_5_filter_174_qs)
7710 );
7711
7712 // F[filter_175]: 15:15
7713 prim_subreg #(
7714 .DW (1),
7715 .SwAccess(prim_subreg_pkg::SwAccessRW),
7716 .RESVAL (1'h0),
7717 .Mubi (1'b0)
7718 ) u_cmd_filter_5_filter_175 (
7719 .clk_i (clk_i),
7720 .rst_ni (rst_ni),
7721
7722 // from register interface
7723 .we (cmd_filter_5_we),
7724 .wd (cmd_filter_5_filter_175_wd),
7725
7726 // from internal hardware
7727 .de (1'b0),
7728 .d ('0),
7729
7730 // to internal hardware
7731 .qe (),
7732 .q (reg2hw.cmd_filter[175].q),
7733 .ds (),
7734
7735 // to register interface (read)
7736 .qs (cmd_filter_5_filter_175_qs)
7737 );
7738
7739 // F[filter_176]: 16:16
7740 prim_subreg #(
7741 .DW (1),
7742 .SwAccess(prim_subreg_pkg::SwAccessRW),
7743 .RESVAL (1'h0),
7744 .Mubi (1'b0)
7745 ) u_cmd_filter_5_filter_176 (
7746 .clk_i (clk_i),
7747 .rst_ni (rst_ni),
7748
7749 // from register interface
7750 .we (cmd_filter_5_we),
7751 .wd (cmd_filter_5_filter_176_wd),
7752
7753 // from internal hardware
7754 .de (1'b0),
7755 .d ('0),
7756
7757 // to internal hardware
7758 .qe (),
7759 .q (reg2hw.cmd_filter[176].q),
7760 .ds (),
7761
7762 // to register interface (read)
7763 .qs (cmd_filter_5_filter_176_qs)
7764 );
7765
7766 // F[filter_177]: 17:17
7767 prim_subreg #(
7768 .DW (1),
7769 .SwAccess(prim_subreg_pkg::SwAccessRW),
7770 .RESVAL (1'h0),
7771 .Mubi (1'b0)
7772 ) u_cmd_filter_5_filter_177 (
7773 .clk_i (clk_i),
7774 .rst_ni (rst_ni),
7775
7776 // from register interface
7777 .we (cmd_filter_5_we),
7778 .wd (cmd_filter_5_filter_177_wd),
7779
7780 // from internal hardware
7781 .de (1'b0),
7782 .d ('0),
7783
7784 // to internal hardware
7785 .qe (),
7786 .q (reg2hw.cmd_filter[177].q),
7787 .ds (),
7788
7789 // to register interface (read)
7790 .qs (cmd_filter_5_filter_177_qs)
7791 );
7792
7793 // F[filter_178]: 18:18
7794 prim_subreg #(
7795 .DW (1),
7796 .SwAccess(prim_subreg_pkg::SwAccessRW),
7797 .RESVAL (1'h0),
7798 .Mubi (1'b0)
7799 ) u_cmd_filter_5_filter_178 (
7800 .clk_i (clk_i),
7801 .rst_ni (rst_ni),
7802
7803 // from register interface
7804 .we (cmd_filter_5_we),
7805 .wd (cmd_filter_5_filter_178_wd),
7806
7807 // from internal hardware
7808 .de (1'b0),
7809 .d ('0),
7810
7811 // to internal hardware
7812 .qe (),
7813 .q (reg2hw.cmd_filter[178].q),
7814 .ds (),
7815
7816 // to register interface (read)
7817 .qs (cmd_filter_5_filter_178_qs)
7818 );
7819
7820 // F[filter_179]: 19:19
7821 prim_subreg #(
7822 .DW (1),
7823 .SwAccess(prim_subreg_pkg::SwAccessRW),
7824 .RESVAL (1'h0),
7825 .Mubi (1'b0)
7826 ) u_cmd_filter_5_filter_179 (
7827 .clk_i (clk_i),
7828 .rst_ni (rst_ni),
7829
7830 // from register interface
7831 .we (cmd_filter_5_we),
7832 .wd (cmd_filter_5_filter_179_wd),
7833
7834 // from internal hardware
7835 .de (1'b0),
7836 .d ('0),
7837
7838 // to internal hardware
7839 .qe (),
7840 .q (reg2hw.cmd_filter[179].q),
7841 .ds (),
7842
7843 // to register interface (read)
7844 .qs (cmd_filter_5_filter_179_qs)
7845 );
7846
7847 // F[filter_180]: 20:20
7848 prim_subreg #(
7849 .DW (1),
7850 .SwAccess(prim_subreg_pkg::SwAccessRW),
7851 .RESVAL (1'h0),
7852 .Mubi (1'b0)
7853 ) u_cmd_filter_5_filter_180 (
7854 .clk_i (clk_i),
7855 .rst_ni (rst_ni),
7856
7857 // from register interface
7858 .we (cmd_filter_5_we),
7859 .wd (cmd_filter_5_filter_180_wd),
7860
7861 // from internal hardware
7862 .de (1'b0),
7863 .d ('0),
7864
7865 // to internal hardware
7866 .qe (),
7867 .q (reg2hw.cmd_filter[180].q),
7868 .ds (),
7869
7870 // to register interface (read)
7871 .qs (cmd_filter_5_filter_180_qs)
7872 );
7873
7874 // F[filter_181]: 21:21
7875 prim_subreg #(
7876 .DW (1),
7877 .SwAccess(prim_subreg_pkg::SwAccessRW),
7878 .RESVAL (1'h0),
7879 .Mubi (1'b0)
7880 ) u_cmd_filter_5_filter_181 (
7881 .clk_i (clk_i),
7882 .rst_ni (rst_ni),
7883
7884 // from register interface
7885 .we (cmd_filter_5_we),
7886 .wd (cmd_filter_5_filter_181_wd),
7887
7888 // from internal hardware
7889 .de (1'b0),
7890 .d ('0),
7891
7892 // to internal hardware
7893 .qe (),
7894 .q (reg2hw.cmd_filter[181].q),
7895 .ds (),
7896
7897 // to register interface (read)
7898 .qs (cmd_filter_5_filter_181_qs)
7899 );
7900
7901 // F[filter_182]: 22:22
7902 prim_subreg #(
7903 .DW (1),
7904 .SwAccess(prim_subreg_pkg::SwAccessRW),
7905 .RESVAL (1'h0),
7906 .Mubi (1'b0)
7907 ) u_cmd_filter_5_filter_182 (
7908 .clk_i (clk_i),
7909 .rst_ni (rst_ni),
7910
7911 // from register interface
7912 .we (cmd_filter_5_we),
7913 .wd (cmd_filter_5_filter_182_wd),
7914
7915 // from internal hardware
7916 .de (1'b0),
7917 .d ('0),
7918
7919 // to internal hardware
7920 .qe (),
7921 .q (reg2hw.cmd_filter[182].q),
7922 .ds (),
7923
7924 // to register interface (read)
7925 .qs (cmd_filter_5_filter_182_qs)
7926 );
7927
7928 // F[filter_183]: 23:23
7929 prim_subreg #(
7930 .DW (1),
7931 .SwAccess(prim_subreg_pkg::SwAccessRW),
7932 .RESVAL (1'h0),
7933 .Mubi (1'b0)
7934 ) u_cmd_filter_5_filter_183 (
7935 .clk_i (clk_i),
7936 .rst_ni (rst_ni),
7937
7938 // from register interface
7939 .we (cmd_filter_5_we),
7940 .wd (cmd_filter_5_filter_183_wd),
7941
7942 // from internal hardware
7943 .de (1'b0),
7944 .d ('0),
7945
7946 // to internal hardware
7947 .qe (),
7948 .q (reg2hw.cmd_filter[183].q),
7949 .ds (),
7950
7951 // to register interface (read)
7952 .qs (cmd_filter_5_filter_183_qs)
7953 );
7954
7955 // F[filter_184]: 24:24
7956 prim_subreg #(
7957 .DW (1),
7958 .SwAccess(prim_subreg_pkg::SwAccessRW),
7959 .RESVAL (1'h0),
7960 .Mubi (1'b0)
7961 ) u_cmd_filter_5_filter_184 (
7962 .clk_i (clk_i),
7963 .rst_ni (rst_ni),
7964
7965 // from register interface
7966 .we (cmd_filter_5_we),
7967 .wd (cmd_filter_5_filter_184_wd),
7968
7969 // from internal hardware
7970 .de (1'b0),
7971 .d ('0),
7972
7973 // to internal hardware
7974 .qe (),
7975 .q (reg2hw.cmd_filter[184].q),
7976 .ds (),
7977
7978 // to register interface (read)
7979 .qs (cmd_filter_5_filter_184_qs)
7980 );
7981
7982 // F[filter_185]: 25:25
7983 prim_subreg #(
7984 .DW (1),
7985 .SwAccess(prim_subreg_pkg::SwAccessRW),
7986 .RESVAL (1'h0),
7987 .Mubi (1'b0)
7988 ) u_cmd_filter_5_filter_185 (
7989 .clk_i (clk_i),
7990 .rst_ni (rst_ni),
7991
7992 // from register interface
7993 .we (cmd_filter_5_we),
7994 .wd (cmd_filter_5_filter_185_wd),
7995
7996 // from internal hardware
7997 .de (1'b0),
7998 .d ('0),
7999
8000 // to internal hardware
8001 .qe (),
8002 .q (reg2hw.cmd_filter[185].q),
8003 .ds (),
8004
8005 // to register interface (read)
8006 .qs (cmd_filter_5_filter_185_qs)
8007 );
8008
8009 // F[filter_186]: 26:26
8010 prim_subreg #(
8011 .DW (1),
8012 .SwAccess(prim_subreg_pkg::SwAccessRW),
8013 .RESVAL (1'h0),
8014 .Mubi (1'b0)
8015 ) u_cmd_filter_5_filter_186 (
8016 .clk_i (clk_i),
8017 .rst_ni (rst_ni),
8018
8019 // from register interface
8020 .we (cmd_filter_5_we),
8021 .wd (cmd_filter_5_filter_186_wd),
8022
8023 // from internal hardware
8024 .de (1'b0),
8025 .d ('0),
8026
8027 // to internal hardware
8028 .qe (),
8029 .q (reg2hw.cmd_filter[186].q),
8030 .ds (),
8031
8032 // to register interface (read)
8033 .qs (cmd_filter_5_filter_186_qs)
8034 );
8035
8036 // F[filter_187]: 27:27
8037 prim_subreg #(
8038 .DW (1),
8039 .SwAccess(prim_subreg_pkg::SwAccessRW),
8040 .RESVAL (1'h0),
8041 .Mubi (1'b0)
8042 ) u_cmd_filter_5_filter_187 (
8043 .clk_i (clk_i),
8044 .rst_ni (rst_ni),
8045
8046 // from register interface
8047 .we (cmd_filter_5_we),
8048 .wd (cmd_filter_5_filter_187_wd),
8049
8050 // from internal hardware
8051 .de (1'b0),
8052 .d ('0),
8053
8054 // to internal hardware
8055 .qe (),
8056 .q (reg2hw.cmd_filter[187].q),
8057 .ds (),
8058
8059 // to register interface (read)
8060 .qs (cmd_filter_5_filter_187_qs)
8061 );
8062
8063 // F[filter_188]: 28:28
8064 prim_subreg #(
8065 .DW (1),
8066 .SwAccess(prim_subreg_pkg::SwAccessRW),
8067 .RESVAL (1'h0),
8068 .Mubi (1'b0)
8069 ) u_cmd_filter_5_filter_188 (
8070 .clk_i (clk_i),
8071 .rst_ni (rst_ni),
8072
8073 // from register interface
8074 .we (cmd_filter_5_we),
8075 .wd (cmd_filter_5_filter_188_wd),
8076
8077 // from internal hardware
8078 .de (1'b0),
8079 .d ('0),
8080
8081 // to internal hardware
8082 .qe (),
8083 .q (reg2hw.cmd_filter[188].q),
8084 .ds (),
8085
8086 // to register interface (read)
8087 .qs (cmd_filter_5_filter_188_qs)
8088 );
8089
8090 // F[filter_189]: 29:29
8091 prim_subreg #(
8092 .DW (1),
8093 .SwAccess(prim_subreg_pkg::SwAccessRW),
8094 .RESVAL (1'h0),
8095 .Mubi (1'b0)
8096 ) u_cmd_filter_5_filter_189 (
8097 .clk_i (clk_i),
8098 .rst_ni (rst_ni),
8099
8100 // from register interface
8101 .we (cmd_filter_5_we),
8102 .wd (cmd_filter_5_filter_189_wd),
8103
8104 // from internal hardware
8105 .de (1'b0),
8106 .d ('0),
8107
8108 // to internal hardware
8109 .qe (),
8110 .q (reg2hw.cmd_filter[189].q),
8111 .ds (),
8112
8113 // to register interface (read)
8114 .qs (cmd_filter_5_filter_189_qs)
8115 );
8116
8117 // F[filter_190]: 30:30
8118 prim_subreg #(
8119 .DW (1),
8120 .SwAccess(prim_subreg_pkg::SwAccessRW),
8121 .RESVAL (1'h0),
8122 .Mubi (1'b0)
8123 ) u_cmd_filter_5_filter_190 (
8124 .clk_i (clk_i),
8125 .rst_ni (rst_ni),
8126
8127 // from register interface
8128 .we (cmd_filter_5_we),
8129 .wd (cmd_filter_5_filter_190_wd),
8130
8131 // from internal hardware
8132 .de (1'b0),
8133 .d ('0),
8134
8135 // to internal hardware
8136 .qe (),
8137 .q (reg2hw.cmd_filter[190].q),
8138 .ds (),
8139
8140 // to register interface (read)
8141 .qs (cmd_filter_5_filter_190_qs)
8142 );
8143
8144 // F[filter_191]: 31:31
8145 prim_subreg #(
8146 .DW (1),
8147 .SwAccess(prim_subreg_pkg::SwAccessRW),
8148 .RESVAL (1'h0),
8149 .Mubi (1'b0)
8150 ) u_cmd_filter_5_filter_191 (
8151 .clk_i (clk_i),
8152 .rst_ni (rst_ni),
8153
8154 // from register interface
8155 .we (cmd_filter_5_we),
8156 .wd (cmd_filter_5_filter_191_wd),
8157
8158 // from internal hardware
8159 .de (1'b0),
8160 .d ('0),
8161
8162 // to internal hardware
8163 .qe (),
8164 .q (reg2hw.cmd_filter[191].q),
8165 .ds (),
8166
8167 // to register interface (read)
8168 .qs (cmd_filter_5_filter_191_qs)
8169 );
8170
8171
8172 // Subregister 6 of Multireg cmd_filter
8173 // R[cmd_filter_6]: V(False)
8174 // F[filter_192]: 0:0
8175 prim_subreg #(
8176 .DW (1),
8177 .SwAccess(prim_subreg_pkg::SwAccessRW),
8178 .RESVAL (1'h0),
8179 .Mubi (1'b0)
8180 ) u_cmd_filter_6_filter_192 (
8181 .clk_i (clk_i),
8182 .rst_ni (rst_ni),
8183
8184 // from register interface
8185 .we (cmd_filter_6_we),
8186 .wd (cmd_filter_6_filter_192_wd),
8187
8188 // from internal hardware
8189 .de (1'b0),
8190 .d ('0),
8191
8192 // to internal hardware
8193 .qe (),
8194 .q (reg2hw.cmd_filter[192].q),
8195 .ds (),
8196
8197 // to register interface (read)
8198 .qs (cmd_filter_6_filter_192_qs)
8199 );
8200
8201 // F[filter_193]: 1:1
8202 prim_subreg #(
8203 .DW (1),
8204 .SwAccess(prim_subreg_pkg::SwAccessRW),
8205 .RESVAL (1'h0),
8206 .Mubi (1'b0)
8207 ) u_cmd_filter_6_filter_193 (
8208 .clk_i (clk_i),
8209 .rst_ni (rst_ni),
8210
8211 // from register interface
8212 .we (cmd_filter_6_we),
8213 .wd (cmd_filter_6_filter_193_wd),
8214
8215 // from internal hardware
8216 .de (1'b0),
8217 .d ('0),
8218
8219 // to internal hardware
8220 .qe (),
8221 .q (reg2hw.cmd_filter[193].q),
8222 .ds (),
8223
8224 // to register interface (read)
8225 .qs (cmd_filter_6_filter_193_qs)
8226 );
8227
8228 // F[filter_194]: 2:2
8229 prim_subreg #(
8230 .DW (1),
8231 .SwAccess(prim_subreg_pkg::SwAccessRW),
8232 .RESVAL (1'h0),
8233 .Mubi (1'b0)
8234 ) u_cmd_filter_6_filter_194 (
8235 .clk_i (clk_i),
8236 .rst_ni (rst_ni),
8237
8238 // from register interface
8239 .we (cmd_filter_6_we),
8240 .wd (cmd_filter_6_filter_194_wd),
8241
8242 // from internal hardware
8243 .de (1'b0),
8244 .d ('0),
8245
8246 // to internal hardware
8247 .qe (),
8248 .q (reg2hw.cmd_filter[194].q),
8249 .ds (),
8250
8251 // to register interface (read)
8252 .qs (cmd_filter_6_filter_194_qs)
8253 );
8254
8255 // F[filter_195]: 3:3
8256 prim_subreg #(
8257 .DW (1),
8258 .SwAccess(prim_subreg_pkg::SwAccessRW),
8259 .RESVAL (1'h0),
8260 .Mubi (1'b0)
8261 ) u_cmd_filter_6_filter_195 (
8262 .clk_i (clk_i),
8263 .rst_ni (rst_ni),
8264
8265 // from register interface
8266 .we (cmd_filter_6_we),
8267 .wd (cmd_filter_6_filter_195_wd),
8268
8269 // from internal hardware
8270 .de (1'b0),
8271 .d ('0),
8272
8273 // to internal hardware
8274 .qe (),
8275 .q (reg2hw.cmd_filter[195].q),
8276 .ds (),
8277
8278 // to register interface (read)
8279 .qs (cmd_filter_6_filter_195_qs)
8280 );
8281
8282 // F[filter_196]: 4:4
8283 prim_subreg #(
8284 .DW (1),
8285 .SwAccess(prim_subreg_pkg::SwAccessRW),
8286 .RESVAL (1'h0),
8287 .Mubi (1'b0)
8288 ) u_cmd_filter_6_filter_196 (
8289 .clk_i (clk_i),
8290 .rst_ni (rst_ni),
8291
8292 // from register interface
8293 .we (cmd_filter_6_we),
8294 .wd (cmd_filter_6_filter_196_wd),
8295
8296 // from internal hardware
8297 .de (1'b0),
8298 .d ('0),
8299
8300 // to internal hardware
8301 .qe (),
8302 .q (reg2hw.cmd_filter[196].q),
8303 .ds (),
8304
8305 // to register interface (read)
8306 .qs (cmd_filter_6_filter_196_qs)
8307 );
8308
8309 // F[filter_197]: 5:5
8310 prim_subreg #(
8311 .DW (1),
8312 .SwAccess(prim_subreg_pkg::SwAccessRW),
8313 .RESVAL (1'h0),
8314 .Mubi (1'b0)
8315 ) u_cmd_filter_6_filter_197 (
8316 .clk_i (clk_i),
8317 .rst_ni (rst_ni),
8318
8319 // from register interface
8320 .we (cmd_filter_6_we),
8321 .wd (cmd_filter_6_filter_197_wd),
8322
8323 // from internal hardware
8324 .de (1'b0),
8325 .d ('0),
8326
8327 // to internal hardware
8328 .qe (),
8329 .q (reg2hw.cmd_filter[197].q),
8330 .ds (),
8331
8332 // to register interface (read)
8333 .qs (cmd_filter_6_filter_197_qs)
8334 );
8335
8336 // F[filter_198]: 6:6
8337 prim_subreg #(
8338 .DW (1),
8339 .SwAccess(prim_subreg_pkg::SwAccessRW),
8340 .RESVAL (1'h0),
8341 .Mubi (1'b0)
8342 ) u_cmd_filter_6_filter_198 (
8343 .clk_i (clk_i),
8344 .rst_ni (rst_ni),
8345
8346 // from register interface
8347 .we (cmd_filter_6_we),
8348 .wd (cmd_filter_6_filter_198_wd),
8349
8350 // from internal hardware
8351 .de (1'b0),
8352 .d ('0),
8353
8354 // to internal hardware
8355 .qe (),
8356 .q (reg2hw.cmd_filter[198].q),
8357 .ds (),
8358
8359 // to register interface (read)
8360 .qs (cmd_filter_6_filter_198_qs)
8361 );
8362
8363 // F[filter_199]: 7:7
8364 prim_subreg #(
8365 .DW (1),
8366 .SwAccess(prim_subreg_pkg::SwAccessRW),
8367 .RESVAL (1'h0),
8368 .Mubi (1'b0)
8369 ) u_cmd_filter_6_filter_199 (
8370 .clk_i (clk_i),
8371 .rst_ni (rst_ni),
8372
8373 // from register interface
8374 .we (cmd_filter_6_we),
8375 .wd (cmd_filter_6_filter_199_wd),
8376
8377 // from internal hardware
8378 .de (1'b0),
8379 .d ('0),
8380
8381 // to internal hardware
8382 .qe (),
8383 .q (reg2hw.cmd_filter[199].q),
8384 .ds (),
8385
8386 // to register interface (read)
8387 .qs (cmd_filter_6_filter_199_qs)
8388 );
8389
8390 // F[filter_200]: 8:8
8391 prim_subreg #(
8392 .DW (1),
8393 .SwAccess(prim_subreg_pkg::SwAccessRW),
8394 .RESVAL (1'h0),
8395 .Mubi (1'b0)
8396 ) u_cmd_filter_6_filter_200 (
8397 .clk_i (clk_i),
8398 .rst_ni (rst_ni),
8399
8400 // from register interface
8401 .we (cmd_filter_6_we),
8402 .wd (cmd_filter_6_filter_200_wd),
8403
8404 // from internal hardware
8405 .de (1'b0),
8406 .d ('0),
8407
8408 // to internal hardware
8409 .qe (),
8410 .q (reg2hw.cmd_filter[200].q),
8411 .ds (),
8412
8413 // to register interface (read)
8414 .qs (cmd_filter_6_filter_200_qs)
8415 );
8416
8417 // F[filter_201]: 9:9
8418 prim_subreg #(
8419 .DW (1),
8420 .SwAccess(prim_subreg_pkg::SwAccessRW),
8421 .RESVAL (1'h0),
8422 .Mubi (1'b0)
8423 ) u_cmd_filter_6_filter_201 (
8424 .clk_i (clk_i),
8425 .rst_ni (rst_ni),
8426
8427 // from register interface
8428 .we (cmd_filter_6_we),
8429 .wd (cmd_filter_6_filter_201_wd),
8430
8431 // from internal hardware
8432 .de (1'b0),
8433 .d ('0),
8434
8435 // to internal hardware
8436 .qe (),
8437 .q (reg2hw.cmd_filter[201].q),
8438 .ds (),
8439
8440 // to register interface (read)
8441 .qs (cmd_filter_6_filter_201_qs)
8442 );
8443
8444 // F[filter_202]: 10:10
8445 prim_subreg #(
8446 .DW (1),
8447 .SwAccess(prim_subreg_pkg::SwAccessRW),
8448 .RESVAL (1'h0),
8449 .Mubi (1'b0)
8450 ) u_cmd_filter_6_filter_202 (
8451 .clk_i (clk_i),
8452 .rst_ni (rst_ni),
8453
8454 // from register interface
8455 .we (cmd_filter_6_we),
8456 .wd (cmd_filter_6_filter_202_wd),
8457
8458 // from internal hardware
8459 .de (1'b0),
8460 .d ('0),
8461
8462 // to internal hardware
8463 .qe (),
8464 .q (reg2hw.cmd_filter[202].q),
8465 .ds (),
8466
8467 // to register interface (read)
8468 .qs (cmd_filter_6_filter_202_qs)
8469 );
8470
8471 // F[filter_203]: 11:11
8472 prim_subreg #(
8473 .DW (1),
8474 .SwAccess(prim_subreg_pkg::SwAccessRW),
8475 .RESVAL (1'h0),
8476 .Mubi (1'b0)
8477 ) u_cmd_filter_6_filter_203 (
8478 .clk_i (clk_i),
8479 .rst_ni (rst_ni),
8480
8481 // from register interface
8482 .we (cmd_filter_6_we),
8483 .wd (cmd_filter_6_filter_203_wd),
8484
8485 // from internal hardware
8486 .de (1'b0),
8487 .d ('0),
8488
8489 // to internal hardware
8490 .qe (),
8491 .q (reg2hw.cmd_filter[203].q),
8492 .ds (),
8493
8494 // to register interface (read)
8495 .qs (cmd_filter_6_filter_203_qs)
8496 );
8497
8498 // F[filter_204]: 12:12
8499 prim_subreg #(
8500 .DW (1),
8501 .SwAccess(prim_subreg_pkg::SwAccessRW),
8502 .RESVAL (1'h0),
8503 .Mubi (1'b0)
8504 ) u_cmd_filter_6_filter_204 (
8505 .clk_i (clk_i),
8506 .rst_ni (rst_ni),
8507
8508 // from register interface
8509 .we (cmd_filter_6_we),
8510 .wd (cmd_filter_6_filter_204_wd),
8511
8512 // from internal hardware
8513 .de (1'b0),
8514 .d ('0),
8515
8516 // to internal hardware
8517 .qe (),
8518 .q (reg2hw.cmd_filter[204].q),
8519 .ds (),
8520
8521 // to register interface (read)
8522 .qs (cmd_filter_6_filter_204_qs)
8523 );
8524
8525 // F[filter_205]: 13:13
8526 prim_subreg #(
8527 .DW (1),
8528 .SwAccess(prim_subreg_pkg::SwAccessRW),
8529 .RESVAL (1'h0),
8530 .Mubi (1'b0)
8531 ) u_cmd_filter_6_filter_205 (
8532 .clk_i (clk_i),
8533 .rst_ni (rst_ni),
8534
8535 // from register interface
8536 .we (cmd_filter_6_we),
8537 .wd (cmd_filter_6_filter_205_wd),
8538
8539 // from internal hardware
8540 .de (1'b0),
8541 .d ('0),
8542
8543 // to internal hardware
8544 .qe (),
8545 .q (reg2hw.cmd_filter[205].q),
8546 .ds (),
8547
8548 // to register interface (read)
8549 .qs (cmd_filter_6_filter_205_qs)
8550 );
8551
8552 // F[filter_206]: 14:14
8553 prim_subreg #(
8554 .DW (1),
8555 .SwAccess(prim_subreg_pkg::SwAccessRW),
8556 .RESVAL (1'h0),
8557 .Mubi (1'b0)
8558 ) u_cmd_filter_6_filter_206 (
8559 .clk_i (clk_i),
8560 .rst_ni (rst_ni),
8561
8562 // from register interface
8563 .we (cmd_filter_6_we),
8564 .wd (cmd_filter_6_filter_206_wd),
8565
8566 // from internal hardware
8567 .de (1'b0),
8568 .d ('0),
8569
8570 // to internal hardware
8571 .qe (),
8572 .q (reg2hw.cmd_filter[206].q),
8573 .ds (),
8574
8575 // to register interface (read)
8576 .qs (cmd_filter_6_filter_206_qs)
8577 );
8578
8579 // F[filter_207]: 15:15
8580 prim_subreg #(
8581 .DW (1),
8582 .SwAccess(prim_subreg_pkg::SwAccessRW),
8583 .RESVAL (1'h0),
8584 .Mubi (1'b0)
8585 ) u_cmd_filter_6_filter_207 (
8586 .clk_i (clk_i),
8587 .rst_ni (rst_ni),
8588
8589 // from register interface
8590 .we (cmd_filter_6_we),
8591 .wd (cmd_filter_6_filter_207_wd),
8592
8593 // from internal hardware
8594 .de (1'b0),
8595 .d ('0),
8596
8597 // to internal hardware
8598 .qe (),
8599 .q (reg2hw.cmd_filter[207].q),
8600 .ds (),
8601
8602 // to register interface (read)
8603 .qs (cmd_filter_6_filter_207_qs)
8604 );
8605
8606 // F[filter_208]: 16:16
8607 prim_subreg #(
8608 .DW (1),
8609 .SwAccess(prim_subreg_pkg::SwAccessRW),
8610 .RESVAL (1'h0),
8611 .Mubi (1'b0)
8612 ) u_cmd_filter_6_filter_208 (
8613 .clk_i (clk_i),
8614 .rst_ni (rst_ni),
8615
8616 // from register interface
8617 .we (cmd_filter_6_we),
8618 .wd (cmd_filter_6_filter_208_wd),
8619
8620 // from internal hardware
8621 .de (1'b0),
8622 .d ('0),
8623
8624 // to internal hardware
8625 .qe (),
8626 .q (reg2hw.cmd_filter[208].q),
8627 .ds (),
8628
8629 // to register interface (read)
8630 .qs (cmd_filter_6_filter_208_qs)
8631 );
8632
8633 // F[filter_209]: 17:17
8634 prim_subreg #(
8635 .DW (1),
8636 .SwAccess(prim_subreg_pkg::SwAccessRW),
8637 .RESVAL (1'h0),
8638 .Mubi (1'b0)
8639 ) u_cmd_filter_6_filter_209 (
8640 .clk_i (clk_i),
8641 .rst_ni (rst_ni),
8642
8643 // from register interface
8644 .we (cmd_filter_6_we),
8645 .wd (cmd_filter_6_filter_209_wd),
8646
8647 // from internal hardware
8648 .de (1'b0),
8649 .d ('0),
8650
8651 // to internal hardware
8652 .qe (),
8653 .q (reg2hw.cmd_filter[209].q),
8654 .ds (),
8655
8656 // to register interface (read)
8657 .qs (cmd_filter_6_filter_209_qs)
8658 );
8659
8660 // F[filter_210]: 18:18
8661 prim_subreg #(
8662 .DW (1),
8663 .SwAccess(prim_subreg_pkg::SwAccessRW),
8664 .RESVAL (1'h0),
8665 .Mubi (1'b0)
8666 ) u_cmd_filter_6_filter_210 (
8667 .clk_i (clk_i),
8668 .rst_ni (rst_ni),
8669
8670 // from register interface
8671 .we (cmd_filter_6_we),
8672 .wd (cmd_filter_6_filter_210_wd),
8673
8674 // from internal hardware
8675 .de (1'b0),
8676 .d ('0),
8677
8678 // to internal hardware
8679 .qe (),
8680 .q (reg2hw.cmd_filter[210].q),
8681 .ds (),
8682
8683 // to register interface (read)
8684 .qs (cmd_filter_6_filter_210_qs)
8685 );
8686
8687 // F[filter_211]: 19:19
8688 prim_subreg #(
8689 .DW (1),
8690 .SwAccess(prim_subreg_pkg::SwAccessRW),
8691 .RESVAL (1'h0),
8692 .Mubi (1'b0)
8693 ) u_cmd_filter_6_filter_211 (
8694 .clk_i (clk_i),
8695 .rst_ni (rst_ni),
8696
8697 // from register interface
8698 .we (cmd_filter_6_we),
8699 .wd (cmd_filter_6_filter_211_wd),
8700
8701 // from internal hardware
8702 .de (1'b0),
8703 .d ('0),
8704
8705 // to internal hardware
8706 .qe (),
8707 .q (reg2hw.cmd_filter[211].q),
8708 .ds (),
8709
8710 // to register interface (read)
8711 .qs (cmd_filter_6_filter_211_qs)
8712 );
8713
8714 // F[filter_212]: 20:20
8715 prim_subreg #(
8716 .DW (1),
8717 .SwAccess(prim_subreg_pkg::SwAccessRW),
8718 .RESVAL (1'h0),
8719 .Mubi (1'b0)
8720 ) u_cmd_filter_6_filter_212 (
8721 .clk_i (clk_i),
8722 .rst_ni (rst_ni),
8723
8724 // from register interface
8725 .we (cmd_filter_6_we),
8726 .wd (cmd_filter_6_filter_212_wd),
8727
8728 // from internal hardware
8729 .de (1'b0),
8730 .d ('0),
8731
8732 // to internal hardware
8733 .qe (),
8734 .q (reg2hw.cmd_filter[212].q),
8735 .ds (),
8736
8737 // to register interface (read)
8738 .qs (cmd_filter_6_filter_212_qs)
8739 );
8740
8741 // F[filter_213]: 21:21
8742 prim_subreg #(
8743 .DW (1),
8744 .SwAccess(prim_subreg_pkg::SwAccessRW),
8745 .RESVAL (1'h0),
8746 .Mubi (1'b0)
8747 ) u_cmd_filter_6_filter_213 (
8748 .clk_i (clk_i),
8749 .rst_ni (rst_ni),
8750
8751 // from register interface
8752 .we (cmd_filter_6_we),
8753 .wd (cmd_filter_6_filter_213_wd),
8754
8755 // from internal hardware
8756 .de (1'b0),
8757 .d ('0),
8758
8759 // to internal hardware
8760 .qe (),
8761 .q (reg2hw.cmd_filter[213].q),
8762 .ds (),
8763
8764 // to register interface (read)
8765 .qs (cmd_filter_6_filter_213_qs)
8766 );
8767
8768 // F[filter_214]: 22:22
8769 prim_subreg #(
8770 .DW (1),
8771 .SwAccess(prim_subreg_pkg::SwAccessRW),
8772 .RESVAL (1'h0),
8773 .Mubi (1'b0)
8774 ) u_cmd_filter_6_filter_214 (
8775 .clk_i (clk_i),
8776 .rst_ni (rst_ni),
8777
8778 // from register interface
8779 .we (cmd_filter_6_we),
8780 .wd (cmd_filter_6_filter_214_wd),
8781
8782 // from internal hardware
8783 .de (1'b0),
8784 .d ('0),
8785
8786 // to internal hardware
8787 .qe (),
8788 .q (reg2hw.cmd_filter[214].q),
8789 .ds (),
8790
8791 // to register interface (read)
8792 .qs (cmd_filter_6_filter_214_qs)
8793 );
8794
8795 // F[filter_215]: 23:23
8796 prim_subreg #(
8797 .DW (1),
8798 .SwAccess(prim_subreg_pkg::SwAccessRW),
8799 .RESVAL (1'h0),
8800 .Mubi (1'b0)
8801 ) u_cmd_filter_6_filter_215 (
8802 .clk_i (clk_i),
8803 .rst_ni (rst_ni),
8804
8805 // from register interface
8806 .we (cmd_filter_6_we),
8807 .wd (cmd_filter_6_filter_215_wd),
8808
8809 // from internal hardware
8810 .de (1'b0),
8811 .d ('0),
8812
8813 // to internal hardware
8814 .qe (),
8815 .q (reg2hw.cmd_filter[215].q),
8816 .ds (),
8817
8818 // to register interface (read)
8819 .qs (cmd_filter_6_filter_215_qs)
8820 );
8821
8822 // F[filter_216]: 24:24
8823 prim_subreg #(
8824 .DW (1),
8825 .SwAccess(prim_subreg_pkg::SwAccessRW),
8826 .RESVAL (1'h0),
8827 .Mubi (1'b0)
8828 ) u_cmd_filter_6_filter_216 (
8829 .clk_i (clk_i),
8830 .rst_ni (rst_ni),
8831
8832 // from register interface
8833 .we (cmd_filter_6_we),
8834 .wd (cmd_filter_6_filter_216_wd),
8835
8836 // from internal hardware
8837 .de (1'b0),
8838 .d ('0),
8839
8840 // to internal hardware
8841 .qe (),
8842 .q (reg2hw.cmd_filter[216].q),
8843 .ds (),
8844
8845 // to register interface (read)
8846 .qs (cmd_filter_6_filter_216_qs)
8847 );
8848
8849 // F[filter_217]: 25:25
8850 prim_subreg #(
8851 .DW (1),
8852 .SwAccess(prim_subreg_pkg::SwAccessRW),
8853 .RESVAL (1'h0),
8854 .Mubi (1'b0)
8855 ) u_cmd_filter_6_filter_217 (
8856 .clk_i (clk_i),
8857 .rst_ni (rst_ni),
8858
8859 // from register interface
8860 .we (cmd_filter_6_we),
8861 .wd (cmd_filter_6_filter_217_wd),
8862
8863 // from internal hardware
8864 .de (1'b0),
8865 .d ('0),
8866
8867 // to internal hardware
8868 .qe (),
8869 .q (reg2hw.cmd_filter[217].q),
8870 .ds (),
8871
8872 // to register interface (read)
8873 .qs (cmd_filter_6_filter_217_qs)
8874 );
8875
8876 // F[filter_218]: 26:26
8877 prim_subreg #(
8878 .DW (1),
8879 .SwAccess(prim_subreg_pkg::SwAccessRW),
8880 .RESVAL (1'h0),
8881 .Mubi (1'b0)
8882 ) u_cmd_filter_6_filter_218 (
8883 .clk_i (clk_i),
8884 .rst_ni (rst_ni),
8885
8886 // from register interface
8887 .we (cmd_filter_6_we),
8888 .wd (cmd_filter_6_filter_218_wd),
8889
8890 // from internal hardware
8891 .de (1'b0),
8892 .d ('0),
8893
8894 // to internal hardware
8895 .qe (),
8896 .q (reg2hw.cmd_filter[218].q),
8897 .ds (),
8898
8899 // to register interface (read)
8900 .qs (cmd_filter_6_filter_218_qs)
8901 );
8902
8903 // F[filter_219]: 27:27
8904 prim_subreg #(
8905 .DW (1),
8906 .SwAccess(prim_subreg_pkg::SwAccessRW),
8907 .RESVAL (1'h0),
8908 .Mubi (1'b0)
8909 ) u_cmd_filter_6_filter_219 (
8910 .clk_i (clk_i),
8911 .rst_ni (rst_ni),
8912
8913 // from register interface
8914 .we (cmd_filter_6_we),
8915 .wd (cmd_filter_6_filter_219_wd),
8916
8917 // from internal hardware
8918 .de (1'b0),
8919 .d ('0),
8920
8921 // to internal hardware
8922 .qe (),
8923 .q (reg2hw.cmd_filter[219].q),
8924 .ds (),
8925
8926 // to register interface (read)
8927 .qs (cmd_filter_6_filter_219_qs)
8928 );
8929
8930 // F[filter_220]: 28:28
8931 prim_subreg #(
8932 .DW (1),
8933 .SwAccess(prim_subreg_pkg::SwAccessRW),
8934 .RESVAL (1'h0),
8935 .Mubi (1'b0)
8936 ) u_cmd_filter_6_filter_220 (
8937 .clk_i (clk_i),
8938 .rst_ni (rst_ni),
8939
8940 // from register interface
8941 .we (cmd_filter_6_we),
8942 .wd (cmd_filter_6_filter_220_wd),
8943
8944 // from internal hardware
8945 .de (1'b0),
8946 .d ('0),
8947
8948 // to internal hardware
8949 .qe (),
8950 .q (reg2hw.cmd_filter[220].q),
8951 .ds (),
8952
8953 // to register interface (read)
8954 .qs (cmd_filter_6_filter_220_qs)
8955 );
8956
8957 // F[filter_221]: 29:29
8958 prim_subreg #(
8959 .DW (1),
8960 .SwAccess(prim_subreg_pkg::SwAccessRW),
8961 .RESVAL (1'h0),
8962 .Mubi (1'b0)
8963 ) u_cmd_filter_6_filter_221 (
8964 .clk_i (clk_i),
8965 .rst_ni (rst_ni),
8966
8967 // from register interface
8968 .we (cmd_filter_6_we),
8969 .wd (cmd_filter_6_filter_221_wd),
8970
8971 // from internal hardware
8972 .de (1'b0),
8973 .d ('0),
8974
8975 // to internal hardware
8976 .qe (),
8977 .q (reg2hw.cmd_filter[221].q),
8978 .ds (),
8979
8980 // to register interface (read)
8981 .qs (cmd_filter_6_filter_221_qs)
8982 );
8983
8984 // F[filter_222]: 30:30
8985 prim_subreg #(
8986 .DW (1),
8987 .SwAccess(prim_subreg_pkg::SwAccessRW),
8988 .RESVAL (1'h0),
8989 .Mubi (1'b0)
8990 ) u_cmd_filter_6_filter_222 (
8991 .clk_i (clk_i),
8992 .rst_ni (rst_ni),
8993
8994 // from register interface
8995 .we (cmd_filter_6_we),
8996 .wd (cmd_filter_6_filter_222_wd),
8997
8998 // from internal hardware
8999 .de (1'b0),
9000 .d ('0),
9001
9002 // to internal hardware
9003 .qe (),
9004 .q (reg2hw.cmd_filter[222].q),
9005 .ds (),
9006
9007 // to register interface (read)
9008 .qs (cmd_filter_6_filter_222_qs)
9009 );
9010
9011 // F[filter_223]: 31:31
9012 prim_subreg #(
9013 .DW (1),
9014 .SwAccess(prim_subreg_pkg::SwAccessRW),
9015 .RESVAL (1'h0),
9016 .Mubi (1'b0)
9017 ) u_cmd_filter_6_filter_223 (
9018 .clk_i (clk_i),
9019 .rst_ni (rst_ni),
9020
9021 // from register interface
9022 .we (cmd_filter_6_we),
9023 .wd (cmd_filter_6_filter_223_wd),
9024
9025 // from internal hardware
9026 .de (1'b0),
9027 .d ('0),
9028
9029 // to internal hardware
9030 .qe (),
9031 .q (reg2hw.cmd_filter[223].q),
9032 .ds (),
9033
9034 // to register interface (read)
9035 .qs (cmd_filter_6_filter_223_qs)
9036 );
9037
9038
9039 // Subregister 7 of Multireg cmd_filter
9040 // R[cmd_filter_7]: V(False)
9041 // F[filter_224]: 0:0
9042 prim_subreg #(
9043 .DW (1),
9044 .SwAccess(prim_subreg_pkg::SwAccessRW),
9045 .RESVAL (1'h0),
9046 .Mubi (1'b0)
9047 ) u_cmd_filter_7_filter_224 (
9048 .clk_i (clk_i),
9049 .rst_ni (rst_ni),
9050
9051 // from register interface
9052 .we (cmd_filter_7_we),
9053 .wd (cmd_filter_7_filter_224_wd),
9054
9055 // from internal hardware
9056 .de (1'b0),
9057 .d ('0),
9058
9059 // to internal hardware
9060 .qe (),
9061 .q (reg2hw.cmd_filter[224].q),
9062 .ds (),
9063
9064 // to register interface (read)
9065 .qs (cmd_filter_7_filter_224_qs)
9066 );
9067
9068 // F[filter_225]: 1:1
9069 prim_subreg #(
9070 .DW (1),
9071 .SwAccess(prim_subreg_pkg::SwAccessRW),
9072 .RESVAL (1'h0),
9073 .Mubi (1'b0)
9074 ) u_cmd_filter_7_filter_225 (
9075 .clk_i (clk_i),
9076 .rst_ni (rst_ni),
9077
9078 // from register interface
9079 .we (cmd_filter_7_we),
9080 .wd (cmd_filter_7_filter_225_wd),
9081
9082 // from internal hardware
9083 .de (1'b0),
9084 .d ('0),
9085
9086 // to internal hardware
9087 .qe (),
9088 .q (reg2hw.cmd_filter[225].q),
9089 .ds (),
9090
9091 // to register interface (read)
9092 .qs (cmd_filter_7_filter_225_qs)
9093 );
9094
9095 // F[filter_226]: 2:2
9096 prim_subreg #(
9097 .DW (1),
9098 .SwAccess(prim_subreg_pkg::SwAccessRW),
9099 .RESVAL (1'h0),
9100 .Mubi (1'b0)
9101 ) u_cmd_filter_7_filter_226 (
9102 .clk_i (clk_i),
9103 .rst_ni (rst_ni),
9104
9105 // from register interface
9106 .we (cmd_filter_7_we),
9107 .wd (cmd_filter_7_filter_226_wd),
9108
9109 // from internal hardware
9110 .de (1'b0),
9111 .d ('0),
9112
9113 // to internal hardware
9114 .qe (),
9115 .q (reg2hw.cmd_filter[226].q),
9116 .ds (),
9117
9118 // to register interface (read)
9119 .qs (cmd_filter_7_filter_226_qs)
9120 );
9121
9122 // F[filter_227]: 3:3
9123 prim_subreg #(
9124 .DW (1),
9125 .SwAccess(prim_subreg_pkg::SwAccessRW),
9126 .RESVAL (1'h0),
9127 .Mubi (1'b0)
9128 ) u_cmd_filter_7_filter_227 (
9129 .clk_i (clk_i),
9130 .rst_ni (rst_ni),
9131
9132 // from register interface
9133 .we (cmd_filter_7_we),
9134 .wd (cmd_filter_7_filter_227_wd),
9135
9136 // from internal hardware
9137 .de (1'b0),
9138 .d ('0),
9139
9140 // to internal hardware
9141 .qe (),
9142 .q (reg2hw.cmd_filter[227].q),
9143 .ds (),
9144
9145 // to register interface (read)
9146 .qs (cmd_filter_7_filter_227_qs)
9147 );
9148
9149 // F[filter_228]: 4:4
9150 prim_subreg #(
9151 .DW (1),
9152 .SwAccess(prim_subreg_pkg::SwAccessRW),
9153 .RESVAL (1'h0),
9154 .Mubi (1'b0)
9155 ) u_cmd_filter_7_filter_228 (
9156 .clk_i (clk_i),
9157 .rst_ni (rst_ni),
9158
9159 // from register interface
9160 .we (cmd_filter_7_we),
9161 .wd (cmd_filter_7_filter_228_wd),
9162
9163 // from internal hardware
9164 .de (1'b0),
9165 .d ('0),
9166
9167 // to internal hardware
9168 .qe (),
9169 .q (reg2hw.cmd_filter[228].q),
9170 .ds (),
9171
9172 // to register interface (read)
9173 .qs (cmd_filter_7_filter_228_qs)
9174 );
9175
9176 // F[filter_229]: 5:5
9177 prim_subreg #(
9178 .DW (1),
9179 .SwAccess(prim_subreg_pkg::SwAccessRW),
9180 .RESVAL (1'h0),
9181 .Mubi (1'b0)
9182 ) u_cmd_filter_7_filter_229 (
9183 .clk_i (clk_i),
9184 .rst_ni (rst_ni),
9185
9186 // from register interface
9187 .we (cmd_filter_7_we),
9188 .wd (cmd_filter_7_filter_229_wd),
9189
9190 // from internal hardware
9191 .de (1'b0),
9192 .d ('0),
9193
9194 // to internal hardware
9195 .qe (),
9196 .q (reg2hw.cmd_filter[229].q),
9197 .ds (),
9198
9199 // to register interface (read)
9200 .qs (cmd_filter_7_filter_229_qs)
9201 );
9202
9203 // F[filter_230]: 6:6
9204 prim_subreg #(
9205 .DW (1),
9206 .SwAccess(prim_subreg_pkg::SwAccessRW),
9207 .RESVAL (1'h0),
9208 .Mubi (1'b0)
9209 ) u_cmd_filter_7_filter_230 (
9210 .clk_i (clk_i),
9211 .rst_ni (rst_ni),
9212
9213 // from register interface
9214 .we (cmd_filter_7_we),
9215 .wd (cmd_filter_7_filter_230_wd),
9216
9217 // from internal hardware
9218 .de (1'b0),
9219 .d ('0),
9220
9221 // to internal hardware
9222 .qe (),
9223 .q (reg2hw.cmd_filter[230].q),
9224 .ds (),
9225
9226 // to register interface (read)
9227 .qs (cmd_filter_7_filter_230_qs)
9228 );
9229
9230 // F[filter_231]: 7:7
9231 prim_subreg #(
9232 .DW (1),
9233 .SwAccess(prim_subreg_pkg::SwAccessRW),
9234 .RESVAL (1'h0),
9235 .Mubi (1'b0)
9236 ) u_cmd_filter_7_filter_231 (
9237 .clk_i (clk_i),
9238 .rst_ni (rst_ni),
9239
9240 // from register interface
9241 .we (cmd_filter_7_we),
9242 .wd (cmd_filter_7_filter_231_wd),
9243
9244 // from internal hardware
9245 .de (1'b0),
9246 .d ('0),
9247
9248 // to internal hardware
9249 .qe (),
9250 .q (reg2hw.cmd_filter[231].q),
9251 .ds (),
9252
9253 // to register interface (read)
9254 .qs (cmd_filter_7_filter_231_qs)
9255 );
9256
9257 // F[filter_232]: 8:8
9258 prim_subreg #(
9259 .DW (1),
9260 .SwAccess(prim_subreg_pkg::SwAccessRW),
9261 .RESVAL (1'h0),
9262 .Mubi (1'b0)
9263 ) u_cmd_filter_7_filter_232 (
9264 .clk_i (clk_i),
9265 .rst_ni (rst_ni),
9266
9267 // from register interface
9268 .we (cmd_filter_7_we),
9269 .wd (cmd_filter_7_filter_232_wd),
9270
9271 // from internal hardware
9272 .de (1'b0),
9273 .d ('0),
9274
9275 // to internal hardware
9276 .qe (),
9277 .q (reg2hw.cmd_filter[232].q),
9278 .ds (),
9279
9280 // to register interface (read)
9281 .qs (cmd_filter_7_filter_232_qs)
9282 );
9283
9284 // F[filter_233]: 9:9
9285 prim_subreg #(
9286 .DW (1),
9287 .SwAccess(prim_subreg_pkg::SwAccessRW),
9288 .RESVAL (1'h0),
9289 .Mubi (1'b0)
9290 ) u_cmd_filter_7_filter_233 (
9291 .clk_i (clk_i),
9292 .rst_ni (rst_ni),
9293
9294 // from register interface
9295 .we (cmd_filter_7_we),
9296 .wd (cmd_filter_7_filter_233_wd),
9297
9298 // from internal hardware
9299 .de (1'b0),
9300 .d ('0),
9301
9302 // to internal hardware
9303 .qe (),
9304 .q (reg2hw.cmd_filter[233].q),
9305 .ds (),
9306
9307 // to register interface (read)
9308 .qs (cmd_filter_7_filter_233_qs)
9309 );
9310
9311 // F[filter_234]: 10:10
9312 prim_subreg #(
9313 .DW (1),
9314 .SwAccess(prim_subreg_pkg::SwAccessRW),
9315 .RESVAL (1'h0),
9316 .Mubi (1'b0)
9317 ) u_cmd_filter_7_filter_234 (
9318 .clk_i (clk_i),
9319 .rst_ni (rst_ni),
9320
9321 // from register interface
9322 .we (cmd_filter_7_we),
9323 .wd (cmd_filter_7_filter_234_wd),
9324
9325 // from internal hardware
9326 .de (1'b0),
9327 .d ('0),
9328
9329 // to internal hardware
9330 .qe (),
9331 .q (reg2hw.cmd_filter[234].q),
9332 .ds (),
9333
9334 // to register interface (read)
9335 .qs (cmd_filter_7_filter_234_qs)
9336 );
9337
9338 // F[filter_235]: 11:11
9339 prim_subreg #(
9340 .DW (1),
9341 .SwAccess(prim_subreg_pkg::SwAccessRW),
9342 .RESVAL (1'h0),
9343 .Mubi (1'b0)
9344 ) u_cmd_filter_7_filter_235 (
9345 .clk_i (clk_i),
9346 .rst_ni (rst_ni),
9347
9348 // from register interface
9349 .we (cmd_filter_7_we),
9350 .wd (cmd_filter_7_filter_235_wd),
9351
9352 // from internal hardware
9353 .de (1'b0),
9354 .d ('0),
9355
9356 // to internal hardware
9357 .qe (),
9358 .q (reg2hw.cmd_filter[235].q),
9359 .ds (),
9360
9361 // to register interface (read)
9362 .qs (cmd_filter_7_filter_235_qs)
9363 );
9364
9365 // F[filter_236]: 12:12
9366 prim_subreg #(
9367 .DW (1),
9368 .SwAccess(prim_subreg_pkg::SwAccessRW),
9369 .RESVAL (1'h0),
9370 .Mubi (1'b0)
9371 ) u_cmd_filter_7_filter_236 (
9372 .clk_i (clk_i),
9373 .rst_ni (rst_ni),
9374
9375 // from register interface
9376 .we (cmd_filter_7_we),
9377 .wd (cmd_filter_7_filter_236_wd),
9378
9379 // from internal hardware
9380 .de (1'b0),
9381 .d ('0),
9382
9383 // to internal hardware
9384 .qe (),
9385 .q (reg2hw.cmd_filter[236].q),
9386 .ds (),
9387
9388 // to register interface (read)
9389 .qs (cmd_filter_7_filter_236_qs)
9390 );
9391
9392 // F[filter_237]: 13:13
9393 prim_subreg #(
9394 .DW (1),
9395 .SwAccess(prim_subreg_pkg::SwAccessRW),
9396 .RESVAL (1'h0),
9397 .Mubi (1'b0)
9398 ) u_cmd_filter_7_filter_237 (
9399 .clk_i (clk_i),
9400 .rst_ni (rst_ni),
9401
9402 // from register interface
9403 .we (cmd_filter_7_we),
9404 .wd (cmd_filter_7_filter_237_wd),
9405
9406 // from internal hardware
9407 .de (1'b0),
9408 .d ('0),
9409
9410 // to internal hardware
9411 .qe (),
9412 .q (reg2hw.cmd_filter[237].q),
9413 .ds (),
9414
9415 // to register interface (read)
9416 .qs (cmd_filter_7_filter_237_qs)
9417 );
9418
9419 // F[filter_238]: 14:14
9420 prim_subreg #(
9421 .DW (1),
9422 .SwAccess(prim_subreg_pkg::SwAccessRW),
9423 .RESVAL (1'h0),
9424 .Mubi (1'b0)
9425 ) u_cmd_filter_7_filter_238 (
9426 .clk_i (clk_i),
9427 .rst_ni (rst_ni),
9428
9429 // from register interface
9430 .we (cmd_filter_7_we),
9431 .wd (cmd_filter_7_filter_238_wd),
9432
9433 // from internal hardware
9434 .de (1'b0),
9435 .d ('0),
9436
9437 // to internal hardware
9438 .qe (),
9439 .q (reg2hw.cmd_filter[238].q),
9440 .ds (),
9441
9442 // to register interface (read)
9443 .qs (cmd_filter_7_filter_238_qs)
9444 );
9445
9446 // F[filter_239]: 15:15
9447 prim_subreg #(
9448 .DW (1),
9449 .SwAccess(prim_subreg_pkg::SwAccessRW),
9450 .RESVAL (1'h0),
9451 .Mubi (1'b0)
9452 ) u_cmd_filter_7_filter_239 (
9453 .clk_i (clk_i),
9454 .rst_ni (rst_ni),
9455
9456 // from register interface
9457 .we (cmd_filter_7_we),
9458 .wd (cmd_filter_7_filter_239_wd),
9459
9460 // from internal hardware
9461 .de (1'b0),
9462 .d ('0),
9463
9464 // to internal hardware
9465 .qe (),
9466 .q (reg2hw.cmd_filter[239].q),
9467 .ds (),
9468
9469 // to register interface (read)
9470 .qs (cmd_filter_7_filter_239_qs)
9471 );
9472
9473 // F[filter_240]: 16:16
9474 prim_subreg #(
9475 .DW (1),
9476 .SwAccess(prim_subreg_pkg::SwAccessRW),
9477 .RESVAL (1'h0),
9478 .Mubi (1'b0)
9479 ) u_cmd_filter_7_filter_240 (
9480 .clk_i (clk_i),
9481 .rst_ni (rst_ni),
9482
9483 // from register interface
9484 .we (cmd_filter_7_we),
9485 .wd (cmd_filter_7_filter_240_wd),
9486
9487 // from internal hardware
9488 .de (1'b0),
9489 .d ('0),
9490
9491 // to internal hardware
9492 .qe (),
9493 .q (reg2hw.cmd_filter[240].q),
9494 .ds (),
9495
9496 // to register interface (read)
9497 .qs (cmd_filter_7_filter_240_qs)
9498 );
9499
9500 // F[filter_241]: 17:17
9501 prim_subreg #(
9502 .DW (1),
9503 .SwAccess(prim_subreg_pkg::SwAccessRW),
9504 .RESVAL (1'h0),
9505 .Mubi (1'b0)
9506 ) u_cmd_filter_7_filter_241 (
9507 .clk_i (clk_i),
9508 .rst_ni (rst_ni),
9509
9510 // from register interface
9511 .we (cmd_filter_7_we),
9512 .wd (cmd_filter_7_filter_241_wd),
9513
9514 // from internal hardware
9515 .de (1'b0),
9516 .d ('0),
9517
9518 // to internal hardware
9519 .qe (),
9520 .q (reg2hw.cmd_filter[241].q),
9521 .ds (),
9522
9523 // to register interface (read)
9524 .qs (cmd_filter_7_filter_241_qs)
9525 );
9526
9527 // F[filter_242]: 18:18
9528 prim_subreg #(
9529 .DW (1),
9530 .SwAccess(prim_subreg_pkg::SwAccessRW),
9531 .RESVAL (1'h0),
9532 .Mubi (1'b0)
9533 ) u_cmd_filter_7_filter_242 (
9534 .clk_i (clk_i),
9535 .rst_ni (rst_ni),
9536
9537 // from register interface
9538 .we (cmd_filter_7_we),
9539 .wd (cmd_filter_7_filter_242_wd),
9540
9541 // from internal hardware
9542 .de (1'b0),
9543 .d ('0),
9544
9545 // to internal hardware
9546 .qe (),
9547 .q (reg2hw.cmd_filter[242].q),
9548 .ds (),
9549
9550 // to register interface (read)
9551 .qs (cmd_filter_7_filter_242_qs)
9552 );
9553
9554 // F[filter_243]: 19:19
9555 prim_subreg #(
9556 .DW (1),
9557 .SwAccess(prim_subreg_pkg::SwAccessRW),
9558 .RESVAL (1'h0),
9559 .Mubi (1'b0)
9560 ) u_cmd_filter_7_filter_243 (
9561 .clk_i (clk_i),
9562 .rst_ni (rst_ni),
9563
9564 // from register interface
9565 .we (cmd_filter_7_we),
9566 .wd (cmd_filter_7_filter_243_wd),
9567
9568 // from internal hardware
9569 .de (1'b0),
9570 .d ('0),
9571
9572 // to internal hardware
9573 .qe (),
9574 .q (reg2hw.cmd_filter[243].q),
9575 .ds (),
9576
9577 // to register interface (read)
9578 .qs (cmd_filter_7_filter_243_qs)
9579 );
9580
9581 // F[filter_244]: 20:20
9582 prim_subreg #(
9583 .DW (1),
9584 .SwAccess(prim_subreg_pkg::SwAccessRW),
9585 .RESVAL (1'h0),
9586 .Mubi (1'b0)
9587 ) u_cmd_filter_7_filter_244 (
9588 .clk_i (clk_i),
9589 .rst_ni (rst_ni),
9590
9591 // from register interface
9592 .we (cmd_filter_7_we),
9593 .wd (cmd_filter_7_filter_244_wd),
9594
9595 // from internal hardware
9596 .de (1'b0),
9597 .d ('0),
9598
9599 // to internal hardware
9600 .qe (),
9601 .q (reg2hw.cmd_filter[244].q),
9602 .ds (),
9603
9604 // to register interface (read)
9605 .qs (cmd_filter_7_filter_244_qs)
9606 );
9607
9608 // F[filter_245]: 21:21
9609 prim_subreg #(
9610 .DW (1),
9611 .SwAccess(prim_subreg_pkg::SwAccessRW),
9612 .RESVAL (1'h0),
9613 .Mubi (1'b0)
9614 ) u_cmd_filter_7_filter_245 (
9615 .clk_i (clk_i),
9616 .rst_ni (rst_ni),
9617
9618 // from register interface
9619 .we (cmd_filter_7_we),
9620 .wd (cmd_filter_7_filter_245_wd),
9621
9622 // from internal hardware
9623 .de (1'b0),
9624 .d ('0),
9625
9626 // to internal hardware
9627 .qe (),
9628 .q (reg2hw.cmd_filter[245].q),
9629 .ds (),
9630
9631 // to register interface (read)
9632 .qs (cmd_filter_7_filter_245_qs)
9633 );
9634
9635 // F[filter_246]: 22:22
9636 prim_subreg #(
9637 .DW (1),
9638 .SwAccess(prim_subreg_pkg::SwAccessRW),
9639 .RESVAL (1'h0),
9640 .Mubi (1'b0)
9641 ) u_cmd_filter_7_filter_246 (
9642 .clk_i (clk_i),
9643 .rst_ni (rst_ni),
9644
9645 // from register interface
9646 .we (cmd_filter_7_we),
9647 .wd (cmd_filter_7_filter_246_wd),
9648
9649 // from internal hardware
9650 .de (1'b0),
9651 .d ('0),
9652
9653 // to internal hardware
9654 .qe (),
9655 .q (reg2hw.cmd_filter[246].q),
9656 .ds (),
9657
9658 // to register interface (read)
9659 .qs (cmd_filter_7_filter_246_qs)
9660 );
9661
9662 // F[filter_247]: 23:23
9663 prim_subreg #(
9664 .DW (1),
9665 .SwAccess(prim_subreg_pkg::SwAccessRW),
9666 .RESVAL (1'h0),
9667 .Mubi (1'b0)
9668 ) u_cmd_filter_7_filter_247 (
9669 .clk_i (clk_i),
9670 .rst_ni (rst_ni),
9671
9672 // from register interface
9673 .we (cmd_filter_7_we),
9674 .wd (cmd_filter_7_filter_247_wd),
9675
9676 // from internal hardware
9677 .de (1'b0),
9678 .d ('0),
9679
9680 // to internal hardware
9681 .qe (),
9682 .q (reg2hw.cmd_filter[247].q),
9683 .ds (),
9684
9685 // to register interface (read)
9686 .qs (cmd_filter_7_filter_247_qs)
9687 );
9688
9689 // F[filter_248]: 24:24
9690 prim_subreg #(
9691 .DW (1),
9692 .SwAccess(prim_subreg_pkg::SwAccessRW),
9693 .RESVAL (1'h0),
9694 .Mubi (1'b0)
9695 ) u_cmd_filter_7_filter_248 (
9696 .clk_i (clk_i),
9697 .rst_ni (rst_ni),
9698
9699 // from register interface
9700 .we (cmd_filter_7_we),
9701 .wd (cmd_filter_7_filter_248_wd),
9702
9703 // from internal hardware
9704 .de (1'b0),
9705 .d ('0),
9706
9707 // to internal hardware
9708 .qe (),
9709 .q (reg2hw.cmd_filter[248].q),
9710 .ds (),
9711
9712 // to register interface (read)
9713 .qs (cmd_filter_7_filter_248_qs)
9714 );
9715
9716 // F[filter_249]: 25:25
9717 prim_subreg #(
9718 .DW (1),
9719 .SwAccess(prim_subreg_pkg::SwAccessRW),
9720 .RESVAL (1'h0),
9721 .Mubi (1'b0)
9722 ) u_cmd_filter_7_filter_249 (
9723 .clk_i (clk_i),
9724 .rst_ni (rst_ni),
9725
9726 // from register interface
9727 .we (cmd_filter_7_we),
9728 .wd (cmd_filter_7_filter_249_wd),
9729
9730 // from internal hardware
9731 .de (1'b0),
9732 .d ('0),
9733
9734 // to internal hardware
9735 .qe (),
9736 .q (reg2hw.cmd_filter[249].q),
9737 .ds (),
9738
9739 // to register interface (read)
9740 .qs (cmd_filter_7_filter_249_qs)
9741 );
9742
9743 // F[filter_250]: 26:26
9744 prim_subreg #(
9745 .DW (1),
9746 .SwAccess(prim_subreg_pkg::SwAccessRW),
9747 .RESVAL (1'h0),
9748 .Mubi (1'b0)
9749 ) u_cmd_filter_7_filter_250 (
9750 .clk_i (clk_i),
9751 .rst_ni (rst_ni),
9752
9753 // from register interface
9754 .we (cmd_filter_7_we),
9755 .wd (cmd_filter_7_filter_250_wd),
9756
9757 // from internal hardware
9758 .de (1'b0),
9759 .d ('0),
9760
9761 // to internal hardware
9762 .qe (),
9763 .q (reg2hw.cmd_filter[250].q),
9764 .ds (),
9765
9766 // to register interface (read)
9767 .qs (cmd_filter_7_filter_250_qs)
9768 );
9769
9770 // F[filter_251]: 27:27
9771 prim_subreg #(
9772 .DW (1),
9773 .SwAccess(prim_subreg_pkg::SwAccessRW),
9774 .RESVAL (1'h0),
9775 .Mubi (1'b0)
9776 ) u_cmd_filter_7_filter_251 (
9777 .clk_i (clk_i),
9778 .rst_ni (rst_ni),
9779
9780 // from register interface
9781 .we (cmd_filter_7_we),
9782 .wd (cmd_filter_7_filter_251_wd),
9783
9784 // from internal hardware
9785 .de (1'b0),
9786 .d ('0),
9787
9788 // to internal hardware
9789 .qe (),
9790 .q (reg2hw.cmd_filter[251].q),
9791 .ds (),
9792
9793 // to register interface (read)
9794 .qs (cmd_filter_7_filter_251_qs)
9795 );
9796
9797 // F[filter_252]: 28:28
9798 prim_subreg #(
9799 .DW (1),
9800 .SwAccess(prim_subreg_pkg::SwAccessRW),
9801 .RESVAL (1'h0),
9802 .Mubi (1'b0)
9803 ) u_cmd_filter_7_filter_252 (
9804 .clk_i (clk_i),
9805 .rst_ni (rst_ni),
9806
9807 // from register interface
9808 .we (cmd_filter_7_we),
9809 .wd (cmd_filter_7_filter_252_wd),
9810
9811 // from internal hardware
9812 .de (1'b0),
9813 .d ('0),
9814
9815 // to internal hardware
9816 .qe (),
9817 .q (reg2hw.cmd_filter[252].q),
9818 .ds (),
9819
9820 // to register interface (read)
9821 .qs (cmd_filter_7_filter_252_qs)
9822 );
9823
9824 // F[filter_253]: 29:29
9825 prim_subreg #(
9826 .DW (1),
9827 .SwAccess(prim_subreg_pkg::SwAccessRW),
9828 .RESVAL (1'h0),
9829 .Mubi (1'b0)
9830 ) u_cmd_filter_7_filter_253 (
9831 .clk_i (clk_i),
9832 .rst_ni (rst_ni),
9833
9834 // from register interface
9835 .we (cmd_filter_7_we),
9836 .wd (cmd_filter_7_filter_253_wd),
9837
9838 // from internal hardware
9839 .de (1'b0),
9840 .d ('0),
9841
9842 // to internal hardware
9843 .qe (),
9844 .q (reg2hw.cmd_filter[253].q),
9845 .ds (),
9846
9847 // to register interface (read)
9848 .qs (cmd_filter_7_filter_253_qs)
9849 );
9850
9851 // F[filter_254]: 30:30
9852 prim_subreg #(
9853 .DW (1),
9854 .SwAccess(prim_subreg_pkg::SwAccessRW),
9855 .RESVAL (1'h0),
9856 .Mubi (1'b0)
9857 ) u_cmd_filter_7_filter_254 (
9858 .clk_i (clk_i),
9859 .rst_ni (rst_ni),
9860
9861 // from register interface
9862 .we (cmd_filter_7_we),
9863 .wd (cmd_filter_7_filter_254_wd),
9864
9865 // from internal hardware
9866 .de (1'b0),
9867 .d ('0),
9868
9869 // to internal hardware
9870 .qe (),
9871 .q (reg2hw.cmd_filter[254].q),
9872 .ds (),
9873
9874 // to register interface (read)
9875 .qs (cmd_filter_7_filter_254_qs)
9876 );
9877
9878 // F[filter_255]: 31:31
9879 prim_subreg #(
9880 .DW (1),
9881 .SwAccess(prim_subreg_pkg::SwAccessRW),
9882 .RESVAL (1'h0),
9883 .Mubi (1'b0)
9884 ) u_cmd_filter_7_filter_255 (
9885 .clk_i (clk_i),
9886 .rst_ni (rst_ni),
9887
9888 // from register interface
9889 .we (cmd_filter_7_we),
9890 .wd (cmd_filter_7_filter_255_wd),
9891
9892 // from internal hardware
9893 .de (1'b0),
9894 .d ('0),
9895
9896 // to internal hardware
9897 .qe (),
9898 .q (reg2hw.cmd_filter[255].q),
9899 .ds (),
9900
9901 // to register interface (read)
9902 .qs (cmd_filter_7_filter_255_qs)
9903 );
9904
9905
9906 // R[addr_swap_mask]: V(False)
9907 prim_subreg #(
9908 .DW (32),
9909 .SwAccess(prim_subreg_pkg::SwAccessRW),
9910 .RESVAL (32'h0),
9911 .Mubi (1'b0)
9912 ) u_addr_swap_mask (
9913 .clk_i (clk_i),
9914 .rst_ni (rst_ni),
9915
9916 // from register interface
9917 .we (addr_swap_mask_we),
9918 .wd (addr_swap_mask_wd),
9919
9920 // from internal hardware
9921 .de (1'b0),
9922 .d ('0),
9923
9924 // to internal hardware
9925 .qe (),
9926 .q (reg2hw.addr_swap_mask.q),
9927 .ds (),
9928
9929 // to register interface (read)
9930 .qs (addr_swap_mask_qs)
9931 );
9932
9933
9934 // R[addr_swap_data]: V(False)
9935 prim_subreg #(
9936 .DW (32),
9937 .SwAccess(prim_subreg_pkg::SwAccessRW),
9938 .RESVAL (32'h0),
9939 .Mubi (1'b0)
9940 ) u_addr_swap_data (
9941 .clk_i (clk_i),
9942 .rst_ni (rst_ni),
9943
9944 // from register interface
9945 .we (addr_swap_data_we),
9946 .wd (addr_swap_data_wd),
9947
9948 // from internal hardware
9949 .de (1'b0),
9950 .d ('0),
9951
9952 // to internal hardware
9953 .qe (),
9954 .q (reg2hw.addr_swap_data.q),
9955 .ds (),
9956
9957 // to register interface (read)
9958 .qs (addr_swap_data_qs)
9959 );
9960
9961
9962 // R[payload_swap_mask]: V(False)
9963 prim_subreg #(
9964 .DW (32),
9965 .SwAccess(prim_subreg_pkg::SwAccessRW),
9966 .RESVAL (32'h0),
9967 .Mubi (1'b0)
9968 ) u_payload_swap_mask (
9969 .clk_i (clk_i),
9970 .rst_ni (rst_ni),
9971
9972 // from register interface
9973 .we (payload_swap_mask_we),
9974 .wd (payload_swap_mask_wd),
9975
9976 // from internal hardware
9977 .de (1'b0),
9978 .d ('0),
9979
9980 // to internal hardware
9981 .qe (),
9982 .q (reg2hw.payload_swap_mask.q),
9983 .ds (),
9984
9985 // to register interface (read)
9986 .qs (payload_swap_mask_qs)
9987 );
9988
9989
9990 // R[payload_swap_data]: V(False)
9991 prim_subreg #(
9992 .DW (32),
9993 .SwAccess(prim_subreg_pkg::SwAccessRW),
9994 .RESVAL (32'h0),
9995 .Mubi (1'b0)
9996 ) u_payload_swap_data (
9997 .clk_i (clk_i),
9998 .rst_ni (rst_ni),
9999
10000 // from register interface
10001 .we (payload_swap_data_we),
10002 .wd (payload_swap_data_wd),
10003
10004 // from internal hardware
10005 .de (1'b0),
10006 .d ('0),
10007
10008 // to internal hardware
10009 .qe (),
10010 .q (reg2hw.payload_swap_data.q),
10011 .ds (),
10012
10013 // to register interface (read)
10014 .qs (payload_swap_data_qs)
10015 );
10016
10017
10018 // Subregister 0 of Multireg cmd_info
10019 // R[cmd_info_0]: V(False)
10020 // F[opcode_0]: 7:0
10021 prim_subreg #(
10022 .DW (8),
10023 .SwAccess(prim_subreg_pkg::SwAccessRW),
10024 .RESVAL (8'h0),
10025 .Mubi (1'b0)
10026 ) u_cmd_info_0_opcode_0 (
10027 .clk_i (clk_i),
10028 .rst_ni (rst_ni),
10029
10030 // from register interface
10031 .we (cmd_info_0_we),
10032 .wd (cmd_info_0_opcode_0_wd),
10033
10034 // from internal hardware
10035 .de (1'b0),
10036 .d ('0),
10037
10038 // to internal hardware
10039 .qe (),
10040 .q (reg2hw.cmd_info[0].opcode.q),
10041 .ds (),
10042
10043 // to register interface (read)
10044 .qs (cmd_info_0_opcode_0_qs)
10045 );
10046
10047 // F[addr_mode_0]: 9:8
10048 prim_subreg #(
10049 .DW (2),
10050 .SwAccess(prim_subreg_pkg::SwAccessRW),
10051 .RESVAL (2'h0),
10052 .Mubi (1'b0)
10053 ) u_cmd_info_0_addr_mode_0 (
10054 .clk_i (clk_i),
10055 .rst_ni (rst_ni),
10056
10057 // from register interface
10058 .we (cmd_info_0_we),
10059 .wd (cmd_info_0_addr_mode_0_wd),
10060
10061 // from internal hardware
10062 .de (1'b0),
10063 .d ('0),
10064
10065 // to internal hardware
10066 .qe (),
10067 .q (reg2hw.cmd_info[0].addr_mode.q),
10068 .ds (),
10069
10070 // to register interface (read)
10071 .qs (cmd_info_0_addr_mode_0_qs)
10072 );
10073
10074 // F[addr_swap_en_0]: 10:10
10075 prim_subreg #(
10076 .DW (1),
10077 .SwAccess(prim_subreg_pkg::SwAccessRW),
10078 .RESVAL (1'h0),
10079 .Mubi (1'b0)
10080 ) u_cmd_info_0_addr_swap_en_0 (
10081 .clk_i (clk_i),
10082 .rst_ni (rst_ni),
10083
10084 // from register interface
10085 .we (cmd_info_0_we),
10086 .wd (cmd_info_0_addr_swap_en_0_wd),
10087
10088 // from internal hardware
10089 .de (1'b0),
10090 .d ('0),
10091
10092 // to internal hardware
10093 .qe (),
10094 .q (reg2hw.cmd_info[0].addr_swap_en.q),
10095 .ds (),
10096
10097 // to register interface (read)
10098 .qs (cmd_info_0_addr_swap_en_0_qs)
10099 );
10100
10101 // F[mbyte_en_0]: 11:11
10102 prim_subreg #(
10103 .DW (1),
10104 .SwAccess(prim_subreg_pkg::SwAccessRW),
10105 .RESVAL (1'h0),
10106 .Mubi (1'b0)
10107 ) u_cmd_info_0_mbyte_en_0 (
10108 .clk_i (clk_i),
10109 .rst_ni (rst_ni),
10110
10111 // from register interface
10112 .we (cmd_info_0_we),
10113 .wd (cmd_info_0_mbyte_en_0_wd),
10114
10115 // from internal hardware
10116 .de (1'b0),
10117 .d ('0),
10118
10119 // to internal hardware
10120 .qe (),
10121 .q (reg2hw.cmd_info[0].mbyte_en.q),
10122 .ds (),
10123
10124 // to register interface (read)
10125 .qs (cmd_info_0_mbyte_en_0_qs)
10126 );
10127
10128 // F[dummy_size_0]: 14:12
10129 prim_subreg #(
10130 .DW (3),
10131 .SwAccess(prim_subreg_pkg::SwAccessRW),
10132 .RESVAL (3'h7),
10133 .Mubi (1'b0)
10134 ) u_cmd_info_0_dummy_size_0 (
10135 .clk_i (clk_i),
10136 .rst_ni (rst_ni),
10137
10138 // from register interface
10139 .we (cmd_info_0_we),
10140 .wd (cmd_info_0_dummy_size_0_wd),
10141
10142 // from internal hardware
10143 .de (1'b0),
10144 .d ('0),
10145
10146 // to internal hardware
10147 .qe (),
10148 .q (reg2hw.cmd_info[0].dummy_size.q),
10149 .ds (),
10150
10151 // to register interface (read)
10152 .qs (cmd_info_0_dummy_size_0_qs)
10153 );
10154
10155 // F[dummy_en_0]: 15:15
10156 prim_subreg #(
10157 .DW (1),
10158 .SwAccess(prim_subreg_pkg::SwAccessRW),
10159 .RESVAL (1'h0),
10160 .Mubi (1'b0)
10161 ) u_cmd_info_0_dummy_en_0 (
10162 .clk_i (clk_i),
10163 .rst_ni (rst_ni),
10164
10165 // from register interface
10166 .we (cmd_info_0_we),
10167 .wd (cmd_info_0_dummy_en_0_wd),
10168
10169 // from internal hardware
10170 .de (1'b0),
10171 .d ('0),
10172
10173 // to internal hardware
10174 .qe (),
10175 .q (reg2hw.cmd_info[0].dummy_en.q),
10176 .ds (),
10177
10178 // to register interface (read)
10179 .qs (cmd_info_0_dummy_en_0_qs)
10180 );
10181
10182 // F[payload_en_0]: 19:16
10183 prim_subreg #(
10184 .DW (4),
10185 .SwAccess(prim_subreg_pkg::SwAccessRW),
10186 .RESVAL (4'h0),
10187 .Mubi (1'b0)
10188 ) u_cmd_info_0_payload_en_0 (
10189 .clk_i (clk_i),
10190 .rst_ni (rst_ni),
10191
10192 // from register interface
10193 .we (cmd_info_0_we),
10194 .wd (cmd_info_0_payload_en_0_wd),
10195
10196 // from internal hardware
10197 .de (1'b0),
10198 .d ('0),
10199
10200 // to internal hardware
10201 .qe (),
10202 .q (reg2hw.cmd_info[0].payload_en.q),
10203 .ds (),
10204
10205 // to register interface (read)
10206 .qs (cmd_info_0_payload_en_0_qs)
10207 );
10208
10209 // F[payload_dir_0]: 20:20
10210 prim_subreg #(
10211 .DW (1),
10212 .SwAccess(prim_subreg_pkg::SwAccessRW),
10213 .RESVAL (1'h0),
10214 .Mubi (1'b0)
10215 ) u_cmd_info_0_payload_dir_0 (
10216 .clk_i (clk_i),
10217 .rst_ni (rst_ni),
10218
10219 // from register interface
10220 .we (cmd_info_0_we),
10221 .wd (cmd_info_0_payload_dir_0_wd),
10222
10223 // from internal hardware
10224 .de (1'b0),
10225 .d ('0),
10226
10227 // to internal hardware
10228 .qe (),
10229 .q (reg2hw.cmd_info[0].payload_dir.q),
10230 .ds (),
10231
10232 // to register interface (read)
10233 .qs (cmd_info_0_payload_dir_0_qs)
10234 );
10235
10236 // F[payload_swap_en_0]: 21:21
10237 prim_subreg #(
10238 .DW (1),
10239 .SwAccess(prim_subreg_pkg::SwAccessRW),
10240 .RESVAL (1'h0),
10241 .Mubi (1'b0)
10242 ) u_cmd_info_0_payload_swap_en_0 (
10243 .clk_i (clk_i),
10244 .rst_ni (rst_ni),
10245
10246 // from register interface
10247 .we (cmd_info_0_we),
10248 .wd (cmd_info_0_payload_swap_en_0_wd),
10249
10250 // from internal hardware
10251 .de (1'b0),
10252 .d ('0),
10253
10254 // to internal hardware
10255 .qe (),
10256 .q (reg2hw.cmd_info[0].payload_swap_en.q),
10257 .ds (),
10258
10259 // to register interface (read)
10260 .qs (cmd_info_0_payload_swap_en_0_qs)
10261 );
10262
10263 // F[read_pipeline_mode_0]: 23:22
10264 prim_subreg #(
10265 .DW (2),
10266 .SwAccess(prim_subreg_pkg::SwAccessRW),
10267 .RESVAL (2'h0),
10268 .Mubi (1'b0)
10269 ) u_cmd_info_0_read_pipeline_mode_0 (
10270 .clk_i (clk_i),
10271 .rst_ni (rst_ni),
10272
10273 // from register interface
10274 .we (cmd_info_0_we),
10275 .wd (cmd_info_0_read_pipeline_mode_0_wd),
10276
10277 // from internal hardware
10278 .de (1'b0),
10279 .d ('0),
10280
10281 // to internal hardware
10282 .qe (),
10283 .q (reg2hw.cmd_info[0].read_pipeline_mode.q),
10284 .ds (),
10285
10286 // to register interface (read)
10287 .qs (cmd_info_0_read_pipeline_mode_0_qs)
10288 );
10289
10290 // F[upload_0]: 24:24
10291 prim_subreg #(
10292 .DW (1),
10293 .SwAccess(prim_subreg_pkg::SwAccessRW),
10294 .RESVAL (1'h0),
10295 .Mubi (1'b0)
10296 ) u_cmd_info_0_upload_0 (
10297 .clk_i (clk_i),
10298 .rst_ni (rst_ni),
10299
10300 // from register interface
10301 .we (cmd_info_0_we),
10302 .wd (cmd_info_0_upload_0_wd),
10303
10304 // from internal hardware
10305 .de (1'b0),
10306 .d ('0),
10307
10308 // to internal hardware
10309 .qe (),
10310 .q (reg2hw.cmd_info[0].upload.q),
10311 .ds (),
10312
10313 // to register interface (read)
10314 .qs (cmd_info_0_upload_0_qs)
10315 );
10316
10317 // F[busy_0]: 25:25
10318 prim_subreg #(
10319 .DW (1),
10320 .SwAccess(prim_subreg_pkg::SwAccessRW),
10321 .RESVAL (1'h0),
10322 .Mubi (1'b0)
10323 ) u_cmd_info_0_busy_0 (
10324 .clk_i (clk_i),
10325 .rst_ni (rst_ni),
10326
10327 // from register interface
10328 .we (cmd_info_0_we),
10329 .wd (cmd_info_0_busy_0_wd),
10330
10331 // from internal hardware
10332 .de (1'b0),
10333 .d ('0),
10334
10335 // to internal hardware
10336 .qe (),
10337 .q (reg2hw.cmd_info[0].busy.q),
10338 .ds (),
10339
10340 // to register interface (read)
10341 .qs (cmd_info_0_busy_0_qs)
10342 );
10343
10344 // F[valid_0]: 31:31
10345 prim_subreg #(
10346 .DW (1),
10347 .SwAccess(prim_subreg_pkg::SwAccessRW),
10348 .RESVAL (1'h0),
10349 .Mubi (1'b0)
10350 ) u_cmd_info_0_valid_0 (
10351 .clk_i (clk_i),
10352 .rst_ni (rst_ni),
10353
10354 // from register interface
10355 .we (cmd_info_0_we),
10356 .wd (cmd_info_0_valid_0_wd),
10357
10358 // from internal hardware
10359 .de (1'b0),
10360 .d ('0),
10361
10362 // to internal hardware
10363 .qe (),
10364 .q (reg2hw.cmd_info[0].valid.q),
10365 .ds (),
10366
10367 // to register interface (read)
10368 .qs (cmd_info_0_valid_0_qs)
10369 );
10370
10371
10372 // Subregister 1 of Multireg cmd_info
10373 // R[cmd_info_1]: V(False)
10374 // F[opcode_1]: 7:0
10375 prim_subreg #(
10376 .DW (8),
10377 .SwAccess(prim_subreg_pkg::SwAccessRW),
10378 .RESVAL (8'h0),
10379 .Mubi (1'b0)
10380 ) u_cmd_info_1_opcode_1 (
10381 .clk_i (clk_i),
10382 .rst_ni (rst_ni),
10383
10384 // from register interface
10385 .we (cmd_info_1_we),
10386 .wd (cmd_info_1_opcode_1_wd),
10387
10388 // from internal hardware
10389 .de (1'b0),
10390 .d ('0),
10391
10392 // to internal hardware
10393 .qe (),
10394 .q (reg2hw.cmd_info[1].opcode.q),
10395 .ds (),
10396
10397 // to register interface (read)
10398 .qs (cmd_info_1_opcode_1_qs)
10399 );
10400
10401 // F[addr_mode_1]: 9:8
10402 prim_subreg #(
10403 .DW (2),
10404 .SwAccess(prim_subreg_pkg::SwAccessRW),
10405 .RESVAL (2'h0),
10406 .Mubi (1'b0)
10407 ) u_cmd_info_1_addr_mode_1 (
10408 .clk_i (clk_i),
10409 .rst_ni (rst_ni),
10410
10411 // from register interface
10412 .we (cmd_info_1_we),
10413 .wd (cmd_info_1_addr_mode_1_wd),
10414
10415 // from internal hardware
10416 .de (1'b0),
10417 .d ('0),
10418
10419 // to internal hardware
10420 .qe (),
10421 .q (reg2hw.cmd_info[1].addr_mode.q),
10422 .ds (),
10423
10424 // to register interface (read)
10425 .qs (cmd_info_1_addr_mode_1_qs)
10426 );
10427
10428 // F[addr_swap_en_1]: 10:10
10429 prim_subreg #(
10430 .DW (1),
10431 .SwAccess(prim_subreg_pkg::SwAccessRW),
10432 .RESVAL (1'h0),
10433 .Mubi (1'b0)
10434 ) u_cmd_info_1_addr_swap_en_1 (
10435 .clk_i (clk_i),
10436 .rst_ni (rst_ni),
10437
10438 // from register interface
10439 .we (cmd_info_1_we),
10440 .wd (cmd_info_1_addr_swap_en_1_wd),
10441
10442 // from internal hardware
10443 .de (1'b0),
10444 .d ('0),
10445
10446 // to internal hardware
10447 .qe (),
10448 .q (reg2hw.cmd_info[1].addr_swap_en.q),
10449 .ds (),
10450
10451 // to register interface (read)
10452 .qs (cmd_info_1_addr_swap_en_1_qs)
10453 );
10454
10455 // F[mbyte_en_1]: 11:11
10456 prim_subreg #(
10457 .DW (1),
10458 .SwAccess(prim_subreg_pkg::SwAccessRW),
10459 .RESVAL (1'h0),
10460 .Mubi (1'b0)
10461 ) u_cmd_info_1_mbyte_en_1 (
10462 .clk_i (clk_i),
10463 .rst_ni (rst_ni),
10464
10465 // from register interface
10466 .we (cmd_info_1_we),
10467 .wd (cmd_info_1_mbyte_en_1_wd),
10468
10469 // from internal hardware
10470 .de (1'b0),
10471 .d ('0),
10472
10473 // to internal hardware
10474 .qe (),
10475 .q (reg2hw.cmd_info[1].mbyte_en.q),
10476 .ds (),
10477
10478 // to register interface (read)
10479 .qs (cmd_info_1_mbyte_en_1_qs)
10480 );
10481
10482 // F[dummy_size_1]: 14:12
10483 prim_subreg #(
10484 .DW (3),
10485 .SwAccess(prim_subreg_pkg::SwAccessRW),
10486 .RESVAL (3'h7),
10487 .Mubi (1'b0)
10488 ) u_cmd_info_1_dummy_size_1 (
10489 .clk_i (clk_i),
10490 .rst_ni (rst_ni),
10491
10492 // from register interface
10493 .we (cmd_info_1_we),
10494 .wd (cmd_info_1_dummy_size_1_wd),
10495
10496 // from internal hardware
10497 .de (1'b0),
10498 .d ('0),
10499
10500 // to internal hardware
10501 .qe (),
10502 .q (reg2hw.cmd_info[1].dummy_size.q),
10503 .ds (),
10504
10505 // to register interface (read)
10506 .qs (cmd_info_1_dummy_size_1_qs)
10507 );
10508
10509 // F[dummy_en_1]: 15:15
10510 prim_subreg #(
10511 .DW (1),
10512 .SwAccess(prim_subreg_pkg::SwAccessRW),
10513 .RESVAL (1'h0),
10514 .Mubi (1'b0)
10515 ) u_cmd_info_1_dummy_en_1 (
10516 .clk_i (clk_i),
10517 .rst_ni (rst_ni),
10518
10519 // from register interface
10520 .we (cmd_info_1_we),
10521 .wd (cmd_info_1_dummy_en_1_wd),
10522
10523 // from internal hardware
10524 .de (1'b0),
10525 .d ('0),
10526
10527 // to internal hardware
10528 .qe (),
10529 .q (reg2hw.cmd_info[1].dummy_en.q),
10530 .ds (),
10531
10532 // to register interface (read)
10533 .qs (cmd_info_1_dummy_en_1_qs)
10534 );
10535
10536 // F[payload_en_1]: 19:16
10537 prim_subreg #(
10538 .DW (4),
10539 .SwAccess(prim_subreg_pkg::SwAccessRW),
10540 .RESVAL (4'h0),
10541 .Mubi (1'b0)
10542 ) u_cmd_info_1_payload_en_1 (
10543 .clk_i (clk_i),
10544 .rst_ni (rst_ni),
10545
10546 // from register interface
10547 .we (cmd_info_1_we),
10548 .wd (cmd_info_1_payload_en_1_wd),
10549
10550 // from internal hardware
10551 .de (1'b0),
10552 .d ('0),
10553
10554 // to internal hardware
10555 .qe (),
10556 .q (reg2hw.cmd_info[1].payload_en.q),
10557 .ds (),
10558
10559 // to register interface (read)
10560 .qs (cmd_info_1_payload_en_1_qs)
10561 );
10562
10563 // F[payload_dir_1]: 20:20
10564 prim_subreg #(
10565 .DW (1),
10566 .SwAccess(prim_subreg_pkg::SwAccessRW),
10567 .RESVAL (1'h0),
10568 .Mubi (1'b0)
10569 ) u_cmd_info_1_payload_dir_1 (
10570 .clk_i (clk_i),
10571 .rst_ni (rst_ni),
10572
10573 // from register interface
10574 .we (cmd_info_1_we),
10575 .wd (cmd_info_1_payload_dir_1_wd),
10576
10577 // from internal hardware
10578 .de (1'b0),
10579 .d ('0),
10580
10581 // to internal hardware
10582 .qe (),
10583 .q (reg2hw.cmd_info[1].payload_dir.q),
10584 .ds (),
10585
10586 // to register interface (read)
10587 .qs (cmd_info_1_payload_dir_1_qs)
10588 );
10589
10590 // F[payload_swap_en_1]: 21:21
10591 prim_subreg #(
10592 .DW (1),
10593 .SwAccess(prim_subreg_pkg::SwAccessRW),
10594 .RESVAL (1'h0),
10595 .Mubi (1'b0)
10596 ) u_cmd_info_1_payload_swap_en_1 (
10597 .clk_i (clk_i),
10598 .rst_ni (rst_ni),
10599
10600 // from register interface
10601 .we (cmd_info_1_we),
10602 .wd (cmd_info_1_payload_swap_en_1_wd),
10603
10604 // from internal hardware
10605 .de (1'b0),
10606 .d ('0),
10607
10608 // to internal hardware
10609 .qe (),
10610 .q (reg2hw.cmd_info[1].payload_swap_en.q),
10611 .ds (),
10612
10613 // to register interface (read)
10614 .qs (cmd_info_1_payload_swap_en_1_qs)
10615 );
10616
10617 // F[read_pipeline_mode_1]: 23:22
10618 prim_subreg #(
10619 .DW (2),
10620 .SwAccess(prim_subreg_pkg::SwAccessRW),
10621 .RESVAL (2'h0),
10622 .Mubi (1'b0)
10623 ) u_cmd_info_1_read_pipeline_mode_1 (
10624 .clk_i (clk_i),
10625 .rst_ni (rst_ni),
10626
10627 // from register interface
10628 .we (cmd_info_1_we),
10629 .wd (cmd_info_1_read_pipeline_mode_1_wd),
10630
10631 // from internal hardware
10632 .de (1'b0),
10633 .d ('0),
10634
10635 // to internal hardware
10636 .qe (),
10637 .q (reg2hw.cmd_info[1].read_pipeline_mode.q),
10638 .ds (),
10639
10640 // to register interface (read)
10641 .qs (cmd_info_1_read_pipeline_mode_1_qs)
10642 );
10643
10644 // F[upload_1]: 24:24
10645 prim_subreg #(
10646 .DW (1),
10647 .SwAccess(prim_subreg_pkg::SwAccessRW),
10648 .RESVAL (1'h0),
10649 .Mubi (1'b0)
10650 ) u_cmd_info_1_upload_1 (
10651 .clk_i (clk_i),
10652 .rst_ni (rst_ni),
10653
10654 // from register interface
10655 .we (cmd_info_1_we),
10656 .wd (cmd_info_1_upload_1_wd),
10657
10658 // from internal hardware
10659 .de (1'b0),
10660 .d ('0),
10661
10662 // to internal hardware
10663 .qe (),
10664 .q (reg2hw.cmd_info[1].upload.q),
10665 .ds (),
10666
10667 // to register interface (read)
10668 .qs (cmd_info_1_upload_1_qs)
10669 );
10670
10671 // F[busy_1]: 25:25
10672 prim_subreg #(
10673 .DW (1),
10674 .SwAccess(prim_subreg_pkg::SwAccessRW),
10675 .RESVAL (1'h0),
10676 .Mubi (1'b0)
10677 ) u_cmd_info_1_busy_1 (
10678 .clk_i (clk_i),
10679 .rst_ni (rst_ni),
10680
10681 // from register interface
10682 .we (cmd_info_1_we),
10683 .wd (cmd_info_1_busy_1_wd),
10684
10685 // from internal hardware
10686 .de (1'b0),
10687 .d ('0),
10688
10689 // to internal hardware
10690 .qe (),
10691 .q (reg2hw.cmd_info[1].busy.q),
10692 .ds (),
10693
10694 // to register interface (read)
10695 .qs (cmd_info_1_busy_1_qs)
10696 );
10697
10698 // F[valid_1]: 31:31
10699 prim_subreg #(
10700 .DW (1),
10701 .SwAccess(prim_subreg_pkg::SwAccessRW),
10702 .RESVAL (1'h0),
10703 .Mubi (1'b0)
10704 ) u_cmd_info_1_valid_1 (
10705 .clk_i (clk_i),
10706 .rst_ni (rst_ni),
10707
10708 // from register interface
10709 .we (cmd_info_1_we),
10710 .wd (cmd_info_1_valid_1_wd),
10711
10712 // from internal hardware
10713 .de (1'b0),
10714 .d ('0),
10715
10716 // to internal hardware
10717 .qe (),
10718 .q (reg2hw.cmd_info[1].valid.q),
10719 .ds (),
10720
10721 // to register interface (read)
10722 .qs (cmd_info_1_valid_1_qs)
10723 );
10724
10725
10726 // Subregister 2 of Multireg cmd_info
10727 // R[cmd_info_2]: V(False)
10728 // F[opcode_2]: 7:0
10729 prim_subreg #(
10730 .DW (8),
10731 .SwAccess(prim_subreg_pkg::SwAccessRW),
10732 .RESVAL (8'h0),
10733 .Mubi (1'b0)
10734 ) u_cmd_info_2_opcode_2 (
10735 .clk_i (clk_i),
10736 .rst_ni (rst_ni),
10737
10738 // from register interface
10739 .we (cmd_info_2_we),
10740 .wd (cmd_info_2_opcode_2_wd),
10741
10742 // from internal hardware
10743 .de (1'b0),
10744 .d ('0),
10745
10746 // to internal hardware
10747 .qe (),
10748 .q (reg2hw.cmd_info[2].opcode.q),
10749 .ds (),
10750
10751 // to register interface (read)
10752 .qs (cmd_info_2_opcode_2_qs)
10753 );
10754
10755 // F[addr_mode_2]: 9:8
10756 prim_subreg #(
10757 .DW (2),
10758 .SwAccess(prim_subreg_pkg::SwAccessRW),
10759 .RESVAL (2'h0),
10760 .Mubi (1'b0)
10761 ) u_cmd_info_2_addr_mode_2 (
10762 .clk_i (clk_i),
10763 .rst_ni (rst_ni),
10764
10765 // from register interface
10766 .we (cmd_info_2_we),
10767 .wd (cmd_info_2_addr_mode_2_wd),
10768
10769 // from internal hardware
10770 .de (1'b0),
10771 .d ('0),
10772
10773 // to internal hardware
10774 .qe (),
10775 .q (reg2hw.cmd_info[2].addr_mode.q),
10776 .ds (),
10777
10778 // to register interface (read)
10779 .qs (cmd_info_2_addr_mode_2_qs)
10780 );
10781
10782 // F[addr_swap_en_2]: 10:10
10783 prim_subreg #(
10784 .DW (1),
10785 .SwAccess(prim_subreg_pkg::SwAccessRW),
10786 .RESVAL (1'h0),
10787 .Mubi (1'b0)
10788 ) u_cmd_info_2_addr_swap_en_2 (
10789 .clk_i (clk_i),
10790 .rst_ni (rst_ni),
10791
10792 // from register interface
10793 .we (cmd_info_2_we),
10794 .wd (cmd_info_2_addr_swap_en_2_wd),
10795
10796 // from internal hardware
10797 .de (1'b0),
10798 .d ('0),
10799
10800 // to internal hardware
10801 .qe (),
10802 .q (reg2hw.cmd_info[2].addr_swap_en.q),
10803 .ds (),
10804
10805 // to register interface (read)
10806 .qs (cmd_info_2_addr_swap_en_2_qs)
10807 );
10808
10809 // F[mbyte_en_2]: 11:11
10810 prim_subreg #(
10811 .DW (1),
10812 .SwAccess(prim_subreg_pkg::SwAccessRW),
10813 .RESVAL (1'h0),
10814 .Mubi (1'b0)
10815 ) u_cmd_info_2_mbyte_en_2 (
10816 .clk_i (clk_i),
10817 .rst_ni (rst_ni),
10818
10819 // from register interface
10820 .we (cmd_info_2_we),
10821 .wd (cmd_info_2_mbyte_en_2_wd),
10822
10823 // from internal hardware
10824 .de (1'b0),
10825 .d ('0),
10826
10827 // to internal hardware
10828 .qe (),
10829 .q (reg2hw.cmd_info[2].mbyte_en.q),
10830 .ds (),
10831
10832 // to register interface (read)
10833 .qs (cmd_info_2_mbyte_en_2_qs)
10834 );
10835
10836 // F[dummy_size_2]: 14:12
10837 prim_subreg #(
10838 .DW (3),
10839 .SwAccess(prim_subreg_pkg::SwAccessRW),
10840 .RESVAL (3'h7),
10841 .Mubi (1'b0)
10842 ) u_cmd_info_2_dummy_size_2 (
10843 .clk_i (clk_i),
10844 .rst_ni (rst_ni),
10845
10846 // from register interface
10847 .we (cmd_info_2_we),
10848 .wd (cmd_info_2_dummy_size_2_wd),
10849
10850 // from internal hardware
10851 .de (1'b0),
10852 .d ('0),
10853
10854 // to internal hardware
10855 .qe (),
10856 .q (reg2hw.cmd_info[2].dummy_size.q),
10857 .ds (),
10858
10859 // to register interface (read)
10860 .qs (cmd_info_2_dummy_size_2_qs)
10861 );
10862
10863 // F[dummy_en_2]: 15:15
10864 prim_subreg #(
10865 .DW (1),
10866 .SwAccess(prim_subreg_pkg::SwAccessRW),
10867 .RESVAL (1'h0),
10868 .Mubi (1'b0)
10869 ) u_cmd_info_2_dummy_en_2 (
10870 .clk_i (clk_i),
10871 .rst_ni (rst_ni),
10872
10873 // from register interface
10874 .we (cmd_info_2_we),
10875 .wd (cmd_info_2_dummy_en_2_wd),
10876
10877 // from internal hardware
10878 .de (1'b0),
10879 .d ('0),
10880
10881 // to internal hardware
10882 .qe (),
10883 .q (reg2hw.cmd_info[2].dummy_en.q),
10884 .ds (),
10885
10886 // to register interface (read)
10887 .qs (cmd_info_2_dummy_en_2_qs)
10888 );
10889
10890 // F[payload_en_2]: 19:16
10891 prim_subreg #(
10892 .DW (4),
10893 .SwAccess(prim_subreg_pkg::SwAccessRW),
10894 .RESVAL (4'h0),
10895 .Mubi (1'b0)
10896 ) u_cmd_info_2_payload_en_2 (
10897 .clk_i (clk_i),
10898 .rst_ni (rst_ni),
10899
10900 // from register interface
10901 .we (cmd_info_2_we),
10902 .wd (cmd_info_2_payload_en_2_wd),
10903
10904 // from internal hardware
10905 .de (1'b0),
10906 .d ('0),
10907
10908 // to internal hardware
10909 .qe (),
10910 .q (reg2hw.cmd_info[2].payload_en.q),
10911 .ds (),
10912
10913 // to register interface (read)
10914 .qs (cmd_info_2_payload_en_2_qs)
10915 );
10916
10917 // F[payload_dir_2]: 20:20
10918 prim_subreg #(
10919 .DW (1),
10920 .SwAccess(prim_subreg_pkg::SwAccessRW),
10921 .RESVAL (1'h0),
10922 .Mubi (1'b0)
10923 ) u_cmd_info_2_payload_dir_2 (
10924 .clk_i (clk_i),
10925 .rst_ni (rst_ni),
10926
10927 // from register interface
10928 .we (cmd_info_2_we),
10929 .wd (cmd_info_2_payload_dir_2_wd),
10930
10931 // from internal hardware
10932 .de (1'b0),
10933 .d ('0),
10934
10935 // to internal hardware
10936 .qe (),
10937 .q (reg2hw.cmd_info[2].payload_dir.q),
10938 .ds (),
10939
10940 // to register interface (read)
10941 .qs (cmd_info_2_payload_dir_2_qs)
10942 );
10943
10944 // F[payload_swap_en_2]: 21:21
10945 prim_subreg #(
10946 .DW (1),
10947 .SwAccess(prim_subreg_pkg::SwAccessRW),
10948 .RESVAL (1'h0),
10949 .Mubi (1'b0)
10950 ) u_cmd_info_2_payload_swap_en_2 (
10951 .clk_i (clk_i),
10952 .rst_ni (rst_ni),
10953
10954 // from register interface
10955 .we (cmd_info_2_we),
10956 .wd (cmd_info_2_payload_swap_en_2_wd),
10957
10958 // from internal hardware
10959 .de (1'b0),
10960 .d ('0),
10961
10962 // to internal hardware
10963 .qe (),
10964 .q (reg2hw.cmd_info[2].payload_swap_en.q),
10965 .ds (),
10966
10967 // to register interface (read)
10968 .qs (cmd_info_2_payload_swap_en_2_qs)
10969 );
10970
10971 // F[read_pipeline_mode_2]: 23:22
10972 prim_subreg #(
10973 .DW (2),
10974 .SwAccess(prim_subreg_pkg::SwAccessRW),
10975 .RESVAL (2'h0),
10976 .Mubi (1'b0)
10977 ) u_cmd_info_2_read_pipeline_mode_2 (
10978 .clk_i (clk_i),
10979 .rst_ni (rst_ni),
10980
10981 // from register interface
10982 .we (cmd_info_2_we),
10983 .wd (cmd_info_2_read_pipeline_mode_2_wd),
10984
10985 // from internal hardware
10986 .de (1'b0),
10987 .d ('0),
10988
10989 // to internal hardware
10990 .qe (),
10991 .q (reg2hw.cmd_info[2].read_pipeline_mode.q),
10992 .ds (),
10993
10994 // to register interface (read)
10995 .qs (cmd_info_2_read_pipeline_mode_2_qs)
10996 );
10997
10998 // F[upload_2]: 24:24
10999 prim_subreg #(
11000 .DW (1),
11001 .SwAccess(prim_subreg_pkg::SwAccessRW),
11002 .RESVAL (1'h0),
11003 .Mubi (1'b0)
11004 ) u_cmd_info_2_upload_2 (
11005 .clk_i (clk_i),
11006 .rst_ni (rst_ni),
11007
11008 // from register interface
11009 .we (cmd_info_2_we),
11010 .wd (cmd_info_2_upload_2_wd),
11011
11012 // from internal hardware
11013 .de (1'b0),
11014 .d ('0),
11015
11016 // to internal hardware
11017 .qe (),
11018 .q (reg2hw.cmd_info[2].upload.q),
11019 .ds (),
11020
11021 // to register interface (read)
11022 .qs (cmd_info_2_upload_2_qs)
11023 );
11024
11025 // F[busy_2]: 25:25
11026 prim_subreg #(
11027 .DW (1),
11028 .SwAccess(prim_subreg_pkg::SwAccessRW),
11029 .RESVAL (1'h0),
11030 .Mubi (1'b0)
11031 ) u_cmd_info_2_busy_2 (
11032 .clk_i (clk_i),
11033 .rst_ni (rst_ni),
11034
11035 // from register interface
11036 .we (cmd_info_2_we),
11037 .wd (cmd_info_2_busy_2_wd),
11038
11039 // from internal hardware
11040 .de (1'b0),
11041 .d ('0),
11042
11043 // to internal hardware
11044 .qe (),
11045 .q (reg2hw.cmd_info[2].busy.q),
11046 .ds (),
11047
11048 // to register interface (read)
11049 .qs (cmd_info_2_busy_2_qs)
11050 );
11051
11052 // F[valid_2]: 31:31
11053 prim_subreg #(
11054 .DW (1),
11055 .SwAccess(prim_subreg_pkg::SwAccessRW),
11056 .RESVAL (1'h0),
11057 .Mubi (1'b0)
11058 ) u_cmd_info_2_valid_2 (
11059 .clk_i (clk_i),
11060 .rst_ni (rst_ni),
11061
11062 // from register interface
11063 .we (cmd_info_2_we),
11064 .wd (cmd_info_2_valid_2_wd),
11065
11066 // from internal hardware
11067 .de (1'b0),
11068 .d ('0),
11069
11070 // to internal hardware
11071 .qe (),
11072 .q (reg2hw.cmd_info[2].valid.q),
11073 .ds (),
11074
11075 // to register interface (read)
11076 .qs (cmd_info_2_valid_2_qs)
11077 );
11078
11079
11080 // Subregister 3 of Multireg cmd_info
11081 // R[cmd_info_3]: V(False)
11082 // F[opcode_3]: 7:0
11083 prim_subreg #(
11084 .DW (8),
11085 .SwAccess(prim_subreg_pkg::SwAccessRW),
11086 .RESVAL (8'h0),
11087 .Mubi (1'b0)
11088 ) u_cmd_info_3_opcode_3 (
11089 .clk_i (clk_i),
11090 .rst_ni (rst_ni),
11091
11092 // from register interface
11093 .we (cmd_info_3_we),
11094 .wd (cmd_info_3_opcode_3_wd),
11095
11096 // from internal hardware
11097 .de (1'b0),
11098 .d ('0),
11099
11100 // to internal hardware
11101 .qe (),
11102 .q (reg2hw.cmd_info[3].opcode.q),
11103 .ds (),
11104
11105 // to register interface (read)
11106 .qs (cmd_info_3_opcode_3_qs)
11107 );
11108
11109 // F[addr_mode_3]: 9:8
11110 prim_subreg #(
11111 .DW (2),
11112 .SwAccess(prim_subreg_pkg::SwAccessRW),
11113 .RESVAL (2'h0),
11114 .Mubi (1'b0)
11115 ) u_cmd_info_3_addr_mode_3 (
11116 .clk_i (clk_i),
11117 .rst_ni (rst_ni),
11118
11119 // from register interface
11120 .we (cmd_info_3_we),
11121 .wd (cmd_info_3_addr_mode_3_wd),
11122
11123 // from internal hardware
11124 .de (1'b0),
11125 .d ('0),
11126
11127 // to internal hardware
11128 .qe (),
11129 .q (reg2hw.cmd_info[3].addr_mode.q),
11130 .ds (),
11131
11132 // to register interface (read)
11133 .qs (cmd_info_3_addr_mode_3_qs)
11134 );
11135
11136 // F[addr_swap_en_3]: 10:10
11137 prim_subreg #(
11138 .DW (1),
11139 .SwAccess(prim_subreg_pkg::SwAccessRW),
11140 .RESVAL (1'h0),
11141 .Mubi (1'b0)
11142 ) u_cmd_info_3_addr_swap_en_3 (
11143 .clk_i (clk_i),
11144 .rst_ni (rst_ni),
11145
11146 // from register interface
11147 .we (cmd_info_3_we),
11148 .wd (cmd_info_3_addr_swap_en_3_wd),
11149
11150 // from internal hardware
11151 .de (1'b0),
11152 .d ('0),
11153
11154 // to internal hardware
11155 .qe (),
11156 .q (reg2hw.cmd_info[3].addr_swap_en.q),
11157 .ds (),
11158
11159 // to register interface (read)
11160 .qs (cmd_info_3_addr_swap_en_3_qs)
11161 );
11162
11163 // F[mbyte_en_3]: 11:11
11164 prim_subreg #(
11165 .DW (1),
11166 .SwAccess(prim_subreg_pkg::SwAccessRW),
11167 .RESVAL (1'h0),
11168 .Mubi (1'b0)
11169 ) u_cmd_info_3_mbyte_en_3 (
11170 .clk_i (clk_i),
11171 .rst_ni (rst_ni),
11172
11173 // from register interface
11174 .we (cmd_info_3_we),
11175 .wd (cmd_info_3_mbyte_en_3_wd),
11176
11177 // from internal hardware
11178 .de (1'b0),
11179 .d ('0),
11180
11181 // to internal hardware
11182 .qe (),
11183 .q (reg2hw.cmd_info[3].mbyte_en.q),
11184 .ds (),
11185
11186 // to register interface (read)
11187 .qs (cmd_info_3_mbyte_en_3_qs)
11188 );
11189
11190 // F[dummy_size_3]: 14:12
11191 prim_subreg #(
11192 .DW (3),
11193 .SwAccess(prim_subreg_pkg::SwAccessRW),
11194 .RESVAL (3'h7),
11195 .Mubi (1'b0)
11196 ) u_cmd_info_3_dummy_size_3 (
11197 .clk_i (clk_i),
11198 .rst_ni (rst_ni),
11199
11200 // from register interface
11201 .we (cmd_info_3_we),
11202 .wd (cmd_info_3_dummy_size_3_wd),
11203
11204 // from internal hardware
11205 .de (1'b0),
11206 .d ('0),
11207
11208 // to internal hardware
11209 .qe (),
11210 .q (reg2hw.cmd_info[3].dummy_size.q),
11211 .ds (),
11212
11213 // to register interface (read)
11214 .qs (cmd_info_3_dummy_size_3_qs)
11215 );
11216
11217 // F[dummy_en_3]: 15:15
11218 prim_subreg #(
11219 .DW (1),
11220 .SwAccess(prim_subreg_pkg::SwAccessRW),
11221 .RESVAL (1'h0),
11222 .Mubi (1'b0)
11223 ) u_cmd_info_3_dummy_en_3 (
11224 .clk_i (clk_i),
11225 .rst_ni (rst_ni),
11226
11227 // from register interface
11228 .we (cmd_info_3_we),
11229 .wd (cmd_info_3_dummy_en_3_wd),
11230
11231 // from internal hardware
11232 .de (1'b0),
11233 .d ('0),
11234
11235 // to internal hardware
11236 .qe (),
11237 .q (reg2hw.cmd_info[3].dummy_en.q),
11238 .ds (),
11239
11240 // to register interface (read)
11241 .qs (cmd_info_3_dummy_en_3_qs)
11242 );
11243
11244 // F[payload_en_3]: 19:16
11245 prim_subreg #(
11246 .DW (4),
11247 .SwAccess(prim_subreg_pkg::SwAccessRW),
11248 .RESVAL (4'h0),
11249 .Mubi (1'b0)
11250 ) u_cmd_info_3_payload_en_3 (
11251 .clk_i (clk_i),
11252 .rst_ni (rst_ni),
11253
11254 // from register interface
11255 .we (cmd_info_3_we),
11256 .wd (cmd_info_3_payload_en_3_wd),
11257
11258 // from internal hardware
11259 .de (1'b0),
11260 .d ('0),
11261
11262 // to internal hardware
11263 .qe (),
11264 .q (reg2hw.cmd_info[3].payload_en.q),
11265 .ds (),
11266
11267 // to register interface (read)
11268 .qs (cmd_info_3_payload_en_3_qs)
11269 );
11270
11271 // F[payload_dir_3]: 20:20
11272 prim_subreg #(
11273 .DW (1),
11274 .SwAccess(prim_subreg_pkg::SwAccessRW),
11275 .RESVAL (1'h0),
11276 .Mubi (1'b0)
11277 ) u_cmd_info_3_payload_dir_3 (
11278 .clk_i (clk_i),
11279 .rst_ni (rst_ni),
11280
11281 // from register interface
11282 .we (cmd_info_3_we),
11283 .wd (cmd_info_3_payload_dir_3_wd),
11284
11285 // from internal hardware
11286 .de (1'b0),
11287 .d ('0),
11288
11289 // to internal hardware
11290 .qe (),
11291 .q (reg2hw.cmd_info[3].payload_dir.q),
11292 .ds (),
11293
11294 // to register interface (read)
11295 .qs (cmd_info_3_payload_dir_3_qs)
11296 );
11297
11298 // F[payload_swap_en_3]: 21:21
11299 prim_subreg #(
11300 .DW (1),
11301 .SwAccess(prim_subreg_pkg::SwAccessRW),
11302 .RESVAL (1'h0),
11303 .Mubi (1'b0)
11304 ) u_cmd_info_3_payload_swap_en_3 (
11305 .clk_i (clk_i),
11306 .rst_ni (rst_ni),
11307
11308 // from register interface
11309 .we (cmd_info_3_we),
11310 .wd (cmd_info_3_payload_swap_en_3_wd),
11311
11312 // from internal hardware
11313 .de (1'b0),
11314 .d ('0),
11315
11316 // to internal hardware
11317 .qe (),
11318 .q (reg2hw.cmd_info[3].payload_swap_en.q),
11319 .ds (),
11320
11321 // to register interface (read)
11322 .qs (cmd_info_3_payload_swap_en_3_qs)
11323 );
11324
11325 // F[read_pipeline_mode_3]: 23:22
11326 prim_subreg #(
11327 .DW (2),
11328 .SwAccess(prim_subreg_pkg::SwAccessRW),
11329 .RESVAL (2'h0),
11330 .Mubi (1'b0)
11331 ) u_cmd_info_3_read_pipeline_mode_3 (
11332 .clk_i (clk_i),
11333 .rst_ni (rst_ni),
11334
11335 // from register interface
11336 .we (cmd_info_3_we),
11337 .wd (cmd_info_3_read_pipeline_mode_3_wd),
11338
11339 // from internal hardware
11340 .de (1'b0),
11341 .d ('0),
11342
11343 // to internal hardware
11344 .qe (),
11345 .q (reg2hw.cmd_info[3].read_pipeline_mode.q),
11346 .ds (),
11347
11348 // to register interface (read)
11349 .qs (cmd_info_3_read_pipeline_mode_3_qs)
11350 );
11351
11352 // F[upload_3]: 24:24
11353 prim_subreg #(
11354 .DW (1),
11355 .SwAccess(prim_subreg_pkg::SwAccessRW),
11356 .RESVAL (1'h0),
11357 .Mubi (1'b0)
11358 ) u_cmd_info_3_upload_3 (
11359 .clk_i (clk_i),
11360 .rst_ni (rst_ni),
11361
11362 // from register interface
11363 .we (cmd_info_3_we),
11364 .wd (cmd_info_3_upload_3_wd),
11365
11366 // from internal hardware
11367 .de (1'b0),
11368 .d ('0),
11369
11370 // to internal hardware
11371 .qe (),
11372 .q (reg2hw.cmd_info[3].upload.q),
11373 .ds (),
11374
11375 // to register interface (read)
11376 .qs (cmd_info_3_upload_3_qs)
11377 );
11378
11379 // F[busy_3]: 25:25
11380 prim_subreg #(
11381 .DW (1),
11382 .SwAccess(prim_subreg_pkg::SwAccessRW),
11383 .RESVAL (1'h0),
11384 .Mubi (1'b0)
11385 ) u_cmd_info_3_busy_3 (
11386 .clk_i (clk_i),
11387 .rst_ni (rst_ni),
11388
11389 // from register interface
11390 .we (cmd_info_3_we),
11391 .wd (cmd_info_3_busy_3_wd),
11392
11393 // from internal hardware
11394 .de (1'b0),
11395 .d ('0),
11396
11397 // to internal hardware
11398 .qe (),
11399 .q (reg2hw.cmd_info[3].busy.q),
11400 .ds (),
11401
11402 // to register interface (read)
11403 .qs (cmd_info_3_busy_3_qs)
11404 );
11405
11406 // F[valid_3]: 31:31
11407 prim_subreg #(
11408 .DW (1),
11409 .SwAccess(prim_subreg_pkg::SwAccessRW),
11410 .RESVAL (1'h0),
11411 .Mubi (1'b0)
11412 ) u_cmd_info_3_valid_3 (
11413 .clk_i (clk_i),
11414 .rst_ni (rst_ni),
11415
11416 // from register interface
11417 .we (cmd_info_3_we),
11418 .wd (cmd_info_3_valid_3_wd),
11419
11420 // from internal hardware
11421 .de (1'b0),
11422 .d ('0),
11423
11424 // to internal hardware
11425 .qe (),
11426 .q (reg2hw.cmd_info[3].valid.q),
11427 .ds (),
11428
11429 // to register interface (read)
11430 .qs (cmd_info_3_valid_3_qs)
11431 );
11432
11433
11434 // Subregister 4 of Multireg cmd_info
11435 // R[cmd_info_4]: V(False)
11436 // F[opcode_4]: 7:0
11437 prim_subreg #(
11438 .DW (8),
11439 .SwAccess(prim_subreg_pkg::SwAccessRW),
11440 .RESVAL (8'h0),
11441 .Mubi (1'b0)
11442 ) u_cmd_info_4_opcode_4 (
11443 .clk_i (clk_i),
11444 .rst_ni (rst_ni),
11445
11446 // from register interface
11447 .we (cmd_info_4_we),
11448 .wd (cmd_info_4_opcode_4_wd),
11449
11450 // from internal hardware
11451 .de (1'b0),
11452 .d ('0),
11453
11454 // to internal hardware
11455 .qe (),
11456 .q (reg2hw.cmd_info[4].opcode.q),
11457 .ds (),
11458
11459 // to register interface (read)
11460 .qs (cmd_info_4_opcode_4_qs)
11461 );
11462
11463 // F[addr_mode_4]: 9:8
11464 prim_subreg #(
11465 .DW (2),
11466 .SwAccess(prim_subreg_pkg::SwAccessRW),
11467 .RESVAL (2'h0),
11468 .Mubi (1'b0)
11469 ) u_cmd_info_4_addr_mode_4 (
11470 .clk_i (clk_i),
11471 .rst_ni (rst_ni),
11472
11473 // from register interface
11474 .we (cmd_info_4_we),
11475 .wd (cmd_info_4_addr_mode_4_wd),
11476
11477 // from internal hardware
11478 .de (1'b0),
11479 .d ('0),
11480
11481 // to internal hardware
11482 .qe (),
11483 .q (reg2hw.cmd_info[4].addr_mode.q),
11484 .ds (),
11485
11486 // to register interface (read)
11487 .qs (cmd_info_4_addr_mode_4_qs)
11488 );
11489
11490 // F[addr_swap_en_4]: 10:10
11491 prim_subreg #(
11492 .DW (1),
11493 .SwAccess(prim_subreg_pkg::SwAccessRW),
11494 .RESVAL (1'h0),
11495 .Mubi (1'b0)
11496 ) u_cmd_info_4_addr_swap_en_4 (
11497 .clk_i (clk_i),
11498 .rst_ni (rst_ni),
11499
11500 // from register interface
11501 .we (cmd_info_4_we),
11502 .wd (cmd_info_4_addr_swap_en_4_wd),
11503
11504 // from internal hardware
11505 .de (1'b0),
11506 .d ('0),
11507
11508 // to internal hardware
11509 .qe (),
11510 .q (reg2hw.cmd_info[4].addr_swap_en.q),
11511 .ds (),
11512
11513 // to register interface (read)
11514 .qs (cmd_info_4_addr_swap_en_4_qs)
11515 );
11516
11517 // F[mbyte_en_4]: 11:11
11518 prim_subreg #(
11519 .DW (1),
11520 .SwAccess(prim_subreg_pkg::SwAccessRW),
11521 .RESVAL (1'h0),
11522 .Mubi (1'b0)
11523 ) u_cmd_info_4_mbyte_en_4 (
11524 .clk_i (clk_i),
11525 .rst_ni (rst_ni),
11526
11527 // from register interface
11528 .we (cmd_info_4_we),
11529 .wd (cmd_info_4_mbyte_en_4_wd),
11530
11531 // from internal hardware
11532 .de (1'b0),
11533 .d ('0),
11534
11535 // to internal hardware
11536 .qe (),
11537 .q (reg2hw.cmd_info[4].mbyte_en.q),
11538 .ds (),
11539
11540 // to register interface (read)
11541 .qs (cmd_info_4_mbyte_en_4_qs)
11542 );
11543
11544 // F[dummy_size_4]: 14:12
11545 prim_subreg #(
11546 .DW (3),
11547 .SwAccess(prim_subreg_pkg::SwAccessRW),
11548 .RESVAL (3'h7),
11549 .Mubi (1'b0)
11550 ) u_cmd_info_4_dummy_size_4 (
11551 .clk_i (clk_i),
11552 .rst_ni (rst_ni),
11553
11554 // from register interface
11555 .we (cmd_info_4_we),
11556 .wd (cmd_info_4_dummy_size_4_wd),
11557
11558 // from internal hardware
11559 .de (1'b0),
11560 .d ('0),
11561
11562 // to internal hardware
11563 .qe (),
11564 .q (reg2hw.cmd_info[4].dummy_size.q),
11565 .ds (),
11566
11567 // to register interface (read)
11568 .qs (cmd_info_4_dummy_size_4_qs)
11569 );
11570
11571 // F[dummy_en_4]: 15:15
11572 prim_subreg #(
11573 .DW (1),
11574 .SwAccess(prim_subreg_pkg::SwAccessRW),
11575 .RESVAL (1'h0),
11576 .Mubi (1'b0)
11577 ) u_cmd_info_4_dummy_en_4 (
11578 .clk_i (clk_i),
11579 .rst_ni (rst_ni),
11580
11581 // from register interface
11582 .we (cmd_info_4_we),
11583 .wd (cmd_info_4_dummy_en_4_wd),
11584
11585 // from internal hardware
11586 .de (1'b0),
11587 .d ('0),
11588
11589 // to internal hardware
11590 .qe (),
11591 .q (reg2hw.cmd_info[4].dummy_en.q),
11592 .ds (),
11593
11594 // to register interface (read)
11595 .qs (cmd_info_4_dummy_en_4_qs)
11596 );
11597
11598 // F[payload_en_4]: 19:16
11599 prim_subreg #(
11600 .DW (4),
11601 .SwAccess(prim_subreg_pkg::SwAccessRW),
11602 .RESVAL (4'h0),
11603 .Mubi (1'b0)
11604 ) u_cmd_info_4_payload_en_4 (
11605 .clk_i (clk_i),
11606 .rst_ni (rst_ni),
11607
11608 // from register interface
11609 .we (cmd_info_4_we),
11610 .wd (cmd_info_4_payload_en_4_wd),
11611
11612 // from internal hardware
11613 .de (1'b0),
11614 .d ('0),
11615
11616 // to internal hardware
11617 .qe (),
11618 .q (reg2hw.cmd_info[4].payload_en.q),
11619 .ds (),
11620
11621 // to register interface (read)
11622 .qs (cmd_info_4_payload_en_4_qs)
11623 );
11624
11625 // F[payload_dir_4]: 20:20
11626 prim_subreg #(
11627 .DW (1),
11628 .SwAccess(prim_subreg_pkg::SwAccessRW),
11629 .RESVAL (1'h0),
11630 .Mubi (1'b0)
11631 ) u_cmd_info_4_payload_dir_4 (
11632 .clk_i (clk_i),
11633 .rst_ni (rst_ni),
11634
11635 // from register interface
11636 .we (cmd_info_4_we),
11637 .wd (cmd_info_4_payload_dir_4_wd),
11638
11639 // from internal hardware
11640 .de (1'b0),
11641 .d ('0),
11642
11643 // to internal hardware
11644 .qe (),
11645 .q (reg2hw.cmd_info[4].payload_dir.q),
11646 .ds (),
11647
11648 // to register interface (read)
11649 .qs (cmd_info_4_payload_dir_4_qs)
11650 );
11651
11652 // F[payload_swap_en_4]: 21:21
11653 prim_subreg #(
11654 .DW (1),
11655 .SwAccess(prim_subreg_pkg::SwAccessRW),
11656 .RESVAL (1'h0),
11657 .Mubi (1'b0)
11658 ) u_cmd_info_4_payload_swap_en_4 (
11659 .clk_i (clk_i),
11660 .rst_ni (rst_ni),
11661
11662 // from register interface
11663 .we (cmd_info_4_we),
11664 .wd (cmd_info_4_payload_swap_en_4_wd),
11665
11666 // from internal hardware
11667 .de (1'b0),
11668 .d ('0),
11669
11670 // to internal hardware
11671 .qe (),
11672 .q (reg2hw.cmd_info[4].payload_swap_en.q),
11673 .ds (),
11674
11675 // to register interface (read)
11676 .qs (cmd_info_4_payload_swap_en_4_qs)
11677 );
11678
11679 // F[read_pipeline_mode_4]: 23:22
11680 prim_subreg #(
11681 .DW (2),
11682 .SwAccess(prim_subreg_pkg::SwAccessRW),
11683 .RESVAL (2'h0),
11684 .Mubi (1'b0)
11685 ) u_cmd_info_4_read_pipeline_mode_4 (
11686 .clk_i (clk_i),
11687 .rst_ni (rst_ni),
11688
11689 // from register interface
11690 .we (cmd_info_4_we),
11691 .wd (cmd_info_4_read_pipeline_mode_4_wd),
11692
11693 // from internal hardware
11694 .de (1'b0),
11695 .d ('0),
11696
11697 // to internal hardware
11698 .qe (),
11699 .q (reg2hw.cmd_info[4].read_pipeline_mode.q),
11700 .ds (),
11701
11702 // to register interface (read)
11703 .qs (cmd_info_4_read_pipeline_mode_4_qs)
11704 );
11705
11706 // F[upload_4]: 24:24
11707 prim_subreg #(
11708 .DW (1),
11709 .SwAccess(prim_subreg_pkg::SwAccessRW),
11710 .RESVAL (1'h0),
11711 .Mubi (1'b0)
11712 ) u_cmd_info_4_upload_4 (
11713 .clk_i (clk_i),
11714 .rst_ni (rst_ni),
11715
11716 // from register interface
11717 .we (cmd_info_4_we),
11718 .wd (cmd_info_4_upload_4_wd),
11719
11720 // from internal hardware
11721 .de (1'b0),
11722 .d ('0),
11723
11724 // to internal hardware
11725 .qe (),
11726 .q (reg2hw.cmd_info[4].upload.q),
11727 .ds (),
11728
11729 // to register interface (read)
11730 .qs (cmd_info_4_upload_4_qs)
11731 );
11732
11733 // F[busy_4]: 25:25
11734 prim_subreg #(
11735 .DW (1),
11736 .SwAccess(prim_subreg_pkg::SwAccessRW),
11737 .RESVAL (1'h0),
11738 .Mubi (1'b0)
11739 ) u_cmd_info_4_busy_4 (
11740 .clk_i (clk_i),
11741 .rst_ni (rst_ni),
11742
11743 // from register interface
11744 .we (cmd_info_4_we),
11745 .wd (cmd_info_4_busy_4_wd),
11746
11747 // from internal hardware
11748 .de (1'b0),
11749 .d ('0),
11750
11751 // to internal hardware
11752 .qe (),
11753 .q (reg2hw.cmd_info[4].busy.q),
11754 .ds (),
11755
11756 // to register interface (read)
11757 .qs (cmd_info_4_busy_4_qs)
11758 );
11759
11760 // F[valid_4]: 31:31
11761 prim_subreg #(
11762 .DW (1),
11763 .SwAccess(prim_subreg_pkg::SwAccessRW),
11764 .RESVAL (1'h0),
11765 .Mubi (1'b0)
11766 ) u_cmd_info_4_valid_4 (
11767 .clk_i (clk_i),
11768 .rst_ni (rst_ni),
11769
11770 // from register interface
11771 .we (cmd_info_4_we),
11772 .wd (cmd_info_4_valid_4_wd),
11773
11774 // from internal hardware
11775 .de (1'b0),
11776 .d ('0),
11777
11778 // to internal hardware
11779 .qe (),
11780 .q (reg2hw.cmd_info[4].valid.q),
11781 .ds (),
11782
11783 // to register interface (read)
11784 .qs (cmd_info_4_valid_4_qs)
11785 );
11786
11787
11788 // Subregister 5 of Multireg cmd_info
11789 // R[cmd_info_5]: V(False)
11790 // F[opcode_5]: 7:0
11791 prim_subreg #(
11792 .DW (8),
11793 .SwAccess(prim_subreg_pkg::SwAccessRW),
11794 .RESVAL (8'h0),
11795 .Mubi (1'b0)
11796 ) u_cmd_info_5_opcode_5 (
11797 .clk_i (clk_i),
11798 .rst_ni (rst_ni),
11799
11800 // from register interface
11801 .we (cmd_info_5_we),
11802 .wd (cmd_info_5_opcode_5_wd),
11803
11804 // from internal hardware
11805 .de (1'b0),
11806 .d ('0),
11807
11808 // to internal hardware
11809 .qe (),
11810 .q (reg2hw.cmd_info[5].opcode.q),
11811 .ds (),
11812
11813 // to register interface (read)
11814 .qs (cmd_info_5_opcode_5_qs)
11815 );
11816
11817 // F[addr_mode_5]: 9:8
11818 prim_subreg #(
11819 .DW (2),
11820 .SwAccess(prim_subreg_pkg::SwAccessRW),
11821 .RESVAL (2'h0),
11822 .Mubi (1'b0)
11823 ) u_cmd_info_5_addr_mode_5 (
11824 .clk_i (clk_i),
11825 .rst_ni (rst_ni),
11826
11827 // from register interface
11828 .we (cmd_info_5_we),
11829 .wd (cmd_info_5_addr_mode_5_wd),
11830
11831 // from internal hardware
11832 .de (1'b0),
11833 .d ('0),
11834
11835 // to internal hardware
11836 .qe (),
11837 .q (reg2hw.cmd_info[5].addr_mode.q),
11838 .ds (),
11839
11840 // to register interface (read)
11841 .qs (cmd_info_5_addr_mode_5_qs)
11842 );
11843
11844 // F[addr_swap_en_5]: 10:10
11845 prim_subreg #(
11846 .DW (1),
11847 .SwAccess(prim_subreg_pkg::SwAccessRW),
11848 .RESVAL (1'h0),
11849 .Mubi (1'b0)
11850 ) u_cmd_info_5_addr_swap_en_5 (
11851 .clk_i (clk_i),
11852 .rst_ni (rst_ni),
11853
11854 // from register interface
11855 .we (cmd_info_5_we),
11856 .wd (cmd_info_5_addr_swap_en_5_wd),
11857
11858 // from internal hardware
11859 .de (1'b0),
11860 .d ('0),
11861
11862 // to internal hardware
11863 .qe (),
11864 .q (reg2hw.cmd_info[5].addr_swap_en.q),
11865 .ds (),
11866
11867 // to register interface (read)
11868 .qs (cmd_info_5_addr_swap_en_5_qs)
11869 );
11870
11871 // F[mbyte_en_5]: 11:11
11872 prim_subreg #(
11873 .DW (1),
11874 .SwAccess(prim_subreg_pkg::SwAccessRW),
11875 .RESVAL (1'h0),
11876 .Mubi (1'b0)
11877 ) u_cmd_info_5_mbyte_en_5 (
11878 .clk_i (clk_i),
11879 .rst_ni (rst_ni),
11880
11881 // from register interface
11882 .we (cmd_info_5_we),
11883 .wd (cmd_info_5_mbyte_en_5_wd),
11884
11885 // from internal hardware
11886 .de (1'b0),
11887 .d ('0),
11888
11889 // to internal hardware
11890 .qe (),
11891 .q (reg2hw.cmd_info[5].mbyte_en.q),
11892 .ds (),
11893
11894 // to register interface (read)
11895 .qs (cmd_info_5_mbyte_en_5_qs)
11896 );
11897
11898 // F[dummy_size_5]: 14:12
11899 prim_subreg #(
11900 .DW (3),
11901 .SwAccess(prim_subreg_pkg::SwAccessRW),
11902 .RESVAL (3'h7),
11903 .Mubi (1'b0)
11904 ) u_cmd_info_5_dummy_size_5 (
11905 .clk_i (clk_i),
11906 .rst_ni (rst_ni),
11907
11908 // from register interface
11909 .we (cmd_info_5_we),
11910 .wd (cmd_info_5_dummy_size_5_wd),
11911
11912 // from internal hardware
11913 .de (1'b0),
11914 .d ('0),
11915
11916 // to internal hardware
11917 .qe (),
11918 .q (reg2hw.cmd_info[5].dummy_size.q),
11919 .ds (),
11920
11921 // to register interface (read)
11922 .qs (cmd_info_5_dummy_size_5_qs)
11923 );
11924
11925 // F[dummy_en_5]: 15:15
11926 prim_subreg #(
11927 .DW (1),
11928 .SwAccess(prim_subreg_pkg::SwAccessRW),
11929 .RESVAL (1'h0),
11930 .Mubi (1'b0)
11931 ) u_cmd_info_5_dummy_en_5 (
11932 .clk_i (clk_i),
11933 .rst_ni (rst_ni),
11934
11935 // from register interface
11936 .we (cmd_info_5_we),
11937 .wd (cmd_info_5_dummy_en_5_wd),
11938
11939 // from internal hardware
11940 .de (1'b0),
11941 .d ('0),
11942
11943 // to internal hardware
11944 .qe (),
11945 .q (reg2hw.cmd_info[5].dummy_en.q),
11946 .ds (),
11947
11948 // to register interface (read)
11949 .qs (cmd_info_5_dummy_en_5_qs)
11950 );
11951
11952 // F[payload_en_5]: 19:16
11953 prim_subreg #(
11954 .DW (4),
11955 .SwAccess(prim_subreg_pkg::SwAccessRW),
11956 .RESVAL (4'h0),
11957 .Mubi (1'b0)
11958 ) u_cmd_info_5_payload_en_5 (
11959 .clk_i (clk_i),
11960 .rst_ni (rst_ni),
11961
11962 // from register interface
11963 .we (cmd_info_5_we),
11964 .wd (cmd_info_5_payload_en_5_wd),
11965
11966 // from internal hardware
11967 .de (1'b0),
11968 .d ('0),
11969
11970 // to internal hardware
11971 .qe (),
11972 .q (reg2hw.cmd_info[5].payload_en.q),
11973 .ds (),
11974
11975 // to register interface (read)
11976 .qs (cmd_info_5_payload_en_5_qs)
11977 );
11978
11979 // F[payload_dir_5]: 20:20
11980 prim_subreg #(
11981 .DW (1),
11982 .SwAccess(prim_subreg_pkg::SwAccessRW),
11983 .RESVAL (1'h0),
11984 .Mubi (1'b0)
11985 ) u_cmd_info_5_payload_dir_5 (
11986 .clk_i (clk_i),
11987 .rst_ni (rst_ni),
11988
11989 // from register interface
11990 .we (cmd_info_5_we),
11991 .wd (cmd_info_5_payload_dir_5_wd),
11992
11993 // from internal hardware
11994 .de (1'b0),
11995 .d ('0),
11996
11997 // to internal hardware
11998 .qe (),
11999 .q (reg2hw.cmd_info[5].payload_dir.q),
12000 .ds (),
12001
12002 // to register interface (read)
12003 .qs (cmd_info_5_payload_dir_5_qs)
12004 );
12005
12006 // F[payload_swap_en_5]: 21:21
12007 prim_subreg #(
12008 .DW (1),
12009 .SwAccess(prim_subreg_pkg::SwAccessRW),
12010 .RESVAL (1'h0),
12011 .Mubi (1'b0)
12012 ) u_cmd_info_5_payload_swap_en_5 (
12013 .clk_i (clk_i),
12014 .rst_ni (rst_ni),
12015
12016 // from register interface
12017 .we (cmd_info_5_we),
12018 .wd (cmd_info_5_payload_swap_en_5_wd),
12019
12020 // from internal hardware
12021 .de (1'b0),
12022 .d ('0),
12023
12024 // to internal hardware
12025 .qe (),
12026 .q (reg2hw.cmd_info[5].payload_swap_en.q),
12027 .ds (),
12028
12029 // to register interface (read)
12030 .qs (cmd_info_5_payload_swap_en_5_qs)
12031 );
12032
12033 // F[read_pipeline_mode_5]: 23:22
12034 prim_subreg #(
12035 .DW (2),
12036 .SwAccess(prim_subreg_pkg::SwAccessRW),
12037 .RESVAL (2'h0),
12038 .Mubi (1'b0)
12039 ) u_cmd_info_5_read_pipeline_mode_5 (
12040 .clk_i (clk_i),
12041 .rst_ni (rst_ni),
12042
12043 // from register interface
12044 .we (cmd_info_5_we),
12045 .wd (cmd_info_5_read_pipeline_mode_5_wd),
12046
12047 // from internal hardware
12048 .de (1'b0),
12049 .d ('0),
12050
12051 // to internal hardware
12052 .qe (),
12053 .q (reg2hw.cmd_info[5].read_pipeline_mode.q),
12054 .ds (),
12055
12056 // to register interface (read)
12057 .qs (cmd_info_5_read_pipeline_mode_5_qs)
12058 );
12059
12060 // F[upload_5]: 24:24
12061 prim_subreg #(
12062 .DW (1),
12063 .SwAccess(prim_subreg_pkg::SwAccessRW),
12064 .RESVAL (1'h0),
12065 .Mubi (1'b0)
12066 ) u_cmd_info_5_upload_5 (
12067 .clk_i (clk_i),
12068 .rst_ni (rst_ni),
12069
12070 // from register interface
12071 .we (cmd_info_5_we),
12072 .wd (cmd_info_5_upload_5_wd),
12073
12074 // from internal hardware
12075 .de (1'b0),
12076 .d ('0),
12077
12078 // to internal hardware
12079 .qe (),
12080 .q (reg2hw.cmd_info[5].upload.q),
12081 .ds (),
12082
12083 // to register interface (read)
12084 .qs (cmd_info_5_upload_5_qs)
12085 );
12086
12087 // F[busy_5]: 25:25
12088 prim_subreg #(
12089 .DW (1),
12090 .SwAccess(prim_subreg_pkg::SwAccessRW),
12091 .RESVAL (1'h0),
12092 .Mubi (1'b0)
12093 ) u_cmd_info_5_busy_5 (
12094 .clk_i (clk_i),
12095 .rst_ni (rst_ni),
12096
12097 // from register interface
12098 .we (cmd_info_5_we),
12099 .wd (cmd_info_5_busy_5_wd),
12100
12101 // from internal hardware
12102 .de (1'b0),
12103 .d ('0),
12104
12105 // to internal hardware
12106 .qe (),
12107 .q (reg2hw.cmd_info[5].busy.q),
12108 .ds (),
12109
12110 // to register interface (read)
12111 .qs (cmd_info_5_busy_5_qs)
12112 );
12113
12114 // F[valid_5]: 31:31
12115 prim_subreg #(
12116 .DW (1),
12117 .SwAccess(prim_subreg_pkg::SwAccessRW),
12118 .RESVAL (1'h0),
12119 .Mubi (1'b0)
12120 ) u_cmd_info_5_valid_5 (
12121 .clk_i (clk_i),
12122 .rst_ni (rst_ni),
12123
12124 // from register interface
12125 .we (cmd_info_5_we),
12126 .wd (cmd_info_5_valid_5_wd),
12127
12128 // from internal hardware
12129 .de (1'b0),
12130 .d ('0),
12131
12132 // to internal hardware
12133 .qe (),
12134 .q (reg2hw.cmd_info[5].valid.q),
12135 .ds (),
12136
12137 // to register interface (read)
12138 .qs (cmd_info_5_valid_5_qs)
12139 );
12140
12141
12142 // Subregister 6 of Multireg cmd_info
12143 // R[cmd_info_6]: V(False)
12144 // F[opcode_6]: 7:0
12145 prim_subreg #(
12146 .DW (8),
12147 .SwAccess(prim_subreg_pkg::SwAccessRW),
12148 .RESVAL (8'h0),
12149 .Mubi (1'b0)
12150 ) u_cmd_info_6_opcode_6 (
12151 .clk_i (clk_i),
12152 .rst_ni (rst_ni),
12153
12154 // from register interface
12155 .we (cmd_info_6_we),
12156 .wd (cmd_info_6_opcode_6_wd),
12157
12158 // from internal hardware
12159 .de (1'b0),
12160 .d ('0),
12161
12162 // to internal hardware
12163 .qe (),
12164 .q (reg2hw.cmd_info[6].opcode.q),
12165 .ds (),
12166
12167 // to register interface (read)
12168 .qs (cmd_info_6_opcode_6_qs)
12169 );
12170
12171 // F[addr_mode_6]: 9:8
12172 prim_subreg #(
12173 .DW (2),
12174 .SwAccess(prim_subreg_pkg::SwAccessRW),
12175 .RESVAL (2'h0),
12176 .Mubi (1'b0)
12177 ) u_cmd_info_6_addr_mode_6 (
12178 .clk_i (clk_i),
12179 .rst_ni (rst_ni),
12180
12181 // from register interface
12182 .we (cmd_info_6_we),
12183 .wd (cmd_info_6_addr_mode_6_wd),
12184
12185 // from internal hardware
12186 .de (1'b0),
12187 .d ('0),
12188
12189 // to internal hardware
12190 .qe (),
12191 .q (reg2hw.cmd_info[6].addr_mode.q),
12192 .ds (),
12193
12194 // to register interface (read)
12195 .qs (cmd_info_6_addr_mode_6_qs)
12196 );
12197
12198 // F[addr_swap_en_6]: 10:10
12199 prim_subreg #(
12200 .DW (1),
12201 .SwAccess(prim_subreg_pkg::SwAccessRW),
12202 .RESVAL (1'h0),
12203 .Mubi (1'b0)
12204 ) u_cmd_info_6_addr_swap_en_6 (
12205 .clk_i (clk_i),
12206 .rst_ni (rst_ni),
12207
12208 // from register interface
12209 .we (cmd_info_6_we),
12210 .wd (cmd_info_6_addr_swap_en_6_wd),
12211
12212 // from internal hardware
12213 .de (1'b0),
12214 .d ('0),
12215
12216 // to internal hardware
12217 .qe (),
12218 .q (reg2hw.cmd_info[6].addr_swap_en.q),
12219 .ds (),
12220
12221 // to register interface (read)
12222 .qs (cmd_info_6_addr_swap_en_6_qs)
12223 );
12224
12225 // F[mbyte_en_6]: 11:11
12226 prim_subreg #(
12227 .DW (1),
12228 .SwAccess(prim_subreg_pkg::SwAccessRW),
12229 .RESVAL (1'h0),
12230 .Mubi (1'b0)
12231 ) u_cmd_info_6_mbyte_en_6 (
12232 .clk_i (clk_i),
12233 .rst_ni (rst_ni),
12234
12235 // from register interface
12236 .we (cmd_info_6_we),
12237 .wd (cmd_info_6_mbyte_en_6_wd),
12238
12239 // from internal hardware
12240 .de (1'b0),
12241 .d ('0),
12242
12243 // to internal hardware
12244 .qe (),
12245 .q (reg2hw.cmd_info[6].mbyte_en.q),
12246 .ds (),
12247
12248 // to register interface (read)
12249 .qs (cmd_info_6_mbyte_en_6_qs)
12250 );
12251
12252 // F[dummy_size_6]: 14:12
12253 prim_subreg #(
12254 .DW (3),
12255 .SwAccess(prim_subreg_pkg::SwAccessRW),
12256 .RESVAL (3'h7),
12257 .Mubi (1'b0)
12258 ) u_cmd_info_6_dummy_size_6 (
12259 .clk_i (clk_i),
12260 .rst_ni (rst_ni),
12261
12262 // from register interface
12263 .we (cmd_info_6_we),
12264 .wd (cmd_info_6_dummy_size_6_wd),
12265
12266 // from internal hardware
12267 .de (1'b0),
12268 .d ('0),
12269
12270 // to internal hardware
12271 .qe (),
12272 .q (reg2hw.cmd_info[6].dummy_size.q),
12273 .ds (),
12274
12275 // to register interface (read)
12276 .qs (cmd_info_6_dummy_size_6_qs)
12277 );
12278
12279 // F[dummy_en_6]: 15:15
12280 prim_subreg #(
12281 .DW (1),
12282 .SwAccess(prim_subreg_pkg::SwAccessRW),
12283 .RESVAL (1'h0),
12284 .Mubi (1'b0)
12285 ) u_cmd_info_6_dummy_en_6 (
12286 .clk_i (clk_i),
12287 .rst_ni (rst_ni),
12288
12289 // from register interface
12290 .we (cmd_info_6_we),
12291 .wd (cmd_info_6_dummy_en_6_wd),
12292
12293 // from internal hardware
12294 .de (1'b0),
12295 .d ('0),
12296
12297 // to internal hardware
12298 .qe (),
12299 .q (reg2hw.cmd_info[6].dummy_en.q),
12300 .ds (),
12301
12302 // to register interface (read)
12303 .qs (cmd_info_6_dummy_en_6_qs)
12304 );
12305
12306 // F[payload_en_6]: 19:16
12307 prim_subreg #(
12308 .DW (4),
12309 .SwAccess(prim_subreg_pkg::SwAccessRW),
12310 .RESVAL (4'h0),
12311 .Mubi (1'b0)
12312 ) u_cmd_info_6_payload_en_6 (
12313 .clk_i (clk_i),
12314 .rst_ni (rst_ni),
12315
12316 // from register interface
12317 .we (cmd_info_6_we),
12318 .wd (cmd_info_6_payload_en_6_wd),
12319
12320 // from internal hardware
12321 .de (1'b0),
12322 .d ('0),
12323
12324 // to internal hardware
12325 .qe (),
12326 .q (reg2hw.cmd_info[6].payload_en.q),
12327 .ds (),
12328
12329 // to register interface (read)
12330 .qs (cmd_info_6_payload_en_6_qs)
12331 );
12332
12333 // F[payload_dir_6]: 20:20
12334 prim_subreg #(
12335 .DW (1),
12336 .SwAccess(prim_subreg_pkg::SwAccessRW),
12337 .RESVAL (1'h0),
12338 .Mubi (1'b0)
12339 ) u_cmd_info_6_payload_dir_6 (
12340 .clk_i (clk_i),
12341 .rst_ni (rst_ni),
12342
12343 // from register interface
12344 .we (cmd_info_6_we),
12345 .wd (cmd_info_6_payload_dir_6_wd),
12346
12347 // from internal hardware
12348 .de (1'b0),
12349 .d ('0),
12350
12351 // to internal hardware
12352 .qe (),
12353 .q (reg2hw.cmd_info[6].payload_dir.q),
12354 .ds (),
12355
12356 // to register interface (read)
12357 .qs (cmd_info_6_payload_dir_6_qs)
12358 );
12359
12360 // F[payload_swap_en_6]: 21:21
12361 prim_subreg #(
12362 .DW (1),
12363 .SwAccess(prim_subreg_pkg::SwAccessRW),
12364 .RESVAL (1'h0),
12365 .Mubi (1'b0)
12366 ) u_cmd_info_6_payload_swap_en_6 (
12367 .clk_i (clk_i),
12368 .rst_ni (rst_ni),
12369
12370 // from register interface
12371 .we (cmd_info_6_we),
12372 .wd (cmd_info_6_payload_swap_en_6_wd),
12373
12374 // from internal hardware
12375 .de (1'b0),
12376 .d ('0),
12377
12378 // to internal hardware
12379 .qe (),
12380 .q (reg2hw.cmd_info[6].payload_swap_en.q),
12381 .ds (),
12382
12383 // to register interface (read)
12384 .qs (cmd_info_6_payload_swap_en_6_qs)
12385 );
12386
12387 // F[read_pipeline_mode_6]: 23:22
12388 prim_subreg #(
12389 .DW (2),
12390 .SwAccess(prim_subreg_pkg::SwAccessRW),
12391 .RESVAL (2'h0),
12392 .Mubi (1'b0)
12393 ) u_cmd_info_6_read_pipeline_mode_6 (
12394 .clk_i (clk_i),
12395 .rst_ni (rst_ni),
12396
12397 // from register interface
12398 .we (cmd_info_6_we),
12399 .wd (cmd_info_6_read_pipeline_mode_6_wd),
12400
12401 // from internal hardware
12402 .de (1'b0),
12403 .d ('0),
12404
12405 // to internal hardware
12406 .qe (),
12407 .q (reg2hw.cmd_info[6].read_pipeline_mode.q),
12408 .ds (),
12409
12410 // to register interface (read)
12411 .qs (cmd_info_6_read_pipeline_mode_6_qs)
12412 );
12413
12414 // F[upload_6]: 24:24
12415 prim_subreg #(
12416 .DW (1),
12417 .SwAccess(prim_subreg_pkg::SwAccessRW),
12418 .RESVAL (1'h0),
12419 .Mubi (1'b0)
12420 ) u_cmd_info_6_upload_6 (
12421 .clk_i (clk_i),
12422 .rst_ni (rst_ni),
12423
12424 // from register interface
12425 .we (cmd_info_6_we),
12426 .wd (cmd_info_6_upload_6_wd),
12427
12428 // from internal hardware
12429 .de (1'b0),
12430 .d ('0),
12431
12432 // to internal hardware
12433 .qe (),
12434 .q (reg2hw.cmd_info[6].upload.q),
12435 .ds (),
12436
12437 // to register interface (read)
12438 .qs (cmd_info_6_upload_6_qs)
12439 );
12440
12441 // F[busy_6]: 25:25
12442 prim_subreg #(
12443 .DW (1),
12444 .SwAccess(prim_subreg_pkg::SwAccessRW),
12445 .RESVAL (1'h0),
12446 .Mubi (1'b0)
12447 ) u_cmd_info_6_busy_6 (
12448 .clk_i (clk_i),
12449 .rst_ni (rst_ni),
12450
12451 // from register interface
12452 .we (cmd_info_6_we),
12453 .wd (cmd_info_6_busy_6_wd),
12454
12455 // from internal hardware
12456 .de (1'b0),
12457 .d ('0),
12458
12459 // to internal hardware
12460 .qe (),
12461 .q (reg2hw.cmd_info[6].busy.q),
12462 .ds (),
12463
12464 // to register interface (read)
12465 .qs (cmd_info_6_busy_6_qs)
12466 );
12467
12468 // F[valid_6]: 31:31
12469 prim_subreg #(
12470 .DW (1),
12471 .SwAccess(prim_subreg_pkg::SwAccessRW),
12472 .RESVAL (1'h0),
12473 .Mubi (1'b0)
12474 ) u_cmd_info_6_valid_6 (
12475 .clk_i (clk_i),
12476 .rst_ni (rst_ni),
12477
12478 // from register interface
12479 .we (cmd_info_6_we),
12480 .wd (cmd_info_6_valid_6_wd),
12481
12482 // from internal hardware
12483 .de (1'b0),
12484 .d ('0),
12485
12486 // to internal hardware
12487 .qe (),
12488 .q (reg2hw.cmd_info[6].valid.q),
12489 .ds (),
12490
12491 // to register interface (read)
12492 .qs (cmd_info_6_valid_6_qs)
12493 );
12494
12495
12496 // Subregister 7 of Multireg cmd_info
12497 // R[cmd_info_7]: V(False)
12498 // F[opcode_7]: 7:0
12499 prim_subreg #(
12500 .DW (8),
12501 .SwAccess(prim_subreg_pkg::SwAccessRW),
12502 .RESVAL (8'h0),
12503 .Mubi (1'b0)
12504 ) u_cmd_info_7_opcode_7 (
12505 .clk_i (clk_i),
12506 .rst_ni (rst_ni),
12507
12508 // from register interface
12509 .we (cmd_info_7_we),
12510 .wd (cmd_info_7_opcode_7_wd),
12511
12512 // from internal hardware
12513 .de (1'b0),
12514 .d ('0),
12515
12516 // to internal hardware
12517 .qe (),
12518 .q (reg2hw.cmd_info[7].opcode.q),
12519 .ds (),
12520
12521 // to register interface (read)
12522 .qs (cmd_info_7_opcode_7_qs)
12523 );
12524
12525 // F[addr_mode_7]: 9:8
12526 prim_subreg #(
12527 .DW (2),
12528 .SwAccess(prim_subreg_pkg::SwAccessRW),
12529 .RESVAL (2'h0),
12530 .Mubi (1'b0)
12531 ) u_cmd_info_7_addr_mode_7 (
12532 .clk_i (clk_i),
12533 .rst_ni (rst_ni),
12534
12535 // from register interface
12536 .we (cmd_info_7_we),
12537 .wd (cmd_info_7_addr_mode_7_wd),
12538
12539 // from internal hardware
12540 .de (1'b0),
12541 .d ('0),
12542
12543 // to internal hardware
12544 .qe (),
12545 .q (reg2hw.cmd_info[7].addr_mode.q),
12546 .ds (),
12547
12548 // to register interface (read)
12549 .qs (cmd_info_7_addr_mode_7_qs)
12550 );
12551
12552 // F[addr_swap_en_7]: 10:10
12553 prim_subreg #(
12554 .DW (1),
12555 .SwAccess(prim_subreg_pkg::SwAccessRW),
12556 .RESVAL (1'h0),
12557 .Mubi (1'b0)
12558 ) u_cmd_info_7_addr_swap_en_7 (
12559 .clk_i (clk_i),
12560 .rst_ni (rst_ni),
12561
12562 // from register interface
12563 .we (cmd_info_7_we),
12564 .wd (cmd_info_7_addr_swap_en_7_wd),
12565
12566 // from internal hardware
12567 .de (1'b0),
12568 .d ('0),
12569
12570 // to internal hardware
12571 .qe (),
12572 .q (reg2hw.cmd_info[7].addr_swap_en.q),
12573 .ds (),
12574
12575 // to register interface (read)
12576 .qs (cmd_info_7_addr_swap_en_7_qs)
12577 );
12578
12579 // F[mbyte_en_7]: 11:11
12580 prim_subreg #(
12581 .DW (1),
12582 .SwAccess(prim_subreg_pkg::SwAccessRW),
12583 .RESVAL (1'h0),
12584 .Mubi (1'b0)
12585 ) u_cmd_info_7_mbyte_en_7 (
12586 .clk_i (clk_i),
12587 .rst_ni (rst_ni),
12588
12589 // from register interface
12590 .we (cmd_info_7_we),
12591 .wd (cmd_info_7_mbyte_en_7_wd),
12592
12593 // from internal hardware
12594 .de (1'b0),
12595 .d ('0),
12596
12597 // to internal hardware
12598 .qe (),
12599 .q (reg2hw.cmd_info[7].mbyte_en.q),
12600 .ds (),
12601
12602 // to register interface (read)
12603 .qs (cmd_info_7_mbyte_en_7_qs)
12604 );
12605
12606 // F[dummy_size_7]: 14:12
12607 prim_subreg #(
12608 .DW (3),
12609 .SwAccess(prim_subreg_pkg::SwAccessRW),
12610 .RESVAL (3'h7),
12611 .Mubi (1'b0)
12612 ) u_cmd_info_7_dummy_size_7 (
12613 .clk_i (clk_i),
12614 .rst_ni (rst_ni),
12615
12616 // from register interface
12617 .we (cmd_info_7_we),
12618 .wd (cmd_info_7_dummy_size_7_wd),
12619
12620 // from internal hardware
12621 .de (1'b0),
12622 .d ('0),
12623
12624 // to internal hardware
12625 .qe (),
12626 .q (reg2hw.cmd_info[7].dummy_size.q),
12627 .ds (),
12628
12629 // to register interface (read)
12630 .qs (cmd_info_7_dummy_size_7_qs)
12631 );
12632
12633 // F[dummy_en_7]: 15:15
12634 prim_subreg #(
12635 .DW (1),
12636 .SwAccess(prim_subreg_pkg::SwAccessRW),
12637 .RESVAL (1'h0),
12638 .Mubi (1'b0)
12639 ) u_cmd_info_7_dummy_en_7 (
12640 .clk_i (clk_i),
12641 .rst_ni (rst_ni),
12642
12643 // from register interface
12644 .we (cmd_info_7_we),
12645 .wd (cmd_info_7_dummy_en_7_wd),
12646
12647 // from internal hardware
12648 .de (1'b0),
12649 .d ('0),
12650
12651 // to internal hardware
12652 .qe (),
12653 .q (reg2hw.cmd_info[7].dummy_en.q),
12654 .ds (),
12655
12656 // to register interface (read)
12657 .qs (cmd_info_7_dummy_en_7_qs)
12658 );
12659
12660 // F[payload_en_7]: 19:16
12661 prim_subreg #(
12662 .DW (4),
12663 .SwAccess(prim_subreg_pkg::SwAccessRW),
12664 .RESVAL (4'h0),
12665 .Mubi (1'b0)
12666 ) u_cmd_info_7_payload_en_7 (
12667 .clk_i (clk_i),
12668 .rst_ni (rst_ni),
12669
12670 // from register interface
12671 .we (cmd_info_7_we),
12672 .wd (cmd_info_7_payload_en_7_wd),
12673
12674 // from internal hardware
12675 .de (1'b0),
12676 .d ('0),
12677
12678 // to internal hardware
12679 .qe (),
12680 .q (reg2hw.cmd_info[7].payload_en.q),
12681 .ds (),
12682
12683 // to register interface (read)
12684 .qs (cmd_info_7_payload_en_7_qs)
12685 );
12686
12687 // F[payload_dir_7]: 20:20
12688 prim_subreg #(
12689 .DW (1),
12690 .SwAccess(prim_subreg_pkg::SwAccessRW),
12691 .RESVAL (1'h0),
12692 .Mubi (1'b0)
12693 ) u_cmd_info_7_payload_dir_7 (
12694 .clk_i (clk_i),
12695 .rst_ni (rst_ni),
12696
12697 // from register interface
12698 .we (cmd_info_7_we),
12699 .wd (cmd_info_7_payload_dir_7_wd),
12700
12701 // from internal hardware
12702 .de (1'b0),
12703 .d ('0),
12704
12705 // to internal hardware
12706 .qe (),
12707 .q (reg2hw.cmd_info[7].payload_dir.q),
12708 .ds (),
12709
12710 // to register interface (read)
12711 .qs (cmd_info_7_payload_dir_7_qs)
12712 );
12713
12714 // F[payload_swap_en_7]: 21:21
12715 prim_subreg #(
12716 .DW (1),
12717 .SwAccess(prim_subreg_pkg::SwAccessRW),
12718 .RESVAL (1'h0),
12719 .Mubi (1'b0)
12720 ) u_cmd_info_7_payload_swap_en_7 (
12721 .clk_i (clk_i),
12722 .rst_ni (rst_ni),
12723
12724 // from register interface
12725 .we (cmd_info_7_we),
12726 .wd (cmd_info_7_payload_swap_en_7_wd),
12727
12728 // from internal hardware
12729 .de (1'b0),
12730 .d ('0),
12731
12732 // to internal hardware
12733 .qe (),
12734 .q (reg2hw.cmd_info[7].payload_swap_en.q),
12735 .ds (),
12736
12737 // to register interface (read)
12738 .qs (cmd_info_7_payload_swap_en_7_qs)
12739 );
12740
12741 // F[read_pipeline_mode_7]: 23:22
12742 prim_subreg #(
12743 .DW (2),
12744 .SwAccess(prim_subreg_pkg::SwAccessRW),
12745 .RESVAL (2'h0),
12746 .Mubi (1'b0)
12747 ) u_cmd_info_7_read_pipeline_mode_7 (
12748 .clk_i (clk_i),
12749 .rst_ni (rst_ni),
12750
12751 // from register interface
12752 .we (cmd_info_7_we),
12753 .wd (cmd_info_7_read_pipeline_mode_7_wd),
12754
12755 // from internal hardware
12756 .de (1'b0),
12757 .d ('0),
12758
12759 // to internal hardware
12760 .qe (),
12761 .q (reg2hw.cmd_info[7].read_pipeline_mode.q),
12762 .ds (),
12763
12764 // to register interface (read)
12765 .qs (cmd_info_7_read_pipeline_mode_7_qs)
12766 );
12767
12768 // F[upload_7]: 24:24
12769 prim_subreg #(
12770 .DW (1),
12771 .SwAccess(prim_subreg_pkg::SwAccessRW),
12772 .RESVAL (1'h0),
12773 .Mubi (1'b0)
12774 ) u_cmd_info_7_upload_7 (
12775 .clk_i (clk_i),
12776 .rst_ni (rst_ni),
12777
12778 // from register interface
12779 .we (cmd_info_7_we),
12780 .wd (cmd_info_7_upload_7_wd),
12781
12782 // from internal hardware
12783 .de (1'b0),
12784 .d ('0),
12785
12786 // to internal hardware
12787 .qe (),
12788 .q (reg2hw.cmd_info[7].upload.q),
12789 .ds (),
12790
12791 // to register interface (read)
12792 .qs (cmd_info_7_upload_7_qs)
12793 );
12794
12795 // F[busy_7]: 25:25
12796 prim_subreg #(
12797 .DW (1),
12798 .SwAccess(prim_subreg_pkg::SwAccessRW),
12799 .RESVAL (1'h0),
12800 .Mubi (1'b0)
12801 ) u_cmd_info_7_busy_7 (
12802 .clk_i (clk_i),
12803 .rst_ni (rst_ni),
12804
12805 // from register interface
12806 .we (cmd_info_7_we),
12807 .wd (cmd_info_7_busy_7_wd),
12808
12809 // from internal hardware
12810 .de (1'b0),
12811 .d ('0),
12812
12813 // to internal hardware
12814 .qe (),
12815 .q (reg2hw.cmd_info[7].busy.q),
12816 .ds (),
12817
12818 // to register interface (read)
12819 .qs (cmd_info_7_busy_7_qs)
12820 );
12821
12822 // F[valid_7]: 31:31
12823 prim_subreg #(
12824 .DW (1),
12825 .SwAccess(prim_subreg_pkg::SwAccessRW),
12826 .RESVAL (1'h0),
12827 .Mubi (1'b0)
12828 ) u_cmd_info_7_valid_7 (
12829 .clk_i (clk_i),
12830 .rst_ni (rst_ni),
12831
12832 // from register interface
12833 .we (cmd_info_7_we),
12834 .wd (cmd_info_7_valid_7_wd),
12835
12836 // from internal hardware
12837 .de (1'b0),
12838 .d ('0),
12839
12840 // to internal hardware
12841 .qe (),
12842 .q (reg2hw.cmd_info[7].valid.q),
12843 .ds (),
12844
12845 // to register interface (read)
12846 .qs (cmd_info_7_valid_7_qs)
12847 );
12848
12849
12850 // Subregister 8 of Multireg cmd_info
12851 // R[cmd_info_8]: V(False)
12852 // F[opcode_8]: 7:0
12853 prim_subreg #(
12854 .DW (8),
12855 .SwAccess(prim_subreg_pkg::SwAccessRW),
12856 .RESVAL (8'h0),
12857 .Mubi (1'b0)
12858 ) u_cmd_info_8_opcode_8 (
12859 .clk_i (clk_i),
12860 .rst_ni (rst_ni),
12861
12862 // from register interface
12863 .we (cmd_info_8_we),
12864 .wd (cmd_info_8_opcode_8_wd),
12865
12866 // from internal hardware
12867 .de (1'b0),
12868 .d ('0),
12869
12870 // to internal hardware
12871 .qe (),
12872 .q (reg2hw.cmd_info[8].opcode.q),
12873 .ds (),
12874
12875 // to register interface (read)
12876 .qs (cmd_info_8_opcode_8_qs)
12877 );
12878
12879 // F[addr_mode_8]: 9:8
12880 prim_subreg #(
12881 .DW (2),
12882 .SwAccess(prim_subreg_pkg::SwAccessRW),
12883 .RESVAL (2'h0),
12884 .Mubi (1'b0)
12885 ) u_cmd_info_8_addr_mode_8 (
12886 .clk_i (clk_i),
12887 .rst_ni (rst_ni),
12888
12889 // from register interface
12890 .we (cmd_info_8_we),
12891 .wd (cmd_info_8_addr_mode_8_wd),
12892
12893 // from internal hardware
12894 .de (1'b0),
12895 .d ('0),
12896
12897 // to internal hardware
12898 .qe (),
12899 .q (reg2hw.cmd_info[8].addr_mode.q),
12900 .ds (),
12901
12902 // to register interface (read)
12903 .qs (cmd_info_8_addr_mode_8_qs)
12904 );
12905
12906 // F[addr_swap_en_8]: 10:10
12907 prim_subreg #(
12908 .DW (1),
12909 .SwAccess(prim_subreg_pkg::SwAccessRW),
12910 .RESVAL (1'h0),
12911 .Mubi (1'b0)
12912 ) u_cmd_info_8_addr_swap_en_8 (
12913 .clk_i (clk_i),
12914 .rst_ni (rst_ni),
12915
12916 // from register interface
12917 .we (cmd_info_8_we),
12918 .wd (cmd_info_8_addr_swap_en_8_wd),
12919
12920 // from internal hardware
12921 .de (1'b0),
12922 .d ('0),
12923
12924 // to internal hardware
12925 .qe (),
12926 .q (reg2hw.cmd_info[8].addr_swap_en.q),
12927 .ds (),
12928
12929 // to register interface (read)
12930 .qs (cmd_info_8_addr_swap_en_8_qs)
12931 );
12932
12933 // F[mbyte_en_8]: 11:11
12934 prim_subreg #(
12935 .DW (1),
12936 .SwAccess(prim_subreg_pkg::SwAccessRW),
12937 .RESVAL (1'h0),
12938 .Mubi (1'b0)
12939 ) u_cmd_info_8_mbyte_en_8 (
12940 .clk_i (clk_i),
12941 .rst_ni (rst_ni),
12942
12943 // from register interface
12944 .we (cmd_info_8_we),
12945 .wd (cmd_info_8_mbyte_en_8_wd),
12946
12947 // from internal hardware
12948 .de (1'b0),
12949 .d ('0),
12950
12951 // to internal hardware
12952 .qe (),
12953 .q (reg2hw.cmd_info[8].mbyte_en.q),
12954 .ds (),
12955
12956 // to register interface (read)
12957 .qs (cmd_info_8_mbyte_en_8_qs)
12958 );
12959
12960 // F[dummy_size_8]: 14:12
12961 prim_subreg #(
12962 .DW (3),
12963 .SwAccess(prim_subreg_pkg::SwAccessRW),
12964 .RESVAL (3'h7),
12965 .Mubi (1'b0)
12966 ) u_cmd_info_8_dummy_size_8 (
12967 .clk_i (clk_i),
12968 .rst_ni (rst_ni),
12969
12970 // from register interface
12971 .we (cmd_info_8_we),
12972 .wd (cmd_info_8_dummy_size_8_wd),
12973
12974 // from internal hardware
12975 .de (1'b0),
12976 .d ('0),
12977
12978 // to internal hardware
12979 .qe (),
12980 .q (reg2hw.cmd_info[8].dummy_size.q),
12981 .ds (),
12982
12983 // to register interface (read)
12984 .qs (cmd_info_8_dummy_size_8_qs)
12985 );
12986
12987 // F[dummy_en_8]: 15:15
12988 prim_subreg #(
12989 .DW (1),
12990 .SwAccess(prim_subreg_pkg::SwAccessRW),
12991 .RESVAL (1'h0),
12992 .Mubi (1'b0)
12993 ) u_cmd_info_8_dummy_en_8 (
12994 .clk_i (clk_i),
12995 .rst_ni (rst_ni),
12996
12997 // from register interface
12998 .we (cmd_info_8_we),
12999 .wd (cmd_info_8_dummy_en_8_wd),
13000
13001 // from internal hardware
13002 .de (1'b0),
13003 .d ('0),
13004
13005 // to internal hardware
13006 .qe (),
13007 .q (reg2hw.cmd_info[8].dummy_en.q),
13008 .ds (),
13009
13010 // to register interface (read)
13011 .qs (cmd_info_8_dummy_en_8_qs)
13012 );
13013
13014 // F[payload_en_8]: 19:16
13015 prim_subreg #(
13016 .DW (4),
13017 .SwAccess(prim_subreg_pkg::SwAccessRW),
13018 .RESVAL (4'h0),
13019 .Mubi (1'b0)
13020 ) u_cmd_info_8_payload_en_8 (
13021 .clk_i (clk_i),
13022 .rst_ni (rst_ni),
13023
13024 // from register interface
13025 .we (cmd_info_8_we),
13026 .wd (cmd_info_8_payload_en_8_wd),
13027
13028 // from internal hardware
13029 .de (1'b0),
13030 .d ('0),
13031
13032 // to internal hardware
13033 .qe (),
13034 .q (reg2hw.cmd_info[8].payload_en.q),
13035 .ds (),
13036
13037 // to register interface (read)
13038 .qs (cmd_info_8_payload_en_8_qs)
13039 );
13040
13041 // F[payload_dir_8]: 20:20
13042 prim_subreg #(
13043 .DW (1),
13044 .SwAccess(prim_subreg_pkg::SwAccessRW),
13045 .RESVAL (1'h0),
13046 .Mubi (1'b0)
13047 ) u_cmd_info_8_payload_dir_8 (
13048 .clk_i (clk_i),
13049 .rst_ni (rst_ni),
13050
13051 // from register interface
13052 .we (cmd_info_8_we),
13053 .wd (cmd_info_8_payload_dir_8_wd),
13054
13055 // from internal hardware
13056 .de (1'b0),
13057 .d ('0),
13058
13059 // to internal hardware
13060 .qe (),
13061 .q (reg2hw.cmd_info[8].payload_dir.q),
13062 .ds (),
13063
13064 // to register interface (read)
13065 .qs (cmd_info_8_payload_dir_8_qs)
13066 );
13067
13068 // F[payload_swap_en_8]: 21:21
13069 prim_subreg #(
13070 .DW (1),
13071 .SwAccess(prim_subreg_pkg::SwAccessRW),
13072 .RESVAL (1'h0),
13073 .Mubi (1'b0)
13074 ) u_cmd_info_8_payload_swap_en_8 (
13075 .clk_i (clk_i),
13076 .rst_ni (rst_ni),
13077
13078 // from register interface
13079 .we (cmd_info_8_we),
13080 .wd (cmd_info_8_payload_swap_en_8_wd),
13081
13082 // from internal hardware
13083 .de (1'b0),
13084 .d ('0),
13085
13086 // to internal hardware
13087 .qe (),
13088 .q (reg2hw.cmd_info[8].payload_swap_en.q),
13089 .ds (),
13090
13091 // to register interface (read)
13092 .qs (cmd_info_8_payload_swap_en_8_qs)
13093 );
13094
13095 // F[read_pipeline_mode_8]: 23:22
13096 prim_subreg #(
13097 .DW (2),
13098 .SwAccess(prim_subreg_pkg::SwAccessRW),
13099 .RESVAL (2'h0),
13100 .Mubi (1'b0)
13101 ) u_cmd_info_8_read_pipeline_mode_8 (
13102 .clk_i (clk_i),
13103 .rst_ni (rst_ni),
13104
13105 // from register interface
13106 .we (cmd_info_8_we),
13107 .wd (cmd_info_8_read_pipeline_mode_8_wd),
13108
13109 // from internal hardware
13110 .de (1'b0),
13111 .d ('0),
13112
13113 // to internal hardware
13114 .qe (),
13115 .q (reg2hw.cmd_info[8].read_pipeline_mode.q),
13116 .ds (),
13117
13118 // to register interface (read)
13119 .qs (cmd_info_8_read_pipeline_mode_8_qs)
13120 );
13121
13122 // F[upload_8]: 24:24
13123 prim_subreg #(
13124 .DW (1),
13125 .SwAccess(prim_subreg_pkg::SwAccessRW),
13126 .RESVAL (1'h0),
13127 .Mubi (1'b0)
13128 ) u_cmd_info_8_upload_8 (
13129 .clk_i (clk_i),
13130 .rst_ni (rst_ni),
13131
13132 // from register interface
13133 .we (cmd_info_8_we),
13134 .wd (cmd_info_8_upload_8_wd),
13135
13136 // from internal hardware
13137 .de (1'b0),
13138 .d ('0),
13139
13140 // to internal hardware
13141 .qe (),
13142 .q (reg2hw.cmd_info[8].upload.q),
13143 .ds (),
13144
13145 // to register interface (read)
13146 .qs (cmd_info_8_upload_8_qs)
13147 );
13148
13149 // F[busy_8]: 25:25
13150 prim_subreg #(
13151 .DW (1),
13152 .SwAccess(prim_subreg_pkg::SwAccessRW),
13153 .RESVAL (1'h0),
13154 .Mubi (1'b0)
13155 ) u_cmd_info_8_busy_8 (
13156 .clk_i (clk_i),
13157 .rst_ni (rst_ni),
13158
13159 // from register interface
13160 .we (cmd_info_8_we),
13161 .wd (cmd_info_8_busy_8_wd),
13162
13163 // from internal hardware
13164 .de (1'b0),
13165 .d ('0),
13166
13167 // to internal hardware
13168 .qe (),
13169 .q (reg2hw.cmd_info[8].busy.q),
13170 .ds (),
13171
13172 // to register interface (read)
13173 .qs (cmd_info_8_busy_8_qs)
13174 );
13175
13176 // F[valid_8]: 31:31
13177 prim_subreg #(
13178 .DW (1),
13179 .SwAccess(prim_subreg_pkg::SwAccessRW),
13180 .RESVAL (1'h0),
13181 .Mubi (1'b0)
13182 ) u_cmd_info_8_valid_8 (
13183 .clk_i (clk_i),
13184 .rst_ni (rst_ni),
13185
13186 // from register interface
13187 .we (cmd_info_8_we),
13188 .wd (cmd_info_8_valid_8_wd),
13189
13190 // from internal hardware
13191 .de (1'b0),
13192 .d ('0),
13193
13194 // to internal hardware
13195 .qe (),
13196 .q (reg2hw.cmd_info[8].valid.q),
13197 .ds (),
13198
13199 // to register interface (read)
13200 .qs (cmd_info_8_valid_8_qs)
13201 );
13202
13203
13204 // Subregister 9 of Multireg cmd_info
13205 // R[cmd_info_9]: V(False)
13206 // F[opcode_9]: 7:0
13207 prim_subreg #(
13208 .DW (8),
13209 .SwAccess(prim_subreg_pkg::SwAccessRW),
13210 .RESVAL (8'h0),
13211 .Mubi (1'b0)
13212 ) u_cmd_info_9_opcode_9 (
13213 .clk_i (clk_i),
13214 .rst_ni (rst_ni),
13215
13216 // from register interface
13217 .we (cmd_info_9_we),
13218 .wd (cmd_info_9_opcode_9_wd),
13219
13220 // from internal hardware
13221 .de (1'b0),
13222 .d ('0),
13223
13224 // to internal hardware
13225 .qe (),
13226 .q (reg2hw.cmd_info[9].opcode.q),
13227 .ds (),
13228
13229 // to register interface (read)
13230 .qs (cmd_info_9_opcode_9_qs)
13231 );
13232
13233 // F[addr_mode_9]: 9:8
13234 prim_subreg #(
13235 .DW (2),
13236 .SwAccess(prim_subreg_pkg::SwAccessRW),
13237 .RESVAL (2'h0),
13238 .Mubi (1'b0)
13239 ) u_cmd_info_9_addr_mode_9 (
13240 .clk_i (clk_i),
13241 .rst_ni (rst_ni),
13242
13243 // from register interface
13244 .we (cmd_info_9_we),
13245 .wd (cmd_info_9_addr_mode_9_wd),
13246
13247 // from internal hardware
13248 .de (1'b0),
13249 .d ('0),
13250
13251 // to internal hardware
13252 .qe (),
13253 .q (reg2hw.cmd_info[9].addr_mode.q),
13254 .ds (),
13255
13256 // to register interface (read)
13257 .qs (cmd_info_9_addr_mode_9_qs)
13258 );
13259
13260 // F[addr_swap_en_9]: 10:10
13261 prim_subreg #(
13262 .DW (1),
13263 .SwAccess(prim_subreg_pkg::SwAccessRW),
13264 .RESVAL (1'h0),
13265 .Mubi (1'b0)
13266 ) u_cmd_info_9_addr_swap_en_9 (
13267 .clk_i (clk_i),
13268 .rst_ni (rst_ni),
13269
13270 // from register interface
13271 .we (cmd_info_9_we),
13272 .wd (cmd_info_9_addr_swap_en_9_wd),
13273
13274 // from internal hardware
13275 .de (1'b0),
13276 .d ('0),
13277
13278 // to internal hardware
13279 .qe (),
13280 .q (reg2hw.cmd_info[9].addr_swap_en.q),
13281 .ds (),
13282
13283 // to register interface (read)
13284 .qs (cmd_info_9_addr_swap_en_9_qs)
13285 );
13286
13287 // F[mbyte_en_9]: 11:11
13288 prim_subreg #(
13289 .DW (1),
13290 .SwAccess(prim_subreg_pkg::SwAccessRW),
13291 .RESVAL (1'h0),
13292 .Mubi (1'b0)
13293 ) u_cmd_info_9_mbyte_en_9 (
13294 .clk_i (clk_i),
13295 .rst_ni (rst_ni),
13296
13297 // from register interface
13298 .we (cmd_info_9_we),
13299 .wd (cmd_info_9_mbyte_en_9_wd),
13300
13301 // from internal hardware
13302 .de (1'b0),
13303 .d ('0),
13304
13305 // to internal hardware
13306 .qe (),
13307 .q (reg2hw.cmd_info[9].mbyte_en.q),
13308 .ds (),
13309
13310 // to register interface (read)
13311 .qs (cmd_info_9_mbyte_en_9_qs)
13312 );
13313
13314 // F[dummy_size_9]: 14:12
13315 prim_subreg #(
13316 .DW (3),
13317 .SwAccess(prim_subreg_pkg::SwAccessRW),
13318 .RESVAL (3'h7),
13319 .Mubi (1'b0)
13320 ) u_cmd_info_9_dummy_size_9 (
13321 .clk_i (clk_i),
13322 .rst_ni (rst_ni),
13323
13324 // from register interface
13325 .we (cmd_info_9_we),
13326 .wd (cmd_info_9_dummy_size_9_wd),
13327
13328 // from internal hardware
13329 .de (1'b0),
13330 .d ('0),
13331
13332 // to internal hardware
13333 .qe (),
13334 .q (reg2hw.cmd_info[9].dummy_size.q),
13335 .ds (),
13336
13337 // to register interface (read)
13338 .qs (cmd_info_9_dummy_size_9_qs)
13339 );
13340
13341 // F[dummy_en_9]: 15:15
13342 prim_subreg #(
13343 .DW (1),
13344 .SwAccess(prim_subreg_pkg::SwAccessRW),
13345 .RESVAL (1'h0),
13346 .Mubi (1'b0)
13347 ) u_cmd_info_9_dummy_en_9 (
13348 .clk_i (clk_i),
13349 .rst_ni (rst_ni),
13350
13351 // from register interface
13352 .we (cmd_info_9_we),
13353 .wd (cmd_info_9_dummy_en_9_wd),
13354
13355 // from internal hardware
13356 .de (1'b0),
13357 .d ('0),
13358
13359 // to internal hardware
13360 .qe (),
13361 .q (reg2hw.cmd_info[9].dummy_en.q),
13362 .ds (),
13363
13364 // to register interface (read)
13365 .qs (cmd_info_9_dummy_en_9_qs)
13366 );
13367
13368 // F[payload_en_9]: 19:16
13369 prim_subreg #(
13370 .DW (4),
13371 .SwAccess(prim_subreg_pkg::SwAccessRW),
13372 .RESVAL (4'h0),
13373 .Mubi (1'b0)
13374 ) u_cmd_info_9_payload_en_9 (
13375 .clk_i (clk_i),
13376 .rst_ni (rst_ni),
13377
13378 // from register interface
13379 .we (cmd_info_9_we),
13380 .wd (cmd_info_9_payload_en_9_wd),
13381
13382 // from internal hardware
13383 .de (1'b0),
13384 .d ('0),
13385
13386 // to internal hardware
13387 .qe (),
13388 .q (reg2hw.cmd_info[9].payload_en.q),
13389 .ds (),
13390
13391 // to register interface (read)
13392 .qs (cmd_info_9_payload_en_9_qs)
13393 );
13394
13395 // F[payload_dir_9]: 20:20
13396 prim_subreg #(
13397 .DW (1),
13398 .SwAccess(prim_subreg_pkg::SwAccessRW),
13399 .RESVAL (1'h0),
13400 .Mubi (1'b0)
13401 ) u_cmd_info_9_payload_dir_9 (
13402 .clk_i (clk_i),
13403 .rst_ni (rst_ni),
13404
13405 // from register interface
13406 .we (cmd_info_9_we),
13407 .wd (cmd_info_9_payload_dir_9_wd),
13408
13409 // from internal hardware
13410 .de (1'b0),
13411 .d ('0),
13412
13413 // to internal hardware
13414 .qe (),
13415 .q (reg2hw.cmd_info[9].payload_dir.q),
13416 .ds (),
13417
13418 // to register interface (read)
13419 .qs (cmd_info_9_payload_dir_9_qs)
13420 );
13421
13422 // F[payload_swap_en_9]: 21:21
13423 prim_subreg #(
13424 .DW (1),
13425 .SwAccess(prim_subreg_pkg::SwAccessRW),
13426 .RESVAL (1'h0),
13427 .Mubi (1'b0)
13428 ) u_cmd_info_9_payload_swap_en_9 (
13429 .clk_i (clk_i),
13430 .rst_ni (rst_ni),
13431
13432 // from register interface
13433 .we (cmd_info_9_we),
13434 .wd (cmd_info_9_payload_swap_en_9_wd),
13435
13436 // from internal hardware
13437 .de (1'b0),
13438 .d ('0),
13439
13440 // to internal hardware
13441 .qe (),
13442 .q (reg2hw.cmd_info[9].payload_swap_en.q),
13443 .ds (),
13444
13445 // to register interface (read)
13446 .qs (cmd_info_9_payload_swap_en_9_qs)
13447 );
13448
13449 // F[read_pipeline_mode_9]: 23:22
13450 prim_subreg #(
13451 .DW (2),
13452 .SwAccess(prim_subreg_pkg::SwAccessRW),
13453 .RESVAL (2'h0),
13454 .Mubi (1'b0)
13455 ) u_cmd_info_9_read_pipeline_mode_9 (
13456 .clk_i (clk_i),
13457 .rst_ni (rst_ni),
13458
13459 // from register interface
13460 .we (cmd_info_9_we),
13461 .wd (cmd_info_9_read_pipeline_mode_9_wd),
13462
13463 // from internal hardware
13464 .de (1'b0),
13465 .d ('0),
13466
13467 // to internal hardware
13468 .qe (),
13469 .q (reg2hw.cmd_info[9].read_pipeline_mode.q),
13470 .ds (),
13471
13472 // to register interface (read)
13473 .qs (cmd_info_9_read_pipeline_mode_9_qs)
13474 );
13475
13476 // F[upload_9]: 24:24
13477 prim_subreg #(
13478 .DW (1),
13479 .SwAccess(prim_subreg_pkg::SwAccessRW),
13480 .RESVAL (1'h0),
13481 .Mubi (1'b0)
13482 ) u_cmd_info_9_upload_9 (
13483 .clk_i (clk_i),
13484 .rst_ni (rst_ni),
13485
13486 // from register interface
13487 .we (cmd_info_9_we),
13488 .wd (cmd_info_9_upload_9_wd),
13489
13490 // from internal hardware
13491 .de (1'b0),
13492 .d ('0),
13493
13494 // to internal hardware
13495 .qe (),
13496 .q (reg2hw.cmd_info[9].upload.q),
13497 .ds (),
13498
13499 // to register interface (read)
13500 .qs (cmd_info_9_upload_9_qs)
13501 );
13502
13503 // F[busy_9]: 25:25
13504 prim_subreg #(
13505 .DW (1),
13506 .SwAccess(prim_subreg_pkg::SwAccessRW),
13507 .RESVAL (1'h0),
13508 .Mubi (1'b0)
13509 ) u_cmd_info_9_busy_9 (
13510 .clk_i (clk_i),
13511 .rst_ni (rst_ni),
13512
13513 // from register interface
13514 .we (cmd_info_9_we),
13515 .wd (cmd_info_9_busy_9_wd),
13516
13517 // from internal hardware
13518 .de (1'b0),
13519 .d ('0),
13520
13521 // to internal hardware
13522 .qe (),
13523 .q (reg2hw.cmd_info[9].busy.q),
13524 .ds (),
13525
13526 // to register interface (read)
13527 .qs (cmd_info_9_busy_9_qs)
13528 );
13529
13530 // F[valid_9]: 31:31
13531 prim_subreg #(
13532 .DW (1),
13533 .SwAccess(prim_subreg_pkg::SwAccessRW),
13534 .RESVAL (1'h0),
13535 .Mubi (1'b0)
13536 ) u_cmd_info_9_valid_9 (
13537 .clk_i (clk_i),
13538 .rst_ni (rst_ni),
13539
13540 // from register interface
13541 .we (cmd_info_9_we),
13542 .wd (cmd_info_9_valid_9_wd),
13543
13544 // from internal hardware
13545 .de (1'b0),
13546 .d ('0),
13547
13548 // to internal hardware
13549 .qe (),
13550 .q (reg2hw.cmd_info[9].valid.q),
13551 .ds (),
13552
13553 // to register interface (read)
13554 .qs (cmd_info_9_valid_9_qs)
13555 );
13556
13557
13558 // Subregister 10 of Multireg cmd_info
13559 // R[cmd_info_10]: V(False)
13560 // F[opcode_10]: 7:0
13561 prim_subreg #(
13562 .DW (8),
13563 .SwAccess(prim_subreg_pkg::SwAccessRW),
13564 .RESVAL (8'h0),
13565 .Mubi (1'b0)
13566 ) u_cmd_info_10_opcode_10 (
13567 .clk_i (clk_i),
13568 .rst_ni (rst_ni),
13569
13570 // from register interface
13571 .we (cmd_info_10_we),
13572 .wd (cmd_info_10_opcode_10_wd),
13573
13574 // from internal hardware
13575 .de (1'b0),
13576 .d ('0),
13577
13578 // to internal hardware
13579 .qe (),
13580 .q (reg2hw.cmd_info[10].opcode.q),
13581 .ds (),
13582
13583 // to register interface (read)
13584 .qs (cmd_info_10_opcode_10_qs)
13585 );
13586
13587 // F[addr_mode_10]: 9:8
13588 prim_subreg #(
13589 .DW (2),
13590 .SwAccess(prim_subreg_pkg::SwAccessRW),
13591 .RESVAL (2'h0),
13592 .Mubi (1'b0)
13593 ) u_cmd_info_10_addr_mode_10 (
13594 .clk_i (clk_i),
13595 .rst_ni (rst_ni),
13596
13597 // from register interface
13598 .we (cmd_info_10_we),
13599 .wd (cmd_info_10_addr_mode_10_wd),
13600
13601 // from internal hardware
13602 .de (1'b0),
13603 .d ('0),
13604
13605 // to internal hardware
13606 .qe (),
13607 .q (reg2hw.cmd_info[10].addr_mode.q),
13608 .ds (),
13609
13610 // to register interface (read)
13611 .qs (cmd_info_10_addr_mode_10_qs)
13612 );
13613
13614 // F[addr_swap_en_10]: 10:10
13615 prim_subreg #(
13616 .DW (1),
13617 .SwAccess(prim_subreg_pkg::SwAccessRW),
13618 .RESVAL (1'h0),
13619 .Mubi (1'b0)
13620 ) u_cmd_info_10_addr_swap_en_10 (
13621 .clk_i (clk_i),
13622 .rst_ni (rst_ni),
13623
13624 // from register interface
13625 .we (cmd_info_10_we),
13626 .wd (cmd_info_10_addr_swap_en_10_wd),
13627
13628 // from internal hardware
13629 .de (1'b0),
13630 .d ('0),
13631
13632 // to internal hardware
13633 .qe (),
13634 .q (reg2hw.cmd_info[10].addr_swap_en.q),
13635 .ds (),
13636
13637 // to register interface (read)
13638 .qs (cmd_info_10_addr_swap_en_10_qs)
13639 );
13640
13641 // F[mbyte_en_10]: 11:11
13642 prim_subreg #(
13643 .DW (1),
13644 .SwAccess(prim_subreg_pkg::SwAccessRW),
13645 .RESVAL (1'h0),
13646 .Mubi (1'b0)
13647 ) u_cmd_info_10_mbyte_en_10 (
13648 .clk_i (clk_i),
13649 .rst_ni (rst_ni),
13650
13651 // from register interface
13652 .we (cmd_info_10_we),
13653 .wd (cmd_info_10_mbyte_en_10_wd),
13654
13655 // from internal hardware
13656 .de (1'b0),
13657 .d ('0),
13658
13659 // to internal hardware
13660 .qe (),
13661 .q (reg2hw.cmd_info[10].mbyte_en.q),
13662 .ds (),
13663
13664 // to register interface (read)
13665 .qs (cmd_info_10_mbyte_en_10_qs)
13666 );
13667
13668 // F[dummy_size_10]: 14:12
13669 prim_subreg #(
13670 .DW (3),
13671 .SwAccess(prim_subreg_pkg::SwAccessRW),
13672 .RESVAL (3'h7),
13673 .Mubi (1'b0)
13674 ) u_cmd_info_10_dummy_size_10 (
13675 .clk_i (clk_i),
13676 .rst_ni (rst_ni),
13677
13678 // from register interface
13679 .we (cmd_info_10_we),
13680 .wd (cmd_info_10_dummy_size_10_wd),
13681
13682 // from internal hardware
13683 .de (1'b0),
13684 .d ('0),
13685
13686 // to internal hardware
13687 .qe (),
13688 .q (reg2hw.cmd_info[10].dummy_size.q),
13689 .ds (),
13690
13691 // to register interface (read)
13692 .qs (cmd_info_10_dummy_size_10_qs)
13693 );
13694
13695 // F[dummy_en_10]: 15:15
13696 prim_subreg #(
13697 .DW (1),
13698 .SwAccess(prim_subreg_pkg::SwAccessRW),
13699 .RESVAL (1'h0),
13700 .Mubi (1'b0)
13701 ) u_cmd_info_10_dummy_en_10 (
13702 .clk_i (clk_i),
13703 .rst_ni (rst_ni),
13704
13705 // from register interface
13706 .we (cmd_info_10_we),
13707 .wd (cmd_info_10_dummy_en_10_wd),
13708
13709 // from internal hardware
13710 .de (1'b0),
13711 .d ('0),
13712
13713 // to internal hardware
13714 .qe (),
13715 .q (reg2hw.cmd_info[10].dummy_en.q),
13716 .ds (),
13717
13718 // to register interface (read)
13719 .qs (cmd_info_10_dummy_en_10_qs)
13720 );
13721
13722 // F[payload_en_10]: 19:16
13723 prim_subreg #(
13724 .DW (4),
13725 .SwAccess(prim_subreg_pkg::SwAccessRW),
13726 .RESVAL (4'h0),
13727 .Mubi (1'b0)
13728 ) u_cmd_info_10_payload_en_10 (
13729 .clk_i (clk_i),
13730 .rst_ni (rst_ni),
13731
13732 // from register interface
13733 .we (cmd_info_10_we),
13734 .wd (cmd_info_10_payload_en_10_wd),
13735
13736 // from internal hardware
13737 .de (1'b0),
13738 .d ('0),
13739
13740 // to internal hardware
13741 .qe (),
13742 .q (reg2hw.cmd_info[10].payload_en.q),
13743 .ds (),
13744
13745 // to register interface (read)
13746 .qs (cmd_info_10_payload_en_10_qs)
13747 );
13748
13749 // F[payload_dir_10]: 20:20
13750 prim_subreg #(
13751 .DW (1),
13752 .SwAccess(prim_subreg_pkg::SwAccessRW),
13753 .RESVAL (1'h0),
13754 .Mubi (1'b0)
13755 ) u_cmd_info_10_payload_dir_10 (
13756 .clk_i (clk_i),
13757 .rst_ni (rst_ni),
13758
13759 // from register interface
13760 .we (cmd_info_10_we),
13761 .wd (cmd_info_10_payload_dir_10_wd),
13762
13763 // from internal hardware
13764 .de (1'b0),
13765 .d ('0),
13766
13767 // to internal hardware
13768 .qe (),
13769 .q (reg2hw.cmd_info[10].payload_dir.q),
13770 .ds (),
13771
13772 // to register interface (read)
13773 .qs (cmd_info_10_payload_dir_10_qs)
13774 );
13775
13776 // F[payload_swap_en_10]: 21:21
13777 prim_subreg #(
13778 .DW (1),
13779 .SwAccess(prim_subreg_pkg::SwAccessRW),
13780 .RESVAL (1'h0),
13781 .Mubi (1'b0)
13782 ) u_cmd_info_10_payload_swap_en_10 (
13783 .clk_i (clk_i),
13784 .rst_ni (rst_ni),
13785
13786 // from register interface
13787 .we (cmd_info_10_we),
13788 .wd (cmd_info_10_payload_swap_en_10_wd),
13789
13790 // from internal hardware
13791 .de (1'b0),
13792 .d ('0),
13793
13794 // to internal hardware
13795 .qe (),
13796 .q (reg2hw.cmd_info[10].payload_swap_en.q),
13797 .ds (),
13798
13799 // to register interface (read)
13800 .qs (cmd_info_10_payload_swap_en_10_qs)
13801 );
13802
13803 // F[read_pipeline_mode_10]: 23:22
13804 prim_subreg #(
13805 .DW (2),
13806 .SwAccess(prim_subreg_pkg::SwAccessRW),
13807 .RESVAL (2'h0),
13808 .Mubi (1'b0)
13809 ) u_cmd_info_10_read_pipeline_mode_10 (
13810 .clk_i (clk_i),
13811 .rst_ni (rst_ni),
13812
13813 // from register interface
13814 .we (cmd_info_10_we),
13815 .wd (cmd_info_10_read_pipeline_mode_10_wd),
13816
13817 // from internal hardware
13818 .de (1'b0),
13819 .d ('0),
13820
13821 // to internal hardware
13822 .qe (),
13823 .q (reg2hw.cmd_info[10].read_pipeline_mode.q),
13824 .ds (),
13825
13826 // to register interface (read)
13827 .qs (cmd_info_10_read_pipeline_mode_10_qs)
13828 );
13829
13830 // F[upload_10]: 24:24
13831 prim_subreg #(
13832 .DW (1),
13833 .SwAccess(prim_subreg_pkg::SwAccessRW),
13834 .RESVAL (1'h0),
13835 .Mubi (1'b0)
13836 ) u_cmd_info_10_upload_10 (
13837 .clk_i (clk_i),
13838 .rst_ni (rst_ni),
13839
13840 // from register interface
13841 .we (cmd_info_10_we),
13842 .wd (cmd_info_10_upload_10_wd),
13843
13844 // from internal hardware
13845 .de (1'b0),
13846 .d ('0),
13847
13848 // to internal hardware
13849 .qe (),
13850 .q (reg2hw.cmd_info[10].upload.q),
13851 .ds (),
13852
13853 // to register interface (read)
13854 .qs (cmd_info_10_upload_10_qs)
13855 );
13856
13857 // F[busy_10]: 25:25
13858 prim_subreg #(
13859 .DW (1),
13860 .SwAccess(prim_subreg_pkg::SwAccessRW),
13861 .RESVAL (1'h0),
13862 .Mubi (1'b0)
13863 ) u_cmd_info_10_busy_10 (
13864 .clk_i (clk_i),
13865 .rst_ni (rst_ni),
13866
13867 // from register interface
13868 .we (cmd_info_10_we),
13869 .wd (cmd_info_10_busy_10_wd),
13870
13871 // from internal hardware
13872 .de (1'b0),
13873 .d ('0),
13874
13875 // to internal hardware
13876 .qe (),
13877 .q (reg2hw.cmd_info[10].busy.q),
13878 .ds (),
13879
13880 // to register interface (read)
13881 .qs (cmd_info_10_busy_10_qs)
13882 );
13883
13884 // F[valid_10]: 31:31
13885 prim_subreg #(
13886 .DW (1),
13887 .SwAccess(prim_subreg_pkg::SwAccessRW),
13888 .RESVAL (1'h0),
13889 .Mubi (1'b0)
13890 ) u_cmd_info_10_valid_10 (
13891 .clk_i (clk_i),
13892 .rst_ni (rst_ni),
13893
13894 // from register interface
13895 .we (cmd_info_10_we),
13896 .wd (cmd_info_10_valid_10_wd),
13897
13898 // from internal hardware
13899 .de (1'b0),
13900 .d ('0),
13901
13902 // to internal hardware
13903 .qe (),
13904 .q (reg2hw.cmd_info[10].valid.q),
13905 .ds (),
13906
13907 // to register interface (read)
13908 .qs (cmd_info_10_valid_10_qs)
13909 );
13910
13911
13912 // Subregister 11 of Multireg cmd_info
13913 // R[cmd_info_11]: V(False)
13914 // F[opcode_11]: 7:0
13915 prim_subreg #(
13916 .DW (8),
13917 .SwAccess(prim_subreg_pkg::SwAccessRW),
13918 .RESVAL (8'h0),
13919 .Mubi (1'b0)
13920 ) u_cmd_info_11_opcode_11 (
13921 .clk_i (clk_i),
13922 .rst_ni (rst_ni),
13923
13924 // from register interface
13925 .we (cmd_info_11_we),
13926 .wd (cmd_info_11_opcode_11_wd),
13927
13928 // from internal hardware
13929 .de (1'b0),
13930 .d ('0),
13931
13932 // to internal hardware
13933 .qe (),
13934 .q (reg2hw.cmd_info[11].opcode.q),
13935 .ds (),
13936
13937 // to register interface (read)
13938 .qs (cmd_info_11_opcode_11_qs)
13939 );
13940
13941 // F[addr_mode_11]: 9:8
13942 prim_subreg #(
13943 .DW (2),
13944 .SwAccess(prim_subreg_pkg::SwAccessRW),
13945 .RESVAL (2'h0),
13946 .Mubi (1'b0)
13947 ) u_cmd_info_11_addr_mode_11 (
13948 .clk_i (clk_i),
13949 .rst_ni (rst_ni),
13950
13951 // from register interface
13952 .we (cmd_info_11_we),
13953 .wd (cmd_info_11_addr_mode_11_wd),
13954
13955 // from internal hardware
13956 .de (1'b0),
13957 .d ('0),
13958
13959 // to internal hardware
13960 .qe (),
13961 .q (reg2hw.cmd_info[11].addr_mode.q),
13962 .ds (),
13963
13964 // to register interface (read)
13965 .qs (cmd_info_11_addr_mode_11_qs)
13966 );
13967
13968 // F[addr_swap_en_11]: 10:10
13969 prim_subreg #(
13970 .DW (1),
13971 .SwAccess(prim_subreg_pkg::SwAccessRW),
13972 .RESVAL (1'h0),
13973 .Mubi (1'b0)
13974 ) u_cmd_info_11_addr_swap_en_11 (
13975 .clk_i (clk_i),
13976 .rst_ni (rst_ni),
13977
13978 // from register interface
13979 .we (cmd_info_11_we),
13980 .wd (cmd_info_11_addr_swap_en_11_wd),
13981
13982 // from internal hardware
13983 .de (1'b0),
13984 .d ('0),
13985
13986 // to internal hardware
13987 .qe (),
13988 .q (reg2hw.cmd_info[11].addr_swap_en.q),
13989 .ds (),
13990
13991 // to register interface (read)
13992 .qs (cmd_info_11_addr_swap_en_11_qs)
13993 );
13994
13995 // F[mbyte_en_11]: 11:11
13996 prim_subreg #(
13997 .DW (1),
13998 .SwAccess(prim_subreg_pkg::SwAccessRW),
13999 .RESVAL (1'h0),
14000 .Mubi (1'b0)
14001 ) u_cmd_info_11_mbyte_en_11 (
14002 .clk_i (clk_i),
14003 .rst_ni (rst_ni),
14004
14005 // from register interface
14006 .we (cmd_info_11_we),
14007 .wd (cmd_info_11_mbyte_en_11_wd),
14008
14009 // from internal hardware
14010 .de (1'b0),
14011 .d ('0),
14012
14013 // to internal hardware
14014 .qe (),
14015 .q (reg2hw.cmd_info[11].mbyte_en.q),
14016 .ds (),
14017
14018 // to register interface (read)
14019 .qs (cmd_info_11_mbyte_en_11_qs)
14020 );
14021
14022 // F[dummy_size_11]: 14:12
14023 prim_subreg #(
14024 .DW (3),
14025 .SwAccess(prim_subreg_pkg::SwAccessRW),
14026 .RESVAL (3'h7),
14027 .Mubi (1'b0)
14028 ) u_cmd_info_11_dummy_size_11 (
14029 .clk_i (clk_i),
14030 .rst_ni (rst_ni),
14031
14032 // from register interface
14033 .we (cmd_info_11_we),
14034 .wd (cmd_info_11_dummy_size_11_wd),
14035
14036 // from internal hardware
14037 .de (1'b0),
14038 .d ('0),
14039
14040 // to internal hardware
14041 .qe (),
14042 .q (reg2hw.cmd_info[11].dummy_size.q),
14043 .ds (),
14044
14045 // to register interface (read)
14046 .qs (cmd_info_11_dummy_size_11_qs)
14047 );
14048
14049 // F[dummy_en_11]: 15:15
14050 prim_subreg #(
14051 .DW (1),
14052 .SwAccess(prim_subreg_pkg::SwAccessRW),
14053 .RESVAL (1'h0),
14054 .Mubi (1'b0)
14055 ) u_cmd_info_11_dummy_en_11 (
14056 .clk_i (clk_i),
14057 .rst_ni (rst_ni),
14058
14059 // from register interface
14060 .we (cmd_info_11_we),
14061 .wd (cmd_info_11_dummy_en_11_wd),
14062
14063 // from internal hardware
14064 .de (1'b0),
14065 .d ('0),
14066
14067 // to internal hardware
14068 .qe (),
14069 .q (reg2hw.cmd_info[11].dummy_en.q),
14070 .ds (),
14071
14072 // to register interface (read)
14073 .qs (cmd_info_11_dummy_en_11_qs)
14074 );
14075
14076 // F[payload_en_11]: 19:16
14077 prim_subreg #(
14078 .DW (4),
14079 .SwAccess(prim_subreg_pkg::SwAccessRW),
14080 .RESVAL (4'h0),
14081 .Mubi (1'b0)
14082 ) u_cmd_info_11_payload_en_11 (
14083 .clk_i (clk_i),
14084 .rst_ni (rst_ni),
14085
14086 // from register interface
14087 .we (cmd_info_11_we),
14088 .wd (cmd_info_11_payload_en_11_wd),
14089
14090 // from internal hardware
14091 .de (1'b0),
14092 .d ('0),
14093
14094 // to internal hardware
14095 .qe (),
14096 .q (reg2hw.cmd_info[11].payload_en.q),
14097 .ds (),
14098
14099 // to register interface (read)
14100 .qs (cmd_info_11_payload_en_11_qs)
14101 );
14102
14103 // F[payload_dir_11]: 20:20
14104 prim_subreg #(
14105 .DW (1),
14106 .SwAccess(prim_subreg_pkg::SwAccessRW),
14107 .RESVAL (1'h0),
14108 .Mubi (1'b0)
14109 ) u_cmd_info_11_payload_dir_11 (
14110 .clk_i (clk_i),
14111 .rst_ni (rst_ni),
14112
14113 // from register interface
14114 .we (cmd_info_11_we),
14115 .wd (cmd_info_11_payload_dir_11_wd),
14116
14117 // from internal hardware
14118 .de (1'b0),
14119 .d ('0),
14120
14121 // to internal hardware
14122 .qe (),
14123 .q (reg2hw.cmd_info[11].payload_dir.q),
14124 .ds (),
14125
14126 // to register interface (read)
14127 .qs (cmd_info_11_payload_dir_11_qs)
14128 );
14129
14130 // F[payload_swap_en_11]: 21:21
14131 prim_subreg #(
14132 .DW (1),
14133 .SwAccess(prim_subreg_pkg::SwAccessRW),
14134 .RESVAL (1'h0),
14135 .Mubi (1'b0)
14136 ) u_cmd_info_11_payload_swap_en_11 (
14137 .clk_i (clk_i),
14138 .rst_ni (rst_ni),
14139
14140 // from register interface
14141 .we (cmd_info_11_we),
14142 .wd (cmd_info_11_payload_swap_en_11_wd),
14143
14144 // from internal hardware
14145 .de (1'b0),
14146 .d ('0),
14147
14148 // to internal hardware
14149 .qe (),
14150 .q (reg2hw.cmd_info[11].payload_swap_en.q),
14151 .ds (),
14152
14153 // to register interface (read)
14154 .qs (cmd_info_11_payload_swap_en_11_qs)
14155 );
14156
14157 // F[read_pipeline_mode_11]: 23:22
14158 prim_subreg #(
14159 .DW (2),
14160 .SwAccess(prim_subreg_pkg::SwAccessRW),
14161 .RESVAL (2'h0),
14162 .Mubi (1'b0)
14163 ) u_cmd_info_11_read_pipeline_mode_11 (
14164 .clk_i (clk_i),
14165 .rst_ni (rst_ni),
14166
14167 // from register interface
14168 .we (cmd_info_11_we),
14169 .wd (cmd_info_11_read_pipeline_mode_11_wd),
14170
14171 // from internal hardware
14172 .de (1'b0),
14173 .d ('0),
14174
14175 // to internal hardware
14176 .qe (),
14177 .q (reg2hw.cmd_info[11].read_pipeline_mode.q),
14178 .ds (),
14179
14180 // to register interface (read)
14181 .qs (cmd_info_11_read_pipeline_mode_11_qs)
14182 );
14183
14184 // F[upload_11]: 24:24
14185 prim_subreg #(
14186 .DW (1),
14187 .SwAccess(prim_subreg_pkg::SwAccessRW),
14188 .RESVAL (1'h0),
14189 .Mubi (1'b0)
14190 ) u_cmd_info_11_upload_11 (
14191 .clk_i (clk_i),
14192 .rst_ni (rst_ni),
14193
14194 // from register interface
14195 .we (cmd_info_11_we),
14196 .wd (cmd_info_11_upload_11_wd),
14197
14198 // from internal hardware
14199 .de (1'b0),
14200 .d ('0),
14201
14202 // to internal hardware
14203 .qe (),
14204 .q (reg2hw.cmd_info[11].upload.q),
14205 .ds (),
14206
14207 // to register interface (read)
14208 .qs (cmd_info_11_upload_11_qs)
14209 );
14210
14211 // F[busy_11]: 25:25
14212 prim_subreg #(
14213 .DW (1),
14214 .SwAccess(prim_subreg_pkg::SwAccessRW),
14215 .RESVAL (1'h0),
14216 .Mubi (1'b0)
14217 ) u_cmd_info_11_busy_11 (
14218 .clk_i (clk_i),
14219 .rst_ni (rst_ni),
14220
14221 // from register interface
14222 .we (cmd_info_11_we),
14223 .wd (cmd_info_11_busy_11_wd),
14224
14225 // from internal hardware
14226 .de (1'b0),
14227 .d ('0),
14228
14229 // to internal hardware
14230 .qe (),
14231 .q (reg2hw.cmd_info[11].busy.q),
14232 .ds (),
14233
14234 // to register interface (read)
14235 .qs (cmd_info_11_busy_11_qs)
14236 );
14237
14238 // F[valid_11]: 31:31
14239 prim_subreg #(
14240 .DW (1),
14241 .SwAccess(prim_subreg_pkg::SwAccessRW),
14242 .RESVAL (1'h0),
14243 .Mubi (1'b0)
14244 ) u_cmd_info_11_valid_11 (
14245 .clk_i (clk_i),
14246 .rst_ni (rst_ni),
14247
14248 // from register interface
14249 .we (cmd_info_11_we),
14250 .wd (cmd_info_11_valid_11_wd),
14251
14252 // from internal hardware
14253 .de (1'b0),
14254 .d ('0),
14255
14256 // to internal hardware
14257 .qe (),
14258 .q (reg2hw.cmd_info[11].valid.q),
14259 .ds (),
14260
14261 // to register interface (read)
14262 .qs (cmd_info_11_valid_11_qs)
14263 );
14264
14265
14266 // Subregister 12 of Multireg cmd_info
14267 // R[cmd_info_12]: V(False)
14268 // F[opcode_12]: 7:0
14269 prim_subreg #(
14270 .DW (8),
14271 .SwAccess(prim_subreg_pkg::SwAccessRW),
14272 .RESVAL (8'h0),
14273 .Mubi (1'b0)
14274 ) u_cmd_info_12_opcode_12 (
14275 .clk_i (clk_i),
14276 .rst_ni (rst_ni),
14277
14278 // from register interface
14279 .we (cmd_info_12_we),
14280 .wd (cmd_info_12_opcode_12_wd),
14281
14282 // from internal hardware
14283 .de (1'b0),
14284 .d ('0),
14285
14286 // to internal hardware
14287 .qe (),
14288 .q (reg2hw.cmd_info[12].opcode.q),
14289 .ds (),
14290
14291 // to register interface (read)
14292 .qs (cmd_info_12_opcode_12_qs)
14293 );
14294
14295 // F[addr_mode_12]: 9:8
14296 prim_subreg #(
14297 .DW (2),
14298 .SwAccess(prim_subreg_pkg::SwAccessRW),
14299 .RESVAL (2'h0),
14300 .Mubi (1'b0)
14301 ) u_cmd_info_12_addr_mode_12 (
14302 .clk_i (clk_i),
14303 .rst_ni (rst_ni),
14304
14305 // from register interface
14306 .we (cmd_info_12_we),
14307 .wd (cmd_info_12_addr_mode_12_wd),
14308
14309 // from internal hardware
14310 .de (1'b0),
14311 .d ('0),
14312
14313 // to internal hardware
14314 .qe (),
14315 .q (reg2hw.cmd_info[12].addr_mode.q),
14316 .ds (),
14317
14318 // to register interface (read)
14319 .qs (cmd_info_12_addr_mode_12_qs)
14320 );
14321
14322 // F[addr_swap_en_12]: 10:10
14323 prim_subreg #(
14324 .DW (1),
14325 .SwAccess(prim_subreg_pkg::SwAccessRW),
14326 .RESVAL (1'h0),
14327 .Mubi (1'b0)
14328 ) u_cmd_info_12_addr_swap_en_12 (
14329 .clk_i (clk_i),
14330 .rst_ni (rst_ni),
14331
14332 // from register interface
14333 .we (cmd_info_12_we),
14334 .wd (cmd_info_12_addr_swap_en_12_wd),
14335
14336 // from internal hardware
14337 .de (1'b0),
14338 .d ('0),
14339
14340 // to internal hardware
14341 .qe (),
14342 .q (reg2hw.cmd_info[12].addr_swap_en.q),
14343 .ds (),
14344
14345 // to register interface (read)
14346 .qs (cmd_info_12_addr_swap_en_12_qs)
14347 );
14348
14349 // F[mbyte_en_12]: 11:11
14350 prim_subreg #(
14351 .DW (1),
14352 .SwAccess(prim_subreg_pkg::SwAccessRW),
14353 .RESVAL (1'h0),
14354 .Mubi (1'b0)
14355 ) u_cmd_info_12_mbyte_en_12 (
14356 .clk_i (clk_i),
14357 .rst_ni (rst_ni),
14358
14359 // from register interface
14360 .we (cmd_info_12_we),
14361 .wd (cmd_info_12_mbyte_en_12_wd),
14362
14363 // from internal hardware
14364 .de (1'b0),
14365 .d ('0),
14366
14367 // to internal hardware
14368 .qe (),
14369 .q (reg2hw.cmd_info[12].mbyte_en.q),
14370 .ds (),
14371
14372 // to register interface (read)
14373 .qs (cmd_info_12_mbyte_en_12_qs)
14374 );
14375
14376 // F[dummy_size_12]: 14:12
14377 prim_subreg #(
14378 .DW (3),
14379 .SwAccess(prim_subreg_pkg::SwAccessRW),
14380 .RESVAL (3'h7),
14381 .Mubi (1'b0)
14382 ) u_cmd_info_12_dummy_size_12 (
14383 .clk_i (clk_i),
14384 .rst_ni (rst_ni),
14385
14386 // from register interface
14387 .we (cmd_info_12_we),
14388 .wd (cmd_info_12_dummy_size_12_wd),
14389
14390 // from internal hardware
14391 .de (1'b0),
14392 .d ('0),
14393
14394 // to internal hardware
14395 .qe (),
14396 .q (reg2hw.cmd_info[12].dummy_size.q),
14397 .ds (),
14398
14399 // to register interface (read)
14400 .qs (cmd_info_12_dummy_size_12_qs)
14401 );
14402
14403 // F[dummy_en_12]: 15:15
14404 prim_subreg #(
14405 .DW (1),
14406 .SwAccess(prim_subreg_pkg::SwAccessRW),
14407 .RESVAL (1'h0),
14408 .Mubi (1'b0)
14409 ) u_cmd_info_12_dummy_en_12 (
14410 .clk_i (clk_i),
14411 .rst_ni (rst_ni),
14412
14413 // from register interface
14414 .we (cmd_info_12_we),
14415 .wd (cmd_info_12_dummy_en_12_wd),
14416
14417 // from internal hardware
14418 .de (1'b0),
14419 .d ('0),
14420
14421 // to internal hardware
14422 .qe (),
14423 .q (reg2hw.cmd_info[12].dummy_en.q),
14424 .ds (),
14425
14426 // to register interface (read)
14427 .qs (cmd_info_12_dummy_en_12_qs)
14428 );
14429
14430 // F[payload_en_12]: 19:16
14431 prim_subreg #(
14432 .DW (4),
14433 .SwAccess(prim_subreg_pkg::SwAccessRW),
14434 .RESVAL (4'h0),
14435 .Mubi (1'b0)
14436 ) u_cmd_info_12_payload_en_12 (
14437 .clk_i (clk_i),
14438 .rst_ni (rst_ni),
14439
14440 // from register interface
14441 .we (cmd_info_12_we),
14442 .wd (cmd_info_12_payload_en_12_wd),
14443
14444 // from internal hardware
14445 .de (1'b0),
14446 .d ('0),
14447
14448 // to internal hardware
14449 .qe (),
14450 .q (reg2hw.cmd_info[12].payload_en.q),
14451 .ds (),
14452
14453 // to register interface (read)
14454 .qs (cmd_info_12_payload_en_12_qs)
14455 );
14456
14457 // F[payload_dir_12]: 20:20
14458 prim_subreg #(
14459 .DW (1),
14460 .SwAccess(prim_subreg_pkg::SwAccessRW),
14461 .RESVAL (1'h0),
14462 .Mubi (1'b0)
14463 ) u_cmd_info_12_payload_dir_12 (
14464 .clk_i (clk_i),
14465 .rst_ni (rst_ni),
14466
14467 // from register interface
14468 .we (cmd_info_12_we),
14469 .wd (cmd_info_12_payload_dir_12_wd),
14470
14471 // from internal hardware
14472 .de (1'b0),
14473 .d ('0),
14474
14475 // to internal hardware
14476 .qe (),
14477 .q (reg2hw.cmd_info[12].payload_dir.q),
14478 .ds (),
14479
14480 // to register interface (read)
14481 .qs (cmd_info_12_payload_dir_12_qs)
14482 );
14483
14484 // F[payload_swap_en_12]: 21:21
14485 prim_subreg #(
14486 .DW (1),
14487 .SwAccess(prim_subreg_pkg::SwAccessRW),
14488 .RESVAL (1'h0),
14489 .Mubi (1'b0)
14490 ) u_cmd_info_12_payload_swap_en_12 (
14491 .clk_i (clk_i),
14492 .rst_ni (rst_ni),
14493
14494 // from register interface
14495 .we (cmd_info_12_we),
14496 .wd (cmd_info_12_payload_swap_en_12_wd),
14497
14498 // from internal hardware
14499 .de (1'b0),
14500 .d ('0),
14501
14502 // to internal hardware
14503 .qe (),
14504 .q (reg2hw.cmd_info[12].payload_swap_en.q),
14505 .ds (),
14506
14507 // to register interface (read)
14508 .qs (cmd_info_12_payload_swap_en_12_qs)
14509 );
14510
14511 // F[read_pipeline_mode_12]: 23:22
14512 prim_subreg #(
14513 .DW (2),
14514 .SwAccess(prim_subreg_pkg::SwAccessRW),
14515 .RESVAL (2'h0),
14516 .Mubi (1'b0)
14517 ) u_cmd_info_12_read_pipeline_mode_12 (
14518 .clk_i (clk_i),
14519 .rst_ni (rst_ni),
14520
14521 // from register interface
14522 .we (cmd_info_12_we),
14523 .wd (cmd_info_12_read_pipeline_mode_12_wd),
14524
14525 // from internal hardware
14526 .de (1'b0),
14527 .d ('0),
14528
14529 // to internal hardware
14530 .qe (),
14531 .q (reg2hw.cmd_info[12].read_pipeline_mode.q),
14532 .ds (),
14533
14534 // to register interface (read)
14535 .qs (cmd_info_12_read_pipeline_mode_12_qs)
14536 );
14537
14538 // F[upload_12]: 24:24
14539 prim_subreg #(
14540 .DW (1),
14541 .SwAccess(prim_subreg_pkg::SwAccessRW),
14542 .RESVAL (1'h0),
14543 .Mubi (1'b0)
14544 ) u_cmd_info_12_upload_12 (
14545 .clk_i (clk_i),
14546 .rst_ni (rst_ni),
14547
14548 // from register interface
14549 .we (cmd_info_12_we),
14550 .wd (cmd_info_12_upload_12_wd),
14551
14552 // from internal hardware
14553 .de (1'b0),
14554 .d ('0),
14555
14556 // to internal hardware
14557 .qe (),
14558 .q (reg2hw.cmd_info[12].upload.q),
14559 .ds (),
14560
14561 // to register interface (read)
14562 .qs (cmd_info_12_upload_12_qs)
14563 );
14564
14565 // F[busy_12]: 25:25
14566 prim_subreg #(
14567 .DW (1),
14568 .SwAccess(prim_subreg_pkg::SwAccessRW),
14569 .RESVAL (1'h0),
14570 .Mubi (1'b0)
14571 ) u_cmd_info_12_busy_12 (
14572 .clk_i (clk_i),
14573 .rst_ni (rst_ni),
14574
14575 // from register interface
14576 .we (cmd_info_12_we),
14577 .wd (cmd_info_12_busy_12_wd),
14578
14579 // from internal hardware
14580 .de (1'b0),
14581 .d ('0),
14582
14583 // to internal hardware
14584 .qe (),
14585 .q (reg2hw.cmd_info[12].busy.q),
14586 .ds (),
14587
14588 // to register interface (read)
14589 .qs (cmd_info_12_busy_12_qs)
14590 );
14591
14592 // F[valid_12]: 31:31
14593 prim_subreg #(
14594 .DW (1),
14595 .SwAccess(prim_subreg_pkg::SwAccessRW),
14596 .RESVAL (1'h0),
14597 .Mubi (1'b0)
14598 ) u_cmd_info_12_valid_12 (
14599 .clk_i (clk_i),
14600 .rst_ni (rst_ni),
14601
14602 // from register interface
14603 .we (cmd_info_12_we),
14604 .wd (cmd_info_12_valid_12_wd),
14605
14606 // from internal hardware
14607 .de (1'b0),
14608 .d ('0),
14609
14610 // to internal hardware
14611 .qe (),
14612 .q (reg2hw.cmd_info[12].valid.q),
14613 .ds (),
14614
14615 // to register interface (read)
14616 .qs (cmd_info_12_valid_12_qs)
14617 );
14618
14619
14620 // Subregister 13 of Multireg cmd_info
14621 // R[cmd_info_13]: V(False)
14622 // F[opcode_13]: 7:0
14623 prim_subreg #(
14624 .DW (8),
14625 .SwAccess(prim_subreg_pkg::SwAccessRW),
14626 .RESVAL (8'h0),
14627 .Mubi (1'b0)
14628 ) u_cmd_info_13_opcode_13 (
14629 .clk_i (clk_i),
14630 .rst_ni (rst_ni),
14631
14632 // from register interface
14633 .we (cmd_info_13_we),
14634 .wd (cmd_info_13_opcode_13_wd),
14635
14636 // from internal hardware
14637 .de (1'b0),
14638 .d ('0),
14639
14640 // to internal hardware
14641 .qe (),
14642 .q (reg2hw.cmd_info[13].opcode.q),
14643 .ds (),
14644
14645 // to register interface (read)
14646 .qs (cmd_info_13_opcode_13_qs)
14647 );
14648
14649 // F[addr_mode_13]: 9:8
14650 prim_subreg #(
14651 .DW (2),
14652 .SwAccess(prim_subreg_pkg::SwAccessRW),
14653 .RESVAL (2'h0),
14654 .Mubi (1'b0)
14655 ) u_cmd_info_13_addr_mode_13 (
14656 .clk_i (clk_i),
14657 .rst_ni (rst_ni),
14658
14659 // from register interface
14660 .we (cmd_info_13_we),
14661 .wd (cmd_info_13_addr_mode_13_wd),
14662
14663 // from internal hardware
14664 .de (1'b0),
14665 .d ('0),
14666
14667 // to internal hardware
14668 .qe (),
14669 .q (reg2hw.cmd_info[13].addr_mode.q),
14670 .ds (),
14671
14672 // to register interface (read)
14673 .qs (cmd_info_13_addr_mode_13_qs)
14674 );
14675
14676 // F[addr_swap_en_13]: 10:10
14677 prim_subreg #(
14678 .DW (1),
14679 .SwAccess(prim_subreg_pkg::SwAccessRW),
14680 .RESVAL (1'h0),
14681 .Mubi (1'b0)
14682 ) u_cmd_info_13_addr_swap_en_13 (
14683 .clk_i (clk_i),
14684 .rst_ni (rst_ni),
14685
14686 // from register interface
14687 .we (cmd_info_13_we),
14688 .wd (cmd_info_13_addr_swap_en_13_wd),
14689
14690 // from internal hardware
14691 .de (1'b0),
14692 .d ('0),
14693
14694 // to internal hardware
14695 .qe (),
14696 .q (reg2hw.cmd_info[13].addr_swap_en.q),
14697 .ds (),
14698
14699 // to register interface (read)
14700 .qs (cmd_info_13_addr_swap_en_13_qs)
14701 );
14702
14703 // F[mbyte_en_13]: 11:11
14704 prim_subreg #(
14705 .DW (1),
14706 .SwAccess(prim_subreg_pkg::SwAccessRW),
14707 .RESVAL (1'h0),
14708 .Mubi (1'b0)
14709 ) u_cmd_info_13_mbyte_en_13 (
14710 .clk_i (clk_i),
14711 .rst_ni (rst_ni),
14712
14713 // from register interface
14714 .we (cmd_info_13_we),
14715 .wd (cmd_info_13_mbyte_en_13_wd),
14716
14717 // from internal hardware
14718 .de (1'b0),
14719 .d ('0),
14720
14721 // to internal hardware
14722 .qe (),
14723 .q (reg2hw.cmd_info[13].mbyte_en.q),
14724 .ds (),
14725
14726 // to register interface (read)
14727 .qs (cmd_info_13_mbyte_en_13_qs)
14728 );
14729
14730 // F[dummy_size_13]: 14:12
14731 prim_subreg #(
14732 .DW (3),
14733 .SwAccess(prim_subreg_pkg::SwAccessRW),
14734 .RESVAL (3'h7),
14735 .Mubi (1'b0)
14736 ) u_cmd_info_13_dummy_size_13 (
14737 .clk_i (clk_i),
14738 .rst_ni (rst_ni),
14739
14740 // from register interface
14741 .we (cmd_info_13_we),
14742 .wd (cmd_info_13_dummy_size_13_wd),
14743
14744 // from internal hardware
14745 .de (1'b0),
14746 .d ('0),
14747
14748 // to internal hardware
14749 .qe (),
14750 .q (reg2hw.cmd_info[13].dummy_size.q),
14751 .ds (),
14752
14753 // to register interface (read)
14754 .qs (cmd_info_13_dummy_size_13_qs)
14755 );
14756
14757 // F[dummy_en_13]: 15:15
14758 prim_subreg #(
14759 .DW (1),
14760 .SwAccess(prim_subreg_pkg::SwAccessRW),
14761 .RESVAL (1'h0),
14762 .Mubi (1'b0)
14763 ) u_cmd_info_13_dummy_en_13 (
14764 .clk_i (clk_i),
14765 .rst_ni (rst_ni),
14766
14767 // from register interface
14768 .we (cmd_info_13_we),
14769 .wd (cmd_info_13_dummy_en_13_wd),
14770
14771 // from internal hardware
14772 .de (1'b0),
14773 .d ('0),
14774
14775 // to internal hardware
14776 .qe (),
14777 .q (reg2hw.cmd_info[13].dummy_en.q),
14778 .ds (),
14779
14780 // to register interface (read)
14781 .qs (cmd_info_13_dummy_en_13_qs)
14782 );
14783
14784 // F[payload_en_13]: 19:16
14785 prim_subreg #(
14786 .DW (4),
14787 .SwAccess(prim_subreg_pkg::SwAccessRW),
14788 .RESVAL (4'h0),
14789 .Mubi (1'b0)
14790 ) u_cmd_info_13_payload_en_13 (
14791 .clk_i (clk_i),
14792 .rst_ni (rst_ni),
14793
14794 // from register interface
14795 .we (cmd_info_13_we),
14796 .wd (cmd_info_13_payload_en_13_wd),
14797
14798 // from internal hardware
14799 .de (1'b0),
14800 .d ('0),
14801
14802 // to internal hardware
14803 .qe (),
14804 .q (reg2hw.cmd_info[13].payload_en.q),
14805 .ds (),
14806
14807 // to register interface (read)
14808 .qs (cmd_info_13_payload_en_13_qs)
14809 );
14810
14811 // F[payload_dir_13]: 20:20
14812 prim_subreg #(
14813 .DW (1),
14814 .SwAccess(prim_subreg_pkg::SwAccessRW),
14815 .RESVAL (1'h0),
14816 .Mubi (1'b0)
14817 ) u_cmd_info_13_payload_dir_13 (
14818 .clk_i (clk_i),
14819 .rst_ni (rst_ni),
14820
14821 // from register interface
14822 .we (cmd_info_13_we),
14823 .wd (cmd_info_13_payload_dir_13_wd),
14824
14825 // from internal hardware
14826 .de (1'b0),
14827 .d ('0),
14828
14829 // to internal hardware
14830 .qe (),
14831 .q (reg2hw.cmd_info[13].payload_dir.q),
14832 .ds (),
14833
14834 // to register interface (read)
14835 .qs (cmd_info_13_payload_dir_13_qs)
14836 );
14837
14838 // F[payload_swap_en_13]: 21:21
14839 prim_subreg #(
14840 .DW (1),
14841 .SwAccess(prim_subreg_pkg::SwAccessRW),
14842 .RESVAL (1'h0),
14843 .Mubi (1'b0)
14844 ) u_cmd_info_13_payload_swap_en_13 (
14845 .clk_i (clk_i),
14846 .rst_ni (rst_ni),
14847
14848 // from register interface
14849 .we (cmd_info_13_we),
14850 .wd (cmd_info_13_payload_swap_en_13_wd),
14851
14852 // from internal hardware
14853 .de (1'b0),
14854 .d ('0),
14855
14856 // to internal hardware
14857 .qe (),
14858 .q (reg2hw.cmd_info[13].payload_swap_en.q),
14859 .ds (),
14860
14861 // to register interface (read)
14862 .qs (cmd_info_13_payload_swap_en_13_qs)
14863 );
14864
14865 // F[read_pipeline_mode_13]: 23:22
14866 prim_subreg #(
14867 .DW (2),
14868 .SwAccess(prim_subreg_pkg::SwAccessRW),
14869 .RESVAL (2'h0),
14870 .Mubi (1'b0)
14871 ) u_cmd_info_13_read_pipeline_mode_13 (
14872 .clk_i (clk_i),
14873 .rst_ni (rst_ni),
14874
14875 // from register interface
14876 .we (cmd_info_13_we),
14877 .wd (cmd_info_13_read_pipeline_mode_13_wd),
14878
14879 // from internal hardware
14880 .de (1'b0),
14881 .d ('0),
14882
14883 // to internal hardware
14884 .qe (),
14885 .q (reg2hw.cmd_info[13].read_pipeline_mode.q),
14886 .ds (),
14887
14888 // to register interface (read)
14889 .qs (cmd_info_13_read_pipeline_mode_13_qs)
14890 );
14891
14892 // F[upload_13]: 24:24
14893 prim_subreg #(
14894 .DW (1),
14895 .SwAccess(prim_subreg_pkg::SwAccessRW),
14896 .RESVAL (1'h0),
14897 .Mubi (1'b0)
14898 ) u_cmd_info_13_upload_13 (
14899 .clk_i (clk_i),
14900 .rst_ni (rst_ni),
14901
14902 // from register interface
14903 .we (cmd_info_13_we),
14904 .wd (cmd_info_13_upload_13_wd),
14905
14906 // from internal hardware
14907 .de (1'b0),
14908 .d ('0),
14909
14910 // to internal hardware
14911 .qe (),
14912 .q (reg2hw.cmd_info[13].upload.q),
14913 .ds (),
14914
14915 // to register interface (read)
14916 .qs (cmd_info_13_upload_13_qs)
14917 );
14918
14919 // F[busy_13]: 25:25
14920 prim_subreg #(
14921 .DW (1),
14922 .SwAccess(prim_subreg_pkg::SwAccessRW),
14923 .RESVAL (1'h0),
14924 .Mubi (1'b0)
14925 ) u_cmd_info_13_busy_13 (
14926 .clk_i (clk_i),
14927 .rst_ni (rst_ni),
14928
14929 // from register interface
14930 .we (cmd_info_13_we),
14931 .wd (cmd_info_13_busy_13_wd),
14932
14933 // from internal hardware
14934 .de (1'b0),
14935 .d ('0),
14936
14937 // to internal hardware
14938 .qe (),
14939 .q (reg2hw.cmd_info[13].busy.q),
14940 .ds (),
14941
14942 // to register interface (read)
14943 .qs (cmd_info_13_busy_13_qs)
14944 );
14945
14946 // F[valid_13]: 31:31
14947 prim_subreg #(
14948 .DW (1),
14949 .SwAccess(prim_subreg_pkg::SwAccessRW),
14950 .RESVAL (1'h0),
14951 .Mubi (1'b0)
14952 ) u_cmd_info_13_valid_13 (
14953 .clk_i (clk_i),
14954 .rst_ni (rst_ni),
14955
14956 // from register interface
14957 .we (cmd_info_13_we),
14958 .wd (cmd_info_13_valid_13_wd),
14959
14960 // from internal hardware
14961 .de (1'b0),
14962 .d ('0),
14963
14964 // to internal hardware
14965 .qe (),
14966 .q (reg2hw.cmd_info[13].valid.q),
14967 .ds (),
14968
14969 // to register interface (read)
14970 .qs (cmd_info_13_valid_13_qs)
14971 );
14972
14973
14974 // Subregister 14 of Multireg cmd_info
14975 // R[cmd_info_14]: V(False)
14976 // F[opcode_14]: 7:0
14977 prim_subreg #(
14978 .DW (8),
14979 .SwAccess(prim_subreg_pkg::SwAccessRW),
14980 .RESVAL (8'h0),
14981 .Mubi (1'b0)
14982 ) u_cmd_info_14_opcode_14 (
14983 .clk_i (clk_i),
14984 .rst_ni (rst_ni),
14985
14986 // from register interface
14987 .we (cmd_info_14_we),
14988 .wd (cmd_info_14_opcode_14_wd),
14989
14990 // from internal hardware
14991 .de (1'b0),
14992 .d ('0),
14993
14994 // to internal hardware
14995 .qe (),
14996 .q (reg2hw.cmd_info[14].opcode.q),
14997 .ds (),
14998
14999 // to register interface (read)
15000 .qs (cmd_info_14_opcode_14_qs)
15001 );
15002
15003 // F[addr_mode_14]: 9:8
15004 prim_subreg #(
15005 .DW (2),
15006 .SwAccess(prim_subreg_pkg::SwAccessRW),
15007 .RESVAL (2'h0),
15008 .Mubi (1'b0)
15009 ) u_cmd_info_14_addr_mode_14 (
15010 .clk_i (clk_i),
15011 .rst_ni (rst_ni),
15012
15013 // from register interface
15014 .we (cmd_info_14_we),
15015 .wd (cmd_info_14_addr_mode_14_wd),
15016
15017 // from internal hardware
15018 .de (1'b0),
15019 .d ('0),
15020
15021 // to internal hardware
15022 .qe (),
15023 .q (reg2hw.cmd_info[14].addr_mode.q),
15024 .ds (),
15025
15026 // to register interface (read)
15027 .qs (cmd_info_14_addr_mode_14_qs)
15028 );
15029
15030 // F[addr_swap_en_14]: 10:10
15031 prim_subreg #(
15032 .DW (1),
15033 .SwAccess(prim_subreg_pkg::SwAccessRW),
15034 .RESVAL (1'h0),
15035 .Mubi (1'b0)
15036 ) u_cmd_info_14_addr_swap_en_14 (
15037 .clk_i (clk_i),
15038 .rst_ni (rst_ni),
15039
15040 // from register interface
15041 .we (cmd_info_14_we),
15042 .wd (cmd_info_14_addr_swap_en_14_wd),
15043
15044 // from internal hardware
15045 .de (1'b0),
15046 .d ('0),
15047
15048 // to internal hardware
15049 .qe (),
15050 .q (reg2hw.cmd_info[14].addr_swap_en.q),
15051 .ds (),
15052
15053 // to register interface (read)
15054 .qs (cmd_info_14_addr_swap_en_14_qs)
15055 );
15056
15057 // F[mbyte_en_14]: 11:11
15058 prim_subreg #(
15059 .DW (1),
15060 .SwAccess(prim_subreg_pkg::SwAccessRW),
15061 .RESVAL (1'h0),
15062 .Mubi (1'b0)
15063 ) u_cmd_info_14_mbyte_en_14 (
15064 .clk_i (clk_i),
15065 .rst_ni (rst_ni),
15066
15067 // from register interface
15068 .we (cmd_info_14_we),
15069 .wd (cmd_info_14_mbyte_en_14_wd),
15070
15071 // from internal hardware
15072 .de (1'b0),
15073 .d ('0),
15074
15075 // to internal hardware
15076 .qe (),
15077 .q (reg2hw.cmd_info[14].mbyte_en.q),
15078 .ds (),
15079
15080 // to register interface (read)
15081 .qs (cmd_info_14_mbyte_en_14_qs)
15082 );
15083
15084 // F[dummy_size_14]: 14:12
15085 prim_subreg #(
15086 .DW (3),
15087 .SwAccess(prim_subreg_pkg::SwAccessRW),
15088 .RESVAL (3'h7),
15089 .Mubi (1'b0)
15090 ) u_cmd_info_14_dummy_size_14 (
15091 .clk_i (clk_i),
15092 .rst_ni (rst_ni),
15093
15094 // from register interface
15095 .we (cmd_info_14_we),
15096 .wd (cmd_info_14_dummy_size_14_wd),
15097
15098 // from internal hardware
15099 .de (1'b0),
15100 .d ('0),
15101
15102 // to internal hardware
15103 .qe (),
15104 .q (reg2hw.cmd_info[14].dummy_size.q),
15105 .ds (),
15106
15107 // to register interface (read)
15108 .qs (cmd_info_14_dummy_size_14_qs)
15109 );
15110
15111 // F[dummy_en_14]: 15:15
15112 prim_subreg #(
15113 .DW (1),
15114 .SwAccess(prim_subreg_pkg::SwAccessRW),
15115 .RESVAL (1'h0),
15116 .Mubi (1'b0)
15117 ) u_cmd_info_14_dummy_en_14 (
15118 .clk_i (clk_i),
15119 .rst_ni (rst_ni),
15120
15121 // from register interface
15122 .we (cmd_info_14_we),
15123 .wd (cmd_info_14_dummy_en_14_wd),
15124
15125 // from internal hardware
15126 .de (1'b0),
15127 .d ('0),
15128
15129 // to internal hardware
15130 .qe (),
15131 .q (reg2hw.cmd_info[14].dummy_en.q),
15132 .ds (),
15133
15134 // to register interface (read)
15135 .qs (cmd_info_14_dummy_en_14_qs)
15136 );
15137
15138 // F[payload_en_14]: 19:16
15139 prim_subreg #(
15140 .DW (4),
15141 .SwAccess(prim_subreg_pkg::SwAccessRW),
15142 .RESVAL (4'h0),
15143 .Mubi (1'b0)
15144 ) u_cmd_info_14_payload_en_14 (
15145 .clk_i (clk_i),
15146 .rst_ni (rst_ni),
15147
15148 // from register interface
15149 .we (cmd_info_14_we),
15150 .wd (cmd_info_14_payload_en_14_wd),
15151
15152 // from internal hardware
15153 .de (1'b0),
15154 .d ('0),
15155
15156 // to internal hardware
15157 .qe (),
15158 .q (reg2hw.cmd_info[14].payload_en.q),
15159 .ds (),
15160
15161 // to register interface (read)
15162 .qs (cmd_info_14_payload_en_14_qs)
15163 );
15164
15165 // F[payload_dir_14]: 20:20
15166 prim_subreg #(
15167 .DW (1),
15168 .SwAccess(prim_subreg_pkg::SwAccessRW),
15169 .RESVAL (1'h0),
15170 .Mubi (1'b0)
15171 ) u_cmd_info_14_payload_dir_14 (
15172 .clk_i (clk_i),
15173 .rst_ni (rst_ni),
15174
15175 // from register interface
15176 .we (cmd_info_14_we),
15177 .wd (cmd_info_14_payload_dir_14_wd),
15178
15179 // from internal hardware
15180 .de (1'b0),
15181 .d ('0),
15182
15183 // to internal hardware
15184 .qe (),
15185 .q (reg2hw.cmd_info[14].payload_dir.q),
15186 .ds (),
15187
15188 // to register interface (read)
15189 .qs (cmd_info_14_payload_dir_14_qs)
15190 );
15191
15192 // F[payload_swap_en_14]: 21:21
15193 prim_subreg #(
15194 .DW (1),
15195 .SwAccess(prim_subreg_pkg::SwAccessRW),
15196 .RESVAL (1'h0),
15197 .Mubi (1'b0)
15198 ) u_cmd_info_14_payload_swap_en_14 (
15199 .clk_i (clk_i),
15200 .rst_ni (rst_ni),
15201
15202 // from register interface
15203 .we (cmd_info_14_we),
15204 .wd (cmd_info_14_payload_swap_en_14_wd),
15205
15206 // from internal hardware
15207 .de (1'b0),
15208 .d ('0),
15209
15210 // to internal hardware
15211 .qe (),
15212 .q (reg2hw.cmd_info[14].payload_swap_en.q),
15213 .ds (),
15214
15215 // to register interface (read)
15216 .qs (cmd_info_14_payload_swap_en_14_qs)
15217 );
15218
15219 // F[read_pipeline_mode_14]: 23:22
15220 prim_subreg #(
15221 .DW (2),
15222 .SwAccess(prim_subreg_pkg::SwAccessRW),
15223 .RESVAL (2'h0),
15224 .Mubi (1'b0)
15225 ) u_cmd_info_14_read_pipeline_mode_14 (
15226 .clk_i (clk_i),
15227 .rst_ni (rst_ni),
15228
15229 // from register interface
15230 .we (cmd_info_14_we),
15231 .wd (cmd_info_14_read_pipeline_mode_14_wd),
15232
15233 // from internal hardware
15234 .de (1'b0),
15235 .d ('0),
15236
15237 // to internal hardware
15238 .qe (),
15239 .q (reg2hw.cmd_info[14].read_pipeline_mode.q),
15240 .ds (),
15241
15242 // to register interface (read)
15243 .qs (cmd_info_14_read_pipeline_mode_14_qs)
15244 );
15245
15246 // F[upload_14]: 24:24
15247 prim_subreg #(
15248 .DW (1),
15249 .SwAccess(prim_subreg_pkg::SwAccessRW),
15250 .RESVAL (1'h0),
15251 .Mubi (1'b0)
15252 ) u_cmd_info_14_upload_14 (
15253 .clk_i (clk_i),
15254 .rst_ni (rst_ni),
15255
15256 // from register interface
15257 .we (cmd_info_14_we),
15258 .wd (cmd_info_14_upload_14_wd),
15259
15260 // from internal hardware
15261 .de (1'b0),
15262 .d ('0),
15263
15264 // to internal hardware
15265 .qe (),
15266 .q (reg2hw.cmd_info[14].upload.q),
15267 .ds (),
15268
15269 // to register interface (read)
15270 .qs (cmd_info_14_upload_14_qs)
15271 );
15272
15273 // F[busy_14]: 25:25
15274 prim_subreg #(
15275 .DW (1),
15276 .SwAccess(prim_subreg_pkg::SwAccessRW),
15277 .RESVAL (1'h0),
15278 .Mubi (1'b0)
15279 ) u_cmd_info_14_busy_14 (
15280 .clk_i (clk_i),
15281 .rst_ni (rst_ni),
15282
15283 // from register interface
15284 .we (cmd_info_14_we),
15285 .wd (cmd_info_14_busy_14_wd),
15286
15287 // from internal hardware
15288 .de (1'b0),
15289 .d ('0),
15290
15291 // to internal hardware
15292 .qe (),
15293 .q (reg2hw.cmd_info[14].busy.q),
15294 .ds (),
15295
15296 // to register interface (read)
15297 .qs (cmd_info_14_busy_14_qs)
15298 );
15299
15300 // F[valid_14]: 31:31
15301 prim_subreg #(
15302 .DW (1),
15303 .SwAccess(prim_subreg_pkg::SwAccessRW),
15304 .RESVAL (1'h0),
15305 .Mubi (1'b0)
15306 ) u_cmd_info_14_valid_14 (
15307 .clk_i (clk_i),
15308 .rst_ni (rst_ni),
15309
15310 // from register interface
15311 .we (cmd_info_14_we),
15312 .wd (cmd_info_14_valid_14_wd),
15313
15314 // from internal hardware
15315 .de (1'b0),
15316 .d ('0),
15317
15318 // to internal hardware
15319 .qe (),
15320 .q (reg2hw.cmd_info[14].valid.q),
15321 .ds (),
15322
15323 // to register interface (read)
15324 .qs (cmd_info_14_valid_14_qs)
15325 );
15326
15327
15328 // Subregister 15 of Multireg cmd_info
15329 // R[cmd_info_15]: V(False)
15330 // F[opcode_15]: 7:0
15331 prim_subreg #(
15332 .DW (8),
15333 .SwAccess(prim_subreg_pkg::SwAccessRW),
15334 .RESVAL (8'h0),
15335 .Mubi (1'b0)
15336 ) u_cmd_info_15_opcode_15 (
15337 .clk_i (clk_i),
15338 .rst_ni (rst_ni),
15339
15340 // from register interface
15341 .we (cmd_info_15_we),
15342 .wd (cmd_info_15_opcode_15_wd),
15343
15344 // from internal hardware
15345 .de (1'b0),
15346 .d ('0),
15347
15348 // to internal hardware
15349 .qe (),
15350 .q (reg2hw.cmd_info[15].opcode.q),
15351 .ds (),
15352
15353 // to register interface (read)
15354 .qs (cmd_info_15_opcode_15_qs)
15355 );
15356
15357 // F[addr_mode_15]: 9:8
15358 prim_subreg #(
15359 .DW (2),
15360 .SwAccess(prim_subreg_pkg::SwAccessRW),
15361 .RESVAL (2'h0),
15362 .Mubi (1'b0)
15363 ) u_cmd_info_15_addr_mode_15 (
15364 .clk_i (clk_i),
15365 .rst_ni (rst_ni),
15366
15367 // from register interface
15368 .we (cmd_info_15_we),
15369 .wd (cmd_info_15_addr_mode_15_wd),
15370
15371 // from internal hardware
15372 .de (1'b0),
15373 .d ('0),
15374
15375 // to internal hardware
15376 .qe (),
15377 .q (reg2hw.cmd_info[15].addr_mode.q),
15378 .ds (),
15379
15380 // to register interface (read)
15381 .qs (cmd_info_15_addr_mode_15_qs)
15382 );
15383
15384 // F[addr_swap_en_15]: 10:10
15385 prim_subreg #(
15386 .DW (1),
15387 .SwAccess(prim_subreg_pkg::SwAccessRW),
15388 .RESVAL (1'h0),
15389 .Mubi (1'b0)
15390 ) u_cmd_info_15_addr_swap_en_15 (
15391 .clk_i (clk_i),
15392 .rst_ni (rst_ni),
15393
15394 // from register interface
15395 .we (cmd_info_15_we),
15396 .wd (cmd_info_15_addr_swap_en_15_wd),
15397
15398 // from internal hardware
15399 .de (1'b0),
15400 .d ('0),
15401
15402 // to internal hardware
15403 .qe (),
15404 .q (reg2hw.cmd_info[15].addr_swap_en.q),
15405 .ds (),
15406
15407 // to register interface (read)
15408 .qs (cmd_info_15_addr_swap_en_15_qs)
15409 );
15410
15411 // F[mbyte_en_15]: 11:11
15412 prim_subreg #(
15413 .DW (1),
15414 .SwAccess(prim_subreg_pkg::SwAccessRW),
15415 .RESVAL (1'h0),
15416 .Mubi (1'b0)
15417 ) u_cmd_info_15_mbyte_en_15 (
15418 .clk_i (clk_i),
15419 .rst_ni (rst_ni),
15420
15421 // from register interface
15422 .we (cmd_info_15_we),
15423 .wd (cmd_info_15_mbyte_en_15_wd),
15424
15425 // from internal hardware
15426 .de (1'b0),
15427 .d ('0),
15428
15429 // to internal hardware
15430 .qe (),
15431 .q (reg2hw.cmd_info[15].mbyte_en.q),
15432 .ds (),
15433
15434 // to register interface (read)
15435 .qs (cmd_info_15_mbyte_en_15_qs)
15436 );
15437
15438 // F[dummy_size_15]: 14:12
15439 prim_subreg #(
15440 .DW (3),
15441 .SwAccess(prim_subreg_pkg::SwAccessRW),
15442 .RESVAL (3'h7),
15443 .Mubi (1'b0)
15444 ) u_cmd_info_15_dummy_size_15 (
15445 .clk_i (clk_i),
15446 .rst_ni (rst_ni),
15447
15448 // from register interface
15449 .we (cmd_info_15_we),
15450 .wd (cmd_info_15_dummy_size_15_wd),
15451
15452 // from internal hardware
15453 .de (1'b0),
15454 .d ('0),
15455
15456 // to internal hardware
15457 .qe (),
15458 .q (reg2hw.cmd_info[15].dummy_size.q),
15459 .ds (),
15460
15461 // to register interface (read)
15462 .qs (cmd_info_15_dummy_size_15_qs)
15463 );
15464
15465 // F[dummy_en_15]: 15:15
15466 prim_subreg #(
15467 .DW (1),
15468 .SwAccess(prim_subreg_pkg::SwAccessRW),
15469 .RESVAL (1'h0),
15470 .Mubi (1'b0)
15471 ) u_cmd_info_15_dummy_en_15 (
15472 .clk_i (clk_i),
15473 .rst_ni (rst_ni),
15474
15475 // from register interface
15476 .we (cmd_info_15_we),
15477 .wd (cmd_info_15_dummy_en_15_wd),
15478
15479 // from internal hardware
15480 .de (1'b0),
15481 .d ('0),
15482
15483 // to internal hardware
15484 .qe (),
15485 .q (reg2hw.cmd_info[15].dummy_en.q),
15486 .ds (),
15487
15488 // to register interface (read)
15489 .qs (cmd_info_15_dummy_en_15_qs)
15490 );
15491
15492 // F[payload_en_15]: 19:16
15493 prim_subreg #(
15494 .DW (4),
15495 .SwAccess(prim_subreg_pkg::SwAccessRW),
15496 .RESVAL (4'h0),
15497 .Mubi (1'b0)
15498 ) u_cmd_info_15_payload_en_15 (
15499 .clk_i (clk_i),
15500 .rst_ni (rst_ni),
15501
15502 // from register interface
15503 .we (cmd_info_15_we),
15504 .wd (cmd_info_15_payload_en_15_wd),
15505
15506 // from internal hardware
15507 .de (1'b0),
15508 .d ('0),
15509
15510 // to internal hardware
15511 .qe (),
15512 .q (reg2hw.cmd_info[15].payload_en.q),
15513 .ds (),
15514
15515 // to register interface (read)
15516 .qs (cmd_info_15_payload_en_15_qs)
15517 );
15518
15519 // F[payload_dir_15]: 20:20
15520 prim_subreg #(
15521 .DW (1),
15522 .SwAccess(prim_subreg_pkg::SwAccessRW),
15523 .RESVAL (1'h0),
15524 .Mubi (1'b0)
15525 ) u_cmd_info_15_payload_dir_15 (
15526 .clk_i (clk_i),
15527 .rst_ni (rst_ni),
15528
15529 // from register interface
15530 .we (cmd_info_15_we),
15531 .wd (cmd_info_15_payload_dir_15_wd),
15532
15533 // from internal hardware
15534 .de (1'b0),
15535 .d ('0),
15536
15537 // to internal hardware
15538 .qe (),
15539 .q (reg2hw.cmd_info[15].payload_dir.q),
15540 .ds (),
15541
15542 // to register interface (read)
15543 .qs (cmd_info_15_payload_dir_15_qs)
15544 );
15545
15546 // F[payload_swap_en_15]: 21:21
15547 prim_subreg #(
15548 .DW (1),
15549 .SwAccess(prim_subreg_pkg::SwAccessRW),
15550 .RESVAL (1'h0),
15551 .Mubi (1'b0)
15552 ) u_cmd_info_15_payload_swap_en_15 (
15553 .clk_i (clk_i),
15554 .rst_ni (rst_ni),
15555
15556 // from register interface
15557 .we (cmd_info_15_we),
15558 .wd (cmd_info_15_payload_swap_en_15_wd),
15559
15560 // from internal hardware
15561 .de (1'b0),
15562 .d ('0),
15563
15564 // to internal hardware
15565 .qe (),
15566 .q (reg2hw.cmd_info[15].payload_swap_en.q),
15567 .ds (),
15568
15569 // to register interface (read)
15570 .qs (cmd_info_15_payload_swap_en_15_qs)
15571 );
15572
15573 // F[read_pipeline_mode_15]: 23:22
15574 prim_subreg #(
15575 .DW (2),
15576 .SwAccess(prim_subreg_pkg::SwAccessRW),
15577 .RESVAL (2'h0),
15578 .Mubi (1'b0)
15579 ) u_cmd_info_15_read_pipeline_mode_15 (
15580 .clk_i (clk_i),
15581 .rst_ni (rst_ni),
15582
15583 // from register interface
15584 .we (cmd_info_15_we),
15585 .wd (cmd_info_15_read_pipeline_mode_15_wd),
15586
15587 // from internal hardware
15588 .de (1'b0),
15589 .d ('0),
15590
15591 // to internal hardware
15592 .qe (),
15593 .q (reg2hw.cmd_info[15].read_pipeline_mode.q),
15594 .ds (),
15595
15596 // to register interface (read)
15597 .qs (cmd_info_15_read_pipeline_mode_15_qs)
15598 );
15599
15600 // F[upload_15]: 24:24
15601 prim_subreg #(
15602 .DW (1),
15603 .SwAccess(prim_subreg_pkg::SwAccessRW),
15604 .RESVAL (1'h0),
15605 .Mubi (1'b0)
15606 ) u_cmd_info_15_upload_15 (
15607 .clk_i (clk_i),
15608 .rst_ni (rst_ni),
15609
15610 // from register interface
15611 .we (cmd_info_15_we),
15612 .wd (cmd_info_15_upload_15_wd),
15613
15614 // from internal hardware
15615 .de (1'b0),
15616 .d ('0),
15617
15618 // to internal hardware
15619 .qe (),
15620 .q (reg2hw.cmd_info[15].upload.q),
15621 .ds (),
15622
15623 // to register interface (read)
15624 .qs (cmd_info_15_upload_15_qs)
15625 );
15626
15627 // F[busy_15]: 25:25
15628 prim_subreg #(
15629 .DW (1),
15630 .SwAccess(prim_subreg_pkg::SwAccessRW),
15631 .RESVAL (1'h0),
15632 .Mubi (1'b0)
15633 ) u_cmd_info_15_busy_15 (
15634 .clk_i (clk_i),
15635 .rst_ni (rst_ni),
15636
15637 // from register interface
15638 .we (cmd_info_15_we),
15639 .wd (cmd_info_15_busy_15_wd),
15640
15641 // from internal hardware
15642 .de (1'b0),
15643 .d ('0),
15644
15645 // to internal hardware
15646 .qe (),
15647 .q (reg2hw.cmd_info[15].busy.q),
15648 .ds (),
15649
15650 // to register interface (read)
15651 .qs (cmd_info_15_busy_15_qs)
15652 );
15653
15654 // F[valid_15]: 31:31
15655 prim_subreg #(
15656 .DW (1),
15657 .SwAccess(prim_subreg_pkg::SwAccessRW),
15658 .RESVAL (1'h0),
15659 .Mubi (1'b0)
15660 ) u_cmd_info_15_valid_15 (
15661 .clk_i (clk_i),
15662 .rst_ni (rst_ni),
15663
15664 // from register interface
15665 .we (cmd_info_15_we),
15666 .wd (cmd_info_15_valid_15_wd),
15667
15668 // from internal hardware
15669 .de (1'b0),
15670 .d ('0),
15671
15672 // to internal hardware
15673 .qe (),
15674 .q (reg2hw.cmd_info[15].valid.q),
15675 .ds (),
15676
15677 // to register interface (read)
15678 .qs (cmd_info_15_valid_15_qs)
15679 );
15680
15681
15682 // Subregister 16 of Multireg cmd_info
15683 // R[cmd_info_16]: V(False)
15684 // F[opcode_16]: 7:0
15685 prim_subreg #(
15686 .DW (8),
15687 .SwAccess(prim_subreg_pkg::SwAccessRW),
15688 .RESVAL (8'h0),
15689 .Mubi (1'b0)
15690 ) u_cmd_info_16_opcode_16 (
15691 .clk_i (clk_i),
15692 .rst_ni (rst_ni),
15693
15694 // from register interface
15695 .we (cmd_info_16_we),
15696 .wd (cmd_info_16_opcode_16_wd),
15697
15698 // from internal hardware
15699 .de (1'b0),
15700 .d ('0),
15701
15702 // to internal hardware
15703 .qe (),
15704 .q (reg2hw.cmd_info[16].opcode.q),
15705 .ds (),
15706
15707 // to register interface (read)
15708 .qs (cmd_info_16_opcode_16_qs)
15709 );
15710
15711 // F[addr_mode_16]: 9:8
15712 prim_subreg #(
15713 .DW (2),
15714 .SwAccess(prim_subreg_pkg::SwAccessRW),
15715 .RESVAL (2'h0),
15716 .Mubi (1'b0)
15717 ) u_cmd_info_16_addr_mode_16 (
15718 .clk_i (clk_i),
15719 .rst_ni (rst_ni),
15720
15721 // from register interface
15722 .we (cmd_info_16_we),
15723 .wd (cmd_info_16_addr_mode_16_wd),
15724
15725 // from internal hardware
15726 .de (1'b0),
15727 .d ('0),
15728
15729 // to internal hardware
15730 .qe (),
15731 .q (reg2hw.cmd_info[16].addr_mode.q),
15732 .ds (),
15733
15734 // to register interface (read)
15735 .qs (cmd_info_16_addr_mode_16_qs)
15736 );
15737
15738 // F[addr_swap_en_16]: 10:10
15739 prim_subreg #(
15740 .DW (1),
15741 .SwAccess(prim_subreg_pkg::SwAccessRW),
15742 .RESVAL (1'h0),
15743 .Mubi (1'b0)
15744 ) u_cmd_info_16_addr_swap_en_16 (
15745 .clk_i (clk_i),
15746 .rst_ni (rst_ni),
15747
15748 // from register interface
15749 .we (cmd_info_16_we),
15750 .wd (cmd_info_16_addr_swap_en_16_wd),
15751
15752 // from internal hardware
15753 .de (1'b0),
15754 .d ('0),
15755
15756 // to internal hardware
15757 .qe (),
15758 .q (reg2hw.cmd_info[16].addr_swap_en.q),
15759 .ds (),
15760
15761 // to register interface (read)
15762 .qs (cmd_info_16_addr_swap_en_16_qs)
15763 );
15764
15765 // F[mbyte_en_16]: 11:11
15766 prim_subreg #(
15767 .DW (1),
15768 .SwAccess(prim_subreg_pkg::SwAccessRW),
15769 .RESVAL (1'h0),
15770 .Mubi (1'b0)
15771 ) u_cmd_info_16_mbyte_en_16 (
15772 .clk_i (clk_i),
15773 .rst_ni (rst_ni),
15774
15775 // from register interface
15776 .we (cmd_info_16_we),
15777 .wd (cmd_info_16_mbyte_en_16_wd),
15778
15779 // from internal hardware
15780 .de (1'b0),
15781 .d ('0),
15782
15783 // to internal hardware
15784 .qe (),
15785 .q (reg2hw.cmd_info[16].mbyte_en.q),
15786 .ds (),
15787
15788 // to register interface (read)
15789 .qs (cmd_info_16_mbyte_en_16_qs)
15790 );
15791
15792 // F[dummy_size_16]: 14:12
15793 prim_subreg #(
15794 .DW (3),
15795 .SwAccess(prim_subreg_pkg::SwAccessRW),
15796 .RESVAL (3'h7),
15797 .Mubi (1'b0)
15798 ) u_cmd_info_16_dummy_size_16 (
15799 .clk_i (clk_i),
15800 .rst_ni (rst_ni),
15801
15802 // from register interface
15803 .we (cmd_info_16_we),
15804 .wd (cmd_info_16_dummy_size_16_wd),
15805
15806 // from internal hardware
15807 .de (1'b0),
15808 .d ('0),
15809
15810 // to internal hardware
15811 .qe (),
15812 .q (reg2hw.cmd_info[16].dummy_size.q),
15813 .ds (),
15814
15815 // to register interface (read)
15816 .qs (cmd_info_16_dummy_size_16_qs)
15817 );
15818
15819 // F[dummy_en_16]: 15:15
15820 prim_subreg #(
15821 .DW (1),
15822 .SwAccess(prim_subreg_pkg::SwAccessRW),
15823 .RESVAL (1'h0),
15824 .Mubi (1'b0)
15825 ) u_cmd_info_16_dummy_en_16 (
15826 .clk_i (clk_i),
15827 .rst_ni (rst_ni),
15828
15829 // from register interface
15830 .we (cmd_info_16_we),
15831 .wd (cmd_info_16_dummy_en_16_wd),
15832
15833 // from internal hardware
15834 .de (1'b0),
15835 .d ('0),
15836
15837 // to internal hardware
15838 .qe (),
15839 .q (reg2hw.cmd_info[16].dummy_en.q),
15840 .ds (),
15841
15842 // to register interface (read)
15843 .qs (cmd_info_16_dummy_en_16_qs)
15844 );
15845
15846 // F[payload_en_16]: 19:16
15847 prim_subreg #(
15848 .DW (4),
15849 .SwAccess(prim_subreg_pkg::SwAccessRW),
15850 .RESVAL (4'h0),
15851 .Mubi (1'b0)
15852 ) u_cmd_info_16_payload_en_16 (
15853 .clk_i (clk_i),
15854 .rst_ni (rst_ni),
15855
15856 // from register interface
15857 .we (cmd_info_16_we),
15858 .wd (cmd_info_16_payload_en_16_wd),
15859
15860 // from internal hardware
15861 .de (1'b0),
15862 .d ('0),
15863
15864 // to internal hardware
15865 .qe (),
15866 .q (reg2hw.cmd_info[16].payload_en.q),
15867 .ds (),
15868
15869 // to register interface (read)
15870 .qs (cmd_info_16_payload_en_16_qs)
15871 );
15872
15873 // F[payload_dir_16]: 20:20
15874 prim_subreg #(
15875 .DW (1),
15876 .SwAccess(prim_subreg_pkg::SwAccessRW),
15877 .RESVAL (1'h0),
15878 .Mubi (1'b0)
15879 ) u_cmd_info_16_payload_dir_16 (
15880 .clk_i (clk_i),
15881 .rst_ni (rst_ni),
15882
15883 // from register interface
15884 .we (cmd_info_16_we),
15885 .wd (cmd_info_16_payload_dir_16_wd),
15886
15887 // from internal hardware
15888 .de (1'b0),
15889 .d ('0),
15890
15891 // to internal hardware
15892 .qe (),
15893 .q (reg2hw.cmd_info[16].payload_dir.q),
15894 .ds (),
15895
15896 // to register interface (read)
15897 .qs (cmd_info_16_payload_dir_16_qs)
15898 );
15899
15900 // F[payload_swap_en_16]: 21:21
15901 prim_subreg #(
15902 .DW (1),
15903 .SwAccess(prim_subreg_pkg::SwAccessRW),
15904 .RESVAL (1'h0),
15905 .Mubi (1'b0)
15906 ) u_cmd_info_16_payload_swap_en_16 (
15907 .clk_i (clk_i),
15908 .rst_ni (rst_ni),
15909
15910 // from register interface
15911 .we (cmd_info_16_we),
15912 .wd (cmd_info_16_payload_swap_en_16_wd),
15913
15914 // from internal hardware
15915 .de (1'b0),
15916 .d ('0),
15917
15918 // to internal hardware
15919 .qe (),
15920 .q (reg2hw.cmd_info[16].payload_swap_en.q),
15921 .ds (),
15922
15923 // to register interface (read)
15924 .qs (cmd_info_16_payload_swap_en_16_qs)
15925 );
15926
15927 // F[read_pipeline_mode_16]: 23:22
15928 prim_subreg #(
15929 .DW (2),
15930 .SwAccess(prim_subreg_pkg::SwAccessRW),
15931 .RESVAL (2'h0),
15932 .Mubi (1'b0)
15933 ) u_cmd_info_16_read_pipeline_mode_16 (
15934 .clk_i (clk_i),
15935 .rst_ni (rst_ni),
15936
15937 // from register interface
15938 .we (cmd_info_16_we),
15939 .wd (cmd_info_16_read_pipeline_mode_16_wd),
15940
15941 // from internal hardware
15942 .de (1'b0),
15943 .d ('0),
15944
15945 // to internal hardware
15946 .qe (),
15947 .q (reg2hw.cmd_info[16].read_pipeline_mode.q),
15948 .ds (),
15949
15950 // to register interface (read)
15951 .qs (cmd_info_16_read_pipeline_mode_16_qs)
15952 );
15953
15954 // F[upload_16]: 24:24
15955 prim_subreg #(
15956 .DW (1),
15957 .SwAccess(prim_subreg_pkg::SwAccessRW),
15958 .RESVAL (1'h0),
15959 .Mubi (1'b0)
15960 ) u_cmd_info_16_upload_16 (
15961 .clk_i (clk_i),
15962 .rst_ni (rst_ni),
15963
15964 // from register interface
15965 .we (cmd_info_16_we),
15966 .wd (cmd_info_16_upload_16_wd),
15967
15968 // from internal hardware
15969 .de (1'b0),
15970 .d ('0),
15971
15972 // to internal hardware
15973 .qe (),
15974 .q (reg2hw.cmd_info[16].upload.q),
15975 .ds (),
15976
15977 // to register interface (read)
15978 .qs (cmd_info_16_upload_16_qs)
15979 );
15980
15981 // F[busy_16]: 25:25
15982 prim_subreg #(
15983 .DW (1),
15984 .SwAccess(prim_subreg_pkg::SwAccessRW),
15985 .RESVAL (1'h0),
15986 .Mubi (1'b0)
15987 ) u_cmd_info_16_busy_16 (
15988 .clk_i (clk_i),
15989 .rst_ni (rst_ni),
15990
15991 // from register interface
15992 .we (cmd_info_16_we),
15993 .wd (cmd_info_16_busy_16_wd),
15994
15995 // from internal hardware
15996 .de (1'b0),
15997 .d ('0),
15998
15999 // to internal hardware
16000 .qe (),
16001 .q (reg2hw.cmd_info[16].busy.q),
16002 .ds (),
16003
16004 // to register interface (read)
16005 .qs (cmd_info_16_busy_16_qs)
16006 );
16007
16008 // F[valid_16]: 31:31
16009 prim_subreg #(
16010 .DW (1),
16011 .SwAccess(prim_subreg_pkg::SwAccessRW),
16012 .RESVAL (1'h0),
16013 .Mubi (1'b0)
16014 ) u_cmd_info_16_valid_16 (
16015 .clk_i (clk_i),
16016 .rst_ni (rst_ni),
16017
16018 // from register interface
16019 .we (cmd_info_16_we),
16020 .wd (cmd_info_16_valid_16_wd),
16021
16022 // from internal hardware
16023 .de (1'b0),
16024 .d ('0),
16025
16026 // to internal hardware
16027 .qe (),
16028 .q (reg2hw.cmd_info[16].valid.q),
16029 .ds (),
16030
16031 // to register interface (read)
16032 .qs (cmd_info_16_valid_16_qs)
16033 );
16034
16035
16036 // Subregister 17 of Multireg cmd_info
16037 // R[cmd_info_17]: V(False)
16038 // F[opcode_17]: 7:0
16039 prim_subreg #(
16040 .DW (8),
16041 .SwAccess(prim_subreg_pkg::SwAccessRW),
16042 .RESVAL (8'h0),
16043 .Mubi (1'b0)
16044 ) u_cmd_info_17_opcode_17 (
16045 .clk_i (clk_i),
16046 .rst_ni (rst_ni),
16047
16048 // from register interface
16049 .we (cmd_info_17_we),
16050 .wd (cmd_info_17_opcode_17_wd),
16051
16052 // from internal hardware
16053 .de (1'b0),
16054 .d ('0),
16055
16056 // to internal hardware
16057 .qe (),
16058 .q (reg2hw.cmd_info[17].opcode.q),
16059 .ds (),
16060
16061 // to register interface (read)
16062 .qs (cmd_info_17_opcode_17_qs)
16063 );
16064
16065 // F[addr_mode_17]: 9:8
16066 prim_subreg #(
16067 .DW (2),
16068 .SwAccess(prim_subreg_pkg::SwAccessRW),
16069 .RESVAL (2'h0),
16070 .Mubi (1'b0)
16071 ) u_cmd_info_17_addr_mode_17 (
16072 .clk_i (clk_i),
16073 .rst_ni (rst_ni),
16074
16075 // from register interface
16076 .we (cmd_info_17_we),
16077 .wd (cmd_info_17_addr_mode_17_wd),
16078
16079 // from internal hardware
16080 .de (1'b0),
16081 .d ('0),
16082
16083 // to internal hardware
16084 .qe (),
16085 .q (reg2hw.cmd_info[17].addr_mode.q),
16086 .ds (),
16087
16088 // to register interface (read)
16089 .qs (cmd_info_17_addr_mode_17_qs)
16090 );
16091
16092 // F[addr_swap_en_17]: 10:10
16093 prim_subreg #(
16094 .DW (1),
16095 .SwAccess(prim_subreg_pkg::SwAccessRW),
16096 .RESVAL (1'h0),
16097 .Mubi (1'b0)
16098 ) u_cmd_info_17_addr_swap_en_17 (
16099 .clk_i (clk_i),
16100 .rst_ni (rst_ni),
16101
16102 // from register interface
16103 .we (cmd_info_17_we),
16104 .wd (cmd_info_17_addr_swap_en_17_wd),
16105
16106 // from internal hardware
16107 .de (1'b0),
16108 .d ('0),
16109
16110 // to internal hardware
16111 .qe (),
16112 .q (reg2hw.cmd_info[17].addr_swap_en.q),
16113 .ds (),
16114
16115 // to register interface (read)
16116 .qs (cmd_info_17_addr_swap_en_17_qs)
16117 );
16118
16119 // F[mbyte_en_17]: 11:11
16120 prim_subreg #(
16121 .DW (1),
16122 .SwAccess(prim_subreg_pkg::SwAccessRW),
16123 .RESVAL (1'h0),
16124 .Mubi (1'b0)
16125 ) u_cmd_info_17_mbyte_en_17 (
16126 .clk_i (clk_i),
16127 .rst_ni (rst_ni),
16128
16129 // from register interface
16130 .we (cmd_info_17_we),
16131 .wd (cmd_info_17_mbyte_en_17_wd),
16132
16133 // from internal hardware
16134 .de (1'b0),
16135 .d ('0),
16136
16137 // to internal hardware
16138 .qe (),
16139 .q (reg2hw.cmd_info[17].mbyte_en.q),
16140 .ds (),
16141
16142 // to register interface (read)
16143 .qs (cmd_info_17_mbyte_en_17_qs)
16144 );
16145
16146 // F[dummy_size_17]: 14:12
16147 prim_subreg #(
16148 .DW (3),
16149 .SwAccess(prim_subreg_pkg::SwAccessRW),
16150 .RESVAL (3'h7),
16151 .Mubi (1'b0)
16152 ) u_cmd_info_17_dummy_size_17 (
16153 .clk_i (clk_i),
16154 .rst_ni (rst_ni),
16155
16156 // from register interface
16157 .we (cmd_info_17_we),
16158 .wd (cmd_info_17_dummy_size_17_wd),
16159
16160 // from internal hardware
16161 .de (1'b0),
16162 .d ('0),
16163
16164 // to internal hardware
16165 .qe (),
16166 .q (reg2hw.cmd_info[17].dummy_size.q),
16167 .ds (),
16168
16169 // to register interface (read)
16170 .qs (cmd_info_17_dummy_size_17_qs)
16171 );
16172
16173 // F[dummy_en_17]: 15:15
16174 prim_subreg #(
16175 .DW (1),
16176 .SwAccess(prim_subreg_pkg::SwAccessRW),
16177 .RESVAL (1'h0),
16178 .Mubi (1'b0)
16179 ) u_cmd_info_17_dummy_en_17 (
16180 .clk_i (clk_i),
16181 .rst_ni (rst_ni),
16182
16183 // from register interface
16184 .we (cmd_info_17_we),
16185 .wd (cmd_info_17_dummy_en_17_wd),
16186
16187 // from internal hardware
16188 .de (1'b0),
16189 .d ('0),
16190
16191 // to internal hardware
16192 .qe (),
16193 .q (reg2hw.cmd_info[17].dummy_en.q),
16194 .ds (),
16195
16196 // to register interface (read)
16197 .qs (cmd_info_17_dummy_en_17_qs)
16198 );
16199
16200 // F[payload_en_17]: 19:16
16201 prim_subreg #(
16202 .DW (4),
16203 .SwAccess(prim_subreg_pkg::SwAccessRW),
16204 .RESVAL (4'h0),
16205 .Mubi (1'b0)
16206 ) u_cmd_info_17_payload_en_17 (
16207 .clk_i (clk_i),
16208 .rst_ni (rst_ni),
16209
16210 // from register interface
16211 .we (cmd_info_17_we),
16212 .wd (cmd_info_17_payload_en_17_wd),
16213
16214 // from internal hardware
16215 .de (1'b0),
16216 .d ('0),
16217
16218 // to internal hardware
16219 .qe (),
16220 .q (reg2hw.cmd_info[17].payload_en.q),
16221 .ds (),
16222
16223 // to register interface (read)
16224 .qs (cmd_info_17_payload_en_17_qs)
16225 );
16226
16227 // F[payload_dir_17]: 20:20
16228 prim_subreg #(
16229 .DW (1),
16230 .SwAccess(prim_subreg_pkg::SwAccessRW),
16231 .RESVAL (1'h0),
16232 .Mubi (1'b0)
16233 ) u_cmd_info_17_payload_dir_17 (
16234 .clk_i (clk_i),
16235 .rst_ni (rst_ni),
16236
16237 // from register interface
16238 .we (cmd_info_17_we),
16239 .wd (cmd_info_17_payload_dir_17_wd),
16240
16241 // from internal hardware
16242 .de (1'b0),
16243 .d ('0),
16244
16245 // to internal hardware
16246 .qe (),
16247 .q (reg2hw.cmd_info[17].payload_dir.q),
16248 .ds (),
16249
16250 // to register interface (read)
16251 .qs (cmd_info_17_payload_dir_17_qs)
16252 );
16253
16254 // F[payload_swap_en_17]: 21:21
16255 prim_subreg #(
16256 .DW (1),
16257 .SwAccess(prim_subreg_pkg::SwAccessRW),
16258 .RESVAL (1'h0),
16259 .Mubi (1'b0)
16260 ) u_cmd_info_17_payload_swap_en_17 (
16261 .clk_i (clk_i),
16262 .rst_ni (rst_ni),
16263
16264 // from register interface
16265 .we (cmd_info_17_we),
16266 .wd (cmd_info_17_payload_swap_en_17_wd),
16267
16268 // from internal hardware
16269 .de (1'b0),
16270 .d ('0),
16271
16272 // to internal hardware
16273 .qe (),
16274 .q (reg2hw.cmd_info[17].payload_swap_en.q),
16275 .ds (),
16276
16277 // to register interface (read)
16278 .qs (cmd_info_17_payload_swap_en_17_qs)
16279 );
16280
16281 // F[read_pipeline_mode_17]: 23:22
16282 prim_subreg #(
16283 .DW (2),
16284 .SwAccess(prim_subreg_pkg::SwAccessRW),
16285 .RESVAL (2'h0),
16286 .Mubi (1'b0)
16287 ) u_cmd_info_17_read_pipeline_mode_17 (
16288 .clk_i (clk_i),
16289 .rst_ni (rst_ni),
16290
16291 // from register interface
16292 .we (cmd_info_17_we),
16293 .wd (cmd_info_17_read_pipeline_mode_17_wd),
16294
16295 // from internal hardware
16296 .de (1'b0),
16297 .d ('0),
16298
16299 // to internal hardware
16300 .qe (),
16301 .q (reg2hw.cmd_info[17].read_pipeline_mode.q),
16302 .ds (),
16303
16304 // to register interface (read)
16305 .qs (cmd_info_17_read_pipeline_mode_17_qs)
16306 );
16307
16308 // F[upload_17]: 24:24
16309 prim_subreg #(
16310 .DW (1),
16311 .SwAccess(prim_subreg_pkg::SwAccessRW),
16312 .RESVAL (1'h0),
16313 .Mubi (1'b0)
16314 ) u_cmd_info_17_upload_17 (
16315 .clk_i (clk_i),
16316 .rst_ni (rst_ni),
16317
16318 // from register interface
16319 .we (cmd_info_17_we),
16320 .wd (cmd_info_17_upload_17_wd),
16321
16322 // from internal hardware
16323 .de (1'b0),
16324 .d ('0),
16325
16326 // to internal hardware
16327 .qe (),
16328 .q (reg2hw.cmd_info[17].upload.q),
16329 .ds (),
16330
16331 // to register interface (read)
16332 .qs (cmd_info_17_upload_17_qs)
16333 );
16334
16335 // F[busy_17]: 25:25
16336 prim_subreg #(
16337 .DW (1),
16338 .SwAccess(prim_subreg_pkg::SwAccessRW),
16339 .RESVAL (1'h0),
16340 .Mubi (1'b0)
16341 ) u_cmd_info_17_busy_17 (
16342 .clk_i (clk_i),
16343 .rst_ni (rst_ni),
16344
16345 // from register interface
16346 .we (cmd_info_17_we),
16347 .wd (cmd_info_17_busy_17_wd),
16348
16349 // from internal hardware
16350 .de (1'b0),
16351 .d ('0),
16352
16353 // to internal hardware
16354 .qe (),
16355 .q (reg2hw.cmd_info[17].busy.q),
16356 .ds (),
16357
16358 // to register interface (read)
16359 .qs (cmd_info_17_busy_17_qs)
16360 );
16361
16362 // F[valid_17]: 31:31
16363 prim_subreg #(
16364 .DW (1),
16365 .SwAccess(prim_subreg_pkg::SwAccessRW),
16366 .RESVAL (1'h0),
16367 .Mubi (1'b0)
16368 ) u_cmd_info_17_valid_17 (
16369 .clk_i (clk_i),
16370 .rst_ni (rst_ni),
16371
16372 // from register interface
16373 .we (cmd_info_17_we),
16374 .wd (cmd_info_17_valid_17_wd),
16375
16376 // from internal hardware
16377 .de (1'b0),
16378 .d ('0),
16379
16380 // to internal hardware
16381 .qe (),
16382 .q (reg2hw.cmd_info[17].valid.q),
16383 .ds (),
16384
16385 // to register interface (read)
16386 .qs (cmd_info_17_valid_17_qs)
16387 );
16388
16389
16390 // Subregister 18 of Multireg cmd_info
16391 // R[cmd_info_18]: V(False)
16392 // F[opcode_18]: 7:0
16393 prim_subreg #(
16394 .DW (8),
16395 .SwAccess(prim_subreg_pkg::SwAccessRW),
16396 .RESVAL (8'h0),
16397 .Mubi (1'b0)
16398 ) u_cmd_info_18_opcode_18 (
16399 .clk_i (clk_i),
16400 .rst_ni (rst_ni),
16401
16402 // from register interface
16403 .we (cmd_info_18_we),
16404 .wd (cmd_info_18_opcode_18_wd),
16405
16406 // from internal hardware
16407 .de (1'b0),
16408 .d ('0),
16409
16410 // to internal hardware
16411 .qe (),
16412 .q (reg2hw.cmd_info[18].opcode.q),
16413 .ds (),
16414
16415 // to register interface (read)
16416 .qs (cmd_info_18_opcode_18_qs)
16417 );
16418
16419 // F[addr_mode_18]: 9:8
16420 prim_subreg #(
16421 .DW (2),
16422 .SwAccess(prim_subreg_pkg::SwAccessRW),
16423 .RESVAL (2'h0),
16424 .Mubi (1'b0)
16425 ) u_cmd_info_18_addr_mode_18 (
16426 .clk_i (clk_i),
16427 .rst_ni (rst_ni),
16428
16429 // from register interface
16430 .we (cmd_info_18_we),
16431 .wd (cmd_info_18_addr_mode_18_wd),
16432
16433 // from internal hardware
16434 .de (1'b0),
16435 .d ('0),
16436
16437 // to internal hardware
16438 .qe (),
16439 .q (reg2hw.cmd_info[18].addr_mode.q),
16440 .ds (),
16441
16442 // to register interface (read)
16443 .qs (cmd_info_18_addr_mode_18_qs)
16444 );
16445
16446 // F[addr_swap_en_18]: 10:10
16447 prim_subreg #(
16448 .DW (1),
16449 .SwAccess(prim_subreg_pkg::SwAccessRW),
16450 .RESVAL (1'h0),
16451 .Mubi (1'b0)
16452 ) u_cmd_info_18_addr_swap_en_18 (
16453 .clk_i (clk_i),
16454 .rst_ni (rst_ni),
16455
16456 // from register interface
16457 .we (cmd_info_18_we),
16458 .wd (cmd_info_18_addr_swap_en_18_wd),
16459
16460 // from internal hardware
16461 .de (1'b0),
16462 .d ('0),
16463
16464 // to internal hardware
16465 .qe (),
16466 .q (reg2hw.cmd_info[18].addr_swap_en.q),
16467 .ds (),
16468
16469 // to register interface (read)
16470 .qs (cmd_info_18_addr_swap_en_18_qs)
16471 );
16472
16473 // F[mbyte_en_18]: 11:11
16474 prim_subreg #(
16475 .DW (1),
16476 .SwAccess(prim_subreg_pkg::SwAccessRW),
16477 .RESVAL (1'h0),
16478 .Mubi (1'b0)
16479 ) u_cmd_info_18_mbyte_en_18 (
16480 .clk_i (clk_i),
16481 .rst_ni (rst_ni),
16482
16483 // from register interface
16484 .we (cmd_info_18_we),
16485 .wd (cmd_info_18_mbyte_en_18_wd),
16486
16487 // from internal hardware
16488 .de (1'b0),
16489 .d ('0),
16490
16491 // to internal hardware
16492 .qe (),
16493 .q (reg2hw.cmd_info[18].mbyte_en.q),
16494 .ds (),
16495
16496 // to register interface (read)
16497 .qs (cmd_info_18_mbyte_en_18_qs)
16498 );
16499
16500 // F[dummy_size_18]: 14:12
16501 prim_subreg #(
16502 .DW (3),
16503 .SwAccess(prim_subreg_pkg::SwAccessRW),
16504 .RESVAL (3'h7),
16505 .Mubi (1'b0)
16506 ) u_cmd_info_18_dummy_size_18 (
16507 .clk_i (clk_i),
16508 .rst_ni (rst_ni),
16509
16510 // from register interface
16511 .we (cmd_info_18_we),
16512 .wd (cmd_info_18_dummy_size_18_wd),
16513
16514 // from internal hardware
16515 .de (1'b0),
16516 .d ('0),
16517
16518 // to internal hardware
16519 .qe (),
16520 .q (reg2hw.cmd_info[18].dummy_size.q),
16521 .ds (),
16522
16523 // to register interface (read)
16524 .qs (cmd_info_18_dummy_size_18_qs)
16525 );
16526
16527 // F[dummy_en_18]: 15:15
16528 prim_subreg #(
16529 .DW (1),
16530 .SwAccess(prim_subreg_pkg::SwAccessRW),
16531 .RESVAL (1'h0),
16532 .Mubi (1'b0)
16533 ) u_cmd_info_18_dummy_en_18 (
16534 .clk_i (clk_i),
16535 .rst_ni (rst_ni),
16536
16537 // from register interface
16538 .we (cmd_info_18_we),
16539 .wd (cmd_info_18_dummy_en_18_wd),
16540
16541 // from internal hardware
16542 .de (1'b0),
16543 .d ('0),
16544
16545 // to internal hardware
16546 .qe (),
16547 .q (reg2hw.cmd_info[18].dummy_en.q),
16548 .ds (),
16549
16550 // to register interface (read)
16551 .qs (cmd_info_18_dummy_en_18_qs)
16552 );
16553
16554 // F[payload_en_18]: 19:16
16555 prim_subreg #(
16556 .DW (4),
16557 .SwAccess(prim_subreg_pkg::SwAccessRW),
16558 .RESVAL (4'h0),
16559 .Mubi (1'b0)
16560 ) u_cmd_info_18_payload_en_18 (
16561 .clk_i (clk_i),
16562 .rst_ni (rst_ni),
16563
16564 // from register interface
16565 .we (cmd_info_18_we),
16566 .wd (cmd_info_18_payload_en_18_wd),
16567
16568 // from internal hardware
16569 .de (1'b0),
16570 .d ('0),
16571
16572 // to internal hardware
16573 .qe (),
16574 .q (reg2hw.cmd_info[18].payload_en.q),
16575 .ds (),
16576
16577 // to register interface (read)
16578 .qs (cmd_info_18_payload_en_18_qs)
16579 );
16580
16581 // F[payload_dir_18]: 20:20
16582 prim_subreg #(
16583 .DW (1),
16584 .SwAccess(prim_subreg_pkg::SwAccessRW),
16585 .RESVAL (1'h0),
16586 .Mubi (1'b0)
16587 ) u_cmd_info_18_payload_dir_18 (
16588 .clk_i (clk_i),
16589 .rst_ni (rst_ni),
16590
16591 // from register interface
16592 .we (cmd_info_18_we),
16593 .wd (cmd_info_18_payload_dir_18_wd),
16594
16595 // from internal hardware
16596 .de (1'b0),
16597 .d ('0),
16598
16599 // to internal hardware
16600 .qe (),
16601 .q (reg2hw.cmd_info[18].payload_dir.q),
16602 .ds (),
16603
16604 // to register interface (read)
16605 .qs (cmd_info_18_payload_dir_18_qs)
16606 );
16607
16608 // F[payload_swap_en_18]: 21:21
16609 prim_subreg #(
16610 .DW (1),
16611 .SwAccess(prim_subreg_pkg::SwAccessRW),
16612 .RESVAL (1'h0),
16613 .Mubi (1'b0)
16614 ) u_cmd_info_18_payload_swap_en_18 (
16615 .clk_i (clk_i),
16616 .rst_ni (rst_ni),
16617
16618 // from register interface
16619 .we (cmd_info_18_we),
16620 .wd (cmd_info_18_payload_swap_en_18_wd),
16621
16622 // from internal hardware
16623 .de (1'b0),
16624 .d ('0),
16625
16626 // to internal hardware
16627 .qe (),
16628 .q (reg2hw.cmd_info[18].payload_swap_en.q),
16629 .ds (),
16630
16631 // to register interface (read)
16632 .qs (cmd_info_18_payload_swap_en_18_qs)
16633 );
16634
16635 // F[read_pipeline_mode_18]: 23:22
16636 prim_subreg #(
16637 .DW (2),
16638 .SwAccess(prim_subreg_pkg::SwAccessRW),
16639 .RESVAL (2'h0),
16640 .Mubi (1'b0)
16641 ) u_cmd_info_18_read_pipeline_mode_18 (
16642 .clk_i (clk_i),
16643 .rst_ni (rst_ni),
16644
16645 // from register interface
16646 .we (cmd_info_18_we),
16647 .wd (cmd_info_18_read_pipeline_mode_18_wd),
16648
16649 // from internal hardware
16650 .de (1'b0),
16651 .d ('0),
16652
16653 // to internal hardware
16654 .qe (),
16655 .q (reg2hw.cmd_info[18].read_pipeline_mode.q),
16656 .ds (),
16657
16658 // to register interface (read)
16659 .qs (cmd_info_18_read_pipeline_mode_18_qs)
16660 );
16661
16662 // F[upload_18]: 24:24
16663 prim_subreg #(
16664 .DW (1),
16665 .SwAccess(prim_subreg_pkg::SwAccessRW),
16666 .RESVAL (1'h0),
16667 .Mubi (1'b0)
16668 ) u_cmd_info_18_upload_18 (
16669 .clk_i (clk_i),
16670 .rst_ni (rst_ni),
16671
16672 // from register interface
16673 .we (cmd_info_18_we),
16674 .wd (cmd_info_18_upload_18_wd),
16675
16676 // from internal hardware
16677 .de (1'b0),
16678 .d ('0),
16679
16680 // to internal hardware
16681 .qe (),
16682 .q (reg2hw.cmd_info[18].upload.q),
16683 .ds (),
16684
16685 // to register interface (read)
16686 .qs (cmd_info_18_upload_18_qs)
16687 );
16688
16689 // F[busy_18]: 25:25
16690 prim_subreg #(
16691 .DW (1),
16692 .SwAccess(prim_subreg_pkg::SwAccessRW),
16693 .RESVAL (1'h0),
16694 .Mubi (1'b0)
16695 ) u_cmd_info_18_busy_18 (
16696 .clk_i (clk_i),
16697 .rst_ni (rst_ni),
16698
16699 // from register interface
16700 .we (cmd_info_18_we),
16701 .wd (cmd_info_18_busy_18_wd),
16702
16703 // from internal hardware
16704 .de (1'b0),
16705 .d ('0),
16706
16707 // to internal hardware
16708 .qe (),
16709 .q (reg2hw.cmd_info[18].busy.q),
16710 .ds (),
16711
16712 // to register interface (read)
16713 .qs (cmd_info_18_busy_18_qs)
16714 );
16715
16716 // F[valid_18]: 31:31
16717 prim_subreg #(
16718 .DW (1),
16719 .SwAccess(prim_subreg_pkg::SwAccessRW),
16720 .RESVAL (1'h0),
16721 .Mubi (1'b0)
16722 ) u_cmd_info_18_valid_18 (
16723 .clk_i (clk_i),
16724 .rst_ni (rst_ni),
16725
16726 // from register interface
16727 .we (cmd_info_18_we),
16728 .wd (cmd_info_18_valid_18_wd),
16729
16730 // from internal hardware
16731 .de (1'b0),
16732 .d ('0),
16733
16734 // to internal hardware
16735 .qe (),
16736 .q (reg2hw.cmd_info[18].valid.q),
16737 .ds (),
16738
16739 // to register interface (read)
16740 .qs (cmd_info_18_valid_18_qs)
16741 );
16742
16743
16744 // Subregister 19 of Multireg cmd_info
16745 // R[cmd_info_19]: V(False)
16746 // F[opcode_19]: 7:0
16747 prim_subreg #(
16748 .DW (8),
16749 .SwAccess(prim_subreg_pkg::SwAccessRW),
16750 .RESVAL (8'h0),
16751 .Mubi (1'b0)
16752 ) u_cmd_info_19_opcode_19 (
16753 .clk_i (clk_i),
16754 .rst_ni (rst_ni),
16755
16756 // from register interface
16757 .we (cmd_info_19_we),
16758 .wd (cmd_info_19_opcode_19_wd),
16759
16760 // from internal hardware
16761 .de (1'b0),
16762 .d ('0),
16763
16764 // to internal hardware
16765 .qe (),
16766 .q (reg2hw.cmd_info[19].opcode.q),
16767 .ds (),
16768
16769 // to register interface (read)
16770 .qs (cmd_info_19_opcode_19_qs)
16771 );
16772
16773 // F[addr_mode_19]: 9:8
16774 prim_subreg #(
16775 .DW (2),
16776 .SwAccess(prim_subreg_pkg::SwAccessRW),
16777 .RESVAL (2'h0),
16778 .Mubi (1'b0)
16779 ) u_cmd_info_19_addr_mode_19 (
16780 .clk_i (clk_i),
16781 .rst_ni (rst_ni),
16782
16783 // from register interface
16784 .we (cmd_info_19_we),
16785 .wd (cmd_info_19_addr_mode_19_wd),
16786
16787 // from internal hardware
16788 .de (1'b0),
16789 .d ('0),
16790
16791 // to internal hardware
16792 .qe (),
16793 .q (reg2hw.cmd_info[19].addr_mode.q),
16794 .ds (),
16795
16796 // to register interface (read)
16797 .qs (cmd_info_19_addr_mode_19_qs)
16798 );
16799
16800 // F[addr_swap_en_19]: 10:10
16801 prim_subreg #(
16802 .DW (1),
16803 .SwAccess(prim_subreg_pkg::SwAccessRW),
16804 .RESVAL (1'h0),
16805 .Mubi (1'b0)
16806 ) u_cmd_info_19_addr_swap_en_19 (
16807 .clk_i (clk_i),
16808 .rst_ni (rst_ni),
16809
16810 // from register interface
16811 .we (cmd_info_19_we),
16812 .wd (cmd_info_19_addr_swap_en_19_wd),
16813
16814 // from internal hardware
16815 .de (1'b0),
16816 .d ('0),
16817
16818 // to internal hardware
16819 .qe (),
16820 .q (reg2hw.cmd_info[19].addr_swap_en.q),
16821 .ds (),
16822
16823 // to register interface (read)
16824 .qs (cmd_info_19_addr_swap_en_19_qs)
16825 );
16826
16827 // F[mbyte_en_19]: 11:11
16828 prim_subreg #(
16829 .DW (1),
16830 .SwAccess(prim_subreg_pkg::SwAccessRW),
16831 .RESVAL (1'h0),
16832 .Mubi (1'b0)
16833 ) u_cmd_info_19_mbyte_en_19 (
16834 .clk_i (clk_i),
16835 .rst_ni (rst_ni),
16836
16837 // from register interface
16838 .we (cmd_info_19_we),
16839 .wd (cmd_info_19_mbyte_en_19_wd),
16840
16841 // from internal hardware
16842 .de (1'b0),
16843 .d ('0),
16844
16845 // to internal hardware
16846 .qe (),
16847 .q (reg2hw.cmd_info[19].mbyte_en.q),
16848 .ds (),
16849
16850 // to register interface (read)
16851 .qs (cmd_info_19_mbyte_en_19_qs)
16852 );
16853
16854 // F[dummy_size_19]: 14:12
16855 prim_subreg #(
16856 .DW (3),
16857 .SwAccess(prim_subreg_pkg::SwAccessRW),
16858 .RESVAL (3'h7),
16859 .Mubi (1'b0)
16860 ) u_cmd_info_19_dummy_size_19 (
16861 .clk_i (clk_i),
16862 .rst_ni (rst_ni),
16863
16864 // from register interface
16865 .we (cmd_info_19_we),
16866 .wd (cmd_info_19_dummy_size_19_wd),
16867
16868 // from internal hardware
16869 .de (1'b0),
16870 .d ('0),
16871
16872 // to internal hardware
16873 .qe (),
16874 .q (reg2hw.cmd_info[19].dummy_size.q),
16875 .ds (),
16876
16877 // to register interface (read)
16878 .qs (cmd_info_19_dummy_size_19_qs)
16879 );
16880
16881 // F[dummy_en_19]: 15:15
16882 prim_subreg #(
16883 .DW (1),
16884 .SwAccess(prim_subreg_pkg::SwAccessRW),
16885 .RESVAL (1'h0),
16886 .Mubi (1'b0)
16887 ) u_cmd_info_19_dummy_en_19 (
16888 .clk_i (clk_i),
16889 .rst_ni (rst_ni),
16890
16891 // from register interface
16892 .we (cmd_info_19_we),
16893 .wd (cmd_info_19_dummy_en_19_wd),
16894
16895 // from internal hardware
16896 .de (1'b0),
16897 .d ('0),
16898
16899 // to internal hardware
16900 .qe (),
16901 .q (reg2hw.cmd_info[19].dummy_en.q),
16902 .ds (),
16903
16904 // to register interface (read)
16905 .qs (cmd_info_19_dummy_en_19_qs)
16906 );
16907
16908 // F[payload_en_19]: 19:16
16909 prim_subreg #(
16910 .DW (4),
16911 .SwAccess(prim_subreg_pkg::SwAccessRW),
16912 .RESVAL (4'h0),
16913 .Mubi (1'b0)
16914 ) u_cmd_info_19_payload_en_19 (
16915 .clk_i (clk_i),
16916 .rst_ni (rst_ni),
16917
16918 // from register interface
16919 .we (cmd_info_19_we),
16920 .wd (cmd_info_19_payload_en_19_wd),
16921
16922 // from internal hardware
16923 .de (1'b0),
16924 .d ('0),
16925
16926 // to internal hardware
16927 .qe (),
16928 .q (reg2hw.cmd_info[19].payload_en.q),
16929 .ds (),
16930
16931 // to register interface (read)
16932 .qs (cmd_info_19_payload_en_19_qs)
16933 );
16934
16935 // F[payload_dir_19]: 20:20
16936 prim_subreg #(
16937 .DW (1),
16938 .SwAccess(prim_subreg_pkg::SwAccessRW),
16939 .RESVAL (1'h0),
16940 .Mubi (1'b0)
16941 ) u_cmd_info_19_payload_dir_19 (
16942 .clk_i (clk_i),
16943 .rst_ni (rst_ni),
16944
16945 // from register interface
16946 .we (cmd_info_19_we),
16947 .wd (cmd_info_19_payload_dir_19_wd),
16948
16949 // from internal hardware
16950 .de (1'b0),
16951 .d ('0),
16952
16953 // to internal hardware
16954 .qe (),
16955 .q (reg2hw.cmd_info[19].payload_dir.q),
16956 .ds (),
16957
16958 // to register interface (read)
16959 .qs (cmd_info_19_payload_dir_19_qs)
16960 );
16961
16962 // F[payload_swap_en_19]: 21:21
16963 prim_subreg #(
16964 .DW (1),
16965 .SwAccess(prim_subreg_pkg::SwAccessRW),
16966 .RESVAL (1'h0),
16967 .Mubi (1'b0)
16968 ) u_cmd_info_19_payload_swap_en_19 (
16969 .clk_i (clk_i),
16970 .rst_ni (rst_ni),
16971
16972 // from register interface
16973 .we (cmd_info_19_we),
16974 .wd (cmd_info_19_payload_swap_en_19_wd),
16975
16976 // from internal hardware
16977 .de (1'b0),
16978 .d ('0),
16979
16980 // to internal hardware
16981 .qe (),
16982 .q (reg2hw.cmd_info[19].payload_swap_en.q),
16983 .ds (),
16984
16985 // to register interface (read)
16986 .qs (cmd_info_19_payload_swap_en_19_qs)
16987 );
16988
16989 // F[read_pipeline_mode_19]: 23:22
16990 prim_subreg #(
16991 .DW (2),
16992 .SwAccess(prim_subreg_pkg::SwAccessRW),
16993 .RESVAL (2'h0),
16994 .Mubi (1'b0)
16995 ) u_cmd_info_19_read_pipeline_mode_19 (
16996 .clk_i (clk_i),
16997 .rst_ni (rst_ni),
16998
16999 // from register interface
17000 .we (cmd_info_19_we),
17001 .wd (cmd_info_19_read_pipeline_mode_19_wd),
17002
17003 // from internal hardware
17004 .de (1'b0),
17005 .d ('0),
17006
17007 // to internal hardware
17008 .qe (),
17009 .q (reg2hw.cmd_info[19].read_pipeline_mode.q),
17010 .ds (),
17011
17012 // to register interface (read)
17013 .qs (cmd_info_19_read_pipeline_mode_19_qs)
17014 );
17015
17016 // F[upload_19]: 24:24
17017 prim_subreg #(
17018 .DW (1),
17019 .SwAccess(prim_subreg_pkg::SwAccessRW),
17020 .RESVAL (1'h0),
17021 .Mubi (1'b0)
17022 ) u_cmd_info_19_upload_19 (
17023 .clk_i (clk_i),
17024 .rst_ni (rst_ni),
17025
17026 // from register interface
17027 .we (cmd_info_19_we),
17028 .wd (cmd_info_19_upload_19_wd),
17029
17030 // from internal hardware
17031 .de (1'b0),
17032 .d ('0),
17033
17034 // to internal hardware
17035 .qe (),
17036 .q (reg2hw.cmd_info[19].upload.q),
17037 .ds (),
17038
17039 // to register interface (read)
17040 .qs (cmd_info_19_upload_19_qs)
17041 );
17042
17043 // F[busy_19]: 25:25
17044 prim_subreg #(
17045 .DW (1),
17046 .SwAccess(prim_subreg_pkg::SwAccessRW),
17047 .RESVAL (1'h0),
17048 .Mubi (1'b0)
17049 ) u_cmd_info_19_busy_19 (
17050 .clk_i (clk_i),
17051 .rst_ni (rst_ni),
17052
17053 // from register interface
17054 .we (cmd_info_19_we),
17055 .wd (cmd_info_19_busy_19_wd),
17056
17057 // from internal hardware
17058 .de (1'b0),
17059 .d ('0),
17060
17061 // to internal hardware
17062 .qe (),
17063 .q (reg2hw.cmd_info[19].busy.q),
17064 .ds (),
17065
17066 // to register interface (read)
17067 .qs (cmd_info_19_busy_19_qs)
17068 );
17069
17070 // F[valid_19]: 31:31
17071 prim_subreg #(
17072 .DW (1),
17073 .SwAccess(prim_subreg_pkg::SwAccessRW),
17074 .RESVAL (1'h0),
17075 .Mubi (1'b0)
17076 ) u_cmd_info_19_valid_19 (
17077 .clk_i (clk_i),
17078 .rst_ni (rst_ni),
17079
17080 // from register interface
17081 .we (cmd_info_19_we),
17082 .wd (cmd_info_19_valid_19_wd),
17083
17084 // from internal hardware
17085 .de (1'b0),
17086 .d ('0),
17087
17088 // to internal hardware
17089 .qe (),
17090 .q (reg2hw.cmd_info[19].valid.q),
17091 .ds (),
17092
17093 // to register interface (read)
17094 .qs (cmd_info_19_valid_19_qs)
17095 );
17096
17097
17098 // Subregister 20 of Multireg cmd_info
17099 // R[cmd_info_20]: V(False)
17100 // F[opcode_20]: 7:0
17101 prim_subreg #(
17102 .DW (8),
17103 .SwAccess(prim_subreg_pkg::SwAccessRW),
17104 .RESVAL (8'h0),
17105 .Mubi (1'b0)
17106 ) u_cmd_info_20_opcode_20 (
17107 .clk_i (clk_i),
17108 .rst_ni (rst_ni),
17109
17110 // from register interface
17111 .we (cmd_info_20_we),
17112 .wd (cmd_info_20_opcode_20_wd),
17113
17114 // from internal hardware
17115 .de (1'b0),
17116 .d ('0),
17117
17118 // to internal hardware
17119 .qe (),
17120 .q (reg2hw.cmd_info[20].opcode.q),
17121 .ds (),
17122
17123 // to register interface (read)
17124 .qs (cmd_info_20_opcode_20_qs)
17125 );
17126
17127 // F[addr_mode_20]: 9:8
17128 prim_subreg #(
17129 .DW (2),
17130 .SwAccess(prim_subreg_pkg::SwAccessRW),
17131 .RESVAL (2'h0),
17132 .Mubi (1'b0)
17133 ) u_cmd_info_20_addr_mode_20 (
17134 .clk_i (clk_i),
17135 .rst_ni (rst_ni),
17136
17137 // from register interface
17138 .we (cmd_info_20_we),
17139 .wd (cmd_info_20_addr_mode_20_wd),
17140
17141 // from internal hardware
17142 .de (1'b0),
17143 .d ('0),
17144
17145 // to internal hardware
17146 .qe (),
17147 .q (reg2hw.cmd_info[20].addr_mode.q),
17148 .ds (),
17149
17150 // to register interface (read)
17151 .qs (cmd_info_20_addr_mode_20_qs)
17152 );
17153
17154 // F[addr_swap_en_20]: 10:10
17155 prim_subreg #(
17156 .DW (1),
17157 .SwAccess(prim_subreg_pkg::SwAccessRW),
17158 .RESVAL (1'h0),
17159 .Mubi (1'b0)
17160 ) u_cmd_info_20_addr_swap_en_20 (
17161 .clk_i (clk_i),
17162 .rst_ni (rst_ni),
17163
17164 // from register interface
17165 .we (cmd_info_20_we),
17166 .wd (cmd_info_20_addr_swap_en_20_wd),
17167
17168 // from internal hardware
17169 .de (1'b0),
17170 .d ('0),
17171
17172 // to internal hardware
17173 .qe (),
17174 .q (reg2hw.cmd_info[20].addr_swap_en.q),
17175 .ds (),
17176
17177 // to register interface (read)
17178 .qs (cmd_info_20_addr_swap_en_20_qs)
17179 );
17180
17181 // F[mbyte_en_20]: 11:11
17182 prim_subreg #(
17183 .DW (1),
17184 .SwAccess(prim_subreg_pkg::SwAccessRW),
17185 .RESVAL (1'h0),
17186 .Mubi (1'b0)
17187 ) u_cmd_info_20_mbyte_en_20 (
17188 .clk_i (clk_i),
17189 .rst_ni (rst_ni),
17190
17191 // from register interface
17192 .we (cmd_info_20_we),
17193 .wd (cmd_info_20_mbyte_en_20_wd),
17194
17195 // from internal hardware
17196 .de (1'b0),
17197 .d ('0),
17198
17199 // to internal hardware
17200 .qe (),
17201 .q (reg2hw.cmd_info[20].mbyte_en.q),
17202 .ds (),
17203
17204 // to register interface (read)
17205 .qs (cmd_info_20_mbyte_en_20_qs)
17206 );
17207
17208 // F[dummy_size_20]: 14:12
17209 prim_subreg #(
17210 .DW (3),
17211 .SwAccess(prim_subreg_pkg::SwAccessRW),
17212 .RESVAL (3'h7),
17213 .Mubi (1'b0)
17214 ) u_cmd_info_20_dummy_size_20 (
17215 .clk_i (clk_i),
17216 .rst_ni (rst_ni),
17217
17218 // from register interface
17219 .we (cmd_info_20_we),
17220 .wd (cmd_info_20_dummy_size_20_wd),
17221
17222 // from internal hardware
17223 .de (1'b0),
17224 .d ('0),
17225
17226 // to internal hardware
17227 .qe (),
17228 .q (reg2hw.cmd_info[20].dummy_size.q),
17229 .ds (),
17230
17231 // to register interface (read)
17232 .qs (cmd_info_20_dummy_size_20_qs)
17233 );
17234
17235 // F[dummy_en_20]: 15:15
17236 prim_subreg #(
17237 .DW (1),
17238 .SwAccess(prim_subreg_pkg::SwAccessRW),
17239 .RESVAL (1'h0),
17240 .Mubi (1'b0)
17241 ) u_cmd_info_20_dummy_en_20 (
17242 .clk_i (clk_i),
17243 .rst_ni (rst_ni),
17244
17245 // from register interface
17246 .we (cmd_info_20_we),
17247 .wd (cmd_info_20_dummy_en_20_wd),
17248
17249 // from internal hardware
17250 .de (1'b0),
17251 .d ('0),
17252
17253 // to internal hardware
17254 .qe (),
17255 .q (reg2hw.cmd_info[20].dummy_en.q),
17256 .ds (),
17257
17258 // to register interface (read)
17259 .qs (cmd_info_20_dummy_en_20_qs)
17260 );
17261
17262 // F[payload_en_20]: 19:16
17263 prim_subreg #(
17264 .DW (4),
17265 .SwAccess(prim_subreg_pkg::SwAccessRW),
17266 .RESVAL (4'h0),
17267 .Mubi (1'b0)
17268 ) u_cmd_info_20_payload_en_20 (
17269 .clk_i (clk_i),
17270 .rst_ni (rst_ni),
17271
17272 // from register interface
17273 .we (cmd_info_20_we),
17274 .wd (cmd_info_20_payload_en_20_wd),
17275
17276 // from internal hardware
17277 .de (1'b0),
17278 .d ('0),
17279
17280 // to internal hardware
17281 .qe (),
17282 .q (reg2hw.cmd_info[20].payload_en.q),
17283 .ds (),
17284
17285 // to register interface (read)
17286 .qs (cmd_info_20_payload_en_20_qs)
17287 );
17288
17289 // F[payload_dir_20]: 20:20
17290 prim_subreg #(
17291 .DW (1),
17292 .SwAccess(prim_subreg_pkg::SwAccessRW),
17293 .RESVAL (1'h0),
17294 .Mubi (1'b0)
17295 ) u_cmd_info_20_payload_dir_20 (
17296 .clk_i (clk_i),
17297 .rst_ni (rst_ni),
17298
17299 // from register interface
17300 .we (cmd_info_20_we),
17301 .wd (cmd_info_20_payload_dir_20_wd),
17302
17303 // from internal hardware
17304 .de (1'b0),
17305 .d ('0),
17306
17307 // to internal hardware
17308 .qe (),
17309 .q (reg2hw.cmd_info[20].payload_dir.q),
17310 .ds (),
17311
17312 // to register interface (read)
17313 .qs (cmd_info_20_payload_dir_20_qs)
17314 );
17315
17316 // F[payload_swap_en_20]: 21:21
17317 prim_subreg #(
17318 .DW (1),
17319 .SwAccess(prim_subreg_pkg::SwAccessRW),
17320 .RESVAL (1'h0),
17321 .Mubi (1'b0)
17322 ) u_cmd_info_20_payload_swap_en_20 (
17323 .clk_i (clk_i),
17324 .rst_ni (rst_ni),
17325
17326 // from register interface
17327 .we (cmd_info_20_we),
17328 .wd (cmd_info_20_payload_swap_en_20_wd),
17329
17330 // from internal hardware
17331 .de (1'b0),
17332 .d ('0),
17333
17334 // to internal hardware
17335 .qe (),
17336 .q (reg2hw.cmd_info[20].payload_swap_en.q),
17337 .ds (),
17338
17339 // to register interface (read)
17340 .qs (cmd_info_20_payload_swap_en_20_qs)
17341 );
17342
17343 // F[read_pipeline_mode_20]: 23:22
17344 prim_subreg #(
17345 .DW (2),
17346 .SwAccess(prim_subreg_pkg::SwAccessRW),
17347 .RESVAL (2'h0),
17348 .Mubi (1'b0)
17349 ) u_cmd_info_20_read_pipeline_mode_20 (
17350 .clk_i (clk_i),
17351 .rst_ni (rst_ni),
17352
17353 // from register interface
17354 .we (cmd_info_20_we),
17355 .wd (cmd_info_20_read_pipeline_mode_20_wd),
17356
17357 // from internal hardware
17358 .de (1'b0),
17359 .d ('0),
17360
17361 // to internal hardware
17362 .qe (),
17363 .q (reg2hw.cmd_info[20].read_pipeline_mode.q),
17364 .ds (),
17365
17366 // to register interface (read)
17367 .qs (cmd_info_20_read_pipeline_mode_20_qs)
17368 );
17369
17370 // F[upload_20]: 24:24
17371 prim_subreg #(
17372 .DW (1),
17373 .SwAccess(prim_subreg_pkg::SwAccessRW),
17374 .RESVAL (1'h0),
17375 .Mubi (1'b0)
17376 ) u_cmd_info_20_upload_20 (
17377 .clk_i (clk_i),
17378 .rst_ni (rst_ni),
17379
17380 // from register interface
17381 .we (cmd_info_20_we),
17382 .wd (cmd_info_20_upload_20_wd),
17383
17384 // from internal hardware
17385 .de (1'b0),
17386 .d ('0),
17387
17388 // to internal hardware
17389 .qe (),
17390 .q (reg2hw.cmd_info[20].upload.q),
17391 .ds (),
17392
17393 // to register interface (read)
17394 .qs (cmd_info_20_upload_20_qs)
17395 );
17396
17397 // F[busy_20]: 25:25
17398 prim_subreg #(
17399 .DW (1),
17400 .SwAccess(prim_subreg_pkg::SwAccessRW),
17401 .RESVAL (1'h0),
17402 .Mubi (1'b0)
17403 ) u_cmd_info_20_busy_20 (
17404 .clk_i (clk_i),
17405 .rst_ni (rst_ni),
17406
17407 // from register interface
17408 .we (cmd_info_20_we),
17409 .wd (cmd_info_20_busy_20_wd),
17410
17411 // from internal hardware
17412 .de (1'b0),
17413 .d ('0),
17414
17415 // to internal hardware
17416 .qe (),
17417 .q (reg2hw.cmd_info[20].busy.q),
17418 .ds (),
17419
17420 // to register interface (read)
17421 .qs (cmd_info_20_busy_20_qs)
17422 );
17423
17424 // F[valid_20]: 31:31
17425 prim_subreg #(
17426 .DW (1),
17427 .SwAccess(prim_subreg_pkg::SwAccessRW),
17428 .RESVAL (1'h0),
17429 .Mubi (1'b0)
17430 ) u_cmd_info_20_valid_20 (
17431 .clk_i (clk_i),
17432 .rst_ni (rst_ni),
17433
17434 // from register interface
17435 .we (cmd_info_20_we),
17436 .wd (cmd_info_20_valid_20_wd),
17437
17438 // from internal hardware
17439 .de (1'b0),
17440 .d ('0),
17441
17442 // to internal hardware
17443 .qe (),
17444 .q (reg2hw.cmd_info[20].valid.q),
17445 .ds (),
17446
17447 // to register interface (read)
17448 .qs (cmd_info_20_valid_20_qs)
17449 );
17450
17451
17452 // Subregister 21 of Multireg cmd_info
17453 // R[cmd_info_21]: V(False)
17454 // F[opcode_21]: 7:0
17455 prim_subreg #(
17456 .DW (8),
17457 .SwAccess(prim_subreg_pkg::SwAccessRW),
17458 .RESVAL (8'h0),
17459 .Mubi (1'b0)
17460 ) u_cmd_info_21_opcode_21 (
17461 .clk_i (clk_i),
17462 .rst_ni (rst_ni),
17463
17464 // from register interface
17465 .we (cmd_info_21_we),
17466 .wd (cmd_info_21_opcode_21_wd),
17467
17468 // from internal hardware
17469 .de (1'b0),
17470 .d ('0),
17471
17472 // to internal hardware
17473 .qe (),
17474 .q (reg2hw.cmd_info[21].opcode.q),
17475 .ds (),
17476
17477 // to register interface (read)
17478 .qs (cmd_info_21_opcode_21_qs)
17479 );
17480
17481 // F[addr_mode_21]: 9:8
17482 prim_subreg #(
17483 .DW (2),
17484 .SwAccess(prim_subreg_pkg::SwAccessRW),
17485 .RESVAL (2'h0),
17486 .Mubi (1'b0)
17487 ) u_cmd_info_21_addr_mode_21 (
17488 .clk_i (clk_i),
17489 .rst_ni (rst_ni),
17490
17491 // from register interface
17492 .we (cmd_info_21_we),
17493 .wd (cmd_info_21_addr_mode_21_wd),
17494
17495 // from internal hardware
17496 .de (1'b0),
17497 .d ('0),
17498
17499 // to internal hardware
17500 .qe (),
17501 .q (reg2hw.cmd_info[21].addr_mode.q),
17502 .ds (),
17503
17504 // to register interface (read)
17505 .qs (cmd_info_21_addr_mode_21_qs)
17506 );
17507
17508 // F[addr_swap_en_21]: 10:10
17509 prim_subreg #(
17510 .DW (1),
17511 .SwAccess(prim_subreg_pkg::SwAccessRW),
17512 .RESVAL (1'h0),
17513 .Mubi (1'b0)
17514 ) u_cmd_info_21_addr_swap_en_21 (
17515 .clk_i (clk_i),
17516 .rst_ni (rst_ni),
17517
17518 // from register interface
17519 .we (cmd_info_21_we),
17520 .wd (cmd_info_21_addr_swap_en_21_wd),
17521
17522 // from internal hardware
17523 .de (1'b0),
17524 .d ('0),
17525
17526 // to internal hardware
17527 .qe (),
17528 .q (reg2hw.cmd_info[21].addr_swap_en.q),
17529 .ds (),
17530
17531 // to register interface (read)
17532 .qs (cmd_info_21_addr_swap_en_21_qs)
17533 );
17534
17535 // F[mbyte_en_21]: 11:11
17536 prim_subreg #(
17537 .DW (1),
17538 .SwAccess(prim_subreg_pkg::SwAccessRW),
17539 .RESVAL (1'h0),
17540 .Mubi (1'b0)
17541 ) u_cmd_info_21_mbyte_en_21 (
17542 .clk_i (clk_i),
17543 .rst_ni (rst_ni),
17544
17545 // from register interface
17546 .we (cmd_info_21_we),
17547 .wd (cmd_info_21_mbyte_en_21_wd),
17548
17549 // from internal hardware
17550 .de (1'b0),
17551 .d ('0),
17552
17553 // to internal hardware
17554 .qe (),
17555 .q (reg2hw.cmd_info[21].mbyte_en.q),
17556 .ds (),
17557
17558 // to register interface (read)
17559 .qs (cmd_info_21_mbyte_en_21_qs)
17560 );
17561
17562 // F[dummy_size_21]: 14:12
17563 prim_subreg #(
17564 .DW (3),
17565 .SwAccess(prim_subreg_pkg::SwAccessRW),
17566 .RESVAL (3'h7),
17567 .Mubi (1'b0)
17568 ) u_cmd_info_21_dummy_size_21 (
17569 .clk_i (clk_i),
17570 .rst_ni (rst_ni),
17571
17572 // from register interface
17573 .we (cmd_info_21_we),
17574 .wd (cmd_info_21_dummy_size_21_wd),
17575
17576 // from internal hardware
17577 .de (1'b0),
17578 .d ('0),
17579
17580 // to internal hardware
17581 .qe (),
17582 .q (reg2hw.cmd_info[21].dummy_size.q),
17583 .ds (),
17584
17585 // to register interface (read)
17586 .qs (cmd_info_21_dummy_size_21_qs)
17587 );
17588
17589 // F[dummy_en_21]: 15:15
17590 prim_subreg #(
17591 .DW (1),
17592 .SwAccess(prim_subreg_pkg::SwAccessRW),
17593 .RESVAL (1'h0),
17594 .Mubi (1'b0)
17595 ) u_cmd_info_21_dummy_en_21 (
17596 .clk_i (clk_i),
17597 .rst_ni (rst_ni),
17598
17599 // from register interface
17600 .we (cmd_info_21_we),
17601 .wd (cmd_info_21_dummy_en_21_wd),
17602
17603 // from internal hardware
17604 .de (1'b0),
17605 .d ('0),
17606
17607 // to internal hardware
17608 .qe (),
17609 .q (reg2hw.cmd_info[21].dummy_en.q),
17610 .ds (),
17611
17612 // to register interface (read)
17613 .qs (cmd_info_21_dummy_en_21_qs)
17614 );
17615
17616 // F[payload_en_21]: 19:16
17617 prim_subreg #(
17618 .DW (4),
17619 .SwAccess(prim_subreg_pkg::SwAccessRW),
17620 .RESVAL (4'h0),
17621 .Mubi (1'b0)
17622 ) u_cmd_info_21_payload_en_21 (
17623 .clk_i (clk_i),
17624 .rst_ni (rst_ni),
17625
17626 // from register interface
17627 .we (cmd_info_21_we),
17628 .wd (cmd_info_21_payload_en_21_wd),
17629
17630 // from internal hardware
17631 .de (1'b0),
17632 .d ('0),
17633
17634 // to internal hardware
17635 .qe (),
17636 .q (reg2hw.cmd_info[21].payload_en.q),
17637 .ds (),
17638
17639 // to register interface (read)
17640 .qs (cmd_info_21_payload_en_21_qs)
17641 );
17642
17643 // F[payload_dir_21]: 20:20
17644 prim_subreg #(
17645 .DW (1),
17646 .SwAccess(prim_subreg_pkg::SwAccessRW),
17647 .RESVAL (1'h0),
17648 .Mubi (1'b0)
17649 ) u_cmd_info_21_payload_dir_21 (
17650 .clk_i (clk_i),
17651 .rst_ni (rst_ni),
17652
17653 // from register interface
17654 .we (cmd_info_21_we),
17655 .wd (cmd_info_21_payload_dir_21_wd),
17656
17657 // from internal hardware
17658 .de (1'b0),
17659 .d ('0),
17660
17661 // to internal hardware
17662 .qe (),
17663 .q (reg2hw.cmd_info[21].payload_dir.q),
17664 .ds (),
17665
17666 // to register interface (read)
17667 .qs (cmd_info_21_payload_dir_21_qs)
17668 );
17669
17670 // F[payload_swap_en_21]: 21:21
17671 prim_subreg #(
17672 .DW (1),
17673 .SwAccess(prim_subreg_pkg::SwAccessRW),
17674 .RESVAL (1'h0),
17675 .Mubi (1'b0)
17676 ) u_cmd_info_21_payload_swap_en_21 (
17677 .clk_i (clk_i),
17678 .rst_ni (rst_ni),
17679
17680 // from register interface
17681 .we (cmd_info_21_we),
17682 .wd (cmd_info_21_payload_swap_en_21_wd),
17683
17684 // from internal hardware
17685 .de (1'b0),
17686 .d ('0),
17687
17688 // to internal hardware
17689 .qe (),
17690 .q (reg2hw.cmd_info[21].payload_swap_en.q),
17691 .ds (),
17692
17693 // to register interface (read)
17694 .qs (cmd_info_21_payload_swap_en_21_qs)
17695 );
17696
17697 // F[read_pipeline_mode_21]: 23:22
17698 prim_subreg #(
17699 .DW (2),
17700 .SwAccess(prim_subreg_pkg::SwAccessRW),
17701 .RESVAL (2'h0),
17702 .Mubi (1'b0)
17703 ) u_cmd_info_21_read_pipeline_mode_21 (
17704 .clk_i (clk_i),
17705 .rst_ni (rst_ni),
17706
17707 // from register interface
17708 .we (cmd_info_21_we),
17709 .wd (cmd_info_21_read_pipeline_mode_21_wd),
17710
17711 // from internal hardware
17712 .de (1'b0),
17713 .d ('0),
17714
17715 // to internal hardware
17716 .qe (),
17717 .q (reg2hw.cmd_info[21].read_pipeline_mode.q),
17718 .ds (),
17719
17720 // to register interface (read)
17721 .qs (cmd_info_21_read_pipeline_mode_21_qs)
17722 );
17723
17724 // F[upload_21]: 24:24
17725 prim_subreg #(
17726 .DW (1),
17727 .SwAccess(prim_subreg_pkg::SwAccessRW),
17728 .RESVAL (1'h0),
17729 .Mubi (1'b0)
17730 ) u_cmd_info_21_upload_21 (
17731 .clk_i (clk_i),
17732 .rst_ni (rst_ni),
17733
17734 // from register interface
17735 .we (cmd_info_21_we),
17736 .wd (cmd_info_21_upload_21_wd),
17737
17738 // from internal hardware
17739 .de (1'b0),
17740 .d ('0),
17741
17742 // to internal hardware
17743 .qe (),
17744 .q (reg2hw.cmd_info[21].upload.q),
17745 .ds (),
17746
17747 // to register interface (read)
17748 .qs (cmd_info_21_upload_21_qs)
17749 );
17750
17751 // F[busy_21]: 25:25
17752 prim_subreg #(
17753 .DW (1),
17754 .SwAccess(prim_subreg_pkg::SwAccessRW),
17755 .RESVAL (1'h0),
17756 .Mubi (1'b0)
17757 ) u_cmd_info_21_busy_21 (
17758 .clk_i (clk_i),
17759 .rst_ni (rst_ni),
17760
17761 // from register interface
17762 .we (cmd_info_21_we),
17763 .wd (cmd_info_21_busy_21_wd),
17764
17765 // from internal hardware
17766 .de (1'b0),
17767 .d ('0),
17768
17769 // to internal hardware
17770 .qe (),
17771 .q (reg2hw.cmd_info[21].busy.q),
17772 .ds (),
17773
17774 // to register interface (read)
17775 .qs (cmd_info_21_busy_21_qs)
17776 );
17777
17778 // F[valid_21]: 31:31
17779 prim_subreg #(
17780 .DW (1),
17781 .SwAccess(prim_subreg_pkg::SwAccessRW),
17782 .RESVAL (1'h0),
17783 .Mubi (1'b0)
17784 ) u_cmd_info_21_valid_21 (
17785 .clk_i (clk_i),
17786 .rst_ni (rst_ni),
17787
17788 // from register interface
17789 .we (cmd_info_21_we),
17790 .wd (cmd_info_21_valid_21_wd),
17791
17792 // from internal hardware
17793 .de (1'b0),
17794 .d ('0),
17795
17796 // to internal hardware
17797 .qe (),
17798 .q (reg2hw.cmd_info[21].valid.q),
17799 .ds (),
17800
17801 // to register interface (read)
17802 .qs (cmd_info_21_valid_21_qs)
17803 );
17804
17805
17806 // Subregister 22 of Multireg cmd_info
17807 // R[cmd_info_22]: V(False)
17808 // F[opcode_22]: 7:0
17809 prim_subreg #(
17810 .DW (8),
17811 .SwAccess(prim_subreg_pkg::SwAccessRW),
17812 .RESVAL (8'h0),
17813 .Mubi (1'b0)
17814 ) u_cmd_info_22_opcode_22 (
17815 .clk_i (clk_i),
17816 .rst_ni (rst_ni),
17817
17818 // from register interface
17819 .we (cmd_info_22_we),
17820 .wd (cmd_info_22_opcode_22_wd),
17821
17822 // from internal hardware
17823 .de (1'b0),
17824 .d ('0),
17825
17826 // to internal hardware
17827 .qe (),
17828 .q (reg2hw.cmd_info[22].opcode.q),
17829 .ds (),
17830
17831 // to register interface (read)
17832 .qs (cmd_info_22_opcode_22_qs)
17833 );
17834
17835 // F[addr_mode_22]: 9:8
17836 prim_subreg #(
17837 .DW (2),
17838 .SwAccess(prim_subreg_pkg::SwAccessRW),
17839 .RESVAL (2'h0),
17840 .Mubi (1'b0)
17841 ) u_cmd_info_22_addr_mode_22 (
17842 .clk_i (clk_i),
17843 .rst_ni (rst_ni),
17844
17845 // from register interface
17846 .we (cmd_info_22_we),
17847 .wd (cmd_info_22_addr_mode_22_wd),
17848
17849 // from internal hardware
17850 .de (1'b0),
17851 .d ('0),
17852
17853 // to internal hardware
17854 .qe (),
17855 .q (reg2hw.cmd_info[22].addr_mode.q),
17856 .ds (),
17857
17858 // to register interface (read)
17859 .qs (cmd_info_22_addr_mode_22_qs)
17860 );
17861
17862 // F[addr_swap_en_22]: 10:10
17863 prim_subreg #(
17864 .DW (1),
17865 .SwAccess(prim_subreg_pkg::SwAccessRW),
17866 .RESVAL (1'h0),
17867 .Mubi (1'b0)
17868 ) u_cmd_info_22_addr_swap_en_22 (
17869 .clk_i (clk_i),
17870 .rst_ni (rst_ni),
17871
17872 // from register interface
17873 .we (cmd_info_22_we),
17874 .wd (cmd_info_22_addr_swap_en_22_wd),
17875
17876 // from internal hardware
17877 .de (1'b0),
17878 .d ('0),
17879
17880 // to internal hardware
17881 .qe (),
17882 .q (reg2hw.cmd_info[22].addr_swap_en.q),
17883 .ds (),
17884
17885 // to register interface (read)
17886 .qs (cmd_info_22_addr_swap_en_22_qs)
17887 );
17888
17889 // F[mbyte_en_22]: 11:11
17890 prim_subreg #(
17891 .DW (1),
17892 .SwAccess(prim_subreg_pkg::SwAccessRW),
17893 .RESVAL (1'h0),
17894 .Mubi (1'b0)
17895 ) u_cmd_info_22_mbyte_en_22 (
17896 .clk_i (clk_i),
17897 .rst_ni (rst_ni),
17898
17899 // from register interface
17900 .we (cmd_info_22_we),
17901 .wd (cmd_info_22_mbyte_en_22_wd),
17902
17903 // from internal hardware
17904 .de (1'b0),
17905 .d ('0),
17906
17907 // to internal hardware
17908 .qe (),
17909 .q (reg2hw.cmd_info[22].mbyte_en.q),
17910 .ds (),
17911
17912 // to register interface (read)
17913 .qs (cmd_info_22_mbyte_en_22_qs)
17914 );
17915
17916 // F[dummy_size_22]: 14:12
17917 prim_subreg #(
17918 .DW (3),
17919 .SwAccess(prim_subreg_pkg::SwAccessRW),
17920 .RESVAL (3'h7),
17921 .Mubi (1'b0)
17922 ) u_cmd_info_22_dummy_size_22 (
17923 .clk_i (clk_i),
17924 .rst_ni (rst_ni),
17925
17926 // from register interface
17927 .we (cmd_info_22_we),
17928 .wd (cmd_info_22_dummy_size_22_wd),
17929
17930 // from internal hardware
17931 .de (1'b0),
17932 .d ('0),
17933
17934 // to internal hardware
17935 .qe (),
17936 .q (reg2hw.cmd_info[22].dummy_size.q),
17937 .ds (),
17938
17939 // to register interface (read)
17940 .qs (cmd_info_22_dummy_size_22_qs)
17941 );
17942
17943 // F[dummy_en_22]: 15:15
17944 prim_subreg #(
17945 .DW (1),
17946 .SwAccess(prim_subreg_pkg::SwAccessRW),
17947 .RESVAL (1'h0),
17948 .Mubi (1'b0)
17949 ) u_cmd_info_22_dummy_en_22 (
17950 .clk_i (clk_i),
17951 .rst_ni (rst_ni),
17952
17953 // from register interface
17954 .we (cmd_info_22_we),
17955 .wd (cmd_info_22_dummy_en_22_wd),
17956
17957 // from internal hardware
17958 .de (1'b0),
17959 .d ('0),
17960
17961 // to internal hardware
17962 .qe (),
17963 .q (reg2hw.cmd_info[22].dummy_en.q),
17964 .ds (),
17965
17966 // to register interface (read)
17967 .qs (cmd_info_22_dummy_en_22_qs)
17968 );
17969
17970 // F[payload_en_22]: 19:16
17971 prim_subreg #(
17972 .DW (4),
17973 .SwAccess(prim_subreg_pkg::SwAccessRW),
17974 .RESVAL (4'h0),
17975 .Mubi (1'b0)
17976 ) u_cmd_info_22_payload_en_22 (
17977 .clk_i (clk_i),
17978 .rst_ni (rst_ni),
17979
17980 // from register interface
17981 .we (cmd_info_22_we),
17982 .wd (cmd_info_22_payload_en_22_wd),
17983
17984 // from internal hardware
17985 .de (1'b0),
17986 .d ('0),
17987
17988 // to internal hardware
17989 .qe (),
17990 .q (reg2hw.cmd_info[22].payload_en.q),
17991 .ds (),
17992
17993 // to register interface (read)
17994 .qs (cmd_info_22_payload_en_22_qs)
17995 );
17996
17997 // F[payload_dir_22]: 20:20
17998 prim_subreg #(
17999 .DW (1),
18000 .SwAccess(prim_subreg_pkg::SwAccessRW),
18001 .RESVAL (1'h0),
18002 .Mubi (1'b0)
18003 ) u_cmd_info_22_payload_dir_22 (
18004 .clk_i (clk_i),
18005 .rst_ni (rst_ni),
18006
18007 // from register interface
18008 .we (cmd_info_22_we),
18009 .wd (cmd_info_22_payload_dir_22_wd),
18010
18011 // from internal hardware
18012 .de (1'b0),
18013 .d ('0),
18014
18015 // to internal hardware
18016 .qe (),
18017 .q (reg2hw.cmd_info[22].payload_dir.q),
18018 .ds (),
18019
18020 // to register interface (read)
18021 .qs (cmd_info_22_payload_dir_22_qs)
18022 );
18023
18024 // F[payload_swap_en_22]: 21:21
18025 prim_subreg #(
18026 .DW (1),
18027 .SwAccess(prim_subreg_pkg::SwAccessRW),
18028 .RESVAL (1'h0),
18029 .Mubi (1'b0)
18030 ) u_cmd_info_22_payload_swap_en_22 (
18031 .clk_i (clk_i),
18032 .rst_ni (rst_ni),
18033
18034 // from register interface
18035 .we (cmd_info_22_we),
18036 .wd (cmd_info_22_payload_swap_en_22_wd),
18037
18038 // from internal hardware
18039 .de (1'b0),
18040 .d ('0),
18041
18042 // to internal hardware
18043 .qe (),
18044 .q (reg2hw.cmd_info[22].payload_swap_en.q),
18045 .ds (),
18046
18047 // to register interface (read)
18048 .qs (cmd_info_22_payload_swap_en_22_qs)
18049 );
18050
18051 // F[read_pipeline_mode_22]: 23:22
18052 prim_subreg #(
18053 .DW (2),
18054 .SwAccess(prim_subreg_pkg::SwAccessRW),
18055 .RESVAL (2'h0),
18056 .Mubi (1'b0)
18057 ) u_cmd_info_22_read_pipeline_mode_22 (
18058 .clk_i (clk_i),
18059 .rst_ni (rst_ni),
18060
18061 // from register interface
18062 .we (cmd_info_22_we),
18063 .wd (cmd_info_22_read_pipeline_mode_22_wd),
18064
18065 // from internal hardware
18066 .de (1'b0),
18067 .d ('0),
18068
18069 // to internal hardware
18070 .qe (),
18071 .q (reg2hw.cmd_info[22].read_pipeline_mode.q),
18072 .ds (),
18073
18074 // to register interface (read)
18075 .qs (cmd_info_22_read_pipeline_mode_22_qs)
18076 );
18077
18078 // F[upload_22]: 24:24
18079 prim_subreg #(
18080 .DW (1),
18081 .SwAccess(prim_subreg_pkg::SwAccessRW),
18082 .RESVAL (1'h0),
18083 .Mubi (1'b0)
18084 ) u_cmd_info_22_upload_22 (
18085 .clk_i (clk_i),
18086 .rst_ni (rst_ni),
18087
18088 // from register interface
18089 .we (cmd_info_22_we),
18090 .wd (cmd_info_22_upload_22_wd),
18091
18092 // from internal hardware
18093 .de (1'b0),
18094 .d ('0),
18095
18096 // to internal hardware
18097 .qe (),
18098 .q (reg2hw.cmd_info[22].upload.q),
18099 .ds (),
18100
18101 // to register interface (read)
18102 .qs (cmd_info_22_upload_22_qs)
18103 );
18104
18105 // F[busy_22]: 25:25
18106 prim_subreg #(
18107 .DW (1),
18108 .SwAccess(prim_subreg_pkg::SwAccessRW),
18109 .RESVAL (1'h0),
18110 .Mubi (1'b0)
18111 ) u_cmd_info_22_busy_22 (
18112 .clk_i (clk_i),
18113 .rst_ni (rst_ni),
18114
18115 // from register interface
18116 .we (cmd_info_22_we),
18117 .wd (cmd_info_22_busy_22_wd),
18118
18119 // from internal hardware
18120 .de (1'b0),
18121 .d ('0),
18122
18123 // to internal hardware
18124 .qe (),
18125 .q (reg2hw.cmd_info[22].busy.q),
18126 .ds (),
18127
18128 // to register interface (read)
18129 .qs (cmd_info_22_busy_22_qs)
18130 );
18131
18132 // F[valid_22]: 31:31
18133 prim_subreg #(
18134 .DW (1),
18135 .SwAccess(prim_subreg_pkg::SwAccessRW),
18136 .RESVAL (1'h0),
18137 .Mubi (1'b0)
18138 ) u_cmd_info_22_valid_22 (
18139 .clk_i (clk_i),
18140 .rst_ni (rst_ni),
18141
18142 // from register interface
18143 .we (cmd_info_22_we),
18144 .wd (cmd_info_22_valid_22_wd),
18145
18146 // from internal hardware
18147 .de (1'b0),
18148 .d ('0),
18149
18150 // to internal hardware
18151 .qe (),
18152 .q (reg2hw.cmd_info[22].valid.q),
18153 .ds (),
18154
18155 // to register interface (read)
18156 .qs (cmd_info_22_valid_22_qs)
18157 );
18158
18159
18160 // Subregister 23 of Multireg cmd_info
18161 // R[cmd_info_23]: V(False)
18162 // F[opcode_23]: 7:0
18163 prim_subreg #(
18164 .DW (8),
18165 .SwAccess(prim_subreg_pkg::SwAccessRW),
18166 .RESVAL (8'h0),
18167 .Mubi (1'b0)
18168 ) u_cmd_info_23_opcode_23 (
18169 .clk_i (clk_i),
18170 .rst_ni (rst_ni),
18171
18172 // from register interface
18173 .we (cmd_info_23_we),
18174 .wd (cmd_info_23_opcode_23_wd),
18175
18176 // from internal hardware
18177 .de (1'b0),
18178 .d ('0),
18179
18180 // to internal hardware
18181 .qe (),
18182 .q (reg2hw.cmd_info[23].opcode.q),
18183 .ds (),
18184
18185 // to register interface (read)
18186 .qs (cmd_info_23_opcode_23_qs)
18187 );
18188
18189 // F[addr_mode_23]: 9:8
18190 prim_subreg #(
18191 .DW (2),
18192 .SwAccess(prim_subreg_pkg::SwAccessRW),
18193 .RESVAL (2'h0),
18194 .Mubi (1'b0)
18195 ) u_cmd_info_23_addr_mode_23 (
18196 .clk_i (clk_i),
18197 .rst_ni (rst_ni),
18198
18199 // from register interface
18200 .we (cmd_info_23_we),
18201 .wd (cmd_info_23_addr_mode_23_wd),
18202
18203 // from internal hardware
18204 .de (1'b0),
18205 .d ('0),
18206
18207 // to internal hardware
18208 .qe (),
18209 .q (reg2hw.cmd_info[23].addr_mode.q),
18210 .ds (),
18211
18212 // to register interface (read)
18213 .qs (cmd_info_23_addr_mode_23_qs)
18214 );
18215
18216 // F[addr_swap_en_23]: 10:10
18217 prim_subreg #(
18218 .DW (1),
18219 .SwAccess(prim_subreg_pkg::SwAccessRW),
18220 .RESVAL (1'h0),
18221 .Mubi (1'b0)
18222 ) u_cmd_info_23_addr_swap_en_23 (
18223 .clk_i (clk_i),
18224 .rst_ni (rst_ni),
18225
18226 // from register interface
18227 .we (cmd_info_23_we),
18228 .wd (cmd_info_23_addr_swap_en_23_wd),
18229
18230 // from internal hardware
18231 .de (1'b0),
18232 .d ('0),
18233
18234 // to internal hardware
18235 .qe (),
18236 .q (reg2hw.cmd_info[23].addr_swap_en.q),
18237 .ds (),
18238
18239 // to register interface (read)
18240 .qs (cmd_info_23_addr_swap_en_23_qs)
18241 );
18242
18243 // F[mbyte_en_23]: 11:11
18244 prim_subreg #(
18245 .DW (1),
18246 .SwAccess(prim_subreg_pkg::SwAccessRW),
18247 .RESVAL (1'h0),
18248 .Mubi (1'b0)
18249 ) u_cmd_info_23_mbyte_en_23 (
18250 .clk_i (clk_i),
18251 .rst_ni (rst_ni),
18252
18253 // from register interface
18254 .we (cmd_info_23_we),
18255 .wd (cmd_info_23_mbyte_en_23_wd),
18256
18257 // from internal hardware
18258 .de (1'b0),
18259 .d ('0),
18260
18261 // to internal hardware
18262 .qe (),
18263 .q (reg2hw.cmd_info[23].mbyte_en.q),
18264 .ds (),
18265
18266 // to register interface (read)
18267 .qs (cmd_info_23_mbyte_en_23_qs)
18268 );
18269
18270 // F[dummy_size_23]: 14:12
18271 prim_subreg #(
18272 .DW (3),
18273 .SwAccess(prim_subreg_pkg::SwAccessRW),
18274 .RESVAL (3'h7),
18275 .Mubi (1'b0)
18276 ) u_cmd_info_23_dummy_size_23 (
18277 .clk_i (clk_i),
18278 .rst_ni (rst_ni),
18279
18280 // from register interface
18281 .we (cmd_info_23_we),
18282 .wd (cmd_info_23_dummy_size_23_wd),
18283
18284 // from internal hardware
18285 .de (1'b0),
18286 .d ('0),
18287
18288 // to internal hardware
18289 .qe (),
18290 .q (reg2hw.cmd_info[23].dummy_size.q),
18291 .ds (),
18292
18293 // to register interface (read)
18294 .qs (cmd_info_23_dummy_size_23_qs)
18295 );
18296
18297 // F[dummy_en_23]: 15:15
18298 prim_subreg #(
18299 .DW (1),
18300 .SwAccess(prim_subreg_pkg::SwAccessRW),
18301 .RESVAL (1'h0),
18302 .Mubi (1'b0)
18303 ) u_cmd_info_23_dummy_en_23 (
18304 .clk_i (clk_i),
18305 .rst_ni (rst_ni),
18306
18307 // from register interface
18308 .we (cmd_info_23_we),
18309 .wd (cmd_info_23_dummy_en_23_wd),
18310
18311 // from internal hardware
18312 .de (1'b0),
18313 .d ('0),
18314
18315 // to internal hardware
18316 .qe (),
18317 .q (reg2hw.cmd_info[23].dummy_en.q),
18318 .ds (),
18319
18320 // to register interface (read)
18321 .qs (cmd_info_23_dummy_en_23_qs)
18322 );
18323
18324 // F[payload_en_23]: 19:16
18325 prim_subreg #(
18326 .DW (4),
18327 .SwAccess(prim_subreg_pkg::SwAccessRW),
18328 .RESVAL (4'h0),
18329 .Mubi (1'b0)
18330 ) u_cmd_info_23_payload_en_23 (
18331 .clk_i (clk_i),
18332 .rst_ni (rst_ni),
18333
18334 // from register interface
18335 .we (cmd_info_23_we),
18336 .wd (cmd_info_23_payload_en_23_wd),
18337
18338 // from internal hardware
18339 .de (1'b0),
18340 .d ('0),
18341
18342 // to internal hardware
18343 .qe (),
18344 .q (reg2hw.cmd_info[23].payload_en.q),
18345 .ds (),
18346
18347 // to register interface (read)
18348 .qs (cmd_info_23_payload_en_23_qs)
18349 );
18350
18351 // F[payload_dir_23]: 20:20
18352 prim_subreg #(
18353 .DW (1),
18354 .SwAccess(prim_subreg_pkg::SwAccessRW),
18355 .RESVAL (1'h0),
18356 .Mubi (1'b0)
18357 ) u_cmd_info_23_payload_dir_23 (
18358 .clk_i (clk_i),
18359 .rst_ni (rst_ni),
18360
18361 // from register interface
18362 .we (cmd_info_23_we),
18363 .wd (cmd_info_23_payload_dir_23_wd),
18364
18365 // from internal hardware
18366 .de (1'b0),
18367 .d ('0),
18368
18369 // to internal hardware
18370 .qe (),
18371 .q (reg2hw.cmd_info[23].payload_dir.q),
18372 .ds (),
18373
18374 // to register interface (read)
18375 .qs (cmd_info_23_payload_dir_23_qs)
18376 );
18377
18378 // F[payload_swap_en_23]: 21:21
18379 prim_subreg #(
18380 .DW (1),
18381 .SwAccess(prim_subreg_pkg::SwAccessRW),
18382 .RESVAL (1'h0),
18383 .Mubi (1'b0)
18384 ) u_cmd_info_23_payload_swap_en_23 (
18385 .clk_i (clk_i),
18386 .rst_ni (rst_ni),
18387
18388 // from register interface
18389 .we (cmd_info_23_we),
18390 .wd (cmd_info_23_payload_swap_en_23_wd),
18391
18392 // from internal hardware
18393 .de (1'b0),
18394 .d ('0),
18395
18396 // to internal hardware
18397 .qe (),
18398 .q (reg2hw.cmd_info[23].payload_swap_en.q),
18399 .ds (),
18400
18401 // to register interface (read)
18402 .qs (cmd_info_23_payload_swap_en_23_qs)
18403 );
18404
18405 // F[read_pipeline_mode_23]: 23:22
18406 prim_subreg #(
18407 .DW (2),
18408 .SwAccess(prim_subreg_pkg::SwAccessRW),
18409 .RESVAL (2'h0),
18410 .Mubi (1'b0)
18411 ) u_cmd_info_23_read_pipeline_mode_23 (
18412 .clk_i (clk_i),
18413 .rst_ni (rst_ni),
18414
18415 // from register interface
18416 .we (cmd_info_23_we),
18417 .wd (cmd_info_23_read_pipeline_mode_23_wd),
18418
18419 // from internal hardware
18420 .de (1'b0),
18421 .d ('0),
18422
18423 // to internal hardware
18424 .qe (),
18425 .q (reg2hw.cmd_info[23].read_pipeline_mode.q),
18426 .ds (),
18427
18428 // to register interface (read)
18429 .qs (cmd_info_23_read_pipeline_mode_23_qs)
18430 );
18431
18432 // F[upload_23]: 24:24
18433 prim_subreg #(
18434 .DW (1),
18435 .SwAccess(prim_subreg_pkg::SwAccessRW),
18436 .RESVAL (1'h0),
18437 .Mubi (1'b0)
18438 ) u_cmd_info_23_upload_23 (
18439 .clk_i (clk_i),
18440 .rst_ni (rst_ni),
18441
18442 // from register interface
18443 .we (cmd_info_23_we),
18444 .wd (cmd_info_23_upload_23_wd),
18445
18446 // from internal hardware
18447 .de (1'b0),
18448 .d ('0),
18449
18450 // to internal hardware
18451 .qe (),
18452 .q (reg2hw.cmd_info[23].upload.q),
18453 .ds (),
18454
18455 // to register interface (read)
18456 .qs (cmd_info_23_upload_23_qs)
18457 );
18458
18459 // F[busy_23]: 25:25
18460 prim_subreg #(
18461 .DW (1),
18462 .SwAccess(prim_subreg_pkg::SwAccessRW),
18463 .RESVAL (1'h0),
18464 .Mubi (1'b0)
18465 ) u_cmd_info_23_busy_23 (
18466 .clk_i (clk_i),
18467 .rst_ni (rst_ni),
18468
18469 // from register interface
18470 .we (cmd_info_23_we),
18471 .wd (cmd_info_23_busy_23_wd),
18472
18473 // from internal hardware
18474 .de (1'b0),
18475 .d ('0),
18476
18477 // to internal hardware
18478 .qe (),
18479 .q (reg2hw.cmd_info[23].busy.q),
18480 .ds (),
18481
18482 // to register interface (read)
18483 .qs (cmd_info_23_busy_23_qs)
18484 );
18485
18486 // F[valid_23]: 31:31
18487 prim_subreg #(
18488 .DW (1),
18489 .SwAccess(prim_subreg_pkg::SwAccessRW),
18490 .RESVAL (1'h0),
18491 .Mubi (1'b0)
18492 ) u_cmd_info_23_valid_23 (
18493 .clk_i (clk_i),
18494 .rst_ni (rst_ni),
18495
18496 // from register interface
18497 .we (cmd_info_23_we),
18498 .wd (cmd_info_23_valid_23_wd),
18499
18500 // from internal hardware
18501 .de (1'b0),
18502 .d ('0),
18503
18504 // to internal hardware
18505 .qe (),
18506 .q (reg2hw.cmd_info[23].valid.q),
18507 .ds (),
18508
18509 // to register interface (read)
18510 .qs (cmd_info_23_valid_23_qs)
18511 );
18512
18513
18514 // R[cmd_info_en4b]: V(False)
18515 // F[opcode]: 7:0
18516 prim_subreg #(
18517 .DW (8),
18518 .SwAccess(prim_subreg_pkg::SwAccessRW),
18519 .RESVAL (8'h0),
18520 .Mubi (1'b0)
18521 ) u_cmd_info_en4b_opcode (
18522 .clk_i (clk_i),
18523 .rst_ni (rst_ni),
18524
18525 // from register interface
18526 .we (cmd_info_en4b_we),
18527 .wd (cmd_info_en4b_opcode_wd),
18528
18529 // from internal hardware
18530 .de (1'b0),
18531 .d ('0),
18532
18533 // to internal hardware
18534 .qe (),
18535 .q (reg2hw.cmd_info_en4b.opcode.q),
18536 .ds (),
18537
18538 // to register interface (read)
18539 .qs (cmd_info_en4b_opcode_qs)
18540 );
18541
18542 // F[valid]: 31:31
18543 prim_subreg #(
18544 .DW (1),
18545 .SwAccess(prim_subreg_pkg::SwAccessRW),
18546 .RESVAL (1'h0),
18547 .Mubi (1'b0)
18548 ) u_cmd_info_en4b_valid (
18549 .clk_i (clk_i),
18550 .rst_ni (rst_ni),
18551
18552 // from register interface
18553 .we (cmd_info_en4b_we),
18554 .wd (cmd_info_en4b_valid_wd),
18555
18556 // from internal hardware
18557 .de (1'b0),
18558 .d ('0),
18559
18560 // to internal hardware
18561 .qe (),
18562 .q (reg2hw.cmd_info_en4b.valid.q),
18563 .ds (),
18564
18565 // to register interface (read)
18566 .qs (cmd_info_en4b_valid_qs)
18567 );
18568
18569
18570 // R[cmd_info_ex4b]: V(False)
18571 // F[opcode]: 7:0
18572 prim_subreg #(
18573 .DW (8),
18574 .SwAccess(prim_subreg_pkg::SwAccessRW),
18575 .RESVAL (8'h0),
18576 .Mubi (1'b0)
18577 ) u_cmd_info_ex4b_opcode (
18578 .clk_i (clk_i),
18579 .rst_ni (rst_ni),
18580
18581 // from register interface
18582 .we (cmd_info_ex4b_we),
18583 .wd (cmd_info_ex4b_opcode_wd),
18584
18585 // from internal hardware
18586 .de (1'b0),
18587 .d ('0),
18588
18589 // to internal hardware
18590 .qe (),
18591 .q (reg2hw.cmd_info_ex4b.opcode.q),
18592 .ds (),
18593
18594 // to register interface (read)
18595 .qs (cmd_info_ex4b_opcode_qs)
18596 );
18597
18598 // F[valid]: 31:31
18599 prim_subreg #(
18600 .DW (1),
18601 .SwAccess(prim_subreg_pkg::SwAccessRW),
18602 .RESVAL (1'h0),
18603 .Mubi (1'b0)
18604 ) u_cmd_info_ex4b_valid (
18605 .clk_i (clk_i),
18606 .rst_ni (rst_ni),
18607
18608 // from register interface
18609 .we (cmd_info_ex4b_we),
18610 .wd (cmd_info_ex4b_valid_wd),
18611
18612 // from internal hardware
18613 .de (1'b0),
18614 .d ('0),
18615
18616 // to internal hardware
18617 .qe (),
18618 .q (reg2hw.cmd_info_ex4b.valid.q),
18619 .ds (),
18620
18621 // to register interface (read)
18622 .qs (cmd_info_ex4b_valid_qs)
18623 );
18624
18625
18626 // R[cmd_info_wren]: V(False)
18627 // F[opcode]: 7:0
18628 prim_subreg #(
18629 .DW (8),
18630 .SwAccess(prim_subreg_pkg::SwAccessRW),
18631 .RESVAL (8'h0),
18632 .Mubi (1'b0)
18633 ) u_cmd_info_wren_opcode (
18634 .clk_i (clk_i),
18635 .rst_ni (rst_ni),
18636
18637 // from register interface
18638 .we (cmd_info_wren_we),
18639 .wd (cmd_info_wren_opcode_wd),
18640
18641 // from internal hardware
18642 .de (1'b0),
18643 .d ('0),
18644
18645 // to internal hardware
18646 .qe (),
18647 .q (reg2hw.cmd_info_wren.opcode.q),
18648 .ds (),
18649
18650 // to register interface (read)
18651 .qs (cmd_info_wren_opcode_qs)
18652 );
18653
18654 // F[valid]: 31:31
18655 prim_subreg #(
18656 .DW (1),
18657 .SwAccess(prim_subreg_pkg::SwAccessRW),
18658 .RESVAL (1'h0),
18659 .Mubi (1'b0)
18660 ) u_cmd_info_wren_valid (
18661 .clk_i (clk_i),
18662 .rst_ni (rst_ni),
18663
18664 // from register interface
18665 .we (cmd_info_wren_we),
18666 .wd (cmd_info_wren_valid_wd),
18667
18668 // from internal hardware
18669 .de (1'b0),
18670 .d ('0),
18671
18672 // to internal hardware
18673 .qe (),
18674 .q (reg2hw.cmd_info_wren.valid.q),
18675 .ds (),
18676
18677 // to register interface (read)
18678 .qs (cmd_info_wren_valid_qs)
18679 );
18680
18681
18682 // R[cmd_info_wrdi]: V(False)
18683 // F[opcode]: 7:0
18684 prim_subreg #(
18685 .DW (8),
18686 .SwAccess(prim_subreg_pkg::SwAccessRW),
18687 .RESVAL (8'h0),
18688 .Mubi (1'b0)
18689 ) u_cmd_info_wrdi_opcode (
18690 .clk_i (clk_i),
18691 .rst_ni (rst_ni),
18692
18693 // from register interface
18694 .we (cmd_info_wrdi_we),
18695 .wd (cmd_info_wrdi_opcode_wd),
18696
18697 // from internal hardware
18698 .de (1'b0),
18699 .d ('0),
18700
18701 // to internal hardware
18702 .qe (),
18703 .q (reg2hw.cmd_info_wrdi.opcode.q),
18704 .ds (),
18705
18706 // to register interface (read)
18707 .qs (cmd_info_wrdi_opcode_qs)
18708 );
18709
18710 // F[valid]: 31:31
18711 prim_subreg #(
18712 .DW (1),
18713 .SwAccess(prim_subreg_pkg::SwAccessRW),
18714 .RESVAL (1'h0),
18715 .Mubi (1'b0)
18716 ) u_cmd_info_wrdi_valid (
18717 .clk_i (clk_i),
18718 .rst_ni (rst_ni),
18719
18720 // from register interface
18721 .we (cmd_info_wrdi_we),
18722 .wd (cmd_info_wrdi_valid_wd),
18723
18724 // from internal hardware
18725 .de (1'b0),
18726 .d ('0),
18727
18728 // to internal hardware
18729 .qe (),
18730 .q (reg2hw.cmd_info_wrdi.valid.q),
18731 .ds (),
18732
18733 // to register interface (read)
18734 .qs (cmd_info_wrdi_valid_qs)
18735 );
18736
18737
18738 // R[tpm_cap]: V(False)
18739 // F[rev]: 7:0
18740 prim_subreg #(
18741 .DW (8),
18742 .SwAccess(prim_subreg_pkg::SwAccessRO),
18743 .RESVAL (8'h0),
18744 .Mubi (1'b0)
18745 ) u_tpm_cap_rev (
18746 .clk_i (clk_i),
18747 .rst_ni (rst_ni),
18748
18749 // from register interface
18750 .we (1'b0),
18751 .wd ('0),
18752
18753 // from internal hardware
18754 .de (hw2reg.tpm_cap.rev.de),
18755 .d (hw2reg.tpm_cap.rev.d),
18756
18757 // to internal hardware
18758 .qe (),
18759 .q (),
18760 .ds (),
18761
18762 // to register interface (read)
18763 .qs (tpm_cap_rev_qs)
18764 );
18765
18766 // F[locality]: 8:8
18767 prim_subreg #(
18768 .DW (1),
18769 .SwAccess(prim_subreg_pkg::SwAccessRO),
18770 .RESVAL (1'h1),
18771 .Mubi (1'b0)
18772 ) u_tpm_cap_locality (
18773 .clk_i (clk_i),
18774 .rst_ni (rst_ni),
18775
18776 // from register interface
18777 .we (1'b0),
18778 .wd ('0),
18779
18780 // from internal hardware
18781 .de (hw2reg.tpm_cap.locality.de),
18782 .d (hw2reg.tpm_cap.locality.d),
18783
18784 // to internal hardware
18785 .qe (),
18786 .q (),
18787 .ds (),
18788
18789 // to register interface (read)
18790 .qs (tpm_cap_locality_qs)
18791 );
18792
18793 // F[max_wr_size]: 18:16
18794 prim_subreg #(
18795 .DW (3),
18796 .SwAccess(prim_subreg_pkg::SwAccessRO),
18797 .RESVAL (3'h6),
18798 .Mubi (1'b0)
18799 ) u_tpm_cap_max_wr_size (
18800 .clk_i (clk_i),
18801 .rst_ni (rst_ni),
18802
18803 // from register interface
18804 .we (1'b0),
18805 .wd ('0),
18806
18807 // from internal hardware
18808 .de (hw2reg.tpm_cap.max_wr_size.de),
18809 .d (hw2reg.tpm_cap.max_wr_size.d),
18810
18811 // to internal hardware
18812 .qe (),
18813 .q (),
18814 .ds (),
18815
18816 // to register interface (read)
18817 .qs (tpm_cap_max_wr_size_qs)
18818 );
18819
18820 // F[max_rd_size]: 22:20
18821 prim_subreg #(
18822 .DW (3),
18823 .SwAccess(prim_subreg_pkg::SwAccessRO),
18824 .RESVAL (3'h6),
18825 .Mubi (1'b0)
18826 ) u_tpm_cap_max_rd_size (
18827 .clk_i (clk_i),
18828 .rst_ni (rst_ni),
18829
18830 // from register interface
18831 .we (1'b0),
18832 .wd ('0),
18833
18834 // from internal hardware
18835 .de (hw2reg.tpm_cap.max_rd_size.de),
18836 .d (hw2reg.tpm_cap.max_rd_size.d),
18837
18838 // to internal hardware
18839 .qe (),
18840 .q (),
18841 .ds (),
18842
18843 // to register interface (read)
18844 .qs (tpm_cap_max_rd_size_qs)
18845 );
18846
18847
18848 // R[tpm_cfg]: V(False)
18849 // F[en]: 0:0
18850 prim_subreg #(
18851 .DW (1),
18852 .SwAccess(prim_subreg_pkg::SwAccessRW),
18853 .RESVAL (1'h0),
18854 .Mubi (1'b0)
18855 ) u_tpm_cfg_en (
18856 .clk_i (clk_i),
18857 .rst_ni (rst_ni),
18858
18859 // from register interface
18860 .we (tpm_cfg_we),
18861 .wd (tpm_cfg_en_wd),
18862
18863 // from internal hardware
18864 .de (1'b0),
18865 .d ('0),
18866
18867 // to internal hardware
18868 .qe (),
18869 .q (reg2hw.tpm_cfg.en.q),
18870 .ds (),
18871
18872 // to register interface (read)
18873 .qs (tpm_cfg_en_qs)
18874 );
18875
18876 // F[tpm_mode]: 1:1
18877 prim_subreg #(
18878 .DW (1),
18879 .SwAccess(prim_subreg_pkg::SwAccessRW),
18880 .RESVAL (1'h0),
18881 .Mubi (1'b0)
18882 ) u_tpm_cfg_tpm_mode (
18883 .clk_i (clk_i),
18884 .rst_ni (rst_ni),
18885
18886 // from register interface
18887 .we (tpm_cfg_we),
18888 .wd (tpm_cfg_tpm_mode_wd),
18889
18890 // from internal hardware
18891 .de (1'b0),
18892 .d ('0),
18893
18894 // to internal hardware
18895 .qe (),
18896 .q (reg2hw.tpm_cfg.tpm_mode.q),
18897 .ds (),
18898
18899 // to register interface (read)
18900 .qs (tpm_cfg_tpm_mode_qs)
18901 );
18902
18903 // F[hw_reg_dis]: 2:2
18904 prim_subreg #(
18905 .DW (1),
18906 .SwAccess(prim_subreg_pkg::SwAccessRW),
18907 .RESVAL (1'h0),
18908 .Mubi (1'b0)
18909 ) u_tpm_cfg_hw_reg_dis (
18910 .clk_i (clk_i),
18911 .rst_ni (rst_ni),
18912
18913 // from register interface
18914 .we (tpm_cfg_we),
18915 .wd (tpm_cfg_hw_reg_dis_wd),
18916
18917 // from internal hardware
18918 .de (1'b0),
18919 .d ('0),
18920
18921 // to internal hardware
18922 .qe (),
18923 .q (reg2hw.tpm_cfg.hw_reg_dis.q),
18924 .ds (),
18925
18926 // to register interface (read)
18927 .qs (tpm_cfg_hw_reg_dis_qs)
18928 );
18929
18930 // F[tpm_reg_chk_dis]: 3:3
18931 prim_subreg #(
18932 .DW (1),
18933 .SwAccess(prim_subreg_pkg::SwAccessRW),
18934 .RESVAL (1'h0),
18935 .Mubi (1'b0)
18936 ) u_tpm_cfg_tpm_reg_chk_dis (
18937 .clk_i (clk_i),
18938 .rst_ni (rst_ni),
18939
18940 // from register interface
18941 .we (tpm_cfg_we),
18942 .wd (tpm_cfg_tpm_reg_chk_dis_wd),
18943
18944 // from internal hardware
18945 .de (1'b0),
18946 .d ('0),
18947
18948 // to internal hardware
18949 .qe (),
18950 .q (reg2hw.tpm_cfg.tpm_reg_chk_dis.q),
18951 .ds (),
18952
18953 // to register interface (read)
18954 .qs (tpm_cfg_tpm_reg_chk_dis_qs)
18955 );
18956
18957 // F[invalid_locality]: 4:4
18958 prim_subreg #(
18959 .DW (1),
18960 .SwAccess(prim_subreg_pkg::SwAccessRW),
18961 .RESVAL (1'h0),
18962 .Mubi (1'b0)
18963 ) u_tpm_cfg_invalid_locality (
18964 .clk_i (clk_i),
18965 .rst_ni (rst_ni),
18966
18967 // from register interface
18968 .we (tpm_cfg_we),
18969 .wd (tpm_cfg_invalid_locality_wd),
18970
18971 // from internal hardware
18972 .de (1'b0),
18973 .d ('0),
18974
18975 // to internal hardware
18976 .qe (),
18977 .q (reg2hw.tpm_cfg.invalid_locality.q),
18978 .ds (),
18979
18980 // to register interface (read)
18981 .qs (tpm_cfg_invalid_locality_qs)
18982 );
18983
18984
18985 // R[tpm_status]: V(True)
18986 logic tpm_status_qe;
18987 logic [2:0] tpm_status_flds_we;
18988 // This ignores QEs that are set to constant 0 due to read-only fields.
18989 logic unused_tpm_status_flds_we;
18990 unreachable assign unused_tpm_status_flds_we = ^(tpm_status_flds_we & 3'h5);
18991 1/1 assign tpm_status_qe = &(tpm_status_flds_we | 3'h5);
Tests: T5 T13 T31
18992 // F[cmdaddr_notempty]: 0:0
18993 prim_subreg_ext #(
18994 .DW (1)
18995 ) u_tpm_status_cmdaddr_notempty (
18996 .re (tpm_status_re),
18997 .we (1'b0),
18998 .wd ('0),
18999 .d (hw2reg.tpm_status.cmdaddr_notempty.d),
19000 .qre (),
19001 .qe (tpm_status_flds_we[0]),
19002 .q (),
19003 .ds (),
19004 .qs (tpm_status_cmdaddr_notempty_qs)
19005 );
19006
19007 // F[wrfifo_pending]: 1:1
19008 prim_subreg_ext #(
19009 .DW (1)
19010 ) u_tpm_status_wrfifo_pending (
19011 .re (tpm_status_re),
19012 .we (tpm_status_we),
19013 .wd (tpm_status_wrfifo_pending_wd),
19014 .d (hw2reg.tpm_status.wrfifo_pending.d),
19015 .qre (),
19016 .qe (tpm_status_flds_we[1]),
19017 .q (reg2hw.tpm_status.wrfifo_pending.q),
19018 .ds (),
19019 .qs (tpm_status_wrfifo_pending_qs)
19020 );
19021 1/1 assign reg2hw.tpm_status.wrfifo_pending.qe = tpm_status_qe;
Tests: T5 T13 T31
19022
19023 // F[rdfifo_aborted]: 2:2
19024 prim_subreg_ext #(
19025 .DW (1)
19026 ) u_tpm_status_rdfifo_aborted (
19027 .re (tpm_status_re),
19028 .we (1'b0),
19029 .wd ('0),
19030 .d (hw2reg.tpm_status.rdfifo_aborted.d),
19031 .qre (),
19032 .qe (tpm_status_flds_we[2]),
19033 .q (),
19034 .ds (),
19035 .qs (tpm_status_rdfifo_aborted_qs)
19036 );
19037
19038
19039 // Subregister 0 of Multireg tpm_access
19040 // R[tpm_access_0]: V(False)
19041 // F[access_0]: 7:0
19042 prim_subreg #(
19043 .DW (8),
19044 .SwAccess(prim_subreg_pkg::SwAccessRW),
19045 .RESVAL (8'h0),
19046 .Mubi (1'b0)
19047 ) u_tpm_access_0_access_0 (
19048 .clk_i (clk_i),
19049 .rst_ni (rst_ni),
19050
19051 // from register interface
19052 .we (tpm_access_0_we),
19053 .wd (tpm_access_0_access_0_wd),
19054
19055 // from internal hardware
19056 .de (1'b0),
19057 .d ('0),
19058
19059 // to internal hardware
19060 .qe (),
19061 .q (reg2hw.tpm_access[0].q),
19062 .ds (),
19063
19064 // to register interface (read)
19065 .qs (tpm_access_0_access_0_qs)
19066 );
19067
19068 // F[access_1]: 15:8
19069 prim_subreg #(
19070 .DW (8),
19071 .SwAccess(prim_subreg_pkg::SwAccessRW),
19072 .RESVAL (8'h0),
19073 .Mubi (1'b0)
19074 ) u_tpm_access_0_access_1 (
19075 .clk_i (clk_i),
19076 .rst_ni (rst_ni),
19077
19078 // from register interface
19079 .we (tpm_access_0_we),
19080 .wd (tpm_access_0_access_1_wd),
19081
19082 // from internal hardware
19083 .de (1'b0),
19084 .d ('0),
19085
19086 // to internal hardware
19087 .qe (),
19088 .q (reg2hw.tpm_access[1].q),
19089 .ds (),
19090
19091 // to register interface (read)
19092 .qs (tpm_access_0_access_1_qs)
19093 );
19094
19095 // F[access_2]: 23:16
19096 prim_subreg #(
19097 .DW (8),
19098 .SwAccess(prim_subreg_pkg::SwAccessRW),
19099 .RESVAL (8'h0),
19100 .Mubi (1'b0)
19101 ) u_tpm_access_0_access_2 (
19102 .clk_i (clk_i),
19103 .rst_ni (rst_ni),
19104
19105 // from register interface
19106 .we (tpm_access_0_we),
19107 .wd (tpm_access_0_access_2_wd),
19108
19109 // from internal hardware
19110 .de (1'b0),
19111 .d ('0),
19112
19113 // to internal hardware
19114 .qe (),
19115 .q (reg2hw.tpm_access[2].q),
19116 .ds (),
19117
19118 // to register interface (read)
19119 .qs (tpm_access_0_access_2_qs)
19120 );
19121
19122 // F[access_3]: 31:24
19123 prim_subreg #(
19124 .DW (8),
19125 .SwAccess(prim_subreg_pkg::SwAccessRW),
19126 .RESVAL (8'h0),
19127 .Mubi (1'b0)
19128 ) u_tpm_access_0_access_3 (
19129 .clk_i (clk_i),
19130 .rst_ni (rst_ni),
19131
19132 // from register interface
19133 .we (tpm_access_0_we),
19134 .wd (tpm_access_0_access_3_wd),
19135
19136 // from internal hardware
19137 .de (1'b0),
19138 .d ('0),
19139
19140 // to internal hardware
19141 .qe (),
19142 .q (reg2hw.tpm_access[3].q),
19143 .ds (),
19144
19145 // to register interface (read)
19146 .qs (tpm_access_0_access_3_qs)
19147 );
19148
19149
19150 // Subregister 1 of Multireg tpm_access
19151 // R[tpm_access_1]: V(False)
19152 prim_subreg #(
19153 .DW (8),
19154 .SwAccess(prim_subreg_pkg::SwAccessRW),
19155 .RESVAL (8'h0),
19156 .Mubi (1'b0)
19157 ) u_tpm_access_1 (
19158 .clk_i (clk_i),
19159 .rst_ni (rst_ni),
19160
19161 // from register interface
19162 .we (tpm_access_1_we),
19163 .wd (tpm_access_1_wd),
19164
19165 // from internal hardware
19166 .de (1'b0),
19167 .d ('0),
19168
19169 // to internal hardware
19170 .qe (),
19171 .q (reg2hw.tpm_access[4].q),
19172 .ds (),
19173
19174 // to register interface (read)
19175 .qs (tpm_access_1_qs)
19176 );
19177
19178
19179 // R[tpm_sts]: V(False)
19180 prim_subreg #(
19181 .DW (32),
19182 .SwAccess(prim_subreg_pkg::SwAccessRW),
19183 .RESVAL (32'h0),
19184 .Mubi (1'b0)
19185 ) u_tpm_sts (
19186 .clk_i (clk_i),
19187 .rst_ni (rst_ni),
19188
19189 // from register interface
19190 .we (tpm_sts_we),
19191 .wd (tpm_sts_wd),
19192
19193 // from internal hardware
19194 .de (1'b0),
19195 .d ('0),
19196
19197 // to internal hardware
19198 .qe (),
19199 .q (reg2hw.tpm_sts.q),
19200 .ds (),
19201
19202 // to register interface (read)
19203 .qs (tpm_sts_qs)
19204 );
19205
19206
19207 // R[tpm_intf_capability]: V(False)
19208 prim_subreg #(
19209 .DW (32),
19210 .SwAccess(prim_subreg_pkg::SwAccessRW),
19211 .RESVAL (32'h0),
19212 .Mubi (1'b0)
19213 ) u_tpm_intf_capability (
19214 .clk_i (clk_i),
19215 .rst_ni (rst_ni),
19216
19217 // from register interface
19218 .we (tpm_intf_capability_we),
19219 .wd (tpm_intf_capability_wd),
19220
19221 // from internal hardware
19222 .de (1'b0),
19223 .d ('0),
19224
19225 // to internal hardware
19226 .qe (),
19227 .q (reg2hw.tpm_intf_capability.q),
19228 .ds (),
19229
19230 // to register interface (read)
19231 .qs (tpm_intf_capability_qs)
19232 );
19233
19234
19235 // R[tpm_int_enable]: V(False)
19236 prim_subreg #(
19237 .DW (32),
19238 .SwAccess(prim_subreg_pkg::SwAccessRW),
19239 .RESVAL (32'h0),
19240 .Mubi (1'b0)
19241 ) u_tpm_int_enable (
19242 .clk_i (clk_i),
19243 .rst_ni (rst_ni),
19244
19245 // from register interface
19246 .we (tpm_int_enable_we),
19247 .wd (tpm_int_enable_wd),
19248
19249 // from internal hardware
19250 .de (1'b0),
19251 .d ('0),
19252
19253 // to internal hardware
19254 .qe (),
19255 .q (reg2hw.tpm_int_enable.q),
19256 .ds (),
19257
19258 // to register interface (read)
19259 .qs (tpm_int_enable_qs)
19260 );
19261
19262
19263 // R[tpm_int_vector]: V(False)
19264 prim_subreg #(
19265 .DW (8),
19266 .SwAccess(prim_subreg_pkg::SwAccessRW),
19267 .RESVAL (8'h0),
19268 .Mubi (1'b0)
19269 ) u_tpm_int_vector (
19270 .clk_i (clk_i),
19271 .rst_ni (rst_ni),
19272
19273 // from register interface
19274 .we (tpm_int_vector_we),
19275 .wd (tpm_int_vector_wd),
19276
19277 // from internal hardware
19278 .de (1'b0),
19279 .d ('0),
19280
19281 // to internal hardware
19282 .qe (),
19283 .q (reg2hw.tpm_int_vector.q),
19284 .ds (),
19285
19286 // to register interface (read)
19287 .qs (tpm_int_vector_qs)
19288 );
19289
19290
19291 // R[tpm_int_status]: V(False)
19292 prim_subreg #(
19293 .DW (32),
19294 .SwAccess(prim_subreg_pkg::SwAccessRW),
19295 .RESVAL (32'h0),
19296 .Mubi (1'b0)
19297 ) u_tpm_int_status (
19298 .clk_i (clk_i),
19299 .rst_ni (rst_ni),
19300
19301 // from register interface
19302 .we (tpm_int_status_we),
19303 .wd (tpm_int_status_wd),
19304
19305 // from internal hardware
19306 .de (1'b0),
19307 .d ('0),
19308
19309 // to internal hardware
19310 .qe (),
19311 .q (reg2hw.tpm_int_status.q),
19312 .ds (),
19313
19314 // to register interface (read)
19315 .qs (tpm_int_status_qs)
19316 );
19317
19318
19319 // R[tpm_did_vid]: V(False)
19320 // F[vid]: 15:0
19321 prim_subreg #(
19322 .DW (16),
19323 .SwAccess(prim_subreg_pkg::SwAccessRW),
19324 .RESVAL (16'h0),
19325 .Mubi (1'b0)
19326 ) u_tpm_did_vid_vid (
19327 .clk_i (clk_i),
19328 .rst_ni (rst_ni),
19329
19330 // from register interface
19331 .we (tpm_did_vid_we),
19332 .wd (tpm_did_vid_vid_wd),
19333
19334 // from internal hardware
19335 .de (1'b0),
19336 .d ('0),
19337
19338 // to internal hardware
19339 .qe (),
19340 .q (reg2hw.tpm_did_vid.vid.q),
19341 .ds (),
19342
19343 // to register interface (read)
19344 .qs (tpm_did_vid_vid_qs)
19345 );
19346
19347 // F[did]: 31:16
19348 prim_subreg #(
19349 .DW (16),
19350 .SwAccess(prim_subreg_pkg::SwAccessRW),
19351 .RESVAL (16'h0),
19352 .Mubi (1'b0)
19353 ) u_tpm_did_vid_did (
19354 .clk_i (clk_i),
19355 .rst_ni (rst_ni),
19356
19357 // from register interface
19358 .we (tpm_did_vid_we),
19359 .wd (tpm_did_vid_did_wd),
19360
19361 // from internal hardware
19362 .de (1'b0),
19363 .d ('0),
19364
19365 // to internal hardware
19366 .qe (),
19367 .q (reg2hw.tpm_did_vid.did.q),
19368 .ds (),
19369
19370 // to register interface (read)
19371 .qs (tpm_did_vid_did_qs)
19372 );
19373
19374
19375 // R[tpm_rid]: V(False)
19376 prim_subreg #(
19377 .DW (8),
19378 .SwAccess(prim_subreg_pkg::SwAccessRW),
19379 .RESVAL (8'h0),
19380 .Mubi (1'b0)
19381 ) u_tpm_rid (
19382 .clk_i (clk_i),
19383 .rst_ni (rst_ni),
19384
19385 // from register interface
19386 .we (tpm_rid_we),
19387 .wd (tpm_rid_wd),
19388
19389 // from internal hardware
19390 .de (1'b0),
19391 .d ('0),
19392
19393 // to internal hardware
19394 .qe (),
19395 .q (reg2hw.tpm_rid.q),
19396 .ds (),
19397
19398 // to register interface (read)
19399 .qs (tpm_rid_qs)
19400 );
19401
19402
19403 // R[tpm_cmd_addr]: V(True)
19404 logic tpm_cmd_addr_qe;
19405 logic [1:0] tpm_cmd_addr_flds_we;
19406 // In case all fields are read-only the aggregated register QE will be zero as well.
19407 unreachable assign tpm_cmd_addr_qe = &tpm_cmd_addr_flds_we;
19408 // F[addr]: 23:0
19409 prim_subreg_ext #(
19410 .DW (24)
19411 ) u_tpm_cmd_addr_addr (
19412 .re (tpm_cmd_addr_re),
19413 .we (1'b0),
19414 .wd ('0),
19415 .d (hw2reg.tpm_cmd_addr.addr.d),
19416 .qre (reg2hw.tpm_cmd_addr.addr.re),
19417 .qe (tpm_cmd_addr_flds_we[0]),
19418 .q (reg2hw.tpm_cmd_addr.addr.q),
19419 .ds (),
19420 .qs (tpm_cmd_addr_addr_qs)
19421 );
19422 unreachable assign reg2hw.tpm_cmd_addr.addr.qe = tpm_cmd_addr_qe;
19423
19424 // F[cmd]: 31:24
19425 prim_subreg_ext #(
19426 .DW (8)
19427 ) u_tpm_cmd_addr_cmd (
19428 .re (tpm_cmd_addr_re),
19429 .we (1'b0),
19430 .wd ('0),
19431 .d (hw2reg.tpm_cmd_addr.cmd.d),
19432 .qre (reg2hw.tpm_cmd_addr.cmd.re),
19433 .qe (tpm_cmd_addr_flds_we[1]),
19434 .q (reg2hw.tpm_cmd_addr.cmd.q),
19435 .ds (),
19436 .qs (tpm_cmd_addr_cmd_qs)
19437 );
19438 unreachable assign reg2hw.tpm_cmd_addr.cmd.qe = tpm_cmd_addr_qe;
19439
19440
19441 // R[tpm_read_fifo]: V(True)
19442 logic tpm_read_fifo_qe;
19443 logic [0:0] tpm_read_fifo_flds_we;
19444 1/1 assign tpm_read_fifo_qe = &tpm_read_fifo_flds_we;
Tests: T5 T13 T30
19445 prim_subreg_ext #(
19446 .DW (32)
19447 ) u_tpm_read_fifo (
19448 .re (1'b0),
19449 .we (tpm_read_fifo_we),
19450 .wd (tpm_read_fifo_wd),
19451 .d ('0),
19452 .qre (),
19453 .qe (tpm_read_fifo_flds_we[0]),
19454 .q (reg2hw.tpm_read_fifo.q),
19455 .ds (),
19456 .qs ()
19457 );
19458 1/1 assign reg2hw.tpm_read_fifo.qe = tpm_read_fifo_qe;
Tests: T5 T13 T30
19459
19460
19461
19462 logic [72:0] addr_hit;
19463 always_comb begin
19464 1/1 addr_hit = '0;
Tests: T1 T2 T3
19465 1/1 addr_hit[ 0] = (reg_addr == SPI_DEVICE_INTR_STATE_OFFSET);
Tests: T1 T2 T3
19466 1/1 addr_hit[ 1] = (reg_addr == SPI_DEVICE_INTR_ENABLE_OFFSET);
Tests: T1 T2 T3
19467 1/1 addr_hit[ 2] = (reg_addr == SPI_DEVICE_INTR_TEST_OFFSET);
Tests: T1 T2 T3
19468 1/1 addr_hit[ 3] = (reg_addr == SPI_DEVICE_ALERT_TEST_OFFSET);
Tests: T1 T2 T3
19469 1/1 addr_hit[ 4] = (reg_addr == SPI_DEVICE_CONTROL_OFFSET);
Tests: T1 T2 T3
19470 1/1 addr_hit[ 5] = (reg_addr == SPI_DEVICE_CFG_OFFSET);
Tests: T1 T2 T3
19471 1/1 addr_hit[ 6] = (reg_addr == SPI_DEVICE_STATUS_OFFSET);
Tests: T1 T2 T3
19472 1/1 addr_hit[ 7] = (reg_addr == SPI_DEVICE_INTERCEPT_EN_OFFSET);
Tests: T1 T2 T3
19473 1/1 addr_hit[ 8] = (reg_addr == SPI_DEVICE_ADDR_MODE_OFFSET);
Tests: T1 T2 T3
19474 1/1 addr_hit[ 9] = (reg_addr == SPI_DEVICE_LAST_READ_ADDR_OFFSET);
Tests: T1 T2 T3
19475 1/1 addr_hit[10] = (reg_addr == SPI_DEVICE_FLASH_STATUS_OFFSET);
Tests: T1 T2 T3
19476 1/1 addr_hit[11] = (reg_addr == SPI_DEVICE_JEDEC_CC_OFFSET);
Tests: T1 T2 T3
19477 1/1 addr_hit[12] = (reg_addr == SPI_DEVICE_JEDEC_ID_OFFSET);
Tests: T1 T2 T3
19478 1/1 addr_hit[13] = (reg_addr == SPI_DEVICE_READ_THRESHOLD_OFFSET);
Tests: T1 T2 T3
19479 1/1 addr_hit[14] = (reg_addr == SPI_DEVICE_MAILBOX_ADDR_OFFSET);
Tests: T1 T2 T3
19480 1/1 addr_hit[15] = (reg_addr == SPI_DEVICE_UPLOAD_STATUS_OFFSET);
Tests: T1 T2 T3
19481 1/1 addr_hit[16] = (reg_addr == SPI_DEVICE_UPLOAD_STATUS2_OFFSET);
Tests: T1 T2 T3
19482 1/1 addr_hit[17] = (reg_addr == SPI_DEVICE_UPLOAD_CMDFIFO_OFFSET);
Tests: T1 T2 T3
19483 1/1 addr_hit[18] = (reg_addr == SPI_DEVICE_UPLOAD_ADDRFIFO_OFFSET);
Tests: T1 T2 T3
19484 1/1 addr_hit[19] = (reg_addr == SPI_DEVICE_CMD_FILTER_0_OFFSET);
Tests: T1 T2 T3
19485 1/1 addr_hit[20] = (reg_addr == SPI_DEVICE_CMD_FILTER_1_OFFSET);
Tests: T1 T2 T3
19486 1/1 addr_hit[21] = (reg_addr == SPI_DEVICE_CMD_FILTER_2_OFFSET);
Tests: T1 T2 T3
19487 1/1 addr_hit[22] = (reg_addr == SPI_DEVICE_CMD_FILTER_3_OFFSET);
Tests: T1 T2 T3
19488 1/1 addr_hit[23] = (reg_addr == SPI_DEVICE_CMD_FILTER_4_OFFSET);
Tests: T1 T2 T3
19489 1/1 addr_hit[24] = (reg_addr == SPI_DEVICE_CMD_FILTER_5_OFFSET);
Tests: T1 T2 T3
19490 1/1 addr_hit[25] = (reg_addr == SPI_DEVICE_CMD_FILTER_6_OFFSET);
Tests: T1 T2 T3
19491 1/1 addr_hit[26] = (reg_addr == SPI_DEVICE_CMD_FILTER_7_OFFSET);
Tests: T1 T2 T3
19492 1/1 addr_hit[27] = (reg_addr == SPI_DEVICE_ADDR_SWAP_MASK_OFFSET);
Tests: T1 T2 T3
19493 1/1 addr_hit[28] = (reg_addr == SPI_DEVICE_ADDR_SWAP_DATA_OFFSET);
Tests: T1 T2 T3
19494 1/1 addr_hit[29] = (reg_addr == SPI_DEVICE_PAYLOAD_SWAP_MASK_OFFSET);
Tests: T1 T2 T3
19495 1/1 addr_hit[30] = (reg_addr == SPI_DEVICE_PAYLOAD_SWAP_DATA_OFFSET);
Tests: T1 T2 T3
19496 1/1 addr_hit[31] = (reg_addr == SPI_DEVICE_CMD_INFO_0_OFFSET);
Tests: T1 T2 T3
19497 1/1 addr_hit[32] = (reg_addr == SPI_DEVICE_CMD_INFO_1_OFFSET);
Tests: T1 T2 T3
19498 1/1 addr_hit[33] = (reg_addr == SPI_DEVICE_CMD_INFO_2_OFFSET);
Tests: T1 T2 T3
19499 1/1 addr_hit[34] = (reg_addr == SPI_DEVICE_CMD_INFO_3_OFFSET);
Tests: T1 T2 T3
19500 1/1 addr_hit[35] = (reg_addr == SPI_DEVICE_CMD_INFO_4_OFFSET);
Tests: T1 T2 T3
19501 1/1 addr_hit[36] = (reg_addr == SPI_DEVICE_CMD_INFO_5_OFFSET);
Tests: T1 T2 T3
19502 1/1 addr_hit[37] = (reg_addr == SPI_DEVICE_CMD_INFO_6_OFFSET);
Tests: T1 T2 T3
19503 1/1 addr_hit[38] = (reg_addr == SPI_DEVICE_CMD_INFO_7_OFFSET);
Tests: T1 T2 T3
19504 1/1 addr_hit[39] = (reg_addr == SPI_DEVICE_CMD_INFO_8_OFFSET);
Tests: T1 T2 T3
19505 1/1 addr_hit[40] = (reg_addr == SPI_DEVICE_CMD_INFO_9_OFFSET);
Tests: T1 T2 T3
19506 1/1 addr_hit[41] = (reg_addr == SPI_DEVICE_CMD_INFO_10_OFFSET);
Tests: T1 T2 T3
19507 1/1 addr_hit[42] = (reg_addr == SPI_DEVICE_CMD_INFO_11_OFFSET);
Tests: T1 T2 T3
19508 1/1 addr_hit[43] = (reg_addr == SPI_DEVICE_CMD_INFO_12_OFFSET);
Tests: T1 T2 T3
19509 1/1 addr_hit[44] = (reg_addr == SPI_DEVICE_CMD_INFO_13_OFFSET);
Tests: T1 T2 T3
19510 1/1 addr_hit[45] = (reg_addr == SPI_DEVICE_CMD_INFO_14_OFFSET);
Tests: T1 T2 T3
19511 1/1 addr_hit[46] = (reg_addr == SPI_DEVICE_CMD_INFO_15_OFFSET);
Tests: T1 T2 T3
19512 1/1 addr_hit[47] = (reg_addr == SPI_DEVICE_CMD_INFO_16_OFFSET);
Tests: T1 T2 T3
19513 1/1 addr_hit[48] = (reg_addr == SPI_DEVICE_CMD_INFO_17_OFFSET);
Tests: T1 T2 T3
19514 1/1 addr_hit[49] = (reg_addr == SPI_DEVICE_CMD_INFO_18_OFFSET);
Tests: T1 T2 T3
19515 1/1 addr_hit[50] = (reg_addr == SPI_DEVICE_CMD_INFO_19_OFFSET);
Tests: T1 T2 T3
19516 1/1 addr_hit[51] = (reg_addr == SPI_DEVICE_CMD_INFO_20_OFFSET);
Tests: T1 T2 T3
19517 1/1 addr_hit[52] = (reg_addr == SPI_DEVICE_CMD_INFO_21_OFFSET);
Tests: T1 T2 T3
19518 1/1 addr_hit[53] = (reg_addr == SPI_DEVICE_CMD_INFO_22_OFFSET);
Tests: T1 T2 T3
19519 1/1 addr_hit[54] = (reg_addr == SPI_DEVICE_CMD_INFO_23_OFFSET);
Tests: T1 T2 T3
19520 1/1 addr_hit[55] = (reg_addr == SPI_DEVICE_CMD_INFO_EN4B_OFFSET);
Tests: T1 T2 T3
19521 1/1 addr_hit[56] = (reg_addr == SPI_DEVICE_CMD_INFO_EX4B_OFFSET);
Tests: T1 T2 T3
19522 1/1 addr_hit[57] = (reg_addr == SPI_DEVICE_CMD_INFO_WREN_OFFSET);
Tests: T1 T2 T3
19523 1/1 addr_hit[58] = (reg_addr == SPI_DEVICE_CMD_INFO_WRDI_OFFSET);
Tests: T1 T2 T3
19524 1/1 addr_hit[59] = (reg_addr == SPI_DEVICE_TPM_CAP_OFFSET);
Tests: T1 T2 T3
19525 1/1 addr_hit[60] = (reg_addr == SPI_DEVICE_TPM_CFG_OFFSET);
Tests: T1 T2 T3
19526 1/1 addr_hit[61] = (reg_addr == SPI_DEVICE_TPM_STATUS_OFFSET);
Tests: T1 T2 T3
19527 1/1 addr_hit[62] = (reg_addr == SPI_DEVICE_TPM_ACCESS_0_OFFSET);
Tests: T1 T2 T3
19528 1/1 addr_hit[63] = (reg_addr == SPI_DEVICE_TPM_ACCESS_1_OFFSET);
Tests: T1 T2 T3
19529 1/1 addr_hit[64] = (reg_addr == SPI_DEVICE_TPM_STS_OFFSET);
Tests: T1 T2 T3
19530 1/1 addr_hit[65] = (reg_addr == SPI_DEVICE_TPM_INTF_CAPABILITY_OFFSET);
Tests: T1 T2 T3
19531 1/1 addr_hit[66] = (reg_addr == SPI_DEVICE_TPM_INT_ENABLE_OFFSET);
Tests: T1 T2 T3
19532 1/1 addr_hit[67] = (reg_addr == SPI_DEVICE_TPM_INT_VECTOR_OFFSET);
Tests: T1 T2 T3
19533 1/1 addr_hit[68] = (reg_addr == SPI_DEVICE_TPM_INT_STATUS_OFFSET);
Tests: T1 T2 T3
19534 1/1 addr_hit[69] = (reg_addr == SPI_DEVICE_TPM_DID_VID_OFFSET);
Tests: T1 T2 T3
19535 1/1 addr_hit[70] = (reg_addr == SPI_DEVICE_TPM_RID_OFFSET);
Tests: T1 T2 T3
19536 1/1 addr_hit[71] = (reg_addr == SPI_DEVICE_TPM_CMD_ADDR_OFFSET);
Tests: T1 T2 T3
19537 1/1 addr_hit[72] = (reg_addr == SPI_DEVICE_TPM_READ_FIFO_OFFSET);
Tests: T1 T2 T3
19538 end
19539
19540 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T2 T3
19541
19542 // Check sub-word write is permitted
19543 always_comb begin
19544 1/1 wr_err = (reg_we &
Tests: T1 T2 T3
19545 ((addr_hit[ 0] & (|(SPI_DEVICE_PERMIT[ 0] & ~reg_be))) |
19546 (addr_hit[ 1] & (|(SPI_DEVICE_PERMIT[ 1] & ~reg_be))) |
19547 (addr_hit[ 2] & (|(SPI_DEVICE_PERMIT[ 2] & ~reg_be))) |
19548 (addr_hit[ 3] & (|(SPI_DEVICE_PERMIT[ 3] & ~reg_be))) |
19549 (addr_hit[ 4] & (|(SPI_DEVICE_PERMIT[ 4] & ~reg_be))) |
19550 (addr_hit[ 5] & (|(SPI_DEVICE_PERMIT[ 5] & ~reg_be))) |
19551 (addr_hit[ 6] & (|(SPI_DEVICE_PERMIT[ 6] & ~reg_be))) |
19552 (addr_hit[ 7] & (|(SPI_DEVICE_PERMIT[ 7] & ~reg_be))) |
19553 (addr_hit[ 8] & (|(SPI_DEVICE_PERMIT[ 8] & ~reg_be))) |
19554 (addr_hit[ 9] & (|(SPI_DEVICE_PERMIT[ 9] & ~reg_be))) |
19555 (addr_hit[10] & (|(SPI_DEVICE_PERMIT[10] & ~reg_be))) |
19556 (addr_hit[11] & (|(SPI_DEVICE_PERMIT[11] & ~reg_be))) |
19557 (addr_hit[12] & (|(SPI_DEVICE_PERMIT[12] & ~reg_be))) |
19558 (addr_hit[13] & (|(SPI_DEVICE_PERMIT[13] & ~reg_be))) |
19559 (addr_hit[14] & (|(SPI_DEVICE_PERMIT[14] & ~reg_be))) |
19560 (addr_hit[15] & (|(SPI_DEVICE_PERMIT[15] & ~reg_be))) |
19561 (addr_hit[16] & (|(SPI_DEVICE_PERMIT[16] & ~reg_be))) |
19562 (addr_hit[17] & (|(SPI_DEVICE_PERMIT[17] & ~reg_be))) |
19563 (addr_hit[18] & (|(SPI_DEVICE_PERMIT[18] & ~reg_be))) |
19564 (addr_hit[19] & (|(SPI_DEVICE_PERMIT[19] & ~reg_be))) |
19565 (addr_hit[20] & (|(SPI_DEVICE_PERMIT[20] & ~reg_be))) |
19566 (addr_hit[21] & (|(SPI_DEVICE_PERMIT[21] & ~reg_be))) |
19567 (addr_hit[22] & (|(SPI_DEVICE_PERMIT[22] & ~reg_be))) |
19568 (addr_hit[23] & (|(SPI_DEVICE_PERMIT[23] & ~reg_be))) |
19569 (addr_hit[24] & (|(SPI_DEVICE_PERMIT[24] & ~reg_be))) |
19570 (addr_hit[25] & (|(SPI_DEVICE_PERMIT[25] & ~reg_be))) |
19571 (addr_hit[26] & (|(SPI_DEVICE_PERMIT[26] & ~reg_be))) |
19572 (addr_hit[27] & (|(SPI_DEVICE_PERMIT[27] & ~reg_be))) |
19573 (addr_hit[28] & (|(SPI_DEVICE_PERMIT[28] & ~reg_be))) |
19574 (addr_hit[29] & (|(SPI_DEVICE_PERMIT[29] & ~reg_be))) |
19575 (addr_hit[30] & (|(SPI_DEVICE_PERMIT[30] & ~reg_be))) |
19576 (addr_hit[31] & (|(SPI_DEVICE_PERMIT[31] & ~reg_be))) |
19577 (addr_hit[32] & (|(SPI_DEVICE_PERMIT[32] & ~reg_be))) |
19578 (addr_hit[33] & (|(SPI_DEVICE_PERMIT[33] & ~reg_be))) |
19579 (addr_hit[34] & (|(SPI_DEVICE_PERMIT[34] & ~reg_be))) |
19580 (addr_hit[35] & (|(SPI_DEVICE_PERMIT[35] & ~reg_be))) |
19581 (addr_hit[36] & (|(SPI_DEVICE_PERMIT[36] & ~reg_be))) |
19582 (addr_hit[37] & (|(SPI_DEVICE_PERMIT[37] & ~reg_be))) |
19583 (addr_hit[38] & (|(SPI_DEVICE_PERMIT[38] & ~reg_be))) |
19584 (addr_hit[39] & (|(SPI_DEVICE_PERMIT[39] & ~reg_be))) |
19585 (addr_hit[40] & (|(SPI_DEVICE_PERMIT[40] & ~reg_be))) |
19586 (addr_hit[41] & (|(SPI_DEVICE_PERMIT[41] & ~reg_be))) |
19587 (addr_hit[42] & (|(SPI_DEVICE_PERMIT[42] & ~reg_be))) |
19588 (addr_hit[43] & (|(SPI_DEVICE_PERMIT[43] & ~reg_be))) |
19589 (addr_hit[44] & (|(SPI_DEVICE_PERMIT[44] & ~reg_be))) |
19590 (addr_hit[45] & (|(SPI_DEVICE_PERMIT[45] & ~reg_be))) |
19591 (addr_hit[46] & (|(SPI_DEVICE_PERMIT[46] & ~reg_be))) |
19592 (addr_hit[47] & (|(SPI_DEVICE_PERMIT[47] & ~reg_be))) |
19593 (addr_hit[48] & (|(SPI_DEVICE_PERMIT[48] & ~reg_be))) |
19594 (addr_hit[49] & (|(SPI_DEVICE_PERMIT[49] & ~reg_be))) |
19595 (addr_hit[50] & (|(SPI_DEVICE_PERMIT[50] & ~reg_be))) |
19596 (addr_hit[51] & (|(SPI_DEVICE_PERMIT[51] & ~reg_be))) |
19597 (addr_hit[52] & (|(SPI_DEVICE_PERMIT[52] & ~reg_be))) |
19598 (addr_hit[53] & (|(SPI_DEVICE_PERMIT[53] & ~reg_be))) |
19599 (addr_hit[54] & (|(SPI_DEVICE_PERMIT[54] & ~reg_be))) |
19600 (addr_hit[55] & (|(SPI_DEVICE_PERMIT[55] & ~reg_be))) |
19601 (addr_hit[56] & (|(SPI_DEVICE_PERMIT[56] & ~reg_be))) |
19602 (addr_hit[57] & (|(SPI_DEVICE_PERMIT[57] & ~reg_be))) |
19603 (addr_hit[58] & (|(SPI_DEVICE_PERMIT[58] & ~reg_be))) |
19604 (addr_hit[59] & (|(SPI_DEVICE_PERMIT[59] & ~reg_be))) |
19605 (addr_hit[60] & (|(SPI_DEVICE_PERMIT[60] & ~reg_be))) |
19606 (addr_hit[61] & (|(SPI_DEVICE_PERMIT[61] & ~reg_be))) |
19607 (addr_hit[62] & (|(SPI_DEVICE_PERMIT[62] & ~reg_be))) |
19608 (addr_hit[63] & (|(SPI_DEVICE_PERMIT[63] & ~reg_be))) |
19609 (addr_hit[64] & (|(SPI_DEVICE_PERMIT[64] & ~reg_be))) |
19610 (addr_hit[65] & (|(SPI_DEVICE_PERMIT[65] & ~reg_be))) |
19611 (addr_hit[66] & (|(SPI_DEVICE_PERMIT[66] & ~reg_be))) |
19612 (addr_hit[67] & (|(SPI_DEVICE_PERMIT[67] & ~reg_be))) |
19613 (addr_hit[68] & (|(SPI_DEVICE_PERMIT[68] & ~reg_be))) |
19614 (addr_hit[69] & (|(SPI_DEVICE_PERMIT[69] & ~reg_be))) |
19615 (addr_hit[70] & (|(SPI_DEVICE_PERMIT[70] & ~reg_be))) |
19616 (addr_hit[71] & (|(SPI_DEVICE_PERMIT[71] & ~reg_be))) |
19617 (addr_hit[72] & (|(SPI_DEVICE_PERMIT[72] & ~reg_be)))));
19618 end
19619
19620 // Generate write-enables
19621 1/1 assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
Tests: T1 T2 T3
19622
19623 1/1 assign intr_state_upload_cmdfifo_not_empty_wd = reg_wdata[0];
Tests: T1 T2 T3
19624
19625 1/1 assign intr_state_upload_payload_not_empty_wd = reg_wdata[1];
Tests: T1 T2 T3
19626
19627 1/1 assign intr_state_upload_payload_overflow_wd = reg_wdata[2];
Tests: T1 T2 T3
19628
19629 1/1 assign intr_state_readbuf_watermark_wd = reg_wdata[3];
Tests: T1 T2 T3
19630
19631 1/1 assign intr_state_readbuf_flip_wd = reg_wdata[4];
Tests: T1 T2 T3
19632
19633 1/1 assign intr_state_tpm_rdfifo_cmd_end_wd = reg_wdata[6];
Tests: T1 T2 T3
19634
19635 1/1 assign intr_state_tpm_rdfifo_drop_wd = reg_wdata[7];
Tests: T1 T2 T3
19636 1/1 assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
Tests: T1 T2 T4
19637
19638 1/1 assign intr_enable_upload_cmdfifo_not_empty_wd = reg_wdata[0];
Tests: T1 T2 T3
19639
19640 1/1 assign intr_enable_upload_payload_not_empty_wd = reg_wdata[1];
Tests: T1 T2 T3
19641
19642 1/1 assign intr_enable_upload_payload_overflow_wd = reg_wdata[2];
Tests: T1 T2 T3
19643
19644 1/1 assign intr_enable_readbuf_watermark_wd = reg_wdata[3];
Tests: T1 T2 T3
19645
19646 1/1 assign intr_enable_readbuf_flip_wd = reg_wdata[4];
Tests: T1 T2 T3
19647
19648 1/1 assign intr_enable_tpm_header_not_empty_wd = reg_wdata[5];
Tests: T1 T2 T3
19649
19650 1/1 assign intr_enable_tpm_rdfifo_cmd_end_wd = reg_wdata[6];
Tests: T1 T2 T3
19651
19652 1/1 assign intr_enable_tpm_rdfifo_drop_wd = reg_wdata[7];
Tests: T1 T2 T3
19653 1/1 assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T2 T4
19654
19655 1/1 assign intr_test_upload_cmdfifo_not_empty_wd = reg_wdata[0];
Tests: T1 T2 T3
19656
19657 1/1 assign intr_test_upload_payload_not_empty_wd = reg_wdata[1];
Tests: T1 T2 T3
19658
19659 1/1 assign intr_test_upload_payload_overflow_wd = reg_wdata[2];
Tests: T1 T2 T3
19660
19661 1/1 assign intr_test_readbuf_watermark_wd = reg_wdata[3];
Tests: T1 T2 T3
19662
19663 1/1 assign intr_test_readbuf_flip_wd = reg_wdata[4];
Tests: T1 T2 T3
19664
19665 1/1 assign intr_test_tpm_header_not_empty_wd = reg_wdata[5];
Tests: T1 T2 T3
19666
19667 1/1 assign intr_test_tpm_rdfifo_cmd_end_wd = reg_wdata[6];
Tests: T1 T2 T3
19668
19669 1/1 assign intr_test_tpm_rdfifo_drop_wd = reg_wdata[7];
Tests: T1 T2 T3
19670 1/1 assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
Tests: T1 T2 T4
19671
19672 1/1 assign alert_test_wd = reg_wdata[0];
Tests: T1 T2 T3
19673 1/1 assign control_we = addr_hit[4] & reg_we & !reg_error;
Tests: T1 T2 T4
19674
19675 1/1 assign control_flash_status_fifo_clr_wd = reg_wdata[0];
Tests: T1 T2 T3
19676
19677 1/1 assign control_flash_read_buffer_clr_wd = reg_wdata[1];
Tests: T1 T2 T3
19678
19679 1/1 assign control_mode_wd = reg_wdata[5:4];
Tests: T1 T2 T3
19680 1/1 assign cfg_we = addr_hit[5] & reg_we & !reg_error;
Tests: T1 T2 T4
19681
19682 1/1 assign cfg_tx_order_wd = reg_wdata[2];
Tests: T1 T2 T3
19683
19684 1/1 assign cfg_rx_order_wd = reg_wdata[3];
Tests: T1 T2 T3
19685
19686 1/1 assign cfg_mailbox_en_wd = reg_wdata[24];
Tests: T1 T2 T3
19687 1/1 assign status_re = addr_hit[6] & reg_re & !reg_error;
Tests: T1 T2 T3
19688 1/1 assign intercept_en_we = addr_hit[7] & reg_we & !reg_error;
Tests: T1 T2 T3
19689
19690 1/1 assign intercept_en_status_wd = reg_wdata[0];
Tests: T1 T2 T3
19691
19692 1/1 assign intercept_en_jedec_wd = reg_wdata[1];
Tests: T1 T2 T3
19693
19694 1/1 assign intercept_en_sfdp_wd = reg_wdata[2];
Tests: T1 T2 T3
19695
19696 1/1 assign intercept_en_mbx_wd = reg_wdata[3];
Tests: T1 T2 T3
19697 1/1 assign addr_mode_re = addr_hit[8] & reg_re & !reg_error;
Tests: T1 T2 T3
19698 1/1 assign addr_mode_we = addr_hit[8] & reg_we & !reg_error;
Tests: T1 T2 T4
19699
19700 1/1 assign addr_mode_addr_4b_en_wd = reg_wdata[0];
Tests: T1 T2 T3
19701 1/1 assign last_read_addr_re = addr_hit[9] & reg_re & !reg_error;
Tests: T1 T2 T3
19702 1/1 assign flash_status_re = addr_hit[10] & reg_re & !reg_error;
Tests: T1 T2 T3
19703 1/1 assign flash_status_we = addr_hit[10] & reg_we & !reg_error;
Tests: T1 T2 T4
19704
19705 1/1 assign flash_status_busy_wd = reg_wdata[0];
Tests: T1 T2 T3
19706
19707 1/1 assign flash_status_wel_wd = reg_wdata[1];
Tests: T1 T2 T3
19708
19709 1/1 assign flash_status_status_wd = reg_wdata[23:2];
Tests: T1 T2 T3
19710 1/1 assign jedec_cc_we = addr_hit[11] & reg_we & !reg_error;
Tests: T1 T2 T3
19711
19712 1/1 assign jedec_cc_cc_wd = reg_wdata[7:0];
Tests: T1 T2 T3
19713
19714 1/1 assign jedec_cc_num_cc_wd = reg_wdata[15:8];
Tests: T1 T2 T3
19715 1/1 assign jedec_id_we = addr_hit[12] & reg_we & !reg_error;
Tests: T1 T2 T4
19716
19717 1/1 assign jedec_id_id_wd = reg_wdata[15:0];
Tests: T1 T2 T3
19718
19719 1/1 assign jedec_id_mf_wd = reg_wdata[23:16];
Tests: T1 T2 T3
19720 1/1 assign read_threshold_we = addr_hit[13] & reg_we & !reg_error;
Tests: T1 T2 T4
19721
19722 1/1 assign read_threshold_wd = reg_wdata[9:0];
Tests: T1 T2 T3
19723 1/1 assign mailbox_addr_we = addr_hit[14] & reg_we & !reg_error;
Tests: T1 T2 T4
19724
19725 1/1 assign mailbox_addr_wd = reg_wdata[31:0];
Tests: T1 T2 T3
19726 1/1 assign upload_cmdfifo_re = addr_hit[17] & reg_re & !reg_error;
Tests: T1 T2 T3
19727 1/1 assign upload_addrfifo_re = addr_hit[18] & reg_re & !reg_error;
Tests: T1 T2 T3
19728 1/1 assign cmd_filter_0_we = addr_hit[19] & reg_we & !reg_error;
Tests: T1 T2 T4
19729
19730 1/1 assign cmd_filter_0_filter_0_wd = reg_wdata[0];
Tests: T1 T2 T3
19731
19732 1/1 assign cmd_filter_0_filter_1_wd = reg_wdata[1];
Tests: T1 T2 T3
19733
19734 1/1 assign cmd_filter_0_filter_2_wd = reg_wdata[2];
Tests: T1 T2 T3
19735
19736 1/1 assign cmd_filter_0_filter_3_wd = reg_wdata[3];
Tests: T1 T2 T3
19737
19738 1/1 assign cmd_filter_0_filter_4_wd = reg_wdata[4];
Tests: T1 T2 T3
19739
19740 1/1 assign cmd_filter_0_filter_5_wd = reg_wdata[5];
Tests: T1 T2 T3
19741
19742 1/1 assign cmd_filter_0_filter_6_wd = reg_wdata[6];
Tests: T1 T2 T3
19743
19744 1/1 assign cmd_filter_0_filter_7_wd = reg_wdata[7];
Tests: T1 T2 T3
19745
19746 1/1 assign cmd_filter_0_filter_8_wd = reg_wdata[8];
Tests: T1 T2 T3
19747
19748 1/1 assign cmd_filter_0_filter_9_wd = reg_wdata[9];
Tests: T1 T2 T3
19749
19750 1/1 assign cmd_filter_0_filter_10_wd = reg_wdata[10];
Tests: T1 T2 T3
19751
19752 1/1 assign cmd_filter_0_filter_11_wd = reg_wdata[11];
Tests: T1 T2 T3
19753
19754 1/1 assign cmd_filter_0_filter_12_wd = reg_wdata[12];
Tests: T1 T2 T3
19755
19756 1/1 assign cmd_filter_0_filter_13_wd = reg_wdata[13];
Tests: T1 T2 T3
19757
19758 1/1 assign cmd_filter_0_filter_14_wd = reg_wdata[14];
Tests: T1 T2 T3
19759
19760 1/1 assign cmd_filter_0_filter_15_wd = reg_wdata[15];
Tests: T1 T2 T3
19761
19762 1/1 assign cmd_filter_0_filter_16_wd = reg_wdata[16];
Tests: T1 T2 T3
19763
19764 1/1 assign cmd_filter_0_filter_17_wd = reg_wdata[17];
Tests: T1 T2 T3
19765
19766 1/1 assign cmd_filter_0_filter_18_wd = reg_wdata[18];
Tests: T1 T2 T3
19767
19768 1/1 assign cmd_filter_0_filter_19_wd = reg_wdata[19];
Tests: T1 T2 T3
19769
19770 1/1 assign cmd_filter_0_filter_20_wd = reg_wdata[20];
Tests: T1 T2 T3
19771
19772 1/1 assign cmd_filter_0_filter_21_wd = reg_wdata[21];
Tests: T1 T2 T3
19773
19774 1/1 assign cmd_filter_0_filter_22_wd = reg_wdata[22];
Tests: T1 T2 T3
19775
19776 1/1 assign cmd_filter_0_filter_23_wd = reg_wdata[23];
Tests: T1 T2 T3
19777
19778 1/1 assign cmd_filter_0_filter_24_wd = reg_wdata[24];
Tests: T1 T2 T3
19779
19780 1/1 assign cmd_filter_0_filter_25_wd = reg_wdata[25];
Tests: T1 T2 T3
19781
19782 1/1 assign cmd_filter_0_filter_26_wd = reg_wdata[26];
Tests: T1 T2 T3
19783
19784 1/1 assign cmd_filter_0_filter_27_wd = reg_wdata[27];
Tests: T1 T2 T3
19785
19786 1/1 assign cmd_filter_0_filter_28_wd = reg_wdata[28];
Tests: T1 T2 T3
19787
19788 1/1 assign cmd_filter_0_filter_29_wd = reg_wdata[29];
Tests: T1 T2 T3
19789
19790 1/1 assign cmd_filter_0_filter_30_wd = reg_wdata[30];
Tests: T1 T2 T3
19791
19792 1/1 assign cmd_filter_0_filter_31_wd = reg_wdata[31];
Tests: T1 T2 T3
19793 1/1 assign cmd_filter_1_we = addr_hit[20] & reg_we & !reg_error;
Tests: T1 T2 T4
19794
19795 1/1 assign cmd_filter_1_filter_32_wd = reg_wdata[0];
Tests: T1 T2 T3
19796
19797 1/1 assign cmd_filter_1_filter_33_wd = reg_wdata[1];
Tests: T1 T2 T3
19798
19799 1/1 assign cmd_filter_1_filter_34_wd = reg_wdata[2];
Tests: T1 T2 T3
19800
19801 1/1 assign cmd_filter_1_filter_35_wd = reg_wdata[3];
Tests: T1 T2 T3
19802
19803 1/1 assign cmd_filter_1_filter_36_wd = reg_wdata[4];
Tests: T1 T2 T3
19804
19805 1/1 assign cmd_filter_1_filter_37_wd = reg_wdata[5];
Tests: T1 T2 T3
19806
19807 1/1 assign cmd_filter_1_filter_38_wd = reg_wdata[6];
Tests: T1 T2 T3
19808
19809 1/1 assign cmd_filter_1_filter_39_wd = reg_wdata[7];
Tests: T1 T2 T3
19810
19811 1/1 assign cmd_filter_1_filter_40_wd = reg_wdata[8];
Tests: T1 T2 T3
19812
19813 1/1 assign cmd_filter_1_filter_41_wd = reg_wdata[9];
Tests: T1 T2 T3
19814
19815 1/1 assign cmd_filter_1_filter_42_wd = reg_wdata[10];
Tests: T1 T2 T3
19816
19817 1/1 assign cmd_filter_1_filter_43_wd = reg_wdata[11];
Tests: T1 T2 T3
19818
19819 1/1 assign cmd_filter_1_filter_44_wd = reg_wdata[12];
Tests: T1 T2 T3
19820
19821 1/1 assign cmd_filter_1_filter_45_wd = reg_wdata[13];
Tests: T1 T2 T3
19822
19823 1/1 assign cmd_filter_1_filter_46_wd = reg_wdata[14];
Tests: T1 T2 T3
19824
19825 1/1 assign cmd_filter_1_filter_47_wd = reg_wdata[15];
Tests: T1 T2 T3
19826
19827 1/1 assign cmd_filter_1_filter_48_wd = reg_wdata[16];
Tests: T1 T2 T3
19828
19829 1/1 assign cmd_filter_1_filter_49_wd = reg_wdata[17];
Tests: T1 T2 T3
19830
19831 1/1 assign cmd_filter_1_filter_50_wd = reg_wdata[18];
Tests: T1 T2 T3
19832
19833 1/1 assign cmd_filter_1_filter_51_wd = reg_wdata[19];
Tests: T1 T2 T3
19834
19835 1/1 assign cmd_filter_1_filter_52_wd = reg_wdata[20];
Tests: T1 T2 T3
19836
19837 1/1 assign cmd_filter_1_filter_53_wd = reg_wdata[21];
Tests: T1 T2 T3
19838
19839 1/1 assign cmd_filter_1_filter_54_wd = reg_wdata[22];
Tests: T1 T2 T3
19840
19841 1/1 assign cmd_filter_1_filter_55_wd = reg_wdata[23];
Tests: T1 T2 T3
19842
19843 1/1 assign cmd_filter_1_filter_56_wd = reg_wdata[24];
Tests: T1 T2 T3
19844
19845 1/1 assign cmd_filter_1_filter_57_wd = reg_wdata[25];
Tests: T1 T2 T3
19846
19847 1/1 assign cmd_filter_1_filter_58_wd = reg_wdata[26];
Tests: T1 T2 T3
19848
19849 1/1 assign cmd_filter_1_filter_59_wd = reg_wdata[27];
Tests: T1 T2 T3
19850
19851 1/1 assign cmd_filter_1_filter_60_wd = reg_wdata[28];
Tests: T1 T2 T3
19852
19853 1/1 assign cmd_filter_1_filter_61_wd = reg_wdata[29];
Tests: T1 T2 T3
19854
19855 1/1 assign cmd_filter_1_filter_62_wd = reg_wdata[30];
Tests: T1 T2 T3
19856
19857 1/1 assign cmd_filter_1_filter_63_wd = reg_wdata[31];
Tests: T1 T2 T3
19858 1/1 assign cmd_filter_2_we = addr_hit[21] & reg_we & !reg_error;
Tests: T1 T2 T4
19859
19860 1/1 assign cmd_filter_2_filter_64_wd = reg_wdata[0];
Tests: T1 T2 T3
19861
19862 1/1 assign cmd_filter_2_filter_65_wd = reg_wdata[1];
Tests: T1 T2 T3
19863
19864 1/1 assign cmd_filter_2_filter_66_wd = reg_wdata[2];
Tests: T1 T2 T3
19865
19866 1/1 assign cmd_filter_2_filter_67_wd = reg_wdata[3];
Tests: T1 T2 T3
19867
19868 1/1 assign cmd_filter_2_filter_68_wd = reg_wdata[4];
Tests: T1 T2 T3
19869
19870 1/1 assign cmd_filter_2_filter_69_wd = reg_wdata[5];
Tests: T1 T2 T3
19871
19872 1/1 assign cmd_filter_2_filter_70_wd = reg_wdata[6];
Tests: T1 T2 T3
19873
19874 1/1 assign cmd_filter_2_filter_71_wd = reg_wdata[7];
Tests: T1 T2 T3
19875
19876 1/1 assign cmd_filter_2_filter_72_wd = reg_wdata[8];
Tests: T1 T2 T3
19877
19878 1/1 assign cmd_filter_2_filter_73_wd = reg_wdata[9];
Tests: T1 T2 T3
19879
19880 1/1 assign cmd_filter_2_filter_74_wd = reg_wdata[10];
Tests: T1 T2 T3
19881
19882 1/1 assign cmd_filter_2_filter_75_wd = reg_wdata[11];
Tests: T1 T2 T3
19883
19884 1/1 assign cmd_filter_2_filter_76_wd = reg_wdata[12];
Tests: T1 T2 T3
19885
19886 1/1 assign cmd_filter_2_filter_77_wd = reg_wdata[13];
Tests: T1 T2 T3
19887
19888 1/1 assign cmd_filter_2_filter_78_wd = reg_wdata[14];
Tests: T1 T2 T3
19889
19890 1/1 assign cmd_filter_2_filter_79_wd = reg_wdata[15];
Tests: T1 T2 T3
19891
19892 1/1 assign cmd_filter_2_filter_80_wd = reg_wdata[16];
Tests: T1 T2 T3
19893
19894 1/1 assign cmd_filter_2_filter_81_wd = reg_wdata[17];
Tests: T1 T2 T3
19895
19896 1/1 assign cmd_filter_2_filter_82_wd = reg_wdata[18];
Tests: T1 T2 T3
19897
19898 1/1 assign cmd_filter_2_filter_83_wd = reg_wdata[19];
Tests: T1 T2 T3
19899
19900 1/1 assign cmd_filter_2_filter_84_wd = reg_wdata[20];
Tests: T1 T2 T3
19901
19902 1/1 assign cmd_filter_2_filter_85_wd = reg_wdata[21];
Tests: T1 T2 T3
19903
19904 1/1 assign cmd_filter_2_filter_86_wd = reg_wdata[22];
Tests: T1 T2 T3
19905
19906 1/1 assign cmd_filter_2_filter_87_wd = reg_wdata[23];
Tests: T1 T2 T3
19907
19908 1/1 assign cmd_filter_2_filter_88_wd = reg_wdata[24];
Tests: T1 T2 T3
19909
19910 1/1 assign cmd_filter_2_filter_89_wd = reg_wdata[25];
Tests: T1 T2 T3
19911
19912 1/1 assign cmd_filter_2_filter_90_wd = reg_wdata[26];
Tests: T1 T2 T3
19913
19914 1/1 assign cmd_filter_2_filter_91_wd = reg_wdata[27];
Tests: T1 T2 T3
19915
19916 1/1 assign cmd_filter_2_filter_92_wd = reg_wdata[28];
Tests: T1 T2 T3
19917
19918 1/1 assign cmd_filter_2_filter_93_wd = reg_wdata[29];
Tests: T1 T2 T3
19919
19920 1/1 assign cmd_filter_2_filter_94_wd = reg_wdata[30];
Tests: T1 T2 T3
19921
19922 1/1 assign cmd_filter_2_filter_95_wd = reg_wdata[31];
Tests: T1 T2 T3
19923 1/1 assign cmd_filter_3_we = addr_hit[22] & reg_we & !reg_error;
Tests: T1 T2 T4
19924
19925 1/1 assign cmd_filter_3_filter_96_wd = reg_wdata[0];
Tests: T1 T2 T3
19926
19927 1/1 assign cmd_filter_3_filter_97_wd = reg_wdata[1];
Tests: T1 T2 T3
19928
19929 1/1 assign cmd_filter_3_filter_98_wd = reg_wdata[2];
Tests: T1 T2 T3
19930
19931 1/1 assign cmd_filter_3_filter_99_wd = reg_wdata[3];
Tests: T1 T2 T3
19932
19933 1/1 assign cmd_filter_3_filter_100_wd = reg_wdata[4];
Tests: T1 T2 T3
19934
19935 1/1 assign cmd_filter_3_filter_101_wd = reg_wdata[5];
Tests: T1 T2 T3
19936
19937 1/1 assign cmd_filter_3_filter_102_wd = reg_wdata[6];
Tests: T1 T2 T3
19938
19939 1/1 assign cmd_filter_3_filter_103_wd = reg_wdata[7];
Tests: T1 T2 T3
19940
19941 1/1 assign cmd_filter_3_filter_104_wd = reg_wdata[8];
Tests: T1 T2 T3
19942
19943 1/1 assign cmd_filter_3_filter_105_wd = reg_wdata[9];
Tests: T1 T2 T3
19944
19945 1/1 assign cmd_filter_3_filter_106_wd = reg_wdata[10];
Tests: T1 T2 T3
19946
19947 1/1 assign cmd_filter_3_filter_107_wd = reg_wdata[11];
Tests: T1 T2 T3
19948
19949 1/1 assign cmd_filter_3_filter_108_wd = reg_wdata[12];
Tests: T1 T2 T3
19950
19951 1/1 assign cmd_filter_3_filter_109_wd = reg_wdata[13];
Tests: T1 T2 T3
19952
19953 1/1 assign cmd_filter_3_filter_110_wd = reg_wdata[14];
Tests: T1 T2 T3
19954
19955 1/1 assign cmd_filter_3_filter_111_wd = reg_wdata[15];
Tests: T1 T2 T3
19956
19957 1/1 assign cmd_filter_3_filter_112_wd = reg_wdata[16];
Tests: T1 T2 T3
19958
19959 1/1 assign cmd_filter_3_filter_113_wd = reg_wdata[17];
Tests: T1 T2 T3
19960
19961 1/1 assign cmd_filter_3_filter_114_wd = reg_wdata[18];
Tests: T1 T2 T3
19962
19963 1/1 assign cmd_filter_3_filter_115_wd = reg_wdata[19];
Tests: T1 T2 T3
19964
19965 1/1 assign cmd_filter_3_filter_116_wd = reg_wdata[20];
Tests: T1 T2 T3
19966
19967 1/1 assign cmd_filter_3_filter_117_wd = reg_wdata[21];
Tests: T1 T2 T3
19968
19969 1/1 assign cmd_filter_3_filter_118_wd = reg_wdata[22];
Tests: T1 T2 T3
19970
19971 1/1 assign cmd_filter_3_filter_119_wd = reg_wdata[23];
Tests: T1 T2 T3
19972
19973 1/1 assign cmd_filter_3_filter_120_wd = reg_wdata[24];
Tests: T1 T2 T3
19974
19975 1/1 assign cmd_filter_3_filter_121_wd = reg_wdata[25];
Tests: T1 T2 T3
19976
19977 1/1 assign cmd_filter_3_filter_122_wd = reg_wdata[26];
Tests: T1 T2 T3
19978
19979 1/1 assign cmd_filter_3_filter_123_wd = reg_wdata[27];
Tests: T1 T2 T3
19980
19981 1/1 assign cmd_filter_3_filter_124_wd = reg_wdata[28];
Tests: T1 T2 T3
19982
19983 1/1 assign cmd_filter_3_filter_125_wd = reg_wdata[29];
Tests: T1 T2 T3
19984
19985 1/1 assign cmd_filter_3_filter_126_wd = reg_wdata[30];
Tests: T1 T2 T3
19986
19987 1/1 assign cmd_filter_3_filter_127_wd = reg_wdata[31];
Tests: T1 T2 T3
19988 1/1 assign cmd_filter_4_we = addr_hit[23] & reg_we & !reg_error;
Tests: T1 T2 T4
19989
19990 1/1 assign cmd_filter_4_filter_128_wd = reg_wdata[0];
Tests: T1 T2 T3
19991
19992 1/1 assign cmd_filter_4_filter_129_wd = reg_wdata[1];
Tests: T1 T2 T3
19993
19994 1/1 assign cmd_filter_4_filter_130_wd = reg_wdata[2];
Tests: T1 T2 T3
19995
19996 1/1 assign cmd_filter_4_filter_131_wd = reg_wdata[3];
Tests: T1 T2 T3
19997
19998 1/1 assign cmd_filter_4_filter_132_wd = reg_wdata[4];
Tests: T1 T2 T3
19999
20000 1/1 assign cmd_filter_4_filter_133_wd = reg_wdata[5];
Tests: T1 T2 T3
20001
20002 1/1 assign cmd_filter_4_filter_134_wd = reg_wdata[6];
Tests: T1 T2 T3
20003
20004 1/1 assign cmd_filter_4_filter_135_wd = reg_wdata[7];
Tests: T1 T2 T3
20005
20006 1/1 assign cmd_filter_4_filter_136_wd = reg_wdata[8];
Tests: T1 T2 T3
20007
20008 1/1 assign cmd_filter_4_filter_137_wd = reg_wdata[9];
Tests: T1 T2 T3
20009
20010 1/1 assign cmd_filter_4_filter_138_wd = reg_wdata[10];
Tests: T1 T2 T3
20011
20012 1/1 assign cmd_filter_4_filter_139_wd = reg_wdata[11];
Tests: T1 T2 T3
20013
20014 1/1 assign cmd_filter_4_filter_140_wd = reg_wdata[12];
Tests: T1 T2 T3
20015
20016 1/1 assign cmd_filter_4_filter_141_wd = reg_wdata[13];
Tests: T1 T2 T3
20017
20018 1/1 assign cmd_filter_4_filter_142_wd = reg_wdata[14];
Tests: T1 T2 T3
20019
20020 1/1 assign cmd_filter_4_filter_143_wd = reg_wdata[15];
Tests: T1 T2 T3
20021
20022 1/1 assign cmd_filter_4_filter_144_wd = reg_wdata[16];
Tests: T1 T2 T3
20023
20024 1/1 assign cmd_filter_4_filter_145_wd = reg_wdata[17];
Tests: T1 T2 T3
20025
20026 1/1 assign cmd_filter_4_filter_146_wd = reg_wdata[18];
Tests: T1 T2 T3
20027
20028 1/1 assign cmd_filter_4_filter_147_wd = reg_wdata[19];
Tests: T1 T2 T3
20029
20030 1/1 assign cmd_filter_4_filter_148_wd = reg_wdata[20];
Tests: T1 T2 T3
20031
20032 1/1 assign cmd_filter_4_filter_149_wd = reg_wdata[21];
Tests: T1 T2 T3
20033
20034 1/1 assign cmd_filter_4_filter_150_wd = reg_wdata[22];
Tests: T1 T2 T3
20035
20036 1/1 assign cmd_filter_4_filter_151_wd = reg_wdata[23];
Tests: T1 T2 T3
20037
20038 1/1 assign cmd_filter_4_filter_152_wd = reg_wdata[24];
Tests: T1 T2 T3
20039
20040 1/1 assign cmd_filter_4_filter_153_wd = reg_wdata[25];
Tests: T1 T2 T3
20041
20042 1/1 assign cmd_filter_4_filter_154_wd = reg_wdata[26];
Tests: T1 T2 T3
20043
20044 1/1 assign cmd_filter_4_filter_155_wd = reg_wdata[27];
Tests: T1 T2 T3
20045
20046 1/1 assign cmd_filter_4_filter_156_wd = reg_wdata[28];
Tests: T1 T2 T3
20047
20048 1/1 assign cmd_filter_4_filter_157_wd = reg_wdata[29];
Tests: T1 T2 T3
20049
20050 1/1 assign cmd_filter_4_filter_158_wd = reg_wdata[30];
Tests: T1 T2 T3
20051
20052 1/1 assign cmd_filter_4_filter_159_wd = reg_wdata[31];
Tests: T1 T2 T3
20053 1/1 assign cmd_filter_5_we = addr_hit[24] & reg_we & !reg_error;
Tests: T1 T2 T4
20054
20055 1/1 assign cmd_filter_5_filter_160_wd = reg_wdata[0];
Tests: T1 T2 T3
20056
20057 1/1 assign cmd_filter_5_filter_161_wd = reg_wdata[1];
Tests: T1 T2 T3
20058
20059 1/1 assign cmd_filter_5_filter_162_wd = reg_wdata[2];
Tests: T1 T2 T3
20060
20061 1/1 assign cmd_filter_5_filter_163_wd = reg_wdata[3];
Tests: T1 T2 T3
20062
20063 1/1 assign cmd_filter_5_filter_164_wd = reg_wdata[4];
Tests: T1 T2 T3
20064
20065 1/1 assign cmd_filter_5_filter_165_wd = reg_wdata[5];
Tests: T1 T2 T3
20066
20067 1/1 assign cmd_filter_5_filter_166_wd = reg_wdata[6];
Tests: T1 T2 T3
20068
20069 1/1 assign cmd_filter_5_filter_167_wd = reg_wdata[7];
Tests: T1 T2 T3
20070
20071 1/1 assign cmd_filter_5_filter_168_wd = reg_wdata[8];
Tests: T1 T2 T3
20072
20073 1/1 assign cmd_filter_5_filter_169_wd = reg_wdata[9];
Tests: T1 T2 T3
20074
20075 1/1 assign cmd_filter_5_filter_170_wd = reg_wdata[10];
Tests: T1 T2 T3
20076
20077 1/1 assign cmd_filter_5_filter_171_wd = reg_wdata[11];
Tests: T1 T2 T3
20078
20079 1/1 assign cmd_filter_5_filter_172_wd = reg_wdata[12];
Tests: T1 T2 T3
20080
20081 1/1 assign cmd_filter_5_filter_173_wd = reg_wdata[13];
Tests: T1 T2 T3
20082
20083 1/1 assign cmd_filter_5_filter_174_wd = reg_wdata[14];
Tests: T1 T2 T3
20084
20085 1/1 assign cmd_filter_5_filter_175_wd = reg_wdata[15];
Tests: T1 T2 T3
20086
20087 1/1 assign cmd_filter_5_filter_176_wd = reg_wdata[16];
Tests: T1 T2 T3
20088
20089 1/1 assign cmd_filter_5_filter_177_wd = reg_wdata[17];
Tests: T1 T2 T3
20090
20091 1/1 assign cmd_filter_5_filter_178_wd = reg_wdata[18];
Tests: T1 T2 T3
20092
20093 1/1 assign cmd_filter_5_filter_179_wd = reg_wdata[19];
Tests: T1 T2 T3
20094
20095 1/1 assign cmd_filter_5_filter_180_wd = reg_wdata[20];
Tests: T1 T2 T3
20096
20097 1/1 assign cmd_filter_5_filter_181_wd = reg_wdata[21];
Tests: T1 T2 T3
20098
20099 1/1 assign cmd_filter_5_filter_182_wd = reg_wdata[22];
Tests: T1 T2 T3
20100
20101 1/1 assign cmd_filter_5_filter_183_wd = reg_wdata[23];
Tests: T1 T2 T3
20102
20103 1/1 assign cmd_filter_5_filter_184_wd = reg_wdata[24];
Tests: T1 T2 T3
20104
20105 1/1 assign cmd_filter_5_filter_185_wd = reg_wdata[25];
Tests: T1 T2 T3
20106
20107 1/1 assign cmd_filter_5_filter_186_wd = reg_wdata[26];
Tests: T1 T2 T3
20108
20109 1/1 assign cmd_filter_5_filter_187_wd = reg_wdata[27];
Tests: T1 T2 T3
20110
20111 1/1 assign cmd_filter_5_filter_188_wd = reg_wdata[28];
Tests: T1 T2 T3
20112
20113 1/1 assign cmd_filter_5_filter_189_wd = reg_wdata[29];
Tests: T1 T2 T3
20114
20115 1/1 assign cmd_filter_5_filter_190_wd = reg_wdata[30];
Tests: T1 T2 T3
20116
20117 1/1 assign cmd_filter_5_filter_191_wd = reg_wdata[31];
Tests: T1 T2 T3
20118 1/1 assign cmd_filter_6_we = addr_hit[25] & reg_we & !reg_error;
Tests: T1 T2 T4
20119
20120 1/1 assign cmd_filter_6_filter_192_wd = reg_wdata[0];
Tests: T1 T2 T3
20121
20122 1/1 assign cmd_filter_6_filter_193_wd = reg_wdata[1];
Tests: T1 T2 T3
20123
20124 1/1 assign cmd_filter_6_filter_194_wd = reg_wdata[2];
Tests: T1 T2 T3
20125
20126 1/1 assign cmd_filter_6_filter_195_wd = reg_wdata[3];
Tests: T1 T2 T3
20127
20128 1/1 assign cmd_filter_6_filter_196_wd = reg_wdata[4];
Tests: T1 T2 T3
20129
20130 1/1 assign cmd_filter_6_filter_197_wd = reg_wdata[5];
Tests: T1 T2 T3
20131
20132 1/1 assign cmd_filter_6_filter_198_wd = reg_wdata[6];
Tests: T1 T2 T3
20133
20134 1/1 assign cmd_filter_6_filter_199_wd = reg_wdata[7];
Tests: T1 T2 T3
20135
20136 1/1 assign cmd_filter_6_filter_200_wd = reg_wdata[8];
Tests: T1 T2 T3
20137
20138 1/1 assign cmd_filter_6_filter_201_wd = reg_wdata[9];
Tests: T1 T2 T3
20139
20140 1/1 assign cmd_filter_6_filter_202_wd = reg_wdata[10];
Tests: T1 T2 T3
20141
20142 1/1 assign cmd_filter_6_filter_203_wd = reg_wdata[11];
Tests: T1 T2 T3
20143
20144 1/1 assign cmd_filter_6_filter_204_wd = reg_wdata[12];
Tests: T1 T2 T3
20145
20146 1/1 assign cmd_filter_6_filter_205_wd = reg_wdata[13];
Tests: T1 T2 T3
20147
20148 1/1 assign cmd_filter_6_filter_206_wd = reg_wdata[14];
Tests: T1 T2 T3
20149
20150 1/1 assign cmd_filter_6_filter_207_wd = reg_wdata[15];
Tests: T1 T2 T3
20151
20152 1/1 assign cmd_filter_6_filter_208_wd = reg_wdata[16];
Tests: T1 T2 T3
20153
20154 1/1 assign cmd_filter_6_filter_209_wd = reg_wdata[17];
Tests: T1 T2 T3
20155
20156 1/1 assign cmd_filter_6_filter_210_wd = reg_wdata[18];
Tests: T1 T2 T3
20157
20158 1/1 assign cmd_filter_6_filter_211_wd = reg_wdata[19];
Tests: T1 T2 T3
20159
20160 1/1 assign cmd_filter_6_filter_212_wd = reg_wdata[20];
Tests: T1 T2 T3
20161
20162 1/1 assign cmd_filter_6_filter_213_wd = reg_wdata[21];
Tests: T1 T2 T3
20163
20164 1/1 assign cmd_filter_6_filter_214_wd = reg_wdata[22];
Tests: T1 T2 T3
20165
20166 1/1 assign cmd_filter_6_filter_215_wd = reg_wdata[23];
Tests: T1 T2 T3
20167
20168 1/1 assign cmd_filter_6_filter_216_wd = reg_wdata[24];
Tests: T1 T2 T3
20169
20170 1/1 assign cmd_filter_6_filter_217_wd = reg_wdata[25];
Tests: T1 T2 T3
20171
20172 1/1 assign cmd_filter_6_filter_218_wd = reg_wdata[26];
Tests: T1 T2 T3
20173
20174 1/1 assign cmd_filter_6_filter_219_wd = reg_wdata[27];
Tests: T1 T2 T3
20175
20176 1/1 assign cmd_filter_6_filter_220_wd = reg_wdata[28];
Tests: T1 T2 T3
20177
20178 1/1 assign cmd_filter_6_filter_221_wd = reg_wdata[29];
Tests: T1 T2 T3
20179
20180 1/1 assign cmd_filter_6_filter_222_wd = reg_wdata[30];
Tests: T1 T2 T3
20181
20182 1/1 assign cmd_filter_6_filter_223_wd = reg_wdata[31];
Tests: T1 T2 T3
20183 1/1 assign cmd_filter_7_we = addr_hit[26] & reg_we & !reg_error;
Tests: T1 T2 T3
20184
20185 1/1 assign cmd_filter_7_filter_224_wd = reg_wdata[0];
Tests: T1 T2 T3
20186
20187 1/1 assign cmd_filter_7_filter_225_wd = reg_wdata[1];
Tests: T1 T2 T3
20188
20189 1/1 assign cmd_filter_7_filter_226_wd = reg_wdata[2];
Tests: T1 T2 T3
20190
20191 1/1 assign cmd_filter_7_filter_227_wd = reg_wdata[3];
Tests: T1 T2 T3
20192
20193 1/1 assign cmd_filter_7_filter_228_wd = reg_wdata[4];
Tests: T1 T2 T3
20194
20195 1/1 assign cmd_filter_7_filter_229_wd = reg_wdata[5];
Tests: T1 T2 T3
20196
20197 1/1 assign cmd_filter_7_filter_230_wd = reg_wdata[6];
Tests: T1 T2 T3
20198
20199 1/1 assign cmd_filter_7_filter_231_wd = reg_wdata[7];
Tests: T1 T2 T3
20200
20201 1/1 assign cmd_filter_7_filter_232_wd = reg_wdata[8];
Tests: T1 T2 T3
20202
20203 1/1 assign cmd_filter_7_filter_233_wd = reg_wdata[9];
Tests: T1 T2 T3
20204
20205 1/1 assign cmd_filter_7_filter_234_wd = reg_wdata[10];
Tests: T1 T2 T3
20206
20207 1/1 assign cmd_filter_7_filter_235_wd = reg_wdata[11];
Tests: T1 T2 T3
20208
20209 1/1 assign cmd_filter_7_filter_236_wd = reg_wdata[12];
Tests: T1 T2 T3
20210
20211 1/1 assign cmd_filter_7_filter_237_wd = reg_wdata[13];
Tests: T1 T2 T3
20212
20213 1/1 assign cmd_filter_7_filter_238_wd = reg_wdata[14];
Tests: T1 T2 T3
20214
20215 1/1 assign cmd_filter_7_filter_239_wd = reg_wdata[15];
Tests: T1 T2 T3
20216
20217 1/1 assign cmd_filter_7_filter_240_wd = reg_wdata[16];
Tests: T1 T2 T3
20218
20219 1/1 assign cmd_filter_7_filter_241_wd = reg_wdata[17];
Tests: T1 T2 T3
20220
20221 1/1 assign cmd_filter_7_filter_242_wd = reg_wdata[18];
Tests: T1 T2 T3
20222
20223 1/1 assign cmd_filter_7_filter_243_wd = reg_wdata[19];
Tests: T1 T2 T3
20224
20225 1/1 assign cmd_filter_7_filter_244_wd = reg_wdata[20];
Tests: T1 T2 T3
20226
20227 1/1 assign cmd_filter_7_filter_245_wd = reg_wdata[21];
Tests: T1 T2 T3
20228
20229 1/1 assign cmd_filter_7_filter_246_wd = reg_wdata[22];
Tests: T1 T2 T3
20230
20231 1/1 assign cmd_filter_7_filter_247_wd = reg_wdata[23];
Tests: T1 T2 T3
20232
20233 1/1 assign cmd_filter_7_filter_248_wd = reg_wdata[24];
Tests: T1 T2 T3
20234
20235 1/1 assign cmd_filter_7_filter_249_wd = reg_wdata[25];
Tests: T1 T2 T3
20236
20237 1/1 assign cmd_filter_7_filter_250_wd = reg_wdata[26];
Tests: T1 T2 T3
20238
20239 1/1 assign cmd_filter_7_filter_251_wd = reg_wdata[27];
Tests: T1 T2 T3
20240
20241 1/1 assign cmd_filter_7_filter_252_wd = reg_wdata[28];
Tests: T1 T2 T3
20242
20243 1/1 assign cmd_filter_7_filter_253_wd = reg_wdata[29];
Tests: T1 T2 T3
20244
20245 1/1 assign cmd_filter_7_filter_254_wd = reg_wdata[30];
Tests: T1 T2 T3
20246
20247 1/1 assign cmd_filter_7_filter_255_wd = reg_wdata[31];
Tests: T1 T2 T3
20248 1/1 assign addr_swap_mask_we = addr_hit[27] & reg_we & !reg_error;
Tests: T1 T2 T4
20249
20250 1/1 assign addr_swap_mask_wd = reg_wdata[31:0];
Tests: T1 T2 T3
20251 1/1 assign addr_swap_data_we = addr_hit[28] & reg_we & !reg_error;
Tests: T1 T2 T4
20252
20253 1/1 assign addr_swap_data_wd = reg_wdata[31:0];
Tests: T1 T2 T3
20254 1/1 assign payload_swap_mask_we = addr_hit[29] & reg_we & !reg_error;
Tests: T1 T2 T3
20255
20256 1/1 assign payload_swap_mask_wd = reg_wdata[31:0];
Tests: T1 T2 T3
20257 1/1 assign payload_swap_data_we = addr_hit[30] & reg_we & !reg_error;
Tests: T1 T2 T4
20258
20259 1/1 assign payload_swap_data_wd = reg_wdata[31:0];
Tests: T1 T2 T3
20260 1/1 assign cmd_info_0_we = addr_hit[31] & reg_we & !reg_error;
Tests: T1 T2 T4
20261
20262 1/1 assign cmd_info_0_opcode_0_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20263
20264 1/1 assign cmd_info_0_addr_mode_0_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20265
20266 1/1 assign cmd_info_0_addr_swap_en_0_wd = reg_wdata[10];
Tests: T1 T2 T3
20267
20268 1/1 assign cmd_info_0_mbyte_en_0_wd = reg_wdata[11];
Tests: T1 T2 T3
20269
20270 1/1 assign cmd_info_0_dummy_size_0_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20271
20272 1/1 assign cmd_info_0_dummy_en_0_wd = reg_wdata[15];
Tests: T1 T2 T3
20273
20274 1/1 assign cmd_info_0_payload_en_0_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20275
20276 1/1 assign cmd_info_0_payload_dir_0_wd = reg_wdata[20];
Tests: T1 T2 T3
20277
20278 1/1 assign cmd_info_0_payload_swap_en_0_wd = reg_wdata[21];
Tests: T1 T2 T3
20279
20280 1/1 assign cmd_info_0_read_pipeline_mode_0_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20281
20282 1/1 assign cmd_info_0_upload_0_wd = reg_wdata[24];
Tests: T1 T2 T3
20283
20284 1/1 assign cmd_info_0_busy_0_wd = reg_wdata[25];
Tests: T1 T2 T3
20285
20286 1/1 assign cmd_info_0_valid_0_wd = reg_wdata[31];
Tests: T1 T2 T3
20287 1/1 assign cmd_info_1_we = addr_hit[32] & reg_we & !reg_error;
Tests: T1 T2 T4
20288
20289 1/1 assign cmd_info_1_opcode_1_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20290
20291 1/1 assign cmd_info_1_addr_mode_1_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20292
20293 1/1 assign cmd_info_1_addr_swap_en_1_wd = reg_wdata[10];
Tests: T1 T2 T3
20294
20295 1/1 assign cmd_info_1_mbyte_en_1_wd = reg_wdata[11];
Tests: T1 T2 T3
20296
20297 1/1 assign cmd_info_1_dummy_size_1_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20298
20299 1/1 assign cmd_info_1_dummy_en_1_wd = reg_wdata[15];
Tests: T1 T2 T3
20300
20301 1/1 assign cmd_info_1_payload_en_1_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20302
20303 1/1 assign cmd_info_1_payload_dir_1_wd = reg_wdata[20];
Tests: T1 T2 T3
20304
20305 1/1 assign cmd_info_1_payload_swap_en_1_wd = reg_wdata[21];
Tests: T1 T2 T3
20306
20307 1/1 assign cmd_info_1_read_pipeline_mode_1_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20308
20309 1/1 assign cmd_info_1_upload_1_wd = reg_wdata[24];
Tests: T1 T2 T3
20310
20311 1/1 assign cmd_info_1_busy_1_wd = reg_wdata[25];
Tests: T1 T2 T3
20312
20313 1/1 assign cmd_info_1_valid_1_wd = reg_wdata[31];
Tests: T1 T2 T3
20314 1/1 assign cmd_info_2_we = addr_hit[33] & reg_we & !reg_error;
Tests: T1 T2 T4
20315
20316 1/1 assign cmd_info_2_opcode_2_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20317
20318 1/1 assign cmd_info_2_addr_mode_2_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20319
20320 1/1 assign cmd_info_2_addr_swap_en_2_wd = reg_wdata[10];
Tests: T1 T2 T3
20321
20322 1/1 assign cmd_info_2_mbyte_en_2_wd = reg_wdata[11];
Tests: T1 T2 T3
20323
20324 1/1 assign cmd_info_2_dummy_size_2_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20325
20326 1/1 assign cmd_info_2_dummy_en_2_wd = reg_wdata[15];
Tests: T1 T2 T3
20327
20328 1/1 assign cmd_info_2_payload_en_2_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20329
20330 1/1 assign cmd_info_2_payload_dir_2_wd = reg_wdata[20];
Tests: T1 T2 T3
20331
20332 1/1 assign cmd_info_2_payload_swap_en_2_wd = reg_wdata[21];
Tests: T1 T2 T3
20333
20334 1/1 assign cmd_info_2_read_pipeline_mode_2_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20335
20336 1/1 assign cmd_info_2_upload_2_wd = reg_wdata[24];
Tests: T1 T2 T3
20337
20338 1/1 assign cmd_info_2_busy_2_wd = reg_wdata[25];
Tests: T1 T2 T3
20339
20340 1/1 assign cmd_info_2_valid_2_wd = reg_wdata[31];
Tests: T1 T2 T3
20341 1/1 assign cmd_info_3_we = addr_hit[34] & reg_we & !reg_error;
Tests: T1 T2 T4
20342
20343 1/1 assign cmd_info_3_opcode_3_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20344
20345 1/1 assign cmd_info_3_addr_mode_3_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20346
20347 1/1 assign cmd_info_3_addr_swap_en_3_wd = reg_wdata[10];
Tests: T1 T2 T3
20348
20349 1/1 assign cmd_info_3_mbyte_en_3_wd = reg_wdata[11];
Tests: T1 T2 T3
20350
20351 1/1 assign cmd_info_3_dummy_size_3_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20352
20353 1/1 assign cmd_info_3_dummy_en_3_wd = reg_wdata[15];
Tests: T1 T2 T3
20354
20355 1/1 assign cmd_info_3_payload_en_3_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20356
20357 1/1 assign cmd_info_3_payload_dir_3_wd = reg_wdata[20];
Tests: T1 T2 T3
20358
20359 1/1 assign cmd_info_3_payload_swap_en_3_wd = reg_wdata[21];
Tests: T1 T2 T3
20360
20361 1/1 assign cmd_info_3_read_pipeline_mode_3_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20362
20363 1/1 assign cmd_info_3_upload_3_wd = reg_wdata[24];
Tests: T1 T2 T3
20364
20365 1/1 assign cmd_info_3_busy_3_wd = reg_wdata[25];
Tests: T1 T2 T3
20366
20367 1/1 assign cmd_info_3_valid_3_wd = reg_wdata[31];
Tests: T1 T2 T3
20368 1/1 assign cmd_info_4_we = addr_hit[35] & reg_we & !reg_error;
Tests: T1 T2 T4
20369
20370 1/1 assign cmd_info_4_opcode_4_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20371
20372 1/1 assign cmd_info_4_addr_mode_4_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20373
20374 1/1 assign cmd_info_4_addr_swap_en_4_wd = reg_wdata[10];
Tests: T1 T2 T3
20375
20376 1/1 assign cmd_info_4_mbyte_en_4_wd = reg_wdata[11];
Tests: T1 T2 T3
20377
20378 1/1 assign cmd_info_4_dummy_size_4_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20379
20380 1/1 assign cmd_info_4_dummy_en_4_wd = reg_wdata[15];
Tests: T1 T2 T3
20381
20382 1/1 assign cmd_info_4_payload_en_4_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20383
20384 1/1 assign cmd_info_4_payload_dir_4_wd = reg_wdata[20];
Tests: T1 T2 T3
20385
20386 1/1 assign cmd_info_4_payload_swap_en_4_wd = reg_wdata[21];
Tests: T1 T2 T3
20387
20388 1/1 assign cmd_info_4_read_pipeline_mode_4_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20389
20390 1/1 assign cmd_info_4_upload_4_wd = reg_wdata[24];
Tests: T1 T2 T3
20391
20392 1/1 assign cmd_info_4_busy_4_wd = reg_wdata[25];
Tests: T1 T2 T3
20393
20394 1/1 assign cmd_info_4_valid_4_wd = reg_wdata[31];
Tests: T1 T2 T3
20395 1/1 assign cmd_info_5_we = addr_hit[36] & reg_we & !reg_error;
Tests: T1 T2 T4
20396
20397 1/1 assign cmd_info_5_opcode_5_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20398
20399 1/1 assign cmd_info_5_addr_mode_5_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20400
20401 1/1 assign cmd_info_5_addr_swap_en_5_wd = reg_wdata[10];
Tests: T1 T2 T3
20402
20403 1/1 assign cmd_info_5_mbyte_en_5_wd = reg_wdata[11];
Tests: T1 T2 T3
20404
20405 1/1 assign cmd_info_5_dummy_size_5_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20406
20407 1/1 assign cmd_info_5_dummy_en_5_wd = reg_wdata[15];
Tests: T1 T2 T3
20408
20409 1/1 assign cmd_info_5_payload_en_5_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20410
20411 1/1 assign cmd_info_5_payload_dir_5_wd = reg_wdata[20];
Tests: T1 T2 T3
20412
20413 1/1 assign cmd_info_5_payload_swap_en_5_wd = reg_wdata[21];
Tests: T1 T2 T3
20414
20415 1/1 assign cmd_info_5_read_pipeline_mode_5_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20416
20417 1/1 assign cmd_info_5_upload_5_wd = reg_wdata[24];
Tests: T1 T2 T3
20418
20419 1/1 assign cmd_info_5_busy_5_wd = reg_wdata[25];
Tests: T1 T2 T3
20420
20421 1/1 assign cmd_info_5_valid_5_wd = reg_wdata[31];
Tests: T1 T2 T3
20422 1/1 assign cmd_info_6_we = addr_hit[37] & reg_we & !reg_error;
Tests: T1 T2 T4
20423
20424 1/1 assign cmd_info_6_opcode_6_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20425
20426 1/1 assign cmd_info_6_addr_mode_6_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20427
20428 1/1 assign cmd_info_6_addr_swap_en_6_wd = reg_wdata[10];
Tests: T1 T2 T3
20429
20430 1/1 assign cmd_info_6_mbyte_en_6_wd = reg_wdata[11];
Tests: T1 T2 T3
20431
20432 1/1 assign cmd_info_6_dummy_size_6_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20433
20434 1/1 assign cmd_info_6_dummy_en_6_wd = reg_wdata[15];
Tests: T1 T2 T3
20435
20436 1/1 assign cmd_info_6_payload_en_6_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20437
20438 1/1 assign cmd_info_6_payload_dir_6_wd = reg_wdata[20];
Tests: T1 T2 T3
20439
20440 1/1 assign cmd_info_6_payload_swap_en_6_wd = reg_wdata[21];
Tests: T1 T2 T3
20441
20442 1/1 assign cmd_info_6_read_pipeline_mode_6_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20443
20444 1/1 assign cmd_info_6_upload_6_wd = reg_wdata[24];
Tests: T1 T2 T3
20445
20446 1/1 assign cmd_info_6_busy_6_wd = reg_wdata[25];
Tests: T1 T2 T3
20447
20448 1/1 assign cmd_info_6_valid_6_wd = reg_wdata[31];
Tests: T1 T2 T3
20449 1/1 assign cmd_info_7_we = addr_hit[38] & reg_we & !reg_error;
Tests: T1 T2 T4
20450
20451 1/1 assign cmd_info_7_opcode_7_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20452
20453 1/1 assign cmd_info_7_addr_mode_7_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20454
20455 1/1 assign cmd_info_7_addr_swap_en_7_wd = reg_wdata[10];
Tests: T1 T2 T3
20456
20457 1/1 assign cmd_info_7_mbyte_en_7_wd = reg_wdata[11];
Tests: T1 T2 T3
20458
20459 1/1 assign cmd_info_7_dummy_size_7_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20460
20461 1/1 assign cmd_info_7_dummy_en_7_wd = reg_wdata[15];
Tests: T1 T2 T3
20462
20463 1/1 assign cmd_info_7_payload_en_7_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20464
20465 1/1 assign cmd_info_7_payload_dir_7_wd = reg_wdata[20];
Tests: T1 T2 T3
20466
20467 1/1 assign cmd_info_7_payload_swap_en_7_wd = reg_wdata[21];
Tests: T1 T2 T3
20468
20469 1/1 assign cmd_info_7_read_pipeline_mode_7_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20470
20471 1/1 assign cmd_info_7_upload_7_wd = reg_wdata[24];
Tests: T1 T2 T3
20472
20473 1/1 assign cmd_info_7_busy_7_wd = reg_wdata[25];
Tests: T1 T2 T3
20474
20475 1/1 assign cmd_info_7_valid_7_wd = reg_wdata[31];
Tests: T1 T2 T3
20476 1/1 assign cmd_info_8_we = addr_hit[39] & reg_we & !reg_error;
Tests: T1 T2 T3
20477
20478 1/1 assign cmd_info_8_opcode_8_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20479
20480 1/1 assign cmd_info_8_addr_mode_8_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20481
20482 1/1 assign cmd_info_8_addr_swap_en_8_wd = reg_wdata[10];
Tests: T1 T2 T3
20483
20484 1/1 assign cmd_info_8_mbyte_en_8_wd = reg_wdata[11];
Tests: T1 T2 T3
20485
20486 1/1 assign cmd_info_8_dummy_size_8_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20487
20488 1/1 assign cmd_info_8_dummy_en_8_wd = reg_wdata[15];
Tests: T1 T2 T3
20489
20490 1/1 assign cmd_info_8_payload_en_8_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20491
20492 1/1 assign cmd_info_8_payload_dir_8_wd = reg_wdata[20];
Tests: T1 T2 T3
20493
20494 1/1 assign cmd_info_8_payload_swap_en_8_wd = reg_wdata[21];
Tests: T1 T2 T3
20495
20496 1/1 assign cmd_info_8_read_pipeline_mode_8_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20497
20498 1/1 assign cmd_info_8_upload_8_wd = reg_wdata[24];
Tests: T1 T2 T3
20499
20500 1/1 assign cmd_info_8_busy_8_wd = reg_wdata[25];
Tests: T1 T2 T3
20501
20502 1/1 assign cmd_info_8_valid_8_wd = reg_wdata[31];
Tests: T1 T2 T3
20503 1/1 assign cmd_info_9_we = addr_hit[40] & reg_we & !reg_error;
Tests: T1 T2 T4
20504
20505 1/1 assign cmd_info_9_opcode_9_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20506
20507 1/1 assign cmd_info_9_addr_mode_9_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20508
20509 1/1 assign cmd_info_9_addr_swap_en_9_wd = reg_wdata[10];
Tests: T1 T2 T3
20510
20511 1/1 assign cmd_info_9_mbyte_en_9_wd = reg_wdata[11];
Tests: T1 T2 T3
20512
20513 1/1 assign cmd_info_9_dummy_size_9_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20514
20515 1/1 assign cmd_info_9_dummy_en_9_wd = reg_wdata[15];
Tests: T1 T2 T3
20516
20517 1/1 assign cmd_info_9_payload_en_9_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20518
20519 1/1 assign cmd_info_9_payload_dir_9_wd = reg_wdata[20];
Tests: T1 T2 T3
20520
20521 1/1 assign cmd_info_9_payload_swap_en_9_wd = reg_wdata[21];
Tests: T1 T2 T3
20522
20523 1/1 assign cmd_info_9_read_pipeline_mode_9_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20524
20525 1/1 assign cmd_info_9_upload_9_wd = reg_wdata[24];
Tests: T1 T2 T3
20526
20527 1/1 assign cmd_info_9_busy_9_wd = reg_wdata[25];
Tests: T1 T2 T3
20528
20529 1/1 assign cmd_info_9_valid_9_wd = reg_wdata[31];
Tests: T1 T2 T3
20530 1/1 assign cmd_info_10_we = addr_hit[41] & reg_we & !reg_error;
Tests: T1 T2 T4
20531
20532 1/1 assign cmd_info_10_opcode_10_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20533
20534 1/1 assign cmd_info_10_addr_mode_10_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20535
20536 1/1 assign cmd_info_10_addr_swap_en_10_wd = reg_wdata[10];
Tests: T1 T2 T3
20537
20538 1/1 assign cmd_info_10_mbyte_en_10_wd = reg_wdata[11];
Tests: T1 T2 T3
20539
20540 1/1 assign cmd_info_10_dummy_size_10_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20541
20542 1/1 assign cmd_info_10_dummy_en_10_wd = reg_wdata[15];
Tests: T1 T2 T3
20543
20544 1/1 assign cmd_info_10_payload_en_10_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20545
20546 1/1 assign cmd_info_10_payload_dir_10_wd = reg_wdata[20];
Tests: T1 T2 T3
20547
20548 1/1 assign cmd_info_10_payload_swap_en_10_wd = reg_wdata[21];
Tests: T1 T2 T3
20549
20550 1/1 assign cmd_info_10_read_pipeline_mode_10_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20551
20552 1/1 assign cmd_info_10_upload_10_wd = reg_wdata[24];
Tests: T1 T2 T3
20553
20554 1/1 assign cmd_info_10_busy_10_wd = reg_wdata[25];
Tests: T1 T2 T3
20555
20556 1/1 assign cmd_info_10_valid_10_wd = reg_wdata[31];
Tests: T1 T2 T3
20557 1/1 assign cmd_info_11_we = addr_hit[42] & reg_we & !reg_error;
Tests: T1 T2 T4
20558
20559 1/1 assign cmd_info_11_opcode_11_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20560
20561 1/1 assign cmd_info_11_addr_mode_11_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20562
20563 1/1 assign cmd_info_11_addr_swap_en_11_wd = reg_wdata[10];
Tests: T1 T2 T3
20564
20565 1/1 assign cmd_info_11_mbyte_en_11_wd = reg_wdata[11];
Tests: T1 T2 T3
20566
20567 1/1 assign cmd_info_11_dummy_size_11_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20568
20569 1/1 assign cmd_info_11_dummy_en_11_wd = reg_wdata[15];
Tests: T1 T2 T3
20570
20571 1/1 assign cmd_info_11_payload_en_11_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20572
20573 1/1 assign cmd_info_11_payload_dir_11_wd = reg_wdata[20];
Tests: T1 T2 T3
20574
20575 1/1 assign cmd_info_11_payload_swap_en_11_wd = reg_wdata[21];
Tests: T1 T2 T3
20576
20577 1/1 assign cmd_info_11_read_pipeline_mode_11_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20578
20579 1/1 assign cmd_info_11_upload_11_wd = reg_wdata[24];
Tests: T1 T2 T3
20580
20581 1/1 assign cmd_info_11_busy_11_wd = reg_wdata[25];
Tests: T1 T2 T3
20582
20583 1/1 assign cmd_info_11_valid_11_wd = reg_wdata[31];
Tests: T1 T2 T3
20584 1/1 assign cmd_info_12_we = addr_hit[43] & reg_we & !reg_error;
Tests: T1 T2 T4
20585
20586 1/1 assign cmd_info_12_opcode_12_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20587
20588 1/1 assign cmd_info_12_addr_mode_12_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20589
20590 1/1 assign cmd_info_12_addr_swap_en_12_wd = reg_wdata[10];
Tests: T1 T2 T3
20591
20592 1/1 assign cmd_info_12_mbyte_en_12_wd = reg_wdata[11];
Tests: T1 T2 T3
20593
20594 1/1 assign cmd_info_12_dummy_size_12_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20595
20596 1/1 assign cmd_info_12_dummy_en_12_wd = reg_wdata[15];
Tests: T1 T2 T3
20597
20598 1/1 assign cmd_info_12_payload_en_12_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20599
20600 1/1 assign cmd_info_12_payload_dir_12_wd = reg_wdata[20];
Tests: T1 T2 T3
20601
20602 1/1 assign cmd_info_12_payload_swap_en_12_wd = reg_wdata[21];
Tests: T1 T2 T3
20603
20604 1/1 assign cmd_info_12_read_pipeline_mode_12_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20605
20606 1/1 assign cmd_info_12_upload_12_wd = reg_wdata[24];
Tests: T1 T2 T3
20607
20608 1/1 assign cmd_info_12_busy_12_wd = reg_wdata[25];
Tests: T1 T2 T3
20609
20610 1/1 assign cmd_info_12_valid_12_wd = reg_wdata[31];
Tests: T1 T2 T3
20611 1/1 assign cmd_info_13_we = addr_hit[44] & reg_we & !reg_error;
Tests: T1 T2 T4
20612
20613 1/1 assign cmd_info_13_opcode_13_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20614
20615 1/1 assign cmd_info_13_addr_mode_13_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20616
20617 1/1 assign cmd_info_13_addr_swap_en_13_wd = reg_wdata[10];
Tests: T1 T2 T3
20618
20619 1/1 assign cmd_info_13_mbyte_en_13_wd = reg_wdata[11];
Tests: T1 T2 T3
20620
20621 1/1 assign cmd_info_13_dummy_size_13_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20622
20623 1/1 assign cmd_info_13_dummy_en_13_wd = reg_wdata[15];
Tests: T1 T2 T3
20624
20625 1/1 assign cmd_info_13_payload_en_13_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20626
20627 1/1 assign cmd_info_13_payload_dir_13_wd = reg_wdata[20];
Tests: T1 T2 T3
20628
20629 1/1 assign cmd_info_13_payload_swap_en_13_wd = reg_wdata[21];
Tests: T1 T2 T3
20630
20631 1/1 assign cmd_info_13_read_pipeline_mode_13_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20632
20633 1/1 assign cmd_info_13_upload_13_wd = reg_wdata[24];
Tests: T1 T2 T3
20634
20635 1/1 assign cmd_info_13_busy_13_wd = reg_wdata[25];
Tests: T1 T2 T3
20636
20637 1/1 assign cmd_info_13_valid_13_wd = reg_wdata[31];
Tests: T1 T2 T3
20638 1/1 assign cmd_info_14_we = addr_hit[45] & reg_we & !reg_error;
Tests: T1 T2 T4
20639
20640 1/1 assign cmd_info_14_opcode_14_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20641
20642 1/1 assign cmd_info_14_addr_mode_14_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20643
20644 1/1 assign cmd_info_14_addr_swap_en_14_wd = reg_wdata[10];
Tests: T1 T2 T3
20645
20646 1/1 assign cmd_info_14_mbyte_en_14_wd = reg_wdata[11];
Tests: T1 T2 T3
20647
20648 1/1 assign cmd_info_14_dummy_size_14_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20649
20650 1/1 assign cmd_info_14_dummy_en_14_wd = reg_wdata[15];
Tests: T1 T2 T3
20651
20652 1/1 assign cmd_info_14_payload_en_14_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20653
20654 1/1 assign cmd_info_14_payload_dir_14_wd = reg_wdata[20];
Tests: T1 T2 T3
20655
20656 1/1 assign cmd_info_14_payload_swap_en_14_wd = reg_wdata[21];
Tests: T1 T2 T3
20657
20658 1/1 assign cmd_info_14_read_pipeline_mode_14_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20659
20660 1/1 assign cmd_info_14_upload_14_wd = reg_wdata[24];
Tests: T1 T2 T3
20661
20662 1/1 assign cmd_info_14_busy_14_wd = reg_wdata[25];
Tests: T1 T2 T3
20663
20664 1/1 assign cmd_info_14_valid_14_wd = reg_wdata[31];
Tests: T1 T2 T3
20665 1/1 assign cmd_info_15_we = addr_hit[46] & reg_we & !reg_error;
Tests: T1 T2 T4
20666
20667 1/1 assign cmd_info_15_opcode_15_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20668
20669 1/1 assign cmd_info_15_addr_mode_15_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20670
20671 1/1 assign cmd_info_15_addr_swap_en_15_wd = reg_wdata[10];
Tests: T1 T2 T3
20672
20673 1/1 assign cmd_info_15_mbyte_en_15_wd = reg_wdata[11];
Tests: T1 T2 T3
20674
20675 1/1 assign cmd_info_15_dummy_size_15_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20676
20677 1/1 assign cmd_info_15_dummy_en_15_wd = reg_wdata[15];
Tests: T1 T2 T3
20678
20679 1/1 assign cmd_info_15_payload_en_15_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20680
20681 1/1 assign cmd_info_15_payload_dir_15_wd = reg_wdata[20];
Tests: T1 T2 T3
20682
20683 1/1 assign cmd_info_15_payload_swap_en_15_wd = reg_wdata[21];
Tests: T1 T2 T3
20684
20685 1/1 assign cmd_info_15_read_pipeline_mode_15_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20686
20687 1/1 assign cmd_info_15_upload_15_wd = reg_wdata[24];
Tests: T1 T2 T3
20688
20689 1/1 assign cmd_info_15_busy_15_wd = reg_wdata[25];
Tests: T1 T2 T3
20690
20691 1/1 assign cmd_info_15_valid_15_wd = reg_wdata[31];
Tests: T1 T2 T3
20692 1/1 assign cmd_info_16_we = addr_hit[47] & reg_we & !reg_error;
Tests: T1 T2 T4
20693
20694 1/1 assign cmd_info_16_opcode_16_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20695
20696 1/1 assign cmd_info_16_addr_mode_16_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20697
20698 1/1 assign cmd_info_16_addr_swap_en_16_wd = reg_wdata[10];
Tests: T1 T2 T3
20699
20700 1/1 assign cmd_info_16_mbyte_en_16_wd = reg_wdata[11];
Tests: T1 T2 T3
20701
20702 1/1 assign cmd_info_16_dummy_size_16_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20703
20704 1/1 assign cmd_info_16_dummy_en_16_wd = reg_wdata[15];
Tests: T1 T2 T3
20705
20706 1/1 assign cmd_info_16_payload_en_16_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20707
20708 1/1 assign cmd_info_16_payload_dir_16_wd = reg_wdata[20];
Tests: T1 T2 T3
20709
20710 1/1 assign cmd_info_16_payload_swap_en_16_wd = reg_wdata[21];
Tests: T1 T2 T3
20711
20712 1/1 assign cmd_info_16_read_pipeline_mode_16_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20713
20714 1/1 assign cmd_info_16_upload_16_wd = reg_wdata[24];
Tests: T1 T2 T3
20715
20716 1/1 assign cmd_info_16_busy_16_wd = reg_wdata[25];
Tests: T1 T2 T3
20717
20718 1/1 assign cmd_info_16_valid_16_wd = reg_wdata[31];
Tests: T1 T2 T3
20719 1/1 assign cmd_info_17_we = addr_hit[48] & reg_we & !reg_error;
Tests: T1 T2 T4
20720
20721 1/1 assign cmd_info_17_opcode_17_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20722
20723 1/1 assign cmd_info_17_addr_mode_17_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20724
20725 1/1 assign cmd_info_17_addr_swap_en_17_wd = reg_wdata[10];
Tests: T1 T2 T3
20726
20727 1/1 assign cmd_info_17_mbyte_en_17_wd = reg_wdata[11];
Tests: T1 T2 T3
20728
20729 1/1 assign cmd_info_17_dummy_size_17_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20730
20731 1/1 assign cmd_info_17_dummy_en_17_wd = reg_wdata[15];
Tests: T1 T2 T3
20732
20733 1/1 assign cmd_info_17_payload_en_17_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20734
20735 1/1 assign cmd_info_17_payload_dir_17_wd = reg_wdata[20];
Tests: T1 T2 T3
20736
20737 1/1 assign cmd_info_17_payload_swap_en_17_wd = reg_wdata[21];
Tests: T1 T2 T3
20738
20739 1/1 assign cmd_info_17_read_pipeline_mode_17_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20740
20741 1/1 assign cmd_info_17_upload_17_wd = reg_wdata[24];
Tests: T1 T2 T3
20742
20743 1/1 assign cmd_info_17_busy_17_wd = reg_wdata[25];
Tests: T1 T2 T3
20744
20745 1/1 assign cmd_info_17_valid_17_wd = reg_wdata[31];
Tests: T1 T2 T3
20746 1/1 assign cmd_info_18_we = addr_hit[49] & reg_we & !reg_error;
Tests: T1 T2 T4
20747
20748 1/1 assign cmd_info_18_opcode_18_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20749
20750 1/1 assign cmd_info_18_addr_mode_18_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20751
20752 1/1 assign cmd_info_18_addr_swap_en_18_wd = reg_wdata[10];
Tests: T1 T2 T3
20753
20754 1/1 assign cmd_info_18_mbyte_en_18_wd = reg_wdata[11];
Tests: T1 T2 T3
20755
20756 1/1 assign cmd_info_18_dummy_size_18_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20757
20758 1/1 assign cmd_info_18_dummy_en_18_wd = reg_wdata[15];
Tests: T1 T2 T3
20759
20760 1/1 assign cmd_info_18_payload_en_18_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20761
20762 1/1 assign cmd_info_18_payload_dir_18_wd = reg_wdata[20];
Tests: T1 T2 T3
20763
20764 1/1 assign cmd_info_18_payload_swap_en_18_wd = reg_wdata[21];
Tests: T1 T2 T3
20765
20766 1/1 assign cmd_info_18_read_pipeline_mode_18_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20767
20768 1/1 assign cmd_info_18_upload_18_wd = reg_wdata[24];
Tests: T1 T2 T3
20769
20770 1/1 assign cmd_info_18_busy_18_wd = reg_wdata[25];
Tests: T1 T2 T3
20771
20772 1/1 assign cmd_info_18_valid_18_wd = reg_wdata[31];
Tests: T1 T2 T3
20773 1/1 assign cmd_info_19_we = addr_hit[50] & reg_we & !reg_error;
Tests: T1 T2 T4
20774
20775 1/1 assign cmd_info_19_opcode_19_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20776
20777 1/1 assign cmd_info_19_addr_mode_19_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20778
20779 1/1 assign cmd_info_19_addr_swap_en_19_wd = reg_wdata[10];
Tests: T1 T2 T3
20780
20781 1/1 assign cmd_info_19_mbyte_en_19_wd = reg_wdata[11];
Tests: T1 T2 T3
20782
20783 1/1 assign cmd_info_19_dummy_size_19_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20784
20785 1/1 assign cmd_info_19_dummy_en_19_wd = reg_wdata[15];
Tests: T1 T2 T3
20786
20787 1/1 assign cmd_info_19_payload_en_19_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20788
20789 1/1 assign cmd_info_19_payload_dir_19_wd = reg_wdata[20];
Tests: T1 T2 T3
20790
20791 1/1 assign cmd_info_19_payload_swap_en_19_wd = reg_wdata[21];
Tests: T1 T2 T3
20792
20793 1/1 assign cmd_info_19_read_pipeline_mode_19_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20794
20795 1/1 assign cmd_info_19_upload_19_wd = reg_wdata[24];
Tests: T1 T2 T3
20796
20797 1/1 assign cmd_info_19_busy_19_wd = reg_wdata[25];
Tests: T1 T2 T3
20798
20799 1/1 assign cmd_info_19_valid_19_wd = reg_wdata[31];
Tests: T1 T2 T3
20800 1/1 assign cmd_info_20_we = addr_hit[51] & reg_we & !reg_error;
Tests: T1 T2 T4
20801
20802 1/1 assign cmd_info_20_opcode_20_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20803
20804 1/1 assign cmd_info_20_addr_mode_20_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20805
20806 1/1 assign cmd_info_20_addr_swap_en_20_wd = reg_wdata[10];
Tests: T1 T2 T3
20807
20808 1/1 assign cmd_info_20_mbyte_en_20_wd = reg_wdata[11];
Tests: T1 T2 T3
20809
20810 1/1 assign cmd_info_20_dummy_size_20_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20811
20812 1/1 assign cmd_info_20_dummy_en_20_wd = reg_wdata[15];
Tests: T1 T2 T3
20813
20814 1/1 assign cmd_info_20_payload_en_20_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20815
20816 1/1 assign cmd_info_20_payload_dir_20_wd = reg_wdata[20];
Tests: T1 T2 T3
20817
20818 1/1 assign cmd_info_20_payload_swap_en_20_wd = reg_wdata[21];
Tests: T1 T2 T3
20819
20820 1/1 assign cmd_info_20_read_pipeline_mode_20_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20821
20822 1/1 assign cmd_info_20_upload_20_wd = reg_wdata[24];
Tests: T1 T2 T3
20823
20824 1/1 assign cmd_info_20_busy_20_wd = reg_wdata[25];
Tests: T1 T2 T3
20825
20826 1/1 assign cmd_info_20_valid_20_wd = reg_wdata[31];
Tests: T1 T2 T3
20827 1/1 assign cmd_info_21_we = addr_hit[52] & reg_we & !reg_error;
Tests: T1 T2 T4
20828
20829 1/1 assign cmd_info_21_opcode_21_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20830
20831 1/1 assign cmd_info_21_addr_mode_21_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20832
20833 1/1 assign cmd_info_21_addr_swap_en_21_wd = reg_wdata[10];
Tests: T1 T2 T3
20834
20835 1/1 assign cmd_info_21_mbyte_en_21_wd = reg_wdata[11];
Tests: T1 T2 T3
20836
20837 1/1 assign cmd_info_21_dummy_size_21_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20838
20839 1/1 assign cmd_info_21_dummy_en_21_wd = reg_wdata[15];
Tests: T1 T2 T3
20840
20841 1/1 assign cmd_info_21_payload_en_21_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20842
20843 1/1 assign cmd_info_21_payload_dir_21_wd = reg_wdata[20];
Tests: T1 T2 T3
20844
20845 1/1 assign cmd_info_21_payload_swap_en_21_wd = reg_wdata[21];
Tests: T1 T2 T3
20846
20847 1/1 assign cmd_info_21_read_pipeline_mode_21_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20848
20849 1/1 assign cmd_info_21_upload_21_wd = reg_wdata[24];
Tests: T1 T2 T3
20850
20851 1/1 assign cmd_info_21_busy_21_wd = reg_wdata[25];
Tests: T1 T2 T3
20852
20853 1/1 assign cmd_info_21_valid_21_wd = reg_wdata[31];
Tests: T1 T2 T3
20854 1/1 assign cmd_info_22_we = addr_hit[53] & reg_we & !reg_error;
Tests: T1 T2 T4
20855
20856 1/1 assign cmd_info_22_opcode_22_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20857
20858 1/1 assign cmd_info_22_addr_mode_22_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20859
20860 1/1 assign cmd_info_22_addr_swap_en_22_wd = reg_wdata[10];
Tests: T1 T2 T3
20861
20862 1/1 assign cmd_info_22_mbyte_en_22_wd = reg_wdata[11];
Tests: T1 T2 T3
20863
20864 1/1 assign cmd_info_22_dummy_size_22_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20865
20866 1/1 assign cmd_info_22_dummy_en_22_wd = reg_wdata[15];
Tests: T1 T2 T3
20867
20868 1/1 assign cmd_info_22_payload_en_22_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20869
20870 1/1 assign cmd_info_22_payload_dir_22_wd = reg_wdata[20];
Tests: T1 T2 T3
20871
20872 1/1 assign cmd_info_22_payload_swap_en_22_wd = reg_wdata[21];
Tests: T1 T2 T3
20873
20874 1/1 assign cmd_info_22_read_pipeline_mode_22_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20875
20876 1/1 assign cmd_info_22_upload_22_wd = reg_wdata[24];
Tests: T1 T2 T3
20877
20878 1/1 assign cmd_info_22_busy_22_wd = reg_wdata[25];
Tests: T1 T2 T3
20879
20880 1/1 assign cmd_info_22_valid_22_wd = reg_wdata[31];
Tests: T1 T2 T3
20881 1/1 assign cmd_info_23_we = addr_hit[54] & reg_we & !reg_error;
Tests: T1 T2 T4
20882
20883 1/1 assign cmd_info_23_opcode_23_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20884
20885 1/1 assign cmd_info_23_addr_mode_23_wd = reg_wdata[9:8];
Tests: T1 T2 T3
20886
20887 1/1 assign cmd_info_23_addr_swap_en_23_wd = reg_wdata[10];
Tests: T1 T2 T3
20888
20889 1/1 assign cmd_info_23_mbyte_en_23_wd = reg_wdata[11];
Tests: T1 T2 T3
20890
20891 1/1 assign cmd_info_23_dummy_size_23_wd = reg_wdata[14:12];
Tests: T1 T2 T3
20892
20893 1/1 assign cmd_info_23_dummy_en_23_wd = reg_wdata[15];
Tests: T1 T2 T3
20894
20895 1/1 assign cmd_info_23_payload_en_23_wd = reg_wdata[19:16];
Tests: T1 T2 T3
20896
20897 1/1 assign cmd_info_23_payload_dir_23_wd = reg_wdata[20];
Tests: T1 T2 T3
20898
20899 1/1 assign cmd_info_23_payload_swap_en_23_wd = reg_wdata[21];
Tests: T1 T2 T3
20900
20901 1/1 assign cmd_info_23_read_pipeline_mode_23_wd = reg_wdata[23:22];
Tests: T1 T2 T3
20902
20903 1/1 assign cmd_info_23_upload_23_wd = reg_wdata[24];
Tests: T1 T2 T3
20904
20905 1/1 assign cmd_info_23_busy_23_wd = reg_wdata[25];
Tests: T1 T2 T3
20906
20907 1/1 assign cmd_info_23_valid_23_wd = reg_wdata[31];
Tests: T1 T2 T3
20908 1/1 assign cmd_info_en4b_we = addr_hit[55] & reg_we & !reg_error;
Tests: T1 T2 T4
20909
20910 1/1 assign cmd_info_en4b_opcode_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20911
20912 1/1 assign cmd_info_en4b_valid_wd = reg_wdata[31];
Tests: T1 T2 T3
20913 1/1 assign cmd_info_ex4b_we = addr_hit[56] & reg_we & !reg_error;
Tests: T1 T2 T4
20914
20915 1/1 assign cmd_info_ex4b_opcode_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20916
20917 1/1 assign cmd_info_ex4b_valid_wd = reg_wdata[31];
Tests: T1 T2 T3
20918 1/1 assign cmd_info_wren_we = addr_hit[57] & reg_we & !reg_error;
Tests: T1 T2 T4
20919
20920 1/1 assign cmd_info_wren_opcode_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20921
20922 1/1 assign cmd_info_wren_valid_wd = reg_wdata[31];
Tests: T1 T2 T3
20923 1/1 assign cmd_info_wrdi_we = addr_hit[58] & reg_we & !reg_error;
Tests: T1 T2 T4
20924
20925 1/1 assign cmd_info_wrdi_opcode_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20926
20927 1/1 assign cmd_info_wrdi_valid_wd = reg_wdata[31];
Tests: T1 T2 T3
20928 1/1 assign tpm_cfg_we = addr_hit[60] & reg_we & !reg_error;
Tests: T1 T2 T4
20929
20930 1/1 assign tpm_cfg_en_wd = reg_wdata[0];
Tests: T1 T2 T3
20931
20932 1/1 assign tpm_cfg_tpm_mode_wd = reg_wdata[1];
Tests: T1 T2 T3
20933
20934 1/1 assign tpm_cfg_hw_reg_dis_wd = reg_wdata[2];
Tests: T1 T2 T3
20935
20936 1/1 assign tpm_cfg_tpm_reg_chk_dis_wd = reg_wdata[3];
Tests: T1 T2 T3
20937
20938 1/1 assign tpm_cfg_invalid_locality_wd = reg_wdata[4];
Tests: T1 T2 T3
20939 1/1 assign tpm_status_re = addr_hit[61] & reg_re & !reg_error;
Tests: T1 T2 T3
20940 1/1 assign tpm_status_we = addr_hit[61] & reg_we & !reg_error;
Tests: T1 T2 T4
20941
20942 1/1 assign tpm_status_wrfifo_pending_wd = reg_wdata[1];
Tests: T1 T2 T3
20943 1/1 assign tpm_access_0_we = addr_hit[62] & reg_we & !reg_error;
Tests: T1 T2 T4
20944
20945 1/1 assign tpm_access_0_access_0_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20946
20947 1/1 assign tpm_access_0_access_1_wd = reg_wdata[15:8];
Tests: T1 T2 T3
20948
20949 1/1 assign tpm_access_0_access_2_wd = reg_wdata[23:16];
Tests: T1 T2 T3
20950
20951 1/1 assign tpm_access_0_access_3_wd = reg_wdata[31:24];
Tests: T1 T2 T3
20952 1/1 assign tpm_access_1_we = addr_hit[63] & reg_we & !reg_error;
Tests: T1 T2 T4
20953
20954 1/1 assign tpm_access_1_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20955 1/1 assign tpm_sts_we = addr_hit[64] & reg_we & !reg_error;
Tests: T1 T2 T4
20956
20957 1/1 assign tpm_sts_wd = reg_wdata[31:0];
Tests: T1 T2 T3
20958 1/1 assign tpm_intf_capability_we = addr_hit[65] & reg_we & !reg_error;
Tests: T1 T2 T4
20959
20960 1/1 assign tpm_intf_capability_wd = reg_wdata[31:0];
Tests: T1 T2 T3
20961 1/1 assign tpm_int_enable_we = addr_hit[66] & reg_we & !reg_error;
Tests: T1 T2 T4
20962
20963 1/1 assign tpm_int_enable_wd = reg_wdata[31:0];
Tests: T1 T2 T3
20964 1/1 assign tpm_int_vector_we = addr_hit[67] & reg_we & !reg_error;
Tests: T1 T2 T4
20965
20966 1/1 assign tpm_int_vector_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20967 1/1 assign tpm_int_status_we = addr_hit[68] & reg_we & !reg_error;
Tests: T1 T2 T4
20968
20969 1/1 assign tpm_int_status_wd = reg_wdata[31:0];
Tests: T1 T2 T3
20970 1/1 assign tpm_did_vid_we = addr_hit[69] & reg_we & !reg_error;
Tests: T1 T2 T3
20971
20972 1/1 assign tpm_did_vid_vid_wd = reg_wdata[15:0];
Tests: T1 T2 T3
20973
20974 1/1 assign tpm_did_vid_did_wd = reg_wdata[31:16];
Tests: T1 T2 T3
20975 1/1 assign tpm_rid_we = addr_hit[70] & reg_we & !reg_error;
Tests: T1 T2 T4
20976
20977 1/1 assign tpm_rid_wd = reg_wdata[7:0];
Tests: T1 T2 T3
20978 1/1 assign tpm_cmd_addr_re = addr_hit[71] & reg_re & !reg_error;
Tests: T1 T2 T3
20979 1/1 assign tpm_read_fifo_we = addr_hit[72] & reg_we & !reg_error;
Tests: T1 T2 T4
20980
20981 1/1 assign tpm_read_fifo_wd = reg_wdata[31:0];
Tests: T1 T2 T3
20982
20983 // Assign write-enables to checker logic vector.
20984 always_comb begin
20985 1/1 reg_we_check = '0;
Tests: T4 T5 T6
20986 1/1 reg_we_check[0] = intr_state_we;
Tests: T4 T5 T6
20987 1/1 reg_we_check[1] = intr_enable_we;
Tests: T4 T5 T6
20988 1/1 reg_we_check[2] = intr_test_we;
Tests: T4 T5 T6
20989 1/1 reg_we_check[3] = alert_test_we;
Tests: T4 T5 T6
20990 1/1 reg_we_check[4] = control_we;
Tests: T4 T5 T6
20991 1/1 reg_we_check[5] = cfg_we;
Tests: T4 T5 T6
20992 1/1 reg_we_check[6] = 1'b0;
Tests: T4 T5 T6
20993 1/1 reg_we_check[7] = intercept_en_we;
Tests: T4 T5 T6
20994 1/1 reg_we_check[8] = addr_mode_we;
Tests: T4 T5 T6
20995 1/1 reg_we_check[9] = 1'b0;
Tests: T4 T5 T6
20996 1/1 reg_we_check[10] = flash_status_we;
Tests: T4 T5 T6
20997 1/1 reg_we_check[11] = jedec_cc_we;
Tests: T4 T5 T6
20998 1/1 reg_we_check[12] = jedec_id_we;
Tests: T4 T5 T6
20999 1/1 reg_we_check[13] = read_threshold_we;
Tests: T4 T5 T6
21000 1/1 reg_we_check[14] = mailbox_addr_we;
Tests: T4 T5 T6
21001 1/1 reg_we_check[15] = 1'b0;
Tests: T4 T5 T6
21002 1/1 reg_we_check[16] = 1'b0;
Tests: T4 T5 T6
21003 1/1 reg_we_check[17] = 1'b0;
Tests: T4 T5 T6
21004 1/1 reg_we_check[18] = 1'b0;
Tests: T4 T5 T6
21005 1/1 reg_we_check[19] = cmd_filter_0_we;
Tests: T4 T5 T6
21006 1/1 reg_we_check[20] = cmd_filter_1_we;
Tests: T4 T5 T6
21007 1/1 reg_we_check[21] = cmd_filter_2_we;
Tests: T4 T5 T6
21008 1/1 reg_we_check[22] = cmd_filter_3_we;
Tests: T4 T5 T6
21009 1/1 reg_we_check[23] = cmd_filter_4_we;
Tests: T4 T5 T6
21010 1/1 reg_we_check[24] = cmd_filter_5_we;
Tests: T4 T5 T6
21011 1/1 reg_we_check[25] = cmd_filter_6_we;
Tests: T4 T5 T6
21012 1/1 reg_we_check[26] = cmd_filter_7_we;
Tests: T4 T5 T6
21013 1/1 reg_we_check[27] = addr_swap_mask_we;
Tests: T4 T5 T6
21014 1/1 reg_we_check[28] = addr_swap_data_we;
Tests: T4 T5 T6
21015 1/1 reg_we_check[29] = payload_swap_mask_we;
Tests: T4 T5 T6
21016 1/1 reg_we_check[30] = payload_swap_data_we;
Tests: T4 T5 T6
21017 1/1 reg_we_check[31] = cmd_info_0_we;
Tests: T4 T5 T6
21018 1/1 reg_we_check[32] = cmd_info_1_we;
Tests: T4 T5 T6
21019 1/1 reg_we_check[33] = cmd_info_2_we;
Tests: T4 T5 T6
21020 1/1 reg_we_check[34] = cmd_info_3_we;
Tests: T4 T5 T6
21021 1/1 reg_we_check[35] = cmd_info_4_we;
Tests: T4 T5 T6
21022 1/1 reg_we_check[36] = cmd_info_5_we;
Tests: T4 T5 T6
21023 1/1 reg_we_check[37] = cmd_info_6_we;
Tests: T4 T5 T6
21024 1/1 reg_we_check[38] = cmd_info_7_we;
Tests: T4 T5 T6
21025 1/1 reg_we_check[39] = cmd_info_8_we;
Tests: T4 T5 T6
21026 1/1 reg_we_check[40] = cmd_info_9_we;
Tests: T4 T5 T6
21027 1/1 reg_we_check[41] = cmd_info_10_we;
Tests: T4 T5 T6
21028 1/1 reg_we_check[42] = cmd_info_11_we;
Tests: T4 T5 T6
21029 1/1 reg_we_check[43] = cmd_info_12_we;
Tests: T4 T5 T6
21030 1/1 reg_we_check[44] = cmd_info_13_we;
Tests: T4 T5 T6
21031 1/1 reg_we_check[45] = cmd_info_14_we;
Tests: T4 T5 T6
21032 1/1 reg_we_check[46] = cmd_info_15_we;
Tests: T4 T5 T6
21033 1/1 reg_we_check[47] = cmd_info_16_we;
Tests: T4 T5 T6
21034 1/1 reg_we_check[48] = cmd_info_17_we;
Tests: T4 T5 T6
21035 1/1 reg_we_check[49] = cmd_info_18_we;
Tests: T4 T5 T6
21036 1/1 reg_we_check[50] = cmd_info_19_we;
Tests: T4 T5 T6
21037 1/1 reg_we_check[51] = cmd_info_20_we;
Tests: T4 T5 T6
21038 1/1 reg_we_check[52] = cmd_info_21_we;
Tests: T4 T5 T6
21039 1/1 reg_we_check[53] = cmd_info_22_we;
Tests: T4 T5 T6
21040 1/1 reg_we_check[54] = cmd_info_23_we;
Tests: T4 T5 T6
21041 1/1 reg_we_check[55] = cmd_info_en4b_we;
Tests: T4 T5 T6
21042 1/1 reg_we_check[56] = cmd_info_ex4b_we;
Tests: T4 T5 T6
21043 1/1 reg_we_check[57] = cmd_info_wren_we;
Tests: T4 T5 T6
21044 1/1 reg_we_check[58] = cmd_info_wrdi_we;
Tests: T4 T5 T6
21045 1/1 reg_we_check[59] = 1'b0;
Tests: T4 T5 T6
21046 1/1 reg_we_check[60] = tpm_cfg_we;
Tests: T4 T5 T6
21047 1/1 reg_we_check[61] = tpm_status_we;
Tests: T4 T5 T6
21048 1/1 reg_we_check[62] = tpm_access_0_we;
Tests: T4 T5 T6
21049 1/1 reg_we_check[63] = tpm_access_1_we;
Tests: T4 T5 T6
21050 1/1 reg_we_check[64] = tpm_sts_we;
Tests: T4 T5 T6
21051 1/1 reg_we_check[65] = tpm_intf_capability_we;
Tests: T4 T5 T6
21052 1/1 reg_we_check[66] = tpm_int_enable_we;
Tests: T4 T5 T6
21053 1/1 reg_we_check[67] = tpm_int_vector_we;
Tests: T4 T5 T6
21054 1/1 reg_we_check[68] = tpm_int_status_we;
Tests: T4 T5 T6
21055 1/1 reg_we_check[69] = tpm_did_vid_we;
Tests: T4 T5 T6
21056 1/1 reg_we_check[70] = tpm_rid_we;
Tests: T4 T5 T6
21057 1/1 reg_we_check[71] = 1'b0;
Tests: T4 T5 T6
21058 1/1 reg_we_check[72] = tpm_read_fifo_we;
Tests: T4 T5 T6
21059 end
21060
21061 // Read data return
21062 always_comb begin
21063 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
21064 1/1 unique case (1'b1)
Tests: T1 T2 T3
21065 addr_hit[0]: begin
21066 1/1 reg_rdata_next[0] = intr_state_upload_cmdfifo_not_empty_qs;
Tests: T1 T2 T3
21067 1/1 reg_rdata_next[1] = intr_state_upload_payload_not_empty_qs;
Tests: T1 T2 T3
21068 1/1 reg_rdata_next[2] = intr_state_upload_payload_overflow_qs;
Tests: T1 T2 T3
21069 1/1 reg_rdata_next[3] = intr_state_readbuf_watermark_qs;
Tests: T1 T2 T3
21070 1/1 reg_rdata_next[4] = intr_state_readbuf_flip_qs;
Tests: T1 T2 T3
21071 1/1 reg_rdata_next[5] = intr_state_tpm_header_not_empty_qs;
Tests: T1 T2 T3
21072 1/1 reg_rdata_next[6] = intr_state_tpm_rdfifo_cmd_end_qs;
Tests: T1 T2 T3
21073 1/1 reg_rdata_next[7] = intr_state_tpm_rdfifo_drop_qs;
Tests: T1 T2 T3
21074 end
21075
21076 addr_hit[1]: begin
21077 1/1 reg_rdata_next[0] = intr_enable_upload_cmdfifo_not_empty_qs;
Tests: T1 T2 T4
21078 1/1 reg_rdata_next[1] = intr_enable_upload_payload_not_empty_qs;
Tests: T1 T2 T4
21079 1/1 reg_rdata_next[2] = intr_enable_upload_payload_overflow_qs;
Tests: T1 T2 T4
21080 1/1 reg_rdata_next[3] = intr_enable_readbuf_watermark_qs;
Tests: T1 T2 T4
21081 1/1 reg_rdata_next[4] = intr_enable_readbuf_flip_qs;
Tests: T1 T2 T4
21082 1/1 reg_rdata_next[5] = intr_enable_tpm_header_not_empty_qs;
Tests: T1 T2 T4
21083 1/1 reg_rdata_next[6] = intr_enable_tpm_rdfifo_cmd_end_qs;
Tests: T1 T2 T4
21084 1/1 reg_rdata_next[7] = intr_enable_tpm_rdfifo_drop_qs;
Tests: T1 T2 T4
21085 end
21086
21087 addr_hit[2]: begin
21088 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T4
21089 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T4
21090 1/1 reg_rdata_next[2] = '0;
Tests: T1 T2 T4
21091 1/1 reg_rdata_next[3] = '0;
Tests: T1 T2 T4
21092 1/1 reg_rdata_next[4] = '0;
Tests: T1 T2 T4
21093 1/1 reg_rdata_next[5] = '0;
Tests: T1 T2 T4
21094 1/1 reg_rdata_next[6] = '0;
Tests: T1 T2 T4
21095 1/1 reg_rdata_next[7] = '0;
Tests: T1 T2 T4
21096 end
21097
21098 addr_hit[3]: begin
21099 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T4
21100 end
21101
21102 addr_hit[4]: begin
21103 1/1 reg_rdata_next[0] = control_flash_status_fifo_clr_qs;
Tests: T1 T2 T4
21104 1/1 reg_rdata_next[1] = control_flash_read_buffer_clr_qs;
Tests: T1 T2 T4
21105 1/1 reg_rdata_next[5:4] = control_mode_qs;
Tests: T1 T2 T4
21106 end
21107
21108 addr_hit[5]: begin
21109 1/1 reg_rdata_next[2] = cfg_tx_order_qs;
Tests: T1 T2 T4
21110 1/1 reg_rdata_next[3] = cfg_rx_order_qs;
Tests: T1 T2 T4
21111 1/1 reg_rdata_next[24] = cfg_mailbox_en_qs;
Tests: T1 T2 T4
21112 end
21113
21114 addr_hit[6]: begin
21115 1/1 reg_rdata_next[5] = status_csb_qs;
Tests: T1 T2 T4
21116 1/1 reg_rdata_next[6] = status_tpm_csb_qs;
Tests: T1 T2 T4
21117 end
21118
21119 addr_hit[7]: begin
21120 1/1 reg_rdata_next[0] = intercept_en_status_qs;
Tests: T1 T2 T3
21121 1/1 reg_rdata_next[1] = intercept_en_jedec_qs;
Tests: T1 T2 T3
21122 1/1 reg_rdata_next[2] = intercept_en_sfdp_qs;
Tests: T1 T2 T3
21123 1/1 reg_rdata_next[3] = intercept_en_mbx_qs;
Tests: T1 T2 T3
21124 end
21125
21126 addr_hit[8]: begin
21127 1/1 reg_rdata_next[0] = addr_mode_addr_4b_en_qs;
Tests: T1 T2 T4
21128 1/1 reg_rdata_next[31] = addr_mode_pending_qs;
Tests: T1 T2 T4
21129 end
21130
21131 addr_hit[9]: begin
21132 1/1 reg_rdata_next[31:0] = last_read_addr_qs;
Tests: T1 T2 T4
21133 end
21134
21135 addr_hit[10]: begin
21136 1/1 reg_rdata_next[0] = flash_status_busy_qs;
Tests: T1 T2 T4
21137 1/1 reg_rdata_next[1] = flash_status_wel_qs;
Tests: T1 T2 T4
21138 1/1 reg_rdata_next[23:2] = flash_status_status_qs;
Tests: T1 T2 T4
21139 end
21140
21141 addr_hit[11]: begin
21142 1/1 reg_rdata_next[7:0] = jedec_cc_cc_qs;
Tests: T1 T2 T3
21143 1/1 reg_rdata_next[15:8] = jedec_cc_num_cc_qs;
Tests: T1 T2 T3
21144 end
21145
21146 addr_hit[12]: begin
21147 1/1 reg_rdata_next[15:0] = jedec_id_id_qs;
Tests: T1 T2 T4
21148 1/1 reg_rdata_next[23:16] = jedec_id_mf_qs;
Tests: T1 T2 T4
21149 end
21150
21151 addr_hit[13]: begin
21152 1/1 reg_rdata_next[9:0] = read_threshold_qs;
Tests: T1 T2 T4
21153 end
21154
21155 addr_hit[14]: begin
21156 1/1 reg_rdata_next[31:0] = mailbox_addr_qs;
Tests: T1 T2 T4
21157 end
21158
21159 addr_hit[15]: begin
21160 1/1 reg_rdata_next[4:0] = upload_status_cmdfifo_depth_qs;
Tests: T1 T2 T4
21161 1/1 reg_rdata_next[7] = upload_status_cmdfifo_notempty_qs;
Tests: T1 T2 T4
21162 1/1 reg_rdata_next[12:8] = upload_status_addrfifo_depth_qs;
Tests: T1 T2 T4
21163 1/1 reg_rdata_next[15] = upload_status_addrfifo_notempty_qs;
Tests: T1 T2 T4
21164 end
21165
21166 addr_hit[16]: begin
21167 1/1 reg_rdata_next[8:0] = upload_status2_payload_depth_qs;
Tests: T1 T2 T4
21168 1/1 reg_rdata_next[23:16] = upload_status2_payload_start_idx_qs;
Tests: T1 T2 T4
21169 end
21170
21171 addr_hit[17]: begin
21172 1/1 reg_rdata_next[7:0] = upload_cmdfifo_data_qs;
Tests: T1 T2 T4
21173 1/1 reg_rdata_next[13] = upload_cmdfifo_busy_qs;
Tests: T1 T2 T4
21174 1/1 reg_rdata_next[14] = upload_cmdfifo_wel_qs;
Tests: T1 T2 T4
21175 1/1 reg_rdata_next[15] = upload_cmdfifo_addr4b_mode_qs;
Tests: T1 T2 T4
21176 end
21177
21178 addr_hit[18]: begin
21179 1/1 reg_rdata_next[31:0] = upload_addrfifo_qs;
Tests: T1 T2 T4
21180 end
21181
21182 addr_hit[19]: begin
21183 1/1 reg_rdata_next[0] = cmd_filter_0_filter_0_qs;
Tests: T1 T2 T4
21184 1/1 reg_rdata_next[1] = cmd_filter_0_filter_1_qs;
Tests: T1 T2 T4
21185 1/1 reg_rdata_next[2] = cmd_filter_0_filter_2_qs;
Tests: T1 T2 T4
21186 1/1 reg_rdata_next[3] = cmd_filter_0_filter_3_qs;
Tests: T1 T2 T4
21187 1/1 reg_rdata_next[4] = cmd_filter_0_filter_4_qs;
Tests: T1 T2 T4
21188 1/1 reg_rdata_next[5] = cmd_filter_0_filter_5_qs;
Tests: T1 T2 T4
21189 1/1 reg_rdata_next[6] = cmd_filter_0_filter_6_qs;
Tests: T1 T2 T4
21190 1/1 reg_rdata_next[7] = cmd_filter_0_filter_7_qs;
Tests: T1 T2 T4
21191 1/1 reg_rdata_next[8] = cmd_filter_0_filter_8_qs;
Tests: T1 T2 T4
21192 1/1 reg_rdata_next[9] = cmd_filter_0_filter_9_qs;
Tests: T1 T2 T4
21193 1/1 reg_rdata_next[10] = cmd_filter_0_filter_10_qs;
Tests: T1 T2 T4
21194 1/1 reg_rdata_next[11] = cmd_filter_0_filter_11_qs;
Tests: T1 T2 T4
21195 1/1 reg_rdata_next[12] = cmd_filter_0_filter_12_qs;
Tests: T1 T2 T4
21196 1/1 reg_rdata_next[13] = cmd_filter_0_filter_13_qs;
Tests: T1 T2 T4
21197 1/1 reg_rdata_next[14] = cmd_filter_0_filter_14_qs;
Tests: T1 T2 T4
21198 1/1 reg_rdata_next[15] = cmd_filter_0_filter_15_qs;
Tests: T1 T2 T4
21199 1/1 reg_rdata_next[16] = cmd_filter_0_filter_16_qs;
Tests: T1 T2 T4
21200 1/1 reg_rdata_next[17] = cmd_filter_0_filter_17_qs;
Tests: T1 T2 T4
21201 1/1 reg_rdata_next[18] = cmd_filter_0_filter_18_qs;
Tests: T1 T2 T4
21202 1/1 reg_rdata_next[19] = cmd_filter_0_filter_19_qs;
Tests: T1 T2 T4
21203 1/1 reg_rdata_next[20] = cmd_filter_0_filter_20_qs;
Tests: T1 T2 T4
21204 1/1 reg_rdata_next[21] = cmd_filter_0_filter_21_qs;
Tests: T1 T2 T4
21205 1/1 reg_rdata_next[22] = cmd_filter_0_filter_22_qs;
Tests: T1 T2 T4
21206 1/1 reg_rdata_next[23] = cmd_filter_0_filter_23_qs;
Tests: T1 T2 T4
21207 1/1 reg_rdata_next[24] = cmd_filter_0_filter_24_qs;
Tests: T1 T2 T4
21208 1/1 reg_rdata_next[25] = cmd_filter_0_filter_25_qs;
Tests: T1 T2 T4
21209 1/1 reg_rdata_next[26] = cmd_filter_0_filter_26_qs;
Tests: T1 T2 T4
21210 1/1 reg_rdata_next[27] = cmd_filter_0_filter_27_qs;
Tests: T1 T2 T4
21211 1/1 reg_rdata_next[28] = cmd_filter_0_filter_28_qs;
Tests: T1 T2 T4
21212 1/1 reg_rdata_next[29] = cmd_filter_0_filter_29_qs;
Tests: T1 T2 T4
21213 1/1 reg_rdata_next[30] = cmd_filter_0_filter_30_qs;
Tests: T1 T2 T4
21214 1/1 reg_rdata_next[31] = cmd_filter_0_filter_31_qs;
Tests: T1 T2 T4
21215 end
21216
21217 addr_hit[20]: begin
21218 1/1 reg_rdata_next[0] = cmd_filter_1_filter_32_qs;
Tests: T1 T2 T4
21219 1/1 reg_rdata_next[1] = cmd_filter_1_filter_33_qs;
Tests: T1 T2 T4
21220 1/1 reg_rdata_next[2] = cmd_filter_1_filter_34_qs;
Tests: T1 T2 T4
21221 1/1 reg_rdata_next[3] = cmd_filter_1_filter_35_qs;
Tests: T1 T2 T4
21222 1/1 reg_rdata_next[4] = cmd_filter_1_filter_36_qs;
Tests: T1 T2 T4
21223 1/1 reg_rdata_next[5] = cmd_filter_1_filter_37_qs;
Tests: T1 T2 T4
21224 1/1 reg_rdata_next[6] = cmd_filter_1_filter_38_qs;
Tests: T1 T2 T4
21225 1/1 reg_rdata_next[7] = cmd_filter_1_filter_39_qs;
Tests: T1 T2 T4
21226 1/1 reg_rdata_next[8] = cmd_filter_1_filter_40_qs;
Tests: T1 T2 T4
21227 1/1 reg_rdata_next[9] = cmd_filter_1_filter_41_qs;
Tests: T1 T2 T4
21228 1/1 reg_rdata_next[10] = cmd_filter_1_filter_42_qs;
Tests: T1 T2 T4
21229 1/1 reg_rdata_next[11] = cmd_filter_1_filter_43_qs;
Tests: T1 T2 T4
21230 1/1 reg_rdata_next[12] = cmd_filter_1_filter_44_qs;
Tests: T1 T2 T4
21231 1/1 reg_rdata_next[13] = cmd_filter_1_filter_45_qs;
Tests: T1 T2 T4
21232 1/1 reg_rdata_next[14] = cmd_filter_1_filter_46_qs;
Tests: T1 T2 T4
21233 1/1 reg_rdata_next[15] = cmd_filter_1_filter_47_qs;
Tests: T1 T2 T4
21234 1/1 reg_rdata_next[16] = cmd_filter_1_filter_48_qs;
Tests: T1 T2 T4
21235 1/1 reg_rdata_next[17] = cmd_filter_1_filter_49_qs;
Tests: T1 T2 T4
21236 1/1 reg_rdata_next[18] = cmd_filter_1_filter_50_qs;
Tests: T1 T2 T4
21237 1/1 reg_rdata_next[19] = cmd_filter_1_filter_51_qs;
Tests: T1 T2 T4
21238 1/1 reg_rdata_next[20] = cmd_filter_1_filter_52_qs;
Tests: T1 T2 T4
21239 1/1 reg_rdata_next[21] = cmd_filter_1_filter_53_qs;
Tests: T1 T2 T4
21240 1/1 reg_rdata_next[22] = cmd_filter_1_filter_54_qs;
Tests: T1 T2 T4
21241 1/1 reg_rdata_next[23] = cmd_filter_1_filter_55_qs;
Tests: T1 T2 T4
21242 1/1 reg_rdata_next[24] = cmd_filter_1_filter_56_qs;
Tests: T1 T2 T4
21243 1/1 reg_rdata_next[25] = cmd_filter_1_filter_57_qs;
Tests: T1 T2 T4
21244 1/1 reg_rdata_next[26] = cmd_filter_1_filter_58_qs;
Tests: T1 T2 T4
21245 1/1 reg_rdata_next[27] = cmd_filter_1_filter_59_qs;
Tests: T1 T2 T4
21246 1/1 reg_rdata_next[28] = cmd_filter_1_filter_60_qs;
Tests: T1 T2 T4
21247 1/1 reg_rdata_next[29] = cmd_filter_1_filter_61_qs;
Tests: T1 T2 T4
21248 1/1 reg_rdata_next[30] = cmd_filter_1_filter_62_qs;
Tests: T1 T2 T4
21249 1/1 reg_rdata_next[31] = cmd_filter_1_filter_63_qs;
Tests: T1 T2 T4
21250 end
21251
21252 addr_hit[21]: begin
21253 1/1 reg_rdata_next[0] = cmd_filter_2_filter_64_qs;
Tests: T1 T2 T4
21254 1/1 reg_rdata_next[1] = cmd_filter_2_filter_65_qs;
Tests: T1 T2 T4
21255 1/1 reg_rdata_next[2] = cmd_filter_2_filter_66_qs;
Tests: T1 T2 T4
21256 1/1 reg_rdata_next[3] = cmd_filter_2_filter_67_qs;
Tests: T1 T2 T4
21257 1/1 reg_rdata_next[4] = cmd_filter_2_filter_68_qs;
Tests: T1 T2 T4
21258 1/1 reg_rdata_next[5] = cmd_filter_2_filter_69_qs;
Tests: T1 T2 T4
21259 1/1 reg_rdata_next[6] = cmd_filter_2_filter_70_qs;
Tests: T1 T2 T4
21260 1/1 reg_rdata_next[7] = cmd_filter_2_filter_71_qs;
Tests: T1 T2 T4
21261 1/1 reg_rdata_next[8] = cmd_filter_2_filter_72_qs;
Tests: T1 T2 T4
21262 1/1 reg_rdata_next[9] = cmd_filter_2_filter_73_qs;
Tests: T1 T2 T4
21263 1/1 reg_rdata_next[10] = cmd_filter_2_filter_74_qs;
Tests: T1 T2 T4
21264 1/1 reg_rdata_next[11] = cmd_filter_2_filter_75_qs;
Tests: T1 T2 T4
21265 1/1 reg_rdata_next[12] = cmd_filter_2_filter_76_qs;
Tests: T1 T2 T4
21266 1/1 reg_rdata_next[13] = cmd_filter_2_filter_77_qs;
Tests: T1 T2 T4
21267 1/1 reg_rdata_next[14] = cmd_filter_2_filter_78_qs;
Tests: T1 T2 T4
21268 1/1 reg_rdata_next[15] = cmd_filter_2_filter_79_qs;
Tests: T1 T2 T4
21269 1/1 reg_rdata_next[16] = cmd_filter_2_filter_80_qs;
Tests: T1 T2 T4
21270 1/1 reg_rdata_next[17] = cmd_filter_2_filter_81_qs;
Tests: T1 T2 T4
21271 1/1 reg_rdata_next[18] = cmd_filter_2_filter_82_qs;
Tests: T1 T2 T4
21272 1/1 reg_rdata_next[19] = cmd_filter_2_filter_83_qs;
Tests: T1 T2 T4
21273 1/1 reg_rdata_next[20] = cmd_filter_2_filter_84_qs;
Tests: T1 T2 T4
21274 1/1 reg_rdata_next[21] = cmd_filter_2_filter_85_qs;
Tests: T1 T2 T4
21275 1/1 reg_rdata_next[22] = cmd_filter_2_filter_86_qs;
Tests: T1 T2 T4
21276 1/1 reg_rdata_next[23] = cmd_filter_2_filter_87_qs;
Tests: T1 T2 T4
21277 1/1 reg_rdata_next[24] = cmd_filter_2_filter_88_qs;
Tests: T1 T2 T4
21278 1/1 reg_rdata_next[25] = cmd_filter_2_filter_89_qs;
Tests: T1 T2 T4
21279 1/1 reg_rdata_next[26] = cmd_filter_2_filter_90_qs;
Tests: T1 T2 T4
21280 1/1 reg_rdata_next[27] = cmd_filter_2_filter_91_qs;
Tests: T1 T2 T4
21281 1/1 reg_rdata_next[28] = cmd_filter_2_filter_92_qs;
Tests: T1 T2 T4
21282 1/1 reg_rdata_next[29] = cmd_filter_2_filter_93_qs;
Tests: T1 T2 T4
21283 1/1 reg_rdata_next[30] = cmd_filter_2_filter_94_qs;
Tests: T1 T2 T4
21284 1/1 reg_rdata_next[31] = cmd_filter_2_filter_95_qs;
Tests: T1 T2 T4
21285 end
21286
21287 addr_hit[22]: begin
21288 1/1 reg_rdata_next[0] = cmd_filter_3_filter_96_qs;
Tests: T1 T2 T4
21289 1/1 reg_rdata_next[1] = cmd_filter_3_filter_97_qs;
Tests: T1 T2 T4
21290 1/1 reg_rdata_next[2] = cmd_filter_3_filter_98_qs;
Tests: T1 T2 T4
21291 1/1 reg_rdata_next[3] = cmd_filter_3_filter_99_qs;
Tests: T1 T2 T4
21292 1/1 reg_rdata_next[4] = cmd_filter_3_filter_100_qs;
Tests: T1 T2 T4
21293 1/1 reg_rdata_next[5] = cmd_filter_3_filter_101_qs;
Tests: T1 T2 T4
21294 1/1 reg_rdata_next[6] = cmd_filter_3_filter_102_qs;
Tests: T1 T2 T4
21295 1/1 reg_rdata_next[7] = cmd_filter_3_filter_103_qs;
Tests: T1 T2 T4
21296 1/1 reg_rdata_next[8] = cmd_filter_3_filter_104_qs;
Tests: T1 T2 T4
21297 1/1 reg_rdata_next[9] = cmd_filter_3_filter_105_qs;
Tests: T1 T2 T4
21298 1/1 reg_rdata_next[10] = cmd_filter_3_filter_106_qs;
Tests: T1 T2 T4
21299 1/1 reg_rdata_next[11] = cmd_filter_3_filter_107_qs;
Tests: T1 T2 T4
21300 1/1 reg_rdata_next[12] = cmd_filter_3_filter_108_qs;
Tests: T1 T2 T4
21301 1/1 reg_rdata_next[13] = cmd_filter_3_filter_109_qs;
Tests: T1 T2 T4
21302 1/1 reg_rdata_next[14] = cmd_filter_3_filter_110_qs;
Tests: T1 T2 T4
21303 1/1 reg_rdata_next[15] = cmd_filter_3_filter_111_qs;
Tests: T1 T2 T4
21304 1/1 reg_rdata_next[16] = cmd_filter_3_filter_112_qs;
Tests: T1 T2 T4
21305 1/1 reg_rdata_next[17] = cmd_filter_3_filter_113_qs;
Tests: T1 T2 T4
21306 1/1 reg_rdata_next[18] = cmd_filter_3_filter_114_qs;
Tests: T1 T2 T4
21307 1/1 reg_rdata_next[19] = cmd_filter_3_filter_115_qs;
Tests: T1 T2 T4
21308 1/1 reg_rdata_next[20] = cmd_filter_3_filter_116_qs;
Tests: T1 T2 T4
21309 1/1 reg_rdata_next[21] = cmd_filter_3_filter_117_qs;
Tests: T1 T2 T4
21310 1/1 reg_rdata_next[22] = cmd_filter_3_filter_118_qs;
Tests: T1 T2 T4
21311 1/1 reg_rdata_next[23] = cmd_filter_3_filter_119_qs;
Tests: T1 T2 T4
21312 1/1 reg_rdata_next[24] = cmd_filter_3_filter_120_qs;
Tests: T1 T2 T4
21313 1/1 reg_rdata_next[25] = cmd_filter_3_filter_121_qs;
Tests: T1 T2 T4
21314 1/1 reg_rdata_next[26] = cmd_filter_3_filter_122_qs;
Tests: T1 T2 T4
21315 1/1 reg_rdata_next[27] = cmd_filter_3_filter_123_qs;
Tests: T1 T2 T4
21316 1/1 reg_rdata_next[28] = cmd_filter_3_filter_124_qs;
Tests: T1 T2 T4
21317 1/1 reg_rdata_next[29] = cmd_filter_3_filter_125_qs;
Tests: T1 T2 T4
21318 1/1 reg_rdata_next[30] = cmd_filter_3_filter_126_qs;
Tests: T1 T2 T4
21319 1/1 reg_rdata_next[31] = cmd_filter_3_filter_127_qs;
Tests: T1 T2 T4
21320 end
21321
21322 addr_hit[23]: begin
21323 1/1 reg_rdata_next[0] = cmd_filter_4_filter_128_qs;
Tests: T1 T2 T4
21324 1/1 reg_rdata_next[1] = cmd_filter_4_filter_129_qs;
Tests: T1 T2 T4
21325 1/1 reg_rdata_next[2] = cmd_filter_4_filter_130_qs;
Tests: T1 T2 T4
21326 1/1 reg_rdata_next[3] = cmd_filter_4_filter_131_qs;
Tests: T1 T2 T4
21327 1/1 reg_rdata_next[4] = cmd_filter_4_filter_132_qs;
Tests: T1 T2 T4
21328 1/1 reg_rdata_next[5] = cmd_filter_4_filter_133_qs;
Tests: T1 T2 T4
21329 1/1 reg_rdata_next[6] = cmd_filter_4_filter_134_qs;
Tests: T1 T2 T4
21330 1/1 reg_rdata_next[7] = cmd_filter_4_filter_135_qs;
Tests: T1 T2 T4
21331 1/1 reg_rdata_next[8] = cmd_filter_4_filter_136_qs;
Tests: T1 T2 T4
21332 1/1 reg_rdata_next[9] = cmd_filter_4_filter_137_qs;
Tests: T1 T2 T4
21333 1/1 reg_rdata_next[10] = cmd_filter_4_filter_138_qs;
Tests: T1 T2 T4
21334 1/1 reg_rdata_next[11] = cmd_filter_4_filter_139_qs;
Tests: T1 T2 T4
21335 1/1 reg_rdata_next[12] = cmd_filter_4_filter_140_qs;
Tests: T1 T2 T4
21336 1/1 reg_rdata_next[13] = cmd_filter_4_filter_141_qs;
Tests: T1 T2 T4
21337 1/1 reg_rdata_next[14] = cmd_filter_4_filter_142_qs;
Tests: T1 T2 T4
21338 1/1 reg_rdata_next[15] = cmd_filter_4_filter_143_qs;
Tests: T1 T2 T4
21339 1/1 reg_rdata_next[16] = cmd_filter_4_filter_144_qs;
Tests: T1 T2 T4
21340 1/1 reg_rdata_next[17] = cmd_filter_4_filter_145_qs;
Tests: T1 T2 T4
21341 1/1 reg_rdata_next[18] = cmd_filter_4_filter_146_qs;
Tests: T1 T2 T4
21342 1/1 reg_rdata_next[19] = cmd_filter_4_filter_147_qs;
Tests: T1 T2 T4
21343 1/1 reg_rdata_next[20] = cmd_filter_4_filter_148_qs;
Tests: T1 T2 T4
21344 1/1 reg_rdata_next[21] = cmd_filter_4_filter_149_qs;
Tests: T1 T2 T4
21345 1/1 reg_rdata_next[22] = cmd_filter_4_filter_150_qs;
Tests: T1 T2 T4
21346 1/1 reg_rdata_next[23] = cmd_filter_4_filter_151_qs;
Tests: T1 T2 T4
21347 1/1 reg_rdata_next[24] = cmd_filter_4_filter_152_qs;
Tests: T1 T2 T4
21348 1/1 reg_rdata_next[25] = cmd_filter_4_filter_153_qs;
Tests: T1 T2 T4
21349 1/1 reg_rdata_next[26] = cmd_filter_4_filter_154_qs;
Tests: T1 T2 T4
21350 1/1 reg_rdata_next[27] = cmd_filter_4_filter_155_qs;
Tests: T1 T2 T4
21351 1/1 reg_rdata_next[28] = cmd_filter_4_filter_156_qs;
Tests: T1 T2 T4
21352 1/1 reg_rdata_next[29] = cmd_filter_4_filter_157_qs;
Tests: T1 T2 T4
21353 1/1 reg_rdata_next[30] = cmd_filter_4_filter_158_qs;
Tests: T1 T2 T4
21354 1/1 reg_rdata_next[31] = cmd_filter_4_filter_159_qs;
Tests: T1 T2 T4
21355 end
21356
21357 addr_hit[24]: begin
21358 1/1 reg_rdata_next[0] = cmd_filter_5_filter_160_qs;
Tests: T1 T2 T4
21359 1/1 reg_rdata_next[1] = cmd_filter_5_filter_161_qs;
Tests: T1 T2 T4
21360 1/1 reg_rdata_next[2] = cmd_filter_5_filter_162_qs;
Tests: T1 T2 T4
21361 1/1 reg_rdata_next[3] = cmd_filter_5_filter_163_qs;
Tests: T1 T2 T4
21362 1/1 reg_rdata_next[4] = cmd_filter_5_filter_164_qs;
Tests: T1 T2 T4
21363 1/1 reg_rdata_next[5] = cmd_filter_5_filter_165_qs;
Tests: T1 T2 T4
21364 1/1 reg_rdata_next[6] = cmd_filter_5_filter_166_qs;
Tests: T1 T2 T4
21365 1/1 reg_rdata_next[7] = cmd_filter_5_filter_167_qs;
Tests: T1 T2 T4
21366 1/1 reg_rdata_next[8] = cmd_filter_5_filter_168_qs;
Tests: T1 T2 T4
21367 1/1 reg_rdata_next[9] = cmd_filter_5_filter_169_qs;
Tests: T1 T2 T4
21368 1/1 reg_rdata_next[10] = cmd_filter_5_filter_170_qs;
Tests: T1 T2 T4
21369 1/1 reg_rdata_next[11] = cmd_filter_5_filter_171_qs;
Tests: T1 T2 T4
21370 1/1 reg_rdata_next[12] = cmd_filter_5_filter_172_qs;
Tests: T1 T2 T4
21371 1/1 reg_rdata_next[13] = cmd_filter_5_filter_173_qs;
Tests: T1 T2 T4
21372 1/1 reg_rdata_next[14] = cmd_filter_5_filter_174_qs;
Tests: T1 T2 T4
21373 1/1 reg_rdata_next[15] = cmd_filter_5_filter_175_qs;
Tests: T1 T2 T4
21374 1/1 reg_rdata_next[16] = cmd_filter_5_filter_176_qs;
Tests: T1 T2 T4
21375 1/1 reg_rdata_next[17] = cmd_filter_5_filter_177_qs;
Tests: T1 T2 T4
21376 1/1 reg_rdata_next[18] = cmd_filter_5_filter_178_qs;
Tests: T1 T2 T4
21377 1/1 reg_rdata_next[19] = cmd_filter_5_filter_179_qs;
Tests: T1 T2 T4
21378 1/1 reg_rdata_next[20] = cmd_filter_5_filter_180_qs;
Tests: T1 T2 T4
21379 1/1 reg_rdata_next[21] = cmd_filter_5_filter_181_qs;
Tests: T1 T2 T4
21380 1/1 reg_rdata_next[22] = cmd_filter_5_filter_182_qs;
Tests: T1 T2 T4
21381 1/1 reg_rdata_next[23] = cmd_filter_5_filter_183_qs;
Tests: T1 T2 T4
21382 1/1 reg_rdata_next[24] = cmd_filter_5_filter_184_qs;
Tests: T1 T2 T4
21383 1/1 reg_rdata_next[25] = cmd_filter_5_filter_185_qs;
Tests: T1 T2 T4
21384 1/1 reg_rdata_next[26] = cmd_filter_5_filter_186_qs;
Tests: T1 T2 T4
21385 1/1 reg_rdata_next[27] = cmd_filter_5_filter_187_qs;
Tests: T1 T2 T4
21386 1/1 reg_rdata_next[28] = cmd_filter_5_filter_188_qs;
Tests: T1 T2 T4
21387 1/1 reg_rdata_next[29] = cmd_filter_5_filter_189_qs;
Tests: T1 T2 T4
21388 1/1 reg_rdata_next[30] = cmd_filter_5_filter_190_qs;
Tests: T1 T2 T4
21389 1/1 reg_rdata_next[31] = cmd_filter_5_filter_191_qs;
Tests: T1 T2 T4
21390 end
21391
21392 addr_hit[25]: begin
21393 1/1 reg_rdata_next[0] = cmd_filter_6_filter_192_qs;
Tests: T1 T2 T4
21394 1/1 reg_rdata_next[1] = cmd_filter_6_filter_193_qs;
Tests: T1 T2 T4
21395 1/1 reg_rdata_next[2] = cmd_filter_6_filter_194_qs;
Tests: T1 T2 T4
21396 1/1 reg_rdata_next[3] = cmd_filter_6_filter_195_qs;
Tests: T1 T2 T4
21397 1/1 reg_rdata_next[4] = cmd_filter_6_filter_196_qs;
Tests: T1 T2 T4
21398 1/1 reg_rdata_next[5] = cmd_filter_6_filter_197_qs;
Tests: T1 T2 T4
21399 1/1 reg_rdata_next[6] = cmd_filter_6_filter_198_qs;
Tests: T1 T2 T4
21400 1/1 reg_rdata_next[7] = cmd_filter_6_filter_199_qs;
Tests: T1 T2 T4
21401 1/1 reg_rdata_next[8] = cmd_filter_6_filter_200_qs;
Tests: T1 T2 T4
21402 1/1 reg_rdata_next[9] = cmd_filter_6_filter_201_qs;
Tests: T1 T2 T4
21403 1/1 reg_rdata_next[10] = cmd_filter_6_filter_202_qs;
Tests: T1 T2 T4
21404 1/1 reg_rdata_next[11] = cmd_filter_6_filter_203_qs;
Tests: T1 T2 T4
21405 1/1 reg_rdata_next[12] = cmd_filter_6_filter_204_qs;
Tests: T1 T2 T4
21406 1/1 reg_rdata_next[13] = cmd_filter_6_filter_205_qs;
Tests: T1 T2 T4
21407 1/1 reg_rdata_next[14] = cmd_filter_6_filter_206_qs;
Tests: T1 T2 T4
21408 1/1 reg_rdata_next[15] = cmd_filter_6_filter_207_qs;
Tests: T1 T2 T4
21409 1/1 reg_rdata_next[16] = cmd_filter_6_filter_208_qs;
Tests: T1 T2 T4
21410 1/1 reg_rdata_next[17] = cmd_filter_6_filter_209_qs;
Tests: T1 T2 T4
21411 1/1 reg_rdata_next[18] = cmd_filter_6_filter_210_qs;
Tests: T1 T2 T4
21412 1/1 reg_rdata_next[19] = cmd_filter_6_filter_211_qs;
Tests: T1 T2 T4
21413 1/1 reg_rdata_next[20] = cmd_filter_6_filter_212_qs;
Tests: T1 T2 T4
21414 1/1 reg_rdata_next[21] = cmd_filter_6_filter_213_qs;
Tests: T1 T2 T4
21415 1/1 reg_rdata_next[22] = cmd_filter_6_filter_214_qs;
Tests: T1 T2 T4
21416 1/1 reg_rdata_next[23] = cmd_filter_6_filter_215_qs;
Tests: T1 T2 T4
21417 1/1 reg_rdata_next[24] = cmd_filter_6_filter_216_qs;
Tests: T1 T2 T4
21418 1/1 reg_rdata_next[25] = cmd_filter_6_filter_217_qs;
Tests: T1 T2 T4
21419 1/1 reg_rdata_next[26] = cmd_filter_6_filter_218_qs;
Tests: T1 T2 T4
21420 1/1 reg_rdata_next[27] = cmd_filter_6_filter_219_qs;
Tests: T1 T2 T4
21421 1/1 reg_rdata_next[28] = cmd_filter_6_filter_220_qs;
Tests: T1 T2 T4
21422 1/1 reg_rdata_next[29] = cmd_filter_6_filter_221_qs;
Tests: T1 T2 T4
21423 1/1 reg_rdata_next[30] = cmd_filter_6_filter_222_qs;
Tests: T1 T2 T4
21424 1/1 reg_rdata_next[31] = cmd_filter_6_filter_223_qs;
Tests: T1 T2 T4
21425 end
21426
21427 addr_hit[26]: begin
21428 1/1 reg_rdata_next[0] = cmd_filter_7_filter_224_qs;
Tests: T1 T2 T3
21429 1/1 reg_rdata_next[1] = cmd_filter_7_filter_225_qs;
Tests: T1 T2 T3
21430 1/1 reg_rdata_next[2] = cmd_filter_7_filter_226_qs;
Tests: T1 T2 T3
21431 1/1 reg_rdata_next[3] = cmd_filter_7_filter_227_qs;
Tests: T1 T2 T3
21432 1/1 reg_rdata_next[4] = cmd_filter_7_filter_228_qs;
Tests: T1 T2 T3
21433 1/1 reg_rdata_next[5] = cmd_filter_7_filter_229_qs;
Tests: T1 T2 T3
21434 1/1 reg_rdata_next[6] = cmd_filter_7_filter_230_qs;
Tests: T1 T2 T3
21435 1/1 reg_rdata_next[7] = cmd_filter_7_filter_231_qs;
Tests: T1 T2 T3
21436 1/1 reg_rdata_next[8] = cmd_filter_7_filter_232_qs;
Tests: T1 T2 T3
21437 1/1 reg_rdata_next[9] = cmd_filter_7_filter_233_qs;
Tests: T1 T2 T3
21438 1/1 reg_rdata_next[10] = cmd_filter_7_filter_234_qs;
Tests: T1 T2 T3
21439 1/1 reg_rdata_next[11] = cmd_filter_7_filter_235_qs;
Tests: T1 T2 T3
21440 1/1 reg_rdata_next[12] = cmd_filter_7_filter_236_qs;
Tests: T1 T2 T3
21441 1/1 reg_rdata_next[13] = cmd_filter_7_filter_237_qs;
Tests: T1 T2 T3
21442 1/1 reg_rdata_next[14] = cmd_filter_7_filter_238_qs;
Tests: T1 T2 T3
21443 1/1 reg_rdata_next[15] = cmd_filter_7_filter_239_qs;
Tests: T1 T2 T3
21444 1/1 reg_rdata_next[16] = cmd_filter_7_filter_240_qs;
Tests: T1 T2 T3
21445 1/1 reg_rdata_next[17] = cmd_filter_7_filter_241_qs;
Tests: T1 T2 T3
21446 1/1 reg_rdata_next[18] = cmd_filter_7_filter_242_qs;
Tests: T1 T2 T3
21447 1/1 reg_rdata_next[19] = cmd_filter_7_filter_243_qs;
Tests: T1 T2 T3
21448 1/1 reg_rdata_next[20] = cmd_filter_7_filter_244_qs;
Tests: T1 T2 T3
21449 1/1 reg_rdata_next[21] = cmd_filter_7_filter_245_qs;
Tests: T1 T2 T3
21450 1/1 reg_rdata_next[22] = cmd_filter_7_filter_246_qs;
Tests: T1 T2 T3
21451 1/1 reg_rdata_next[23] = cmd_filter_7_filter_247_qs;
Tests: T1 T2 T3
21452 1/1 reg_rdata_next[24] = cmd_filter_7_filter_248_qs;
Tests: T1 T2 T3
21453 1/1 reg_rdata_next[25] = cmd_filter_7_filter_249_qs;
Tests: T1 T2 T3
21454 1/1 reg_rdata_next[26] = cmd_filter_7_filter_250_qs;
Tests: T1 T2 T3
21455 1/1 reg_rdata_next[27] = cmd_filter_7_filter_251_qs;
Tests: T1 T2 T3
21456 1/1 reg_rdata_next[28] = cmd_filter_7_filter_252_qs;
Tests: T1 T2 T3
21457 1/1 reg_rdata_next[29] = cmd_filter_7_filter_253_qs;
Tests: T1 T2 T3
21458 1/1 reg_rdata_next[30] = cmd_filter_7_filter_254_qs;
Tests: T1 T2 T3
21459 1/1 reg_rdata_next[31] = cmd_filter_7_filter_255_qs;
Tests: T1 T2 T3
21460 end
21461
21462 addr_hit[27]: begin
21463 1/1 reg_rdata_next[31:0] = addr_swap_mask_qs;
Tests: T1 T2 T4
21464 end
21465
21466 addr_hit[28]: begin
21467 1/1 reg_rdata_next[31:0] = addr_swap_data_qs;
Tests: T1 T2 T4
21468 end
21469
21470 addr_hit[29]: begin
21471 1/1 reg_rdata_next[31:0] = payload_swap_mask_qs;
Tests: T1 T2 T3
21472 end
21473
21474 addr_hit[30]: begin
21475 1/1 reg_rdata_next[31:0] = payload_swap_data_qs;
Tests: T1 T2 T4
21476 end
21477
21478 addr_hit[31]: begin
21479 1/1 reg_rdata_next[7:0] = cmd_info_0_opcode_0_qs;
Tests: T1 T2 T4
21480 1/1 reg_rdata_next[9:8] = cmd_info_0_addr_mode_0_qs;
Tests: T1 T2 T4
21481 1/1 reg_rdata_next[10] = cmd_info_0_addr_swap_en_0_qs;
Tests: T1 T2 T4
21482 1/1 reg_rdata_next[11] = cmd_info_0_mbyte_en_0_qs;
Tests: T1 T2 T4
21483 1/1 reg_rdata_next[14:12] = cmd_info_0_dummy_size_0_qs;
Tests: T1 T2 T4
21484 1/1 reg_rdata_next[15] = cmd_info_0_dummy_en_0_qs;
Tests: T1 T2 T4
21485 1/1 reg_rdata_next[19:16] = cmd_info_0_payload_en_0_qs;
Tests: T1 T2 T4
21486 1/1 reg_rdata_next[20] = cmd_info_0_payload_dir_0_qs;
Tests: T1 T2 T4
21487 1/1 reg_rdata_next[21] = cmd_info_0_payload_swap_en_0_qs;
Tests: T1 T2 T4
21488 1/1 reg_rdata_next[23:22] = cmd_info_0_read_pipeline_mode_0_qs;
Tests: T1 T2 T4
21489 1/1 reg_rdata_next[24] = cmd_info_0_upload_0_qs;
Tests: T1 T2 T4
21490 1/1 reg_rdata_next[25] = cmd_info_0_busy_0_qs;
Tests: T1 T2 T4
21491 1/1 reg_rdata_next[31] = cmd_info_0_valid_0_qs;
Tests: T1 T2 T4
21492 end
21493
21494 addr_hit[32]: begin
21495 1/1 reg_rdata_next[7:0] = cmd_info_1_opcode_1_qs;
Tests: T1 T2 T4
21496 1/1 reg_rdata_next[9:8] = cmd_info_1_addr_mode_1_qs;
Tests: T1 T2 T4
21497 1/1 reg_rdata_next[10] = cmd_info_1_addr_swap_en_1_qs;
Tests: T1 T2 T4
21498 1/1 reg_rdata_next[11] = cmd_info_1_mbyte_en_1_qs;
Tests: T1 T2 T4
21499 1/1 reg_rdata_next[14:12] = cmd_info_1_dummy_size_1_qs;
Tests: T1 T2 T4
21500 1/1 reg_rdata_next[15] = cmd_info_1_dummy_en_1_qs;
Tests: T1 T2 T4
21501 1/1 reg_rdata_next[19:16] = cmd_info_1_payload_en_1_qs;
Tests: T1 T2 T4
21502 1/1 reg_rdata_next[20] = cmd_info_1_payload_dir_1_qs;
Tests: T1 T2 T4
21503 1/1 reg_rdata_next[21] = cmd_info_1_payload_swap_en_1_qs;
Tests: T1 T2 T4
21504 1/1 reg_rdata_next[23:22] = cmd_info_1_read_pipeline_mode_1_qs;
Tests: T1 T2 T4
21505 1/1 reg_rdata_next[24] = cmd_info_1_upload_1_qs;
Tests: T1 T2 T4
21506 1/1 reg_rdata_next[25] = cmd_info_1_busy_1_qs;
Tests: T1 T2 T4
21507 1/1 reg_rdata_next[31] = cmd_info_1_valid_1_qs;
Tests: T1 T2 T4
21508 end
21509
21510 addr_hit[33]: begin
21511 1/1 reg_rdata_next[7:0] = cmd_info_2_opcode_2_qs;
Tests: T1 T2 T4
21512 1/1 reg_rdata_next[9:8] = cmd_info_2_addr_mode_2_qs;
Tests: T1 T2 T4
21513 1/1 reg_rdata_next[10] = cmd_info_2_addr_swap_en_2_qs;
Tests: T1 T2 T4
21514 1/1 reg_rdata_next[11] = cmd_info_2_mbyte_en_2_qs;
Tests: T1 T2 T4
21515 1/1 reg_rdata_next[14:12] = cmd_info_2_dummy_size_2_qs;
Tests: T1 T2 T4
21516 1/1 reg_rdata_next[15] = cmd_info_2_dummy_en_2_qs;
Tests: T1 T2 T4
21517 1/1 reg_rdata_next[19:16] = cmd_info_2_payload_en_2_qs;
Tests: T1 T2 T4
21518 1/1 reg_rdata_next[20] = cmd_info_2_payload_dir_2_qs;
Tests: T1 T2 T4
21519 1/1 reg_rdata_next[21] = cmd_info_2_payload_swap_en_2_qs;
Tests: T1 T2 T4
21520 1/1 reg_rdata_next[23:22] = cmd_info_2_read_pipeline_mode_2_qs;
Tests: T1 T2 T4
21521 1/1 reg_rdata_next[24] = cmd_info_2_upload_2_qs;
Tests: T1 T2 T4
21522 1/1 reg_rdata_next[25] = cmd_info_2_busy_2_qs;
Tests: T1 T2 T4
21523 1/1 reg_rdata_next[31] = cmd_info_2_valid_2_qs;
Tests: T1 T2 T4
21524 end
21525
21526 addr_hit[34]: begin
21527 1/1 reg_rdata_next[7:0] = cmd_info_3_opcode_3_qs;
Tests: T1 T2 T4
21528 1/1 reg_rdata_next[9:8] = cmd_info_3_addr_mode_3_qs;
Tests: T1 T2 T4
21529 1/1 reg_rdata_next[10] = cmd_info_3_addr_swap_en_3_qs;
Tests: T1 T2 T4
21530 1/1 reg_rdata_next[11] = cmd_info_3_mbyte_en_3_qs;
Tests: T1 T2 T4
21531 1/1 reg_rdata_next[14:12] = cmd_info_3_dummy_size_3_qs;
Tests: T1 T2 T4
21532 1/1 reg_rdata_next[15] = cmd_info_3_dummy_en_3_qs;
Tests: T1 T2 T4
21533 1/1 reg_rdata_next[19:16] = cmd_info_3_payload_en_3_qs;
Tests: T1 T2 T4
21534 1/1 reg_rdata_next[20] = cmd_info_3_payload_dir_3_qs;
Tests: T1 T2 T4
21535 1/1 reg_rdata_next[21] = cmd_info_3_payload_swap_en_3_qs;
Tests: T1 T2 T4
21536 1/1 reg_rdata_next[23:22] = cmd_info_3_read_pipeline_mode_3_qs;
Tests: T1 T2 T4
21537 1/1 reg_rdata_next[24] = cmd_info_3_upload_3_qs;
Tests: T1 T2 T4
21538 1/1 reg_rdata_next[25] = cmd_info_3_busy_3_qs;
Tests: T1 T2 T4
21539 1/1 reg_rdata_next[31] = cmd_info_3_valid_3_qs;
Tests: T1 T2 T4
21540 end
21541
21542 addr_hit[35]: begin
21543 1/1 reg_rdata_next[7:0] = cmd_info_4_opcode_4_qs;
Tests: T1 T2 T4
21544 1/1 reg_rdata_next[9:8] = cmd_info_4_addr_mode_4_qs;
Tests: T1 T2 T4
21545 1/1 reg_rdata_next[10] = cmd_info_4_addr_swap_en_4_qs;
Tests: T1 T2 T4
21546 1/1 reg_rdata_next[11] = cmd_info_4_mbyte_en_4_qs;
Tests: T1 T2 T4
21547 1/1 reg_rdata_next[14:12] = cmd_info_4_dummy_size_4_qs;
Tests: T1 T2 T4
21548 1/1 reg_rdata_next[15] = cmd_info_4_dummy_en_4_qs;
Tests: T1 T2 T4
21549 1/1 reg_rdata_next[19:16] = cmd_info_4_payload_en_4_qs;
Tests: T1 T2 T4
21550 1/1 reg_rdata_next[20] = cmd_info_4_payload_dir_4_qs;
Tests: T1 T2 T4
21551 1/1 reg_rdata_next[21] = cmd_info_4_payload_swap_en_4_qs;
Tests: T1 T2 T4
21552 1/1 reg_rdata_next[23:22] = cmd_info_4_read_pipeline_mode_4_qs;
Tests: T1 T2 T4
21553 1/1 reg_rdata_next[24] = cmd_info_4_upload_4_qs;
Tests: T1 T2 T4
21554 1/1 reg_rdata_next[25] = cmd_info_4_busy_4_qs;
Tests: T1 T2 T4
21555 1/1 reg_rdata_next[31] = cmd_info_4_valid_4_qs;
Tests: T1 T2 T4
21556 end
21557
21558 addr_hit[36]: begin
21559 1/1 reg_rdata_next[7:0] = cmd_info_5_opcode_5_qs;
Tests: T1 T2 T4
21560 1/1 reg_rdata_next[9:8] = cmd_info_5_addr_mode_5_qs;
Tests: T1 T2 T4
21561 1/1 reg_rdata_next[10] = cmd_info_5_addr_swap_en_5_qs;
Tests: T1 T2 T4
21562 1/1 reg_rdata_next[11] = cmd_info_5_mbyte_en_5_qs;
Tests: T1 T2 T4
21563 1/1 reg_rdata_next[14:12] = cmd_info_5_dummy_size_5_qs;
Tests: T1 T2 T4
21564 1/1 reg_rdata_next[15] = cmd_info_5_dummy_en_5_qs;
Tests: T1 T2 T4
21565 1/1 reg_rdata_next[19:16] = cmd_info_5_payload_en_5_qs;
Tests: T1 T2 T4
21566 1/1 reg_rdata_next[20] = cmd_info_5_payload_dir_5_qs;
Tests: T1 T2 T4
21567 1/1 reg_rdata_next[21] = cmd_info_5_payload_swap_en_5_qs;
Tests: T1 T2 T4
21568 1/1 reg_rdata_next[23:22] = cmd_info_5_read_pipeline_mode_5_qs;
Tests: T1 T2 T4
21569 1/1 reg_rdata_next[24] = cmd_info_5_upload_5_qs;
Tests: T1 T2 T4
21570 1/1 reg_rdata_next[25] = cmd_info_5_busy_5_qs;
Tests: T1 T2 T4
21571 1/1 reg_rdata_next[31] = cmd_info_5_valid_5_qs;
Tests: T1 T2 T4
21572 end
21573
21574 addr_hit[37]: begin
21575 1/1 reg_rdata_next[7:0] = cmd_info_6_opcode_6_qs;
Tests: T1 T2 T4
21576 1/1 reg_rdata_next[9:8] = cmd_info_6_addr_mode_6_qs;
Tests: T1 T2 T4
21577 1/1 reg_rdata_next[10] = cmd_info_6_addr_swap_en_6_qs;
Tests: T1 T2 T4
21578 1/1 reg_rdata_next[11] = cmd_info_6_mbyte_en_6_qs;
Tests: T1 T2 T4
21579 1/1 reg_rdata_next[14:12] = cmd_info_6_dummy_size_6_qs;
Tests: T1 T2 T4
21580 1/1 reg_rdata_next[15] = cmd_info_6_dummy_en_6_qs;
Tests: T1 T2 T4
21581 1/1 reg_rdata_next[19:16] = cmd_info_6_payload_en_6_qs;
Tests: T1 T2 T4
21582 1/1 reg_rdata_next[20] = cmd_info_6_payload_dir_6_qs;
Tests: T1 T2 T4
21583 1/1 reg_rdata_next[21] = cmd_info_6_payload_swap_en_6_qs;
Tests: T1 T2 T4
21584 1/1 reg_rdata_next[23:22] = cmd_info_6_read_pipeline_mode_6_qs;
Tests: T1 T2 T4
21585 1/1 reg_rdata_next[24] = cmd_info_6_upload_6_qs;
Tests: T1 T2 T4
21586 1/1 reg_rdata_next[25] = cmd_info_6_busy_6_qs;
Tests: T1 T2 T4
21587 1/1 reg_rdata_next[31] = cmd_info_6_valid_6_qs;
Tests: T1 T2 T4
21588 end
21589
21590 addr_hit[38]: begin
21591 1/1 reg_rdata_next[7:0] = cmd_info_7_opcode_7_qs;
Tests: T1 T2 T4
21592 1/1 reg_rdata_next[9:8] = cmd_info_7_addr_mode_7_qs;
Tests: T1 T2 T4
21593 1/1 reg_rdata_next[10] = cmd_info_7_addr_swap_en_7_qs;
Tests: T1 T2 T4
21594 1/1 reg_rdata_next[11] = cmd_info_7_mbyte_en_7_qs;
Tests: T1 T2 T4
21595 1/1 reg_rdata_next[14:12] = cmd_info_7_dummy_size_7_qs;
Tests: T1 T2 T4
21596 1/1 reg_rdata_next[15] = cmd_info_7_dummy_en_7_qs;
Tests: T1 T2 T4
21597 1/1 reg_rdata_next[19:16] = cmd_info_7_payload_en_7_qs;
Tests: T1 T2 T4
21598 1/1 reg_rdata_next[20] = cmd_info_7_payload_dir_7_qs;
Tests: T1 T2 T4
21599 1/1 reg_rdata_next[21] = cmd_info_7_payload_swap_en_7_qs;
Tests: T1 T2 T4
21600 1/1 reg_rdata_next[23:22] = cmd_info_7_read_pipeline_mode_7_qs;
Tests: T1 T2 T4
21601 1/1 reg_rdata_next[24] = cmd_info_7_upload_7_qs;
Tests: T1 T2 T4
21602 1/1 reg_rdata_next[25] = cmd_info_7_busy_7_qs;
Tests: T1 T2 T4
21603 1/1 reg_rdata_next[31] = cmd_info_7_valid_7_qs;
Tests: T1 T2 T4
21604 end
21605
21606 addr_hit[39]: begin
21607 1/1 reg_rdata_next[7:0] = cmd_info_8_opcode_8_qs;
Tests: T1 T2 T3
21608 1/1 reg_rdata_next[9:8] = cmd_info_8_addr_mode_8_qs;
Tests: T1 T2 T3
21609 1/1 reg_rdata_next[10] = cmd_info_8_addr_swap_en_8_qs;
Tests: T1 T2 T3
21610 1/1 reg_rdata_next[11] = cmd_info_8_mbyte_en_8_qs;
Tests: T1 T2 T3
21611 1/1 reg_rdata_next[14:12] = cmd_info_8_dummy_size_8_qs;
Tests: T1 T2 T3
21612 1/1 reg_rdata_next[15] = cmd_info_8_dummy_en_8_qs;
Tests: T1 T2 T3
21613 1/1 reg_rdata_next[19:16] = cmd_info_8_payload_en_8_qs;
Tests: T1 T2 T3
21614 1/1 reg_rdata_next[20] = cmd_info_8_payload_dir_8_qs;
Tests: T1 T2 T3
21615 1/1 reg_rdata_next[21] = cmd_info_8_payload_swap_en_8_qs;
Tests: T1 T2 T3
21616 1/1 reg_rdata_next[23:22] = cmd_info_8_read_pipeline_mode_8_qs;
Tests: T1 T2 T3
21617 1/1 reg_rdata_next[24] = cmd_info_8_upload_8_qs;
Tests: T1 T2 T3
21618 1/1 reg_rdata_next[25] = cmd_info_8_busy_8_qs;
Tests: T1 T2 T3
21619 1/1 reg_rdata_next[31] = cmd_info_8_valid_8_qs;
Tests: T1 T2 T3
21620 end
21621
21622 addr_hit[40]: begin
21623 1/1 reg_rdata_next[7:0] = cmd_info_9_opcode_9_qs;
Tests: T1 T2 T4
21624 1/1 reg_rdata_next[9:8] = cmd_info_9_addr_mode_9_qs;
Tests: T1 T2 T4
21625 1/1 reg_rdata_next[10] = cmd_info_9_addr_swap_en_9_qs;
Tests: T1 T2 T4
21626 1/1 reg_rdata_next[11] = cmd_info_9_mbyte_en_9_qs;
Tests: T1 T2 T4
21627 1/1 reg_rdata_next[14:12] = cmd_info_9_dummy_size_9_qs;
Tests: T1 T2 T4
21628 1/1 reg_rdata_next[15] = cmd_info_9_dummy_en_9_qs;
Tests: T1 T2 T4
21629 1/1 reg_rdata_next[19:16] = cmd_info_9_payload_en_9_qs;
Tests: T1 T2 T4
21630 1/1 reg_rdata_next[20] = cmd_info_9_payload_dir_9_qs;
Tests: T1 T2 T4
21631 1/1 reg_rdata_next[21] = cmd_info_9_payload_swap_en_9_qs;
Tests: T1 T2 T4
21632 1/1 reg_rdata_next[23:22] = cmd_info_9_read_pipeline_mode_9_qs;
Tests: T1 T2 T4
21633 1/1 reg_rdata_next[24] = cmd_info_9_upload_9_qs;
Tests: T1 T2 T4
21634 1/1 reg_rdata_next[25] = cmd_info_9_busy_9_qs;
Tests: T1 T2 T4
21635 1/1 reg_rdata_next[31] = cmd_info_9_valid_9_qs;
Tests: T1 T2 T4
21636 end
21637
21638 addr_hit[41]: begin
21639 1/1 reg_rdata_next[7:0] = cmd_info_10_opcode_10_qs;
Tests: T1 T2 T4
21640 1/1 reg_rdata_next[9:8] = cmd_info_10_addr_mode_10_qs;
Tests: T1 T2 T4
21641 1/1 reg_rdata_next[10] = cmd_info_10_addr_swap_en_10_qs;
Tests: T1 T2 T4
21642 1/1 reg_rdata_next[11] = cmd_info_10_mbyte_en_10_qs;
Tests: T1 T2 T4
21643 1/1 reg_rdata_next[14:12] = cmd_info_10_dummy_size_10_qs;
Tests: T1 T2 T4
21644 1/1 reg_rdata_next[15] = cmd_info_10_dummy_en_10_qs;
Tests: T1 T2 T4
21645 1/1 reg_rdata_next[19:16] = cmd_info_10_payload_en_10_qs;
Tests: T1 T2 T4
21646 1/1 reg_rdata_next[20] = cmd_info_10_payload_dir_10_qs;
Tests: T1 T2 T4
21647 1/1 reg_rdata_next[21] = cmd_info_10_payload_swap_en_10_qs;
Tests: T1 T2 T4
21648 1/1 reg_rdata_next[23:22] = cmd_info_10_read_pipeline_mode_10_qs;
Tests: T1 T2 T4
21649 1/1 reg_rdata_next[24] = cmd_info_10_upload_10_qs;
Tests: T1 T2 T4
21650 1/1 reg_rdata_next[25] = cmd_info_10_busy_10_qs;
Tests: T1 T2 T4
21651 1/1 reg_rdata_next[31] = cmd_info_10_valid_10_qs;
Tests: T1 T2 T4
21652 end
21653
21654 addr_hit[42]: begin
21655 1/1 reg_rdata_next[7:0] = cmd_info_11_opcode_11_qs;
Tests: T1 T2 T4
21656 1/1 reg_rdata_next[9:8] = cmd_info_11_addr_mode_11_qs;
Tests: T1 T2 T4
21657 1/1 reg_rdata_next[10] = cmd_info_11_addr_swap_en_11_qs;
Tests: T1 T2 T4
21658 1/1 reg_rdata_next[11] = cmd_info_11_mbyte_en_11_qs;
Tests: T1 T2 T4
21659 1/1 reg_rdata_next[14:12] = cmd_info_11_dummy_size_11_qs;
Tests: T1 T2 T4
21660 1/1 reg_rdata_next[15] = cmd_info_11_dummy_en_11_qs;
Tests: T1 T2 T4
21661 1/1 reg_rdata_next[19:16] = cmd_info_11_payload_en_11_qs;
Tests: T1 T2 T4
21662 1/1 reg_rdata_next[20] = cmd_info_11_payload_dir_11_qs;
Tests: T1 T2 T4
21663 1/1 reg_rdata_next[21] = cmd_info_11_payload_swap_en_11_qs;
Tests: T1 T2 T4
21664 1/1 reg_rdata_next[23:22] = cmd_info_11_read_pipeline_mode_11_qs;
Tests: T1 T2 T4
21665 1/1 reg_rdata_next[24] = cmd_info_11_upload_11_qs;
Tests: T1 T2 T4
21666 1/1 reg_rdata_next[25] = cmd_info_11_busy_11_qs;
Tests: T1 T2 T4
21667 1/1 reg_rdata_next[31] = cmd_info_11_valid_11_qs;
Tests: T1 T2 T4
21668 end
21669
21670 addr_hit[43]: begin
21671 1/1 reg_rdata_next[7:0] = cmd_info_12_opcode_12_qs;
Tests: T1 T2 T4
21672 1/1 reg_rdata_next[9:8] = cmd_info_12_addr_mode_12_qs;
Tests: T1 T2 T4
21673 1/1 reg_rdata_next[10] = cmd_info_12_addr_swap_en_12_qs;
Tests: T1 T2 T4
21674 1/1 reg_rdata_next[11] = cmd_info_12_mbyte_en_12_qs;
Tests: T1 T2 T4
21675 1/1 reg_rdata_next[14:12] = cmd_info_12_dummy_size_12_qs;
Tests: T1 T2 T4
21676 1/1 reg_rdata_next[15] = cmd_info_12_dummy_en_12_qs;
Tests: T1 T2 T4
21677 1/1 reg_rdata_next[19:16] = cmd_info_12_payload_en_12_qs;
Tests: T1 T2 T4
21678 1/1 reg_rdata_next[20] = cmd_info_12_payload_dir_12_qs;
Tests: T1 T2 T4
21679 1/1 reg_rdata_next[21] = cmd_info_12_payload_swap_en_12_qs;
Tests: T1 T2 T4
21680 1/1 reg_rdata_next[23:22] = cmd_info_12_read_pipeline_mode_12_qs;
Tests: T1 T2 T4
21681 1/1 reg_rdata_next[24] = cmd_info_12_upload_12_qs;
Tests: T1 T2 T4
21682 1/1 reg_rdata_next[25] = cmd_info_12_busy_12_qs;
Tests: T1 T2 T4
21683 1/1 reg_rdata_next[31] = cmd_info_12_valid_12_qs;
Tests: T1 T2 T4
21684 end
21685
21686 addr_hit[44]: begin
21687 1/1 reg_rdata_next[7:0] = cmd_info_13_opcode_13_qs;
Tests: T1 T2 T4
21688 1/1 reg_rdata_next[9:8] = cmd_info_13_addr_mode_13_qs;
Tests: T1 T2 T4
21689 1/1 reg_rdata_next[10] = cmd_info_13_addr_swap_en_13_qs;
Tests: T1 T2 T4
21690 1/1 reg_rdata_next[11] = cmd_info_13_mbyte_en_13_qs;
Tests: T1 T2 T4
21691 1/1 reg_rdata_next[14:12] = cmd_info_13_dummy_size_13_qs;
Tests: T1 T2 T4
21692 1/1 reg_rdata_next[15] = cmd_info_13_dummy_en_13_qs;
Tests: T1 T2 T4
21693 1/1 reg_rdata_next[19:16] = cmd_info_13_payload_en_13_qs;
Tests: T1 T2 T4
21694 1/1 reg_rdata_next[20] = cmd_info_13_payload_dir_13_qs;
Tests: T1 T2 T4
21695 1/1 reg_rdata_next[21] = cmd_info_13_payload_swap_en_13_qs;
Tests: T1 T2 T4
21696 1/1 reg_rdata_next[23:22] = cmd_info_13_read_pipeline_mode_13_qs;
Tests: T1 T2 T4
21697 1/1 reg_rdata_next[24] = cmd_info_13_upload_13_qs;
Tests: T1 T2 T4
21698 1/1 reg_rdata_next[25] = cmd_info_13_busy_13_qs;
Tests: T1 T2 T4
21699 1/1 reg_rdata_next[31] = cmd_info_13_valid_13_qs;
Tests: T1 T2 T4
21700 end
21701
21702 addr_hit[45]: begin
21703 1/1 reg_rdata_next[7:0] = cmd_info_14_opcode_14_qs;
Tests: T1 T2 T4
21704 1/1 reg_rdata_next[9:8] = cmd_info_14_addr_mode_14_qs;
Tests: T1 T2 T4
21705 1/1 reg_rdata_next[10] = cmd_info_14_addr_swap_en_14_qs;
Tests: T1 T2 T4
21706 1/1 reg_rdata_next[11] = cmd_info_14_mbyte_en_14_qs;
Tests: T1 T2 T4
21707 1/1 reg_rdata_next[14:12] = cmd_info_14_dummy_size_14_qs;
Tests: T1 T2 T4
21708 1/1 reg_rdata_next[15] = cmd_info_14_dummy_en_14_qs;
Tests: T1 T2 T4
21709 1/1 reg_rdata_next[19:16] = cmd_info_14_payload_en_14_qs;
Tests: T1 T2 T4
21710 1/1 reg_rdata_next[20] = cmd_info_14_payload_dir_14_qs;
Tests: T1 T2 T4
21711 1/1 reg_rdata_next[21] = cmd_info_14_payload_swap_en_14_qs;
Tests: T1 T2 T4
21712 1/1 reg_rdata_next[23:22] = cmd_info_14_read_pipeline_mode_14_qs;
Tests: T1 T2 T4
21713 1/1 reg_rdata_next[24] = cmd_info_14_upload_14_qs;
Tests: T1 T2 T4
21714 1/1 reg_rdata_next[25] = cmd_info_14_busy_14_qs;
Tests: T1 T2 T4
21715 1/1 reg_rdata_next[31] = cmd_info_14_valid_14_qs;
Tests: T1 T2 T4
21716 end
21717
21718 addr_hit[46]: begin
21719 1/1 reg_rdata_next[7:0] = cmd_info_15_opcode_15_qs;
Tests: T1 T2 T4
21720 1/1 reg_rdata_next[9:8] = cmd_info_15_addr_mode_15_qs;
Tests: T1 T2 T4
21721 1/1 reg_rdata_next[10] = cmd_info_15_addr_swap_en_15_qs;
Tests: T1 T2 T4
21722 1/1 reg_rdata_next[11] = cmd_info_15_mbyte_en_15_qs;
Tests: T1 T2 T4
21723 1/1 reg_rdata_next[14:12] = cmd_info_15_dummy_size_15_qs;
Tests: T1 T2 T4
21724 1/1 reg_rdata_next[15] = cmd_info_15_dummy_en_15_qs;
Tests: T1 T2 T4
21725 1/1 reg_rdata_next[19:16] = cmd_info_15_payload_en_15_qs;
Tests: T1 T2 T4
21726 1/1 reg_rdata_next[20] = cmd_info_15_payload_dir_15_qs;
Tests: T1 T2 T4
21727 1/1 reg_rdata_next[21] = cmd_info_15_payload_swap_en_15_qs;
Tests: T1 T2 T4
21728 1/1 reg_rdata_next[23:22] = cmd_info_15_read_pipeline_mode_15_qs;
Tests: T1 T2 T4
21729 1/1 reg_rdata_next[24] = cmd_info_15_upload_15_qs;
Tests: T1 T2 T4
21730 1/1 reg_rdata_next[25] = cmd_info_15_busy_15_qs;
Tests: T1 T2 T4
21731 1/1 reg_rdata_next[31] = cmd_info_15_valid_15_qs;
Tests: T1 T2 T4
21732 end
21733
21734 addr_hit[47]: begin
21735 1/1 reg_rdata_next[7:0] = cmd_info_16_opcode_16_qs;
Tests: T1 T2 T4
21736 1/1 reg_rdata_next[9:8] = cmd_info_16_addr_mode_16_qs;
Tests: T1 T2 T4
21737 1/1 reg_rdata_next[10] = cmd_info_16_addr_swap_en_16_qs;
Tests: T1 T2 T4
21738 1/1 reg_rdata_next[11] = cmd_info_16_mbyte_en_16_qs;
Tests: T1 T2 T4
21739 1/1 reg_rdata_next[14:12] = cmd_info_16_dummy_size_16_qs;
Tests: T1 T2 T4
21740 1/1 reg_rdata_next[15] = cmd_info_16_dummy_en_16_qs;
Tests: T1 T2 T4
21741 1/1 reg_rdata_next[19:16] = cmd_info_16_payload_en_16_qs;
Tests: T1 T2 T4
21742 1/1 reg_rdata_next[20] = cmd_info_16_payload_dir_16_qs;
Tests: T1 T2 T4
21743 1/1 reg_rdata_next[21] = cmd_info_16_payload_swap_en_16_qs;
Tests: T1 T2 T4
21744 1/1 reg_rdata_next[23:22] = cmd_info_16_read_pipeline_mode_16_qs;
Tests: T1 T2 T4
21745 1/1 reg_rdata_next[24] = cmd_info_16_upload_16_qs;
Tests: T1 T2 T4
21746 1/1 reg_rdata_next[25] = cmd_info_16_busy_16_qs;
Tests: T1 T2 T4
21747 1/1 reg_rdata_next[31] = cmd_info_16_valid_16_qs;
Tests: T1 T2 T4
21748 end
21749
21750 addr_hit[48]: begin
21751 1/1 reg_rdata_next[7:0] = cmd_info_17_opcode_17_qs;
Tests: T1 T2 T4
21752 1/1 reg_rdata_next[9:8] = cmd_info_17_addr_mode_17_qs;
Tests: T1 T2 T4
21753 1/1 reg_rdata_next[10] = cmd_info_17_addr_swap_en_17_qs;
Tests: T1 T2 T4
21754 1/1 reg_rdata_next[11] = cmd_info_17_mbyte_en_17_qs;
Tests: T1 T2 T4
21755 1/1 reg_rdata_next[14:12] = cmd_info_17_dummy_size_17_qs;
Tests: T1 T2 T4
21756 1/1 reg_rdata_next[15] = cmd_info_17_dummy_en_17_qs;
Tests: T1 T2 T4
21757 1/1 reg_rdata_next[19:16] = cmd_info_17_payload_en_17_qs;
Tests: T1 T2 T4
21758 1/1 reg_rdata_next[20] = cmd_info_17_payload_dir_17_qs;
Tests: T1 T2 T4
21759 1/1 reg_rdata_next[21] = cmd_info_17_payload_swap_en_17_qs;
Tests: T1 T2 T4
21760 1/1 reg_rdata_next[23:22] = cmd_info_17_read_pipeline_mode_17_qs;
Tests: T1 T2 T4
21761 1/1 reg_rdata_next[24] = cmd_info_17_upload_17_qs;
Tests: T1 T2 T4
21762 1/1 reg_rdata_next[25] = cmd_info_17_busy_17_qs;
Tests: T1 T2 T4
21763 1/1 reg_rdata_next[31] = cmd_info_17_valid_17_qs;
Tests: T1 T2 T4
21764 end
21765
21766 addr_hit[49]: begin
21767 1/1 reg_rdata_next[7:0] = cmd_info_18_opcode_18_qs;
Tests: T1 T2 T4
21768 1/1 reg_rdata_next[9:8] = cmd_info_18_addr_mode_18_qs;
Tests: T1 T2 T4
21769 1/1 reg_rdata_next[10] = cmd_info_18_addr_swap_en_18_qs;
Tests: T1 T2 T4
21770 1/1 reg_rdata_next[11] = cmd_info_18_mbyte_en_18_qs;
Tests: T1 T2 T4
21771 1/1 reg_rdata_next[14:12] = cmd_info_18_dummy_size_18_qs;
Tests: T1 T2 T4
21772 1/1 reg_rdata_next[15] = cmd_info_18_dummy_en_18_qs;
Tests: T1 T2 T4
21773 1/1 reg_rdata_next[19:16] = cmd_info_18_payload_en_18_qs;
Tests: T1 T2 T4
21774 1/1 reg_rdata_next[20] = cmd_info_18_payload_dir_18_qs;
Tests: T1 T2 T4
21775 1/1 reg_rdata_next[21] = cmd_info_18_payload_swap_en_18_qs;
Tests: T1 T2 T4
21776 1/1 reg_rdata_next[23:22] = cmd_info_18_read_pipeline_mode_18_qs;
Tests: T1 T2 T4
21777 1/1 reg_rdata_next[24] = cmd_info_18_upload_18_qs;
Tests: T1 T2 T4
21778 1/1 reg_rdata_next[25] = cmd_info_18_busy_18_qs;
Tests: T1 T2 T4
21779 1/1 reg_rdata_next[31] = cmd_info_18_valid_18_qs;
Tests: T1 T2 T4
21780 end
21781
21782 addr_hit[50]: begin
21783 1/1 reg_rdata_next[7:0] = cmd_info_19_opcode_19_qs;
Tests: T1 T2 T4
21784 1/1 reg_rdata_next[9:8] = cmd_info_19_addr_mode_19_qs;
Tests: T1 T2 T4
21785 1/1 reg_rdata_next[10] = cmd_info_19_addr_swap_en_19_qs;
Tests: T1 T2 T4
21786 1/1 reg_rdata_next[11] = cmd_info_19_mbyte_en_19_qs;
Tests: T1 T2 T4
21787 1/1 reg_rdata_next[14:12] = cmd_info_19_dummy_size_19_qs;
Tests: T1 T2 T4
21788 1/1 reg_rdata_next[15] = cmd_info_19_dummy_en_19_qs;
Tests: T1 T2 T4
21789 1/1 reg_rdata_next[19:16] = cmd_info_19_payload_en_19_qs;
Tests: T1 T2 T4
21790 1/1 reg_rdata_next[20] = cmd_info_19_payload_dir_19_qs;
Tests: T1 T2 T4
21791 1/1 reg_rdata_next[21] = cmd_info_19_payload_swap_en_19_qs;
Tests: T1 T2 T4
21792 1/1 reg_rdata_next[23:22] = cmd_info_19_read_pipeline_mode_19_qs;
Tests: T1 T2 T4
21793 1/1 reg_rdata_next[24] = cmd_info_19_upload_19_qs;
Tests: T1 T2 T4
21794 1/1 reg_rdata_next[25] = cmd_info_19_busy_19_qs;
Tests: T1 T2 T4
21795 1/1 reg_rdata_next[31] = cmd_info_19_valid_19_qs;
Tests: T1 T2 T4
21796 end
21797
21798 addr_hit[51]: begin
21799 1/1 reg_rdata_next[7:0] = cmd_info_20_opcode_20_qs;
Tests: T1 T2 T4
21800 1/1 reg_rdata_next[9:8] = cmd_info_20_addr_mode_20_qs;
Tests: T1 T2 T4
21801 1/1 reg_rdata_next[10] = cmd_info_20_addr_swap_en_20_qs;
Tests: T1 T2 T4
21802 1/1 reg_rdata_next[11] = cmd_info_20_mbyte_en_20_qs;
Tests: T1 T2 T4
21803 1/1 reg_rdata_next[14:12] = cmd_info_20_dummy_size_20_qs;
Tests: T1 T2 T4
21804 1/1 reg_rdata_next[15] = cmd_info_20_dummy_en_20_qs;
Tests: T1 T2 T4
21805 1/1 reg_rdata_next[19:16] = cmd_info_20_payload_en_20_qs;
Tests: T1 T2 T4
21806 1/1 reg_rdata_next[20] = cmd_info_20_payload_dir_20_qs;
Tests: T1 T2 T4
21807 1/1 reg_rdata_next[21] = cmd_info_20_payload_swap_en_20_qs;
Tests: T1 T2 T4
21808 1/1 reg_rdata_next[23:22] = cmd_info_20_read_pipeline_mode_20_qs;
Tests: T1 T2 T4
21809 1/1 reg_rdata_next[24] = cmd_info_20_upload_20_qs;
Tests: T1 T2 T4
21810 1/1 reg_rdata_next[25] = cmd_info_20_busy_20_qs;
Tests: T1 T2 T4
21811 1/1 reg_rdata_next[31] = cmd_info_20_valid_20_qs;
Tests: T1 T2 T4
21812 end
21813
21814 addr_hit[52]: begin
21815 1/1 reg_rdata_next[7:0] = cmd_info_21_opcode_21_qs;
Tests: T1 T2 T4
21816 1/1 reg_rdata_next[9:8] = cmd_info_21_addr_mode_21_qs;
Tests: T1 T2 T4
21817 1/1 reg_rdata_next[10] = cmd_info_21_addr_swap_en_21_qs;
Tests: T1 T2 T4
21818 1/1 reg_rdata_next[11] = cmd_info_21_mbyte_en_21_qs;
Tests: T1 T2 T4
21819 1/1 reg_rdata_next[14:12] = cmd_info_21_dummy_size_21_qs;
Tests: T1 T2 T4
21820 1/1 reg_rdata_next[15] = cmd_info_21_dummy_en_21_qs;
Tests: T1 T2 T4
21821 1/1 reg_rdata_next[19:16] = cmd_info_21_payload_en_21_qs;
Tests: T1 T2 T4
21822 1/1 reg_rdata_next[20] = cmd_info_21_payload_dir_21_qs;
Tests: T1 T2 T4
21823 1/1 reg_rdata_next[21] = cmd_info_21_payload_swap_en_21_qs;
Tests: T1 T2 T4
21824 1/1 reg_rdata_next[23:22] = cmd_info_21_read_pipeline_mode_21_qs;
Tests: T1 T2 T4
21825 1/1 reg_rdata_next[24] = cmd_info_21_upload_21_qs;
Tests: T1 T2 T4
21826 1/1 reg_rdata_next[25] = cmd_info_21_busy_21_qs;
Tests: T1 T2 T4
21827 1/1 reg_rdata_next[31] = cmd_info_21_valid_21_qs;
Tests: T1 T2 T4
21828 end
21829
21830 addr_hit[53]: begin
21831 1/1 reg_rdata_next[7:0] = cmd_info_22_opcode_22_qs;
Tests: T1 T2 T4
21832 1/1 reg_rdata_next[9:8] = cmd_info_22_addr_mode_22_qs;
Tests: T1 T2 T4
21833 1/1 reg_rdata_next[10] = cmd_info_22_addr_swap_en_22_qs;
Tests: T1 T2 T4
21834 1/1 reg_rdata_next[11] = cmd_info_22_mbyte_en_22_qs;
Tests: T1 T2 T4
21835 1/1 reg_rdata_next[14:12] = cmd_info_22_dummy_size_22_qs;
Tests: T1 T2 T4
21836 1/1 reg_rdata_next[15] = cmd_info_22_dummy_en_22_qs;
Tests: T1 T2 T4
21837 1/1 reg_rdata_next[19:16] = cmd_info_22_payload_en_22_qs;
Tests: T1 T2 T4
21838 1/1 reg_rdata_next[20] = cmd_info_22_payload_dir_22_qs;
Tests: T1 T2 T4
21839 1/1 reg_rdata_next[21] = cmd_info_22_payload_swap_en_22_qs;
Tests: T1 T2 T4
21840 1/1 reg_rdata_next[23:22] = cmd_info_22_read_pipeline_mode_22_qs;
Tests: T1 T2 T4
21841 1/1 reg_rdata_next[24] = cmd_info_22_upload_22_qs;
Tests: T1 T2 T4
21842 1/1 reg_rdata_next[25] = cmd_info_22_busy_22_qs;
Tests: T1 T2 T4
21843 1/1 reg_rdata_next[31] = cmd_info_22_valid_22_qs;
Tests: T1 T2 T4
21844 end
21845
21846 addr_hit[54]: begin
21847 1/1 reg_rdata_next[7:0] = cmd_info_23_opcode_23_qs;
Tests: T1 T2 T4
21848 1/1 reg_rdata_next[9:8] = cmd_info_23_addr_mode_23_qs;
Tests: T1 T2 T4
21849 1/1 reg_rdata_next[10] = cmd_info_23_addr_swap_en_23_qs;
Tests: T1 T2 T4
21850 1/1 reg_rdata_next[11] = cmd_info_23_mbyte_en_23_qs;
Tests: T1 T2 T4
21851 1/1 reg_rdata_next[14:12] = cmd_info_23_dummy_size_23_qs;
Tests: T1 T2 T4
21852 1/1 reg_rdata_next[15] = cmd_info_23_dummy_en_23_qs;
Tests: T1 T2 T4
21853 1/1 reg_rdata_next[19:16] = cmd_info_23_payload_en_23_qs;
Tests: T1 T2 T4
21854 1/1 reg_rdata_next[20] = cmd_info_23_payload_dir_23_qs;
Tests: T1 T2 T4
21855 1/1 reg_rdata_next[21] = cmd_info_23_payload_swap_en_23_qs;
Tests: T1 T2 T4
21856 1/1 reg_rdata_next[23:22] = cmd_info_23_read_pipeline_mode_23_qs;
Tests: T1 T2 T4
21857 1/1 reg_rdata_next[24] = cmd_info_23_upload_23_qs;
Tests: T1 T2 T4
21858 1/1 reg_rdata_next[25] = cmd_info_23_busy_23_qs;
Tests: T1 T2 T4
21859 1/1 reg_rdata_next[31] = cmd_info_23_valid_23_qs;
Tests: T1 T2 T4
21860 end
21861
21862 addr_hit[55]: begin
21863 1/1 reg_rdata_next[7:0] = cmd_info_en4b_opcode_qs;
Tests: T1 T2 T4
21864 1/1 reg_rdata_next[31] = cmd_info_en4b_valid_qs;
Tests: T1 T2 T4
21865 end
21866
21867 addr_hit[56]: begin
21868 1/1 reg_rdata_next[7:0] = cmd_info_ex4b_opcode_qs;
Tests: T1 T2 T4
21869 1/1 reg_rdata_next[31] = cmd_info_ex4b_valid_qs;
Tests: T1 T2 T4
21870 end
21871
21872 addr_hit[57]: begin
21873 1/1 reg_rdata_next[7:0] = cmd_info_wren_opcode_qs;
Tests: T1 T2 T4
21874 1/1 reg_rdata_next[31] = cmd_info_wren_valid_qs;
Tests: T1 T2 T4
21875 end
21876
21877 addr_hit[58]: begin
21878 1/1 reg_rdata_next[7:0] = cmd_info_wrdi_opcode_qs;
Tests: T1 T2 T4
21879 1/1 reg_rdata_next[31] = cmd_info_wrdi_valid_qs;
Tests: T1 T2 T4
21880 end
21881
21882 addr_hit[59]: begin
21883 1/1 reg_rdata_next[7:0] = tpm_cap_rev_qs;
Tests: T1 T2 T4
21884 1/1 reg_rdata_next[8] = tpm_cap_locality_qs;
Tests: T1 T2 T4
21885 1/1 reg_rdata_next[18:16] = tpm_cap_max_wr_size_qs;
Tests: T1 T2 T4
21886 1/1 reg_rdata_next[22:20] = tpm_cap_max_rd_size_qs;
Tests: T1 T2 T4
21887 end
21888
21889 addr_hit[60]: begin
21890 1/1 reg_rdata_next[0] = tpm_cfg_en_qs;
Tests: T1 T2 T4
21891 1/1 reg_rdata_next[1] = tpm_cfg_tpm_mode_qs;
Tests: T1 T2 T4
21892 1/1 reg_rdata_next[2] = tpm_cfg_hw_reg_dis_qs;
Tests: T1 T2 T4
21893 1/1 reg_rdata_next[3] = tpm_cfg_tpm_reg_chk_dis_qs;
Tests: T1 T2 T4
21894 1/1 reg_rdata_next[4] = tpm_cfg_invalid_locality_qs;
Tests: T1 T2 T4
21895 end
21896
21897 addr_hit[61]: begin
21898 1/1 reg_rdata_next[0] = tpm_status_cmdaddr_notempty_qs;
Tests: T1 T2 T4
21899 1/1 reg_rdata_next[1] = tpm_status_wrfifo_pending_qs;
Tests: T1 T2 T4
21900 1/1 reg_rdata_next[2] = tpm_status_rdfifo_aborted_qs;
Tests: T1 T2 T4
21901 end
21902
21903 addr_hit[62]: begin
21904 1/1 reg_rdata_next[7:0] = tpm_access_0_access_0_qs;
Tests: T1 T2 T4
21905 1/1 reg_rdata_next[15:8] = tpm_access_0_access_1_qs;
Tests: T1 T2 T4
21906 1/1 reg_rdata_next[23:16] = tpm_access_0_access_2_qs;
Tests: T1 T2 T4
21907 1/1 reg_rdata_next[31:24] = tpm_access_0_access_3_qs;
Tests: T1 T2 T4
21908 end
21909
21910 addr_hit[63]: begin
21911 1/1 reg_rdata_next[7:0] = tpm_access_1_qs;
Tests: T1 T2 T4
21912 end
21913
21914 addr_hit[64]: begin
21915 1/1 reg_rdata_next[31:0] = tpm_sts_qs;
Tests: T1 T2 T4
21916 end
21917
21918 addr_hit[65]: begin
21919 1/1 reg_rdata_next[31:0] = tpm_intf_capability_qs;
Tests: T1 T2 T4
21920 end
21921
21922 addr_hit[66]: begin
21923 1/1 reg_rdata_next[31:0] = tpm_int_enable_qs;
Tests: T1 T2 T4
21924 end
21925
21926 addr_hit[67]: begin
21927 1/1 reg_rdata_next[7:0] = tpm_int_vector_qs;
Tests: T1 T2 T4
21928 end
21929
21930 addr_hit[68]: begin
21931 1/1 reg_rdata_next[31:0] = tpm_int_status_qs;
Tests: T1 T2 T4
21932 end
21933
21934 addr_hit[69]: begin
21935 1/1 reg_rdata_next[15:0] = tpm_did_vid_vid_qs;
Tests: T1 T2 T3
21936 1/1 reg_rdata_next[31:16] = tpm_did_vid_did_qs;
Tests: T1 T2 T3
21937 end
21938
21939 addr_hit[70]: begin
21940 1/1 reg_rdata_next[7:0] = tpm_rid_qs;
Tests: T1 T2 T4
21941 end
21942
21943 addr_hit[71]: begin
21944 1/1 reg_rdata_next[23:0] = tpm_cmd_addr_addr_qs;
Tests: T1 T2 T4
21945 1/1 reg_rdata_next[31:24] = tpm_cmd_addr_cmd_qs;
Tests: T1 T2 T4
21946 end
21947
21948 addr_hit[72]: begin
21949 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T4
21950 end
21951
21952 default: begin
21953 reg_rdata_next = '1;
21954 end
21955 endcase
21956 end
21957
21958 // shadow busy
21959 logic shadow_busy;
21960 assign shadow_busy = 1'b0;
21961
21962 // register busy
21963 unreachable assign reg_busy = shadow_busy;
21964
21965 // Unused signal tieoff
21966
21967 // wdata / byte enable are not always fully used
21968 // add a blanket unused statement to handle lint waivers
21969 logic unused_wdata;
21970 logic unused_be;
21971 1/1 assign unused_wdata = ^reg_wdata;
Tests: T1 T2 T3
21972 1/1 assign unused_be = ^reg_be;
Tests: T1 T2 T3