SPI_HOST Simulation Results

Monday May 15 2023 07:07:46 UTC

GitHub Revision: `3d5660d90`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 705130430

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	9.450m	11.393ms	46	50	92.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	17.909us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	16.609us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	465.041us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	36.968us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	31.631us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	16.609us	20	20	100.00
		spi_host_csr_aliasing	3.000s	36.968us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	24.885us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	25.937us	5	5	100.00
V1		TOTAL			111	115	96.52
V2	performance	spi_host_performance	4.000s	128.555us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.633m	19.920ms	49	50	98.00
		spi_host_error_cmd	3.000s	70.460us	50	50	100.00
		spi_host_event	19.700m	106.538ms	50	50	100.00
V2	clock_rate	spi_host_speed	4.617m	25.355ms	48	50	96.00
V2	speed	spi_host_speed	4.617m	25.355ms	48	50	96.00
V2	chip_select_timing	spi_host_speed	4.617m	25.355ms	48	50	96.00
V2	sw_reset	spi_host_sw_reset	3.050m	28.012ms	46	50	92.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	3.275ms	50	50	100.00
V2	cpol_cpha	spi_host_speed	4.617m	25.355ms	48	50	96.00
V2	full_cycle	spi_host_speed	4.617m	25.355ms	48	50	96.00
V2	duplex	spi_host_smoke	9.450m	11.393ms	46	50	92.00
V2	tx_rx_only	spi_host_smoke	9.450m	11.393ms	46	50	92.00
V2	stress_all	spi_host_stress_all	2.617m	3.869ms	48	50	96.00
V2	spien	spi_host_spien	6.683m	19.084ms	49	50	98.00
V2	stall	spi_host_status_stall	11.800m	15.857ms	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	1.217m	3.255ms	50	50	100.00
V2	alert_test	spi_host_alert_test	4.000s	17.191us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	31.941us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	425.085us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	425.085us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	17.909us	5	5	100.00
		spi_host_csr_rw	3.000s	16.609us	20	20	100.00
		spi_host_csr_aliasing	3.000s	36.968us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	62.328us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	17.909us	5	5	100.00
		spi_host_csr_rw	3.000s	16.609us	20	20	100.00
		spi_host_csr_aliasing	3.000s	36.968us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	62.328us	20	20	100.00
V2		TOTAL			679	690	98.41
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	88.735us	20	20	100.00
		spi_host_sec_cm	3.000s	76.150us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	88.735us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			815	830	98.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	9	60.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.08	98.19	95.98	99.74	96.25	95.70	100.00	98.60	91.29

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 8 failures:

Test spi_host_stress_all has 2 failures.

1.spi_host_stress_all.3688573093
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_stress_all/latest/run.log

  UVM_FATAL @ 27016128115 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xebc4a2d4) == 0x0
  UVM_INFO @ 27016128115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.spi_host_stress_all.1072393901
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_stress_all/latest/run.log

  UVM_FATAL @ 21030525183 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x84b45214) == 0x0
  UVM_INFO @ 21030525183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_speed has 1 failures.

8.spi_host_speed.2933489532
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_speed/latest/run.log

  UVM_FATAL @ 119069653888 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd7225114) == 0x0
  UVM_INFO @ 119069653888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_overflow_underflow has 1 failures.

14.spi_host_overflow_underflow.330682289
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_overflow_underflow/latest/run.log

  UVM_FATAL @ 31914589418 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xcb450294) == 0x0
  UVM_INFO @ 31914589418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_smoke has 4 failures.

17.spi_host_smoke.3046437848
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_smoke/latest/run.log

  UVM_FATAL @ 96109482693 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x29baac94) == 0x0
  UVM_INFO @ 96109482693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.spi_host_smoke.2364664598
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_smoke/latest/run.log

  UVM_FATAL @ 117402378492 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x452a3a14) == 0x0
  UVM_INFO @ 117402378492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 4 failures:

Test spi_host_sw_reset has 4 failures.

20.spi_host_sw_reset.1338128160
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 10002890967 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf4c4d114) == 0x0
  UVM_INFO @ 10002890967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.spi_host_sw_reset.1392095084
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 10003085585 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa028a4d4) == 0x0
  UVM_INFO @ 10003085585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=*) == * has 1 failures:
- Test spi_host_speed has 1 failures.
  - 7.spi_host_speed.1700043104
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_speed/latest/run.log
```
  UVM_FATAL @ 10070142481 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0x94635a14) == 0x0
  UVM_INFO @ 10070142481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 23.spi_host_status_stall.1292944439
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_spien has 1 failures.
  - 38.spi_host_spien.1294469386
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 22517583797 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xeff2f714) == 0x1
  UVM_INFO @ 22517583797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```