877a77116
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | spi_host_smoke | 11.000m | 13.905ms | 47 | 50 | 94.00 |
V1 | csr_hw_reset | spi_host_csr_hw_reset | 4.000s | 20.076us | 5 | 5 | 100.00 |
V1 | csr_rw | spi_host_csr_rw | 4.000s | 31.784us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | spi_host_csr_bit_bash | 6.000s | 204.608us | 5 | 5 | 100.00 |
V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 47.714us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 5.000s | 50.063us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 4.000s | 31.784us | 20 | 20 | 100.00 |
spi_host_csr_aliasing | 3.000s | 47.714us | 5 | 5 | 100.00 | ||
V1 | mem_walk | spi_host_mem_walk | 3.000s | 16.045us | 5 | 5 | 100.00 |
V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 23.888us | 5 | 5 | 100.00 |
V1 | TOTAL | 112 | 115 | 97.39 | |||
V2 | performance | spi_host_performance | 4.000s | 87.376us | 50 | 50 | 100.00 |
V2 | error_event_intr | spi_host_overflow_underflow | 3.283m | 4.432ms | 50 | 50 | 100.00 |
spi_host_error_cmd | 5.000s | 18.533us | 50 | 50 | 100.00 | ||
spi_host_event | 23.250m | 33.491ms | 50 | 50 | 100.00 | ||
V2 | clock_rate | spi_host_speed | 5.067m | 94.764ms | 48 | 50 | 96.00 |
V2 | speed | spi_host_speed | 5.067m | 94.764ms | 48 | 50 | 96.00 |
V2 | chip_select_timing | spi_host_speed | 5.067m | 94.764ms | 48 | 50 | 96.00 |
V2 | sw_reset | spi_host_sw_reset | 3.817m | 11.700ms | 46 | 50 | 92.00 |
V2 | passthrough_mode | spi_host_passthrough_mode | 5.000s | 289.147us | 50 | 50 | 100.00 |
V2 | cpol_cpha | spi_host_speed | 5.067m | 94.764ms | 48 | 50 | 96.00 |
V2 | full_cycle | spi_host_speed | 5.067m | 94.764ms | 48 | 50 | 96.00 |
V2 | duplex | spi_host_smoke | 11.000m | 13.905ms | 47 | 50 | 94.00 |
V2 | tx_rx_only | spi_host_smoke | 11.000m | 13.905ms | 47 | 50 | 94.00 |
V2 | stress_all | spi_host_stress_all | 2.517m | 10.202ms | 48 | 50 | 96.00 |
V2 | spien | spi_host_spien | 6.167m | 8.073ms | 49 | 50 | 98.00 |
V2 | stall | spi_host_status_stall | 12.800m | 17.191ms | 50 | 50 | 100.00 |
V2 | Idlecsbactive | spi_host_idlecsbactive | 1.267m | 2.159ms | 50 | 50 | 100.00 |
V2 | alert_test | spi_host_alert_test | 4.000s | 18.459us | 50 | 50 | 100.00 |
V2 | intr_test | spi_host_intr_test | 4.000s | 29.877us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 106.629us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 106.629us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 4.000s | 20.076us | 5 | 5 | 100.00 |
spi_host_csr_rw | 4.000s | 31.784us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 3.000s | 47.714us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 4.000s | 21.836us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | spi_host_csr_hw_reset | 4.000s | 20.076us | 5 | 5 | 100.00 |
spi_host_csr_rw | 4.000s | 31.784us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 3.000s | 47.714us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 4.000s | 21.836us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 681 | 690 | 98.70 | |||
V2S | tl_intg_err | spi_host_tl_intg_err | 4.000s | 88.536us | 20 | 20 | 100.00 |
spi_host_sec_cm | 3.000s | 154.488us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 4.000s | 88.536us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | winbond | winbond | 0 | 0 | -- | ||
V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 818 | 830 | 98.55 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 7 | 87.50 |
V2 | 15 | 15 | 11 | 73.33 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 2 | 0 | 0 | 0.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.08 | 98.19 | 95.98 | 99.74 | 96.25 | 95.70 | 100.00 | 98.60 | 91.29 |
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == *
has 5 failures:
1.spi_host_smoke.218712552
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_smoke/latest/run.log
UVM_FATAL @ 90876379633 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x276cc9d4) == 0x0
UVM_INFO @ 90876379633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.spi_host_smoke.2205626769
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_smoke/latest/run.log
UVM_FATAL @ 147241867622 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe220f114) == 0x0
UVM_INFO @ 147241867622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
8.spi_host_speed.385749013
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_speed/latest/run.log
UVM_FATAL @ 94763854390 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x41212294) == 0x0
UVM_INFO @ 94763854390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.spi_host_speed.4262114034
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_speed/latest/run.log
UVM_FATAL @ 116060968490 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x13b5b454) == 0x0
UVM_INFO @ 116060968490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == *
has 5 failures:
Test spi_host_sw_reset has 3 failures.
9.spi_host_sw_reset.294798575
Line 269, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 11699759177 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x6a5c0cd4) == 0x0
UVM_INFO @ 11699759177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.spi_host_sw_reset.2430778117
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10057920585 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x210a4314) == 0x0
UVM_INFO @ 10057920585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_stress_all has 1 failures.
38.spi_host_stress_all.3217994219
Line 269, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10202401867 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf0885ad4) == 0x0
UVM_INFO @ 10202401867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 1 failures.
46.spi_host_spien.2907545864
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_spien/latest/run.log
UVM_FATAL @ 10021385115 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x76815fd4) == 0x0
UVM_INFO @ 10021385115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == *
has 1 failures:
14.spi_host_sw_reset.2033299278
Line 269, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10384111959 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc93bfa14) == 0x0
UVM_INFO @ 10384111959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == *
has 1 failures:
14.spi_host_stress_all.2572977819
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10074886641 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x1dad1ed4) == 0x0
UVM_INFO @ 10074886641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---