SPI_HOST Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: 12e3b8572e

Branch: os_regression_2024_10_14

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 6.217m 14.805ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 4.000s 29.342us 5 5 100.00
V1 csr_rw spi_host_csr_rw 1.450m 38.215us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 7.000s 238.058us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 4.000s 57.094us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 1.633m 40.189us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 1.450m 38.215us 20 20 100.00
spi_host_csr_aliasing 4.000s 57.094us 5 5 100.00
V1 mem_walk spi_host_mem_walk 3.000s 24.540us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 4.000s 20.739us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 16.000s 52.800us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.133m 25.637ms 50 50 100.00
spi_host_error_cmd 17.000s 19.580us 50 50 100.00
spi_host_event 17.450m 30.039ms 50 50 100.00
V2 clock_rate spi_host_speed 33.000s 1.945ms 50 50 100.00
V2 speed spi_host_speed 33.000s 1.945ms 50 50 100.00
V2 chip_select_timing spi_host_speed 33.000s 1.945ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 4.100m 10.028ms 49 50 98.00
V2 passthrough_mode spi_host_passthrough_mode 19.000s 446.700us 50 50 100.00
V2 cpol_cpha spi_host_speed 33.000s 1.945ms 50 50 100.00
V2 full_cycle spi_host_speed 33.000s 1.945ms 50 50 100.00
V2 duplex spi_host_smoke 6.217m 14.805ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 6.217m 14.805ms 50 50 100.00
V2 stress_all spi_host_stress_all 5.633m 15.045ms 49 50 98.00
V2 spien spi_host_spien 2.400m 3.206ms 50 50 100.00
V2 stall spi_host_status_stall 7.133m 18.574ms 47 50 94.00
V2 Idlecsbactive spi_host_idlecsbactive 58.000s 7.787ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 2.133m 25.637ms 50 50 100.00
V2 alert_test spi_host_alert_test 23.000s 17.849us 50 50 100.00
V2 intr_test spi_host_intr_test 1.550m 38.195us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 1.767m 138.732us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 1.767m 138.732us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 4.000s 29.342us 5 5 100.00
spi_host_csr_rw 1.450m 38.215us 20 20 100.00
spi_host_csr_aliasing 4.000s 57.094us 5 5 100.00
spi_host_same_csr_outstanding 51.000s 60.911us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 4.000s 29.342us 5 5 100.00
spi_host_csr_rw 1.450m 38.215us 20 20 100.00
spi_host_csr_aliasing 4.000s 57.094us 5 5 100.00
spi_host_same_csr_outstanding 51.000s 60.911us 20 20 100.00
V2 TOTAL 685 690 99.28
V2S tl_intg_err spi_host_tl_intg_err 1.550m 100.009us 20 20 100.00
spi_host_sec_cm 3.000s 239.254us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 1.550m 100.009us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 53.317m 100.004ms 1 10 10.00
TOTAL 826 840 98.33

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 12 80.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.89 83.13 92.75 89.83 95.70 100.00 95.22 90.87

Failure Buckets

Past Results