SPI_HOST Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: 9f20940d49

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 7.733m 8.412ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 21.032us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 45.733us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 6.000s 160.868us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 28.529us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 4.000s 31.774us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 45.733us 20 20 100.00
spi_host_csr_aliasing 3.000s 28.529us 5 5 100.00
V1 mem_walk spi_host_mem_walk 3.000s 75.903us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 24.703us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 5.000s 359.089us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.667m 4.673ms 50 50 100.00
spi_host_error_cmd 4.000s 18.396us 50 50 100.00
spi_host_event 9.233m 119.115ms 50 50 100.00
V2 clock_rate spi_host_speed 29.000s 1.397ms 50 50 100.00
V2 speed spi_host_speed 29.000s 1.397ms 50 50 100.00
V2 chip_select_timing spi_host_speed 29.000s 1.397ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 4.983m 10.832ms 49 50 98.00
V2 passthrough_mode spi_host_passthrough_mode 5.000s 272.002us 50 50 100.00
V2 cpol_cpha spi_host_speed 29.000s 1.397ms 50 50 100.00
V2 full_cycle spi_host_speed 29.000s 1.397ms 50 50 100.00
V2 duplex spi_host_smoke 7.733m 8.412ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 7.733m 8.412ms 50 50 100.00
V2 stress_all spi_host_stress_all 6.067m 15.002ms 49 50 98.00
V2 spien spi_host_spien 5.617m 12.310ms 50 50 100.00
V2 stall spi_host_status_stall 8.500m 24.261ms 48 50 96.00
V2 Idlecsbactive spi_host_idlecsbactive 38.000s 4.526ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 2.667m 4.673ms 50 50 100.00
V2 alert_test spi_host_alert_test 3.000s 118.028us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 15.881us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 35.798us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 35.798us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 21.032us 5 5 100.00
spi_host_csr_rw 3.000s 45.733us 20 20 100.00
spi_host_csr_aliasing 3.000s 28.529us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 30.737us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 21.032us 5 5 100.00
spi_host_csr_rw 3.000s 45.733us 20 20 100.00
spi_host_csr_aliasing 3.000s 28.529us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 30.737us 20 20 100.00
V2 TOTAL 686 690 99.42
V2S tl_intg_err spi_host_tl_intg_err 4.000s 522.679us 20 20 100.00
spi_host_sec_cm 3.000s 150.214us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 4.000s 522.679us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 51.983m 176.965ms 3 10 30.00
TOTAL 829 840 98.69

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 12 80.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.02 90.92 83.15 92.77 89.87 95.70 100.00 95.07 90.87

Failure Buckets

Past Results