SPI_HOST Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: 17d5a97c3b

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.000m	58.564ms	49	50	98.00
V1	csr_hw_reset	spi_host_csr_hw_reset	8.000s	57.012us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	46.358us	19	20	95.00
V1	csr_bit_bash	spi_host_csr_bit_bash	11.000s	632.871us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	6.000s	29.223us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	7.000s	26.193us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	46.358us	19	20	95.00
		spi_host_csr_aliasing	6.000s	29.223us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	6.000s	49.134us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	61.552us	4	5	80.00
V1		TOTAL			112	115	97.39
V2	performance	spi_host_performance	10.000s	268.002us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.517m	11.866ms	49	50	98.00
		spi_host_error_cmd	6.000s	20.110us	50	50	100.00
		spi_host_event	20.750m	112.167ms	50	50	100.00
V2	clock_rate	spi_host_speed	6.333m	39.675ms	50	50	100.00
V2	speed	spi_host_speed	6.333m	39.675ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	6.333m	39.675ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	7.000m	28.628ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	10.000s	572.603us	50	50	100.00
V2	cpol_cpha	spi_host_speed	6.333m	39.675ms	50	50	100.00
V2	full_cycle	spi_host_speed	6.333m	39.675ms	50	50	100.00
V2	duplex	spi_host_smoke	10.000m	58.564ms	49	50	98.00
V2	tx_rx_only	spi_host_smoke	10.000m	58.564ms	49	50	98.00
V2	stress_all	spi_host_stress_all	4.167m	30.149ms	49	50	98.00
V2	spien	spi_host_spien	7.683m	60.088ms	50	50	100.00
V2	stall	spi_host_status_stall	9.617m	13.596ms	46	50	92.00
V2	Idlecsbactive	spi_host_idlecsbactive	53.000s	14.742ms	47	50	94.00
V2	alert_test	spi_host_alert_test	13.000s	16.284us	50	50	100.00
V2	intr_test	spi_host_intr_test	8.000s	30.279us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	9.000s	137.878us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	9.000s	137.878us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	8.000s	57.012us	5	5	100.00
		spi_host_csr_rw	5.000s	46.358us	19	20	95.00
		spi_host_csr_aliasing	6.000s	29.223us	5	5	100.00
		spi_host_same_csr_outstanding	8.000s	207.645us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	8.000s	57.012us	5	5	100.00
		spi_host_csr_rw	5.000s	46.358us	19	20	95.00
		spi_host_csr_aliasing	6.000s	29.223us	5	5	100.00
		spi_host_same_csr_outstanding	8.000s	207.645us	20	20	100.00
V2		TOTAL			681	690	98.70
V2S	tl_intg_err	spi_host_tl_intg_err	9.000s	59.600us	20	20	100.00
		spi_host_sec_cm	10.000s	1.554ms	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	9.000s	59.600us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			818	830	98.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	5	62.50
V2	15	15	11	73.33
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.09	98.13	95.98	99.73	96.70	95.70	100.00	98.60	91.29

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 5 failures:

  • Test spi_host_stress_all has 1 failures.

    • 12.spi_host_stress_all.111346945022703440276562638545974589684397437868831777298361487080009951241023
      Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_stress_all/latest/run.log

        UVM_FATAL @ 30398844695 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x5cbcd194) == 0x0
        UVM_INFO @ 30398844695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test spi_host_idlecsbactive has 2 failures.

    • 15.spi_host_idlecsbactive.111453729622731717454019130518836359054516732852614316221540030102108692289392
      Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_idlecsbactive/latest/run.log

        UVM_FATAL @ 10073308873 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x7ed84654) == 0x0
        UVM_INFO @ 10073308873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 30.spi_host_idlecsbactive.69483212929146846963233737733500421879884485667703135211285223861283625689824
      Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_idlecsbactive/latest/run.log

        UVM_FATAL @ 10038260687 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x38b12a54) == 0x0
        UVM_INFO @ 10038260687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test spi_host_status_stall has 2 failures.

    • 19.spi_host_status_stall.56585642835655365208652868854953754011574726028568197206283434983224590537743
      Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 22326924689 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x28da854) == 0x0
        UVM_INFO @ 22326924689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 44.spi_host_status_stall.43924971654365229691280773264083359513752092067434112688394596187790533910132
      Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 105635034015 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe7c7b494) == 0x0
        UVM_INFO @ 105635034015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 2 failures:

  • Test spi_host_status_stall has 2 failures.

    • 18.spi_host_status_stall.77161870358203031850792437613083369174141705519484918642955788092364394924091
      Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 40715952728 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc70e1e14) == 0x1
        UVM_INFO @ 40715952728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 49.spi_host_status_stall.18577293932055556263429602582842269421386015714172019228842983205085053818918
      Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 17145269449 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x320286d4) == 0x1
        UVM_INFO @ 17145269449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test spi_host_smoke has 1 failures.

    • 0.spi_host_smoke.102132062168277824521129948059768296042148457943316080830324462681255692317038
      Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_smoke/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job spi_host-sim-xcelium_run_cover_reg_top killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:

  • Test spi_host_mem_partial_access has 1 failures.

    • 4.spi_host_mem_partial_access.58267063675142730963009687644035798382941803391667534598365817039387250547340
      Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_mem_partial_access/latest/run.log

        Job ID: smart:78f3b998-bc51-4d0f-b5b0-7ceac6053a25
      

• Job spi_host-sim-xcelium_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:

  • Test spi_host_idlecsbactive has 1 failures.

    • 6.spi_host_idlecsbactive.52453442054779308297146118978540138605418690831987967976990268936379731525579
      Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_idlecsbactive/latest/run.log

        Job ID: smart:c7e0a9d6-d44e-4aa1-bc8c-7cf1063f475a
      

• Job spi_host-sim-xcelium_run_cover_reg_top killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:

  • Test spi_host_csr_rw has 1 failures.

    • 8.spi_host_csr_rw.73733063563480847385626686318051318091826947756827456034775018488110851608982
      Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_csr_rw/latest/run.log

        Job ID: smart:70c32e8b-4031-441c-b7b7-991c8d98ca63
      

• Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:

  • Test spi_host_overflow_underflow has 1 failures.

    • 14.spi_host_overflow_underflow.78665250777987961019402056232660684788315751028204107969465846961187753529224
      Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_overflow_underflow/latest/run.log

        UVM_FATAL @ 68092222394 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb96a4414) == 0x0
        UVM_INFO @ 68092222394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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