SPI_HOST Lint Results
Thursday April 18 2024 19:02:27 UTC
Branch: os_regression
Tool: ASCENTLINT
| Build Mode |
Flow Infos |
Flow Warnings |
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Lint Infos |
Lint Warnings |
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Messages for Build Mode 'default'
Lint Infos
I FSM_DEFAULT_REQ: prim_diff_decode.sv:158 Next state register 'gen_async.state_d' has no assignment in the default branch of the case statement for this finite state machine New
I NESTED_SUBPROG: tlul_pkg.sv:143 Function 'prim_mubi_pkg::mubi4_test_invalid' is called from within a function New
I NESTED_SUBPROG: tlul_pkg.sv:176 Function 'extract_h2d_cmd_intg' is called from within a function New
I NESTED_SUBPROG: tlul_pkg.sv:178 Function 'prim_secded_pkg::prim_secded_inv_64_57_enc' is called from within a function New
I NESTED_SUBPROG: tlul_pkg.sv:187 Function 'prim_secded_pkg::prim_secded_inv_39_32_enc' is called from within a function New
I NESTED_SUBPROG: tlul_pkg.sv:196 Function 'get_cmd_intg' is called from within a function New
I NESTED_SUBPROG: tlul_pkg.sv:203 Function 'get_data_intg' is called from within a function New
I VAR_INDEX_WRITE: prim_fifo_sync.sv:124 Variable index expression 'gen_normal_fifo.storage[gen_normal_fifo.fifo_wptr]' encountered New
I VAR_INDEX_WRITE: tlul_adapter_sram.sv:372 Variable index expression 'wmask_intg[woffset]' encountered New
I VAR_INDEX_WRITE: tlul_adapter_sram.sv:373 Variable index expression 'wdata_intg[woffset]' encountered New
I VAR_INDEX_WRITE: tlul_adapter_sram.sv:437 Variable range select expression 'gen_rmask.rmask[8 * i +: 8]' encountered New
I CASE_INC: spi_host.sv:179 Case statement tag not specified for value 'b11 New
I CASE_INC: spi_host.sv:196 Case statement tag not specified for value 'b00 New
I CASE_INC: spi_host.sv:363 Case statement tag not specified for value 'b0000 and 7 other values New
I CASE_INC: spi_host_fsm.sv:403 Case statement tag not specified for value 'b11 New
I CASE_INC: spi_host_fsm.sv:463 Case statement tag not specified for value 'b000 and 3 other values New
I CASE_INC: spi_host_fsm.sv:526 Case statement tag not specified for value 'b000 and 2 other values New
I CASE_INC: spi_host_fsm.sv:584 Case statement tag not specified for value 'b11 New
I CASE_INC: prim_alert_sender.sv:199 Case statement tag not specified for value 'b111 New
I CASE_INC: prim_diff_decode.sv:115 Case statement tag not specified for value 'b11 New
I CASE_INC: tlul_err.sv:62 Case statement tag not specified for value 'h3 New
I ONE_BIT_VEC: spi_host.sv:14 Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'AlertAsyncOn' has a length of one, instance 'spi_host' of module 'spi_host' (NumAlerts=1) New
I ONE_BIT_VEC: spi_host.sv:24 Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'alert_rx_i' has a length of one, instance 'spi_host' of module 'spi_host' (NumAlerts=1) New
I ONE_BIT_VEC: spi_host.sv:25 Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'alert_tx_o' has a length of one, instance 'spi_host' of module 'spi_host' (NumAlerts=1) New
I ONE_BIT_VEC: spi_host.sv:30 Declaration range '[NumCS - 1:0]' ([0:0]) of 'cio_csb_o' has a length of one, instance 'spi_host' of module 'spi_host' (NumCS=1) New
I ONE_BIT_VEC: spi_host.sv:31 Declaration range '[NumCS - 1:0]' ([0:0]) of 'cio_csb_en_o' has a length of one, instance 'spi_host' of module 'spi_host' (NumCS=1) New
I ONE_BIT_VEC: spi_host.sv:53 Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'alert_test' has a length of one, instance 'spi_host' of module 'spi_host' (NumAlerts=1) New
I ONE_BIT_VEC: spi_host.sv:90 Declaration range '[NumCS - 1:0]' ([0:0]) of 'csb' has a length of one, instance 'spi_host' of module 'spi_host' (NumCS=1) New
I ONE_BIT_VEC: spi_host.sv:106 Declaration range '[0:0]' of 'gen_passthrough_implementation.pt_csb' has a length of one New
I ONE_BIT_VEC: spi_host.sv:107 Declaration range '[0:0]' of 'gen_passthrough_implementation.pt_csb_en' has a length of one New
I ONE_BIT_VEC: spi_host_cmd_pkg.sv:48 Declaration range '[CSW - 1:0]' ([0:0]) of 'command_i' has a length of one, instance 'spi_host.u_cmd_queue' of module 'spi_host_command_queue' (CSW=1 ('prim_util_pkg::vbits(spi_host_reg_pkg::NumCS)')) New
I ONE_BIT_VEC: spi_host_cmd_pkg.sv:48 Declaration range '[CSW - 1:0]' ([0:0]) of 'command_i' has a length of one, instance 'spi_host.u_spi_core' of module 'spi_host_core' (CSW=1 ('prim_util_pkg::vbits(spi_host_reg_pkg::NumCS)')) New
I ONE_BIT_VEC: spi_host_cmd_pkg.sv:48 Declaration range '[CSW - 1:0]' ([0:0]) of 'command_i' has a length of one, instance 'spi_host.u_spi_core.u_fsm' of module 'spi_host_fsm' (CSW=1 ('prim_util_pkg::vbits(spi_host_reg_pkg::NumCS)')) New
I ONE_BIT_VEC: spi_host_cmd_pkg.sv:48 Declaration range '[CSW - 1:0]' ([0:0]) of 'command_t' has a length of one, instance 'spi_host' of module 'spi_host' (CSW=1 ('prim_util_pkg::vbits(spi_host_reg_pkg::NumCS)')) New
I ONE_BIT_VEC: spi_host_cmd_pkg.sv:48 Declaration range '[CSW - 1:0]' ([0:0]) of 'core_command' has a length of one, instance 'spi_host' of module 'spi_host' (CSW=1 ('prim_util_pkg::vbits(spi_host_reg_pkg::NumCS)')) New
I ONE_BIT_VEC: spi_host_cmd_pkg.sv:48 Declaration range '[CSW - 1:0]' ([0:0]) of 'core_command_o' has a length of one, instance 'spi_host.u_cmd_queue' of module 'spi_host_command_queue' (CSW=1 ('prim_util_pkg::vbits(spi_host_reg_pkg::NumCS)')) New
I ONE_BIT_VEC: spi_host_cmd_pkg.sv:48 Declaration range '[CSW - 1:0]' ([0:0]) of 'csid' has a length of one, instance 'spi_host' of module 'spi_host' (CSW=1 ('prim_util_pkg::vbits(spi_host_reg_pkg::NumCS)')) New
I ONE_BIT_VEC: spi_host_core.sv:33 Declaration range '[NumCS - 1:0]' ([0:0]) of 'csb_o' has a length of one, instance 'spi_host.u_spi_core' of module 'spi_host_core' (NumCS=1) New
I ONE_BIT_VEC: spi_host_fsm.sv:20 Declaration range '[NumCS - 1:0]' ([0:0]) of 'csb_o' has a length of one, instance 'spi_host.u_spi_core.u_fsm' of module 'spi_host_fsm' (NumCS=1) New
I ONE_BIT_VEC: spi_host_fsm.sv:46 Declaration range '[CSW - 1:0]' ([0:0]) of 'csid' has a length of one, instance 'spi_host.u_spi_core.u_fsm' of module 'spi_host_fsm' (CSW=1 ('prim_util_pkg::vbits(spi_host_reg_pkg::NumCS)')) New
I ONE_BIT_VEC: spi_host_fsm.sv:47 Declaration range '[CSW - 1:0]' ([0:0]) of 'csid_q' has a length of one, instance 'spi_host.u_spi_core.u_fsm' of module 'spi_host_fsm' (CSW=1 ('prim_util_pkg::vbits(spi_host_reg_pkg::NumCS)')) New
I ONE_BIT_VEC: spi_host_fsm.sv:93 Declaration range '[NumCS - 1:0]' ([0:0]) of 'csb_q' has a length of one, instance 'spi_host.u_spi_core.u_fsm' of module 'spi_host_fsm' (NumCS=1) New
I ONE_BIT_VEC: spi_host_reg_pkg.sv:287 Declaration range '[0:0]' of 'configopts' has a length of one New
I ONE_BIT_VEC: spi_host_reg_pkg.sv:287 Declaration range '[0:0]' of 'reg2hw' has a length of one New
I ONE_BIT_VEC: spi_host_reg_pkg.sv:287 Declaration range '[0:0]' of 'spi_host_reg2hw_t' has a length of one New
I ONE_BIT_VEC: spi_host_reg_top.sv:428 Declaration range '[0:0]' of 'alert_test_flds_we' has a length of one New
I ONE_BIT_VEC: prim_buf.sv:24 Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'spi_host.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req.u_secure_anchor_buf' of module 'prim_buf' (Width=1) New
I ONE_BIT_VEC: prim_buf.sv:25 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'spi_host.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req.u_secure_anchor_buf' of module 'prim_buf' (Width=1) New
I ONE_BIT_VEC: prim_flop.sv:22 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'spi_host.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1' of module 'prim_flop' (Width=1) New
I ONE_BIT_VEC: prim_flop.sv:27 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'spi_host.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1' of module 'prim_flop' (Width=1) New
I ONE_BIT_VEC: prim_flop.sv:28 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'spi_host.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1' of module 'prim_flop' (Width=1) New
I ONE_BIT_VEC: prim_flop_en.sv:23 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'spi_host.u_spi_core.u_fsm.u_sck_flop' of module 'prim_flop_en' (Width=1) New
I ONE_BIT_VEC: prim_flop_en.sv:29 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'spi_host.u_spi_core.u_fsm.u_sck_flop' of module 'prim_flop_en' (Width=1) New
I ONE_BIT_VEC: prim_flop_en.sv:30 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'spi_host.u_spi_core.u_fsm.u_sck_flop' of module 'prim_flop_en' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:44 Declaration range '[Width - 1:0]' ([0:0]) of 'event_intr_i' has a length of one, instance 'spi_host.intr_hw_error' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:47 Declaration range '[Width - 1:0]' ([0:0]) of 'reg2hw_intr_enable_q_i' has a length of one, instance 'spi_host.intr_hw_error' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:48 Declaration range '[Width - 1:0]' ([0:0]) of 'reg2hw_intr_test_q_i' has a length of one, instance 'spi_host.intr_hw_error' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:50 Declaration range '[Width - 1:0]' ([0:0]) of 'reg2hw_intr_state_q_i' has a length of one, instance 'spi_host.intr_hw_error' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:52 Declaration range '[Width - 1:0]' ([0:0]) of 'hw2reg_intr_state_d_o' has a length of one, instance 'spi_host.intr_hw_error' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:55 Declaration range '[Width - 1:0]' ([0:0]) of 'intr_o' has a length of one, instance 'spi_host.intr_hw_error' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:58 Declaration range '[Width - 1:0]' ([0:0]) of 'status' has a length of one, instance 'spi_host.intr_hw_error' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:61 Declaration range '[Width - 1:0]' ([0:0]) of 'g_intr_event.new_event' has a length of one, instance 'spi_host.intr_hw_error' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:72 Declaration range '[Width - 1:0]' ([0:0]) of 'g_intr_status.test_q' has a length of one, instance 'spi_host.intr_hw_spi_event' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_fifo_sync.sv:32 Declaration range '[DepthW - 1:0]' ([0:0]) of 'depth_o' has a length of one, instance 'spi_host.u_reg.u_socket.fifo_h.reqfifo' of module 'prim_fifo_sync' (Depth=0,DepthW=1 ('prim_util_pkg::vbits(Depth + 1)')) New
I ONE_BIT_VEC: prim_fifo_sync.sv:63 Declaration range '[gen_normal_fifo.PtrW - 1:0]' ([0:0]) of 'gen_normal_fifo.fifo_wptr' has a length of one, instance 'spi_host.u_window.u_adapter_tx.u_reqfifo' of module 'prim_fifo_sync' (Depth=1,gen_normal_fifo.PtrW=1 ('prim_util_pkg::vbits(Depth)')) New
I ONE_BIT_VEC: prim_fifo_sync.sv:105 Declaration range '[Depth - 1:0]' ([0:0]) of 'gen_normal_fifo.storage' has a length of one, instance 'spi_host.u_window.u_adapter_tx.u_reqfifo' of module 'prim_fifo_sync' (Depth=1,Width=17) New
I ONE_BIT_VEC: prim_fifo_sync_cnt.sv:25 Declaration range '[PtrW - 1:0]' ([0:0]) of 'wptr_o' has a length of one, instance 'spi_host.u_window.u_adapter_tx.u_reqfifo.gen_normal_fifo.u_fifo_cnt' of module 'prim_fifo_sync_cnt' (Depth=1,PtrW=1 ('prim_util_pkg::vbits(Depth)')) New
I ONE_BIT_VEC: prim_fifo_sync_cnt.sv:26 Declaration range '[PtrW - 1:0]' ([0:0]) of 'rptr_o' has a length of one, instance 'spi_host.u_window.u_adapter_tx.u_reqfifo.gen_normal_fifo.u_fifo_cnt' of module 'prim_fifo_sync_cnt' (Depth=1,PtrW=1 ('prim_util_pkg::vbits(Depth)')) New
I ONE_BIT_VEC: prim_fifo_sync_cnt.sv:31 Declaration range '[DepthW - 1:0]' ([0:0]) of 'depth_o' has a length of one, instance 'spi_host.u_window.u_adapter_tx.u_reqfifo.gen_normal_fifo.u_fifo_cnt' of module 'prim_fifo_sync_cnt' (Depth=1,DepthW=1 ('prim_util_pkg::vbits(Depth + 1)')) New
I ONE_BIT_VEC: prim_flop_2sync.sv:11 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'spi_host.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:16 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'spi_host.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:17 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'spi_host.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:20 Declaration range '[Width - 1:0]' ([0:0]) of 'd_o' has a length of one, instance 'spi_host.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:21 Declaration range '[Width - 1:0]' ([0:0]) of 'intq' has a length of one, instance 'spi_host.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_generic_buf.sv:10 Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'spi_host.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req.u_secure_anchor_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1) New
I ONE_BIT_VEC: prim_generic_buf.sv:11 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'spi_host.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req.u_secure_anchor_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1) New
I ONE_BIT_VEC: prim_generic_buf.sv:14 Declaration range '[Width - 1:0]' ([0:0]) of 'inv' has a length of one, instance 'spi_host.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req.u_secure_anchor_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop.sv:9 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'spi_host.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop.sv:13 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'spi_host.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop.sv:14 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'spi_host.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p.u_sync_1.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_en.sv:10 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'spi_host.u_spi_core.u_fsm.u_sck_flop.gen_generic.u_impl_generic' of module 'prim_generic_flop_en' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_en.sv:15 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'spi_host.u_spi_core.u_fsm.u_sck_flop.gen_generic.u_impl_generic' of module 'prim_generic_flop_en' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_en.sv:16 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'spi_host.u_spi_core.u_fsm.u_sck_flop.gen_generic.u_impl_generic' of module 'prim_generic_flop_en' (Width=1) New
I ONE_BIT_VEC: prim_sec_anchor_buf.sv:10 Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'spi_host.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req' of module 'prim_sec_anchor_buf' (Width=1) New
I ONE_BIT_VEC: prim_sec_anchor_buf.sv:11 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'spi_host.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req' of module 'prim_sec_anchor_buf' (Width=1) New
I ONE_BIT_VEC: prim_subreg.sv:12 Declaration range '[DW - 1:0]' ([0:0]) of 'RESVAL' has a length of one, instance 'spi_host.u_reg.u_intr_state_error' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:21 Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'spi_host.u_reg.u_intr_state_error' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:25 Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'spi_host.u_reg.u_intr_state_error' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:29 Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'spi_host.u_reg.u_intr_state_error' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:34 Declaration range '[DW - 1:0]' ([0:0]) of 'ds' has a length of one, instance 'spi_host.u_reg.u_intr_state_error' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:35 Declaration range '[DW - 1:0]' ([0:0]) of 'qs' has a length of one, instance 'spi_host.u_reg.u_intr_state_error' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:39 Declaration range '[DW - 1:0]' ([0:0]) of 'wr_data' has a length of one, instance 'spi_host.u_reg.u_intr_state_error' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:17 Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'spi_host.u_reg.u_intr_state_error.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:21 Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'spi_host.u_reg.u_intr_state_error.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:24 Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'spi_host.u_reg.u_intr_state_error.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:28 Declaration range '[DW - 1:0]' ([0:0]) of 'wr_data' has a length of one, instance 'spi_host.u_reg.u_intr_state_error.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:36 Declaration range '[DW - 1:0]' ([0:0]) of 'gen_w.unused_q' has a length of one, instance 'spi_host.u_reg.u_intr_enable_error.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:47 Declaration range '[DW - 1:0]' ([0:0]) of 'gen_ro.unused_wd' has a length of one, instance 'spi_host.u_reg.u_intr_state_spi_event.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:48 Declaration range '[DW - 1:0]' ([0:0]) of 'gen_ro.unused_q' has a length of one, instance 'spi_host.u_reg.u_intr_state_spi_event.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:12 Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'spi_host.u_reg.u_intr_test_error' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:14 Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'spi_host.u_reg.u_intr_test_error' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:19 Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'spi_host.u_reg.u_intr_test_error' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:20 Declaration range '[DW - 1:0]' ([0:0]) of 'ds' has a length of one, instance 'spi_host.u_reg.u_intr_test_error' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:21 Declaration range '[DW - 1:0]' ([0:0]) of 'qs' has a length of one, instance 'spi_host.u_reg.u_intr_test_error' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:180 Declaration range '[WoffsetWidth - 1:0]' ([0:0]) of 'sram_req_t' has a length of one, instance 'spi_host.u_window.u_adapter_tx' of module 'tlul_adapter_sram' (DataBitWidth=2 ('prim_util_pkg::vbits(SramByte)'),SramByte=4 ('SramDw / 8'),SramDw=32,WoffsetWidth=1 ('(SramByte == top_pkg::TL_DBW) ? 1 : DataBitWidth - prim_util_pkg::vbits(top_pkg::TL_DBW)')) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:180 Declaration range '[WoffsetWidth - 1:0]' ([0:0]) of 'sramreqfifo_wdata' has a length of one, instance 'spi_host.u_window.u_adapter_tx' of module 'tlul_adapter_sram' (DataBitWidth=2 ('prim_util_pkg::vbits(SramByte)'),SramByte=4 ('SramDw / 8'),SramDw=32,WoffsetWidth=1 ('(SramByte == top_pkg::TL_DBW) ? 1 : DataBitWidth - prim_util_pkg::vbits(top_pkg::TL_DBW)')) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:180 Declaration range '[WoffsetWidth - 1:0]' ([0:0]) of 'woffset' has a length of one, instance 'spi_host.u_window.u_adapter_tx' of module 'tlul_adapter_sram' (DataBitWidth=2 ('prim_util_pkg::vbits(SramByte)'),SramByte=4 ('SramDw / 8'),SramDw=32,WoffsetWidth=1 ('(SramByte == top_pkg::TL_DBW) ? 1 : DataBitWidth - prim_util_pkg::vbits(top_pkg::TL_DBW)')) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:331 Declaration range '[WoffsetWidth - 1:0]' ([0:0]) of 'woffset' has a length of one, instance 'spi_host.u_window.u_adapter_tx' of module 'tlul_adapter_sram' (DataBitWidth=2 ('prim_util_pkg::vbits(SramByte)'),SramByte=4 ('SramDw / 8'),SramDw=32,WoffsetWidth=1 ('(SramByte == top_pkg::TL_DBW) ? 1 : DataBitWidth - prim_util_pkg::vbits(top_pkg::TL_DBW)')) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:344 Declaration range '[WidthMult - 1:0]' ([0:0]) of 'wmask_combined' has a length of one, instance 'spi_host.u_window.u_adapter_tx' of module 'tlul_adapter_sram' (DataIntgWidth=7,DataWidth=32 ('EnableDataIntgPt ? top_pkg::TL_DW + DataIntgWidth : top_pkg::TL_DW'),EnableDataIntgPt=0,SramDw=32,WidthMult=1 ('SramDw / top_pkg::TL_DW')) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:345 Declaration range '[WidthMult - 1:0]' ([0:0]) of 'wdata_combined' has a length of one, instance 'spi_host.u_window.u_adapter_tx' of module 'tlul_adapter_sram' (DataIntgWidth=7,DataWidth=32 ('EnableDataIntgPt ? top_pkg::TL_DW + DataIntgWidth : top_pkg::TL_DW'),EnableDataIntgPt=0,SramDw=32,WidthMult=1 ('SramDw / top_pkg::TL_DW')) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:348 Declaration range '[WidthMult - 1:0]' ([0:0]) of 'wmask_int' has a length of one, instance 'spi_host.u_window.u_adapter_tx' of module 'tlul_adapter_sram' (SramDw=32,WidthMult=1 ('SramDw / top_pkg::TL_DW')) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:349 Declaration range '[WidthMult - 1:0]' ([0:0]) of 'wdata_int' has a length of one, instance 'spi_host.u_window.u_adapter_tx' of module 'tlul_adapter_sram' (SramDw=32,WidthMult=1 ('SramDw / top_pkg::TL_DW')) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:352 Declaration range '[WidthMult - 1:0]' ([0:0]) of 'wmask_intg' has a length of one, instance 'spi_host.u_window.u_adapter_tx' of module 'tlul_adapter_sram' (DataIntgWidth=7,SramDw=32,WidthMult=1 ('SramDw / top_pkg::TL_DW')) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:353 Declaration range '[WidthMult - 1:0]' ([0:0]) of 'wdata_intg' has a length of one, instance 'spi_host.u_window.u_adapter_tx' of module 'tlul_adapter_sram' (DataIntgWidth=7,SramDw=32,WidthMult=1 ('SramDw / top_pkg::TL_DW')) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:413 Declaration range '[WidthMult - 1:0]' ([0:0]) of 'rdata_reshaped' has a length of one, instance 'spi_host.u_window.u_adapter_tx' of module 'tlul_adapter_sram' (DataIntgWidth=7,DataWidth=32 ('EnableDataIntgPt ? top_pkg::TL_DW + DataIntgWidth : top_pkg::TL_DW'),EnableDataIntgPt=0,SramDw=32,WidthMult=1 ('SramDw / top_pkg::TL_DW')) New
I ONE_BIT_VEC: tlul_fifo_sync.sv:23 Declaration range '[SpareReqW - 1:0]' ([0:0]) of 'spare_req_i' has a length of one, instance 'spi_host.u_reg.u_socket.gen_dfifo[0].fifo_d' of module 'tlul_fifo_sync' (SpareReqW=1) New
I ONE_BIT_VEC: tlul_fifo_sync.sv:24 Declaration range '[SpareReqW - 1:0]' ([0:0]) of 'spare_req_o' has a length of one, instance 'spi_host.u_reg.u_socket.gen_dfifo[0].fifo_d' of module 'tlul_fifo_sync' (SpareReqW=1) New
I ONE_BIT_VEC: tlul_fifo_sync.sv:25 Declaration range '[SpareRspW - 1:0]' ([0:0]) of 'spare_rsp_i' has a length of one, instance 'spi_host.u_reg.u_socket.fifo_h' of module 'tlul_fifo_sync' (SpareRspW=1) New
I ONE_BIT_VEC: tlul_fifo_sync.sv:26 Declaration range '[SpareRspW - 1:0]' ([0:0]) of 'spare_rsp_o' has a length of one, instance 'spi_host.u_reg.u_socket.fifo_h' of module 'tlul_fifo_sync' (SpareRspW=1) New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'd_sink' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'fifo_win_d2h' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'rx_win_o' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_d2h_t' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_d_i' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_h_o' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_h_o_int' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_i' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o_int' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o_pre' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_out' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_reg_d2h' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_socket_d2h' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_sram_i' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_t_i' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_t_p' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_u_i' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_win_i' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tx_win_o' has a length of one New
I UNREACHABLE: spi_host_fsm.sv:304 'command_ready_int' is assigned to a non-x value within the default branch of a fully specified case statement New
I UNREACHABLE: spi_host_fsm.sv:305 'state_d' is assigned to a non-x value within the default branch of a fully specified case statement New
I EXPLICIT_BITLEN: spi_host_data_fifos.sv:57 Bit length not specified for constant '8' New
I EXPLICIT_BITLEN: spi_host_data_fifos.sv:59 Bit length not specified for constant '8' New
I EXPLICIT_BITLEN: spi_host_fsm.sv:191 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: spi_host_fsm.sv:445 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: spi_host_fsm.sv:454 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: spi_host_fsm.sv:485 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: prim_fifo_sync_cnt.sv:51 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: prim_fifo_sync_cnt.sv:52 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: prim_util_pkg.sv:85 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: tlul_sram_byte.sv:108 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: tlul_err.sv:69 Bit length not specified for constant "'h1" New
I EXPLICIT_BITLEN: tlul_err.sv:77 Bit length not specified for constant "'h2" New
I INSIDE_OP_CONTEXT: tlul_adapter_sram.sv:325 'inside' operator is not within an always block or subprogram New
I MIN_NAME_LEN: spi_device_pkg.sv:30 Name 's' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_device_pkg.sv:36 Name 's' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:26 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:29 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:35 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:38 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:44 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:48 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:54 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:60 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:63 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:66 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:69 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:72 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:78 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:81 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:84 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:87 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:90 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:93 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:96 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:101 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:106 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:110 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:114 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:118 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:125 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:128 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:131 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:134 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:137 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:143 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:146 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:149 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:152 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:155 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:158 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:164 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:167 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:170 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:173 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:176 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:179 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:185 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:189 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:196 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:200 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:204 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:208 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:212 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:216 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:220 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:224 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:228 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:232 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:236 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:240 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:244 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:248 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:255 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:259 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:263 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:267 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:271 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: spi_host_reg_pkg.sv:275 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:80 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:80 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:85 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:106 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:106 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:111 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:124 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:124 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:131 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:131 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:212 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:212 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:217 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:238 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:238 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:243 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:256 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:256 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:263 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:263 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:344 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:344 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:349 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:370 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:370 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:375 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:388 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:388 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:395 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:395 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:476 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:476 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:481 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:502 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:502 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:507 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:520 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:520 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:527 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:527 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg.sv:25 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg.sv:29 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_arb.sv:21 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_arb.sv:24 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_ext.sv:14 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_ext.sv:19 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: tlul_adapter_sram.sv:360 Name 'i' is shorter than minimum length 2 New
I MIN_NAME_LEN: tlul_adapter_sram.sv:436 Name 'i' is shorter than minimum length 2 New
I MIN_NAME_LEN: tlul_sram_byte.sv:191 Name 'i' is shorter than minimum length 2 New
I MIN_NAME_LEN: tlul_socket_1n.sv:45 Name 'N' is shorter than minimum length 2 New
I MULTIPLY: prim_packer_fifo.sv:136 Multiply operation 'gen_unpack_mode.ptr_q * OutW' encountered, instance 'spi_host.u_spi_core.u_select.u_packer' of module 'prim_packer_fifo' (DepthW=2 ('$clog2(MaxW / MinW)'),InW=36,MaxW=36 ('(InW > OutW) ? InW : OutW'),MinW=9 ('(InW < OutW) ? InW : OutW'),OutW=9) New
I CONST_OUTPUT: spi_host_command_queue.sv:57 Output 'qd_o[3]' is driven by constant zero New
I CONST_OUTPUT: spi_host_data_fifos.sv:99 Output 'rx_qd_o[7]' is driven by constant zero New
I CONST_OUTPUT: prim_intr_hw.sv:80 Output 'hw2reg_intr_state_de_o' is driven by constant one in module 'prim_intr_hw' (IntrT="Status") New
I CONST_OUTPUT: prim_fifo_sync.sv:41 Output 'depth_o' is driven by constant zero in module 'prim_fifo_sync' (Width=32'h6d,Depth=32'h0) New
I CONST_OUTPUT: prim_fifo_sync.sv:56 Output 'err_o' is driven by constant zero in module 'prim_fifo_sync' (Width=32'h6d,Depth=32'h0) New
I CONST_OUTPUT: prim_fifo_sync.sv:98 Output 'err_o' is driven by constant zero by port 'gen_normal_fifo.u_fifo_cnt.err_o' in module 'prim_fifo_sync' (Width=32'h2e) New
I CONST_OUTPUT: prim_fifo_sync_cnt.sv:136 Output 'err_o' is driven by constant zero New
I CONST_OUTPUT: prim_fifo_sync_cnt.sv:136 Output 'err_o' is driven by constant zero in module 'prim_fifo_sync_cnt' (Depth=32'h1) New
I CONST_OUTPUT: tlul_adapter_reg.sv:91 Output 'addr_o[1:0]' is driven by constant zeros in module 'tlul_adapter_reg' (RegAw=6) New
I CONST_OUTPUT: tlul_adapter_reg.sv:195 Output 'intg_error_o' is driven by constant zero in module 'tlul_adapter_reg' (RegAw=6) New
I CONST_OUTPUT: tlul_adapter_sram.sv:163 Output 'rmw_in_progress_o' is driven by constant zero by port 'u_sram_byte.rmw_in_progress_o' in module 'tlul_adapter_sram' (SramAw=6,ErrOnRead=1) New
I CONST_OUTPUT: tlul_sram_byte.sv:326 Output 'rmw_in_progress_o' is driven by constant zero New
Past Results