SRAM_CTRL/MAIN Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: `4002b28ec4`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	19.390s	988.289us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.690s	23.779us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.680s	19.547us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.330s	122.118us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.710s	22.583us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.420s	609.578us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.680s	19.547us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	22.583us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.770m	18.445ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.396m	4.751ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	18.130m	28.731ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.497m	9.326ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	47.895m	295.483ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	18.518m	13.467ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.803m	19.084ms	50	50	100.00
V2	executable	sram_ctrl_executable	20.115m	31.713ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	20.500s	1.006ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.963m	45.084ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.469m	1.343ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.453m	1.371ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	12.368m	19.914ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	6.360s	607.543us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	35.866m	62.225ms	0	50	0.00
V2	alert_test	sram_ctrl_alert_test	0.690s	16.601us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.590s	117.100us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.590s	117.100us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.690s	23.779us	5	5	100.00
		sram_ctrl_csr_rw	0.680s	19.547us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	22.583us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.760s	23.886us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.690s	23.779us	5	5	100.00
		sram_ctrl_csr_rw	0.680s	19.547us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	22.583us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.760s	23.886us	20	20	100.00
V2		TOTAL			690	740	93.24
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	59.740s	6.600ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.090s	216.403us	5	5	100.00
		sram_ctrl_tl_intg_err	1.560s	163.314us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.090s	216.403us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.560s	163.314us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	12.368m	19.914ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.680s	19.547us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	20.115m	31.713ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	20.115m	31.713ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	20.115m	31.713ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.803m	19.084ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	59.740s	6.600ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	19.390s	988.289us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	19.390s	988.289us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	20.115m	31.713ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.090s	216.403us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.803m	19.084ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.090s	216.403us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.090s	216.403us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	19.390s	988.289us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.090s	216.403us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	38.434m	624.328us	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			990	1040	95.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.76	100.00	97.98	99.15	100.00	99.71	99.70	94.75

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:455) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@8712827) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }

has 50 failures:

Test sram_ctrl_stress_all has 50 failures.

0.sram_ctrl_stress_all.22244843486364342984552052920228129434311092740590261325958209335522782505959
Line 331, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 62225245969 ps: (cip_base_scoreboard.sv:455) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@8712827) { a_addr: 'he1246910  a_data: 'h6a0b1e3a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha8  a_opcode: 'h4  a_user: 'h1bc97  d_param: 'h0  d_source: 'ha8  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 62225245969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.sram_ctrl_stress_all.328894316634744232050421211304469397286603777357421550533220840082995640723
Line 331, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 62225245969 ps: (cip_base_scoreboard.sv:455) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@8712827) { a_addr: 'he1246910  a_data: 'h6a0b1e3a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha8  a_opcode: 'h4  a_user: 'h1bc97  d_param: 'h0  d_source: 'ha8  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 62225245969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 48 more failures.