SRAM_CTRL/MAIN Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: `9f20940d49`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.635m	1.550ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.100s	24.139us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.100s	15.357us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.860s	123.092us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.180s	38.496us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	8.690s	377.639us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.100s	15.357us	20	20	100.00
		sram_ctrl_csr_aliasing	1.180s	38.496us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.886m	256.131ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.609m	10.214ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	26.485m	102.445ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	8.122m	22.875ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	48.491m	317.246ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	22.827m	113.637ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.167m	18.314ms	50	50	100.00
V2	executable	sram_ctrl_executable	26.528m	26.393ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.438m	1.025ms	50	50	100.00
		sram_ctrl_partial_access_b2b	14.002m	81.729ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.521m	3.039ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.921m	1.705ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	22.150m	97.899ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	6.570s	1.341ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.561h	333.839ms	46	50	92.00
V2	alert_test	sram_ctrl_alert_test	1.060s	23.030us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	7.240s	530.134us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	7.240s	530.134us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.100s	24.139us	5	5	100.00
		sram_ctrl_csr_rw	1.100s	15.357us	20	20	100.00
		sram_ctrl_csr_aliasing	1.180s	38.496us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.260s	26.588us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.100s	24.139us	5	5	100.00
		sram_ctrl_csr_rw	1.100s	15.357us	20	20	100.00
		sram_ctrl_csr_aliasing	1.180s	38.496us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.260s	26.588us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.767m	28.178ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.610s	879.264us	5	5	100.00
		sram_ctrl_tl_intg_err	4.470s	405.735us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.610s	879.264us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.470s	405.735us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	22.150m	97.899ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.100s	15.357us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	26.528m	26.393ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	26.528m	26.393ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	26.528m	26.393ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.167m	18.314ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.767m	28.178ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	1.635m	1.550ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.635m	1.550ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.635m	1.550ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	26.528m	26.393ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.610s	879.264us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.167m	18.314ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.610s	879.264us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.610s	879.264us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.635m	1.550ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.610s	879.264us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.557m	1.729ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1034	1040	99.42

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.00	99.19	94.49	99.72	100.00	96.03	99.12	97.44

Failure Buckets

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 3 failures:

Test sram_ctrl_stress_all has 3 failures.

2.sram_ctrl_stress_all.25633683598347557026826985392797137096835031303233378190206650266303894911702
Line 94, in log /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 424095261 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 424095261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.sram_ctrl_stress_all.45106667136740961835492845664930578765525037337938512277278396859255086199789
Line 90, in log /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 1541488445 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 1541488445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test sram_ctrl_bijection has 1 failures.
  - 9.sram_ctrl_bijection.80478672528209866206851100940807009790790436363805930943574237675521075482840
    Line 83, in log /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:836) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 14.sram_ctrl_stress_all_with_rand_reset.29849606086469090025711881736336485477225803394296388520304598584421433719997
    Line 187, in log /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 51764319382 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 51764319382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 14.sram_ctrl_stress_all.93935241642411885573424342995253724117375046152544638381025211410494028354234
    Line 104, in log /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 49038980235 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x3d1fadb6
  UVM_INFO @ 49038980235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```