SRAM_CTRL/MAIN Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: `12e3b8572e`

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.613m	1.544ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.050s	51.962us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.120s	49.480us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.870s	349.149us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.060s	16.859us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	10.630s	6.870ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.120s	49.480us	20	20	100.00
		sram_ctrl_csr_aliasing	1.060s	16.859us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.931m	14.285ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.685m	27.892ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	30.082m	104.297ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	8.484m	6.711ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	52.614m	243.470ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	23.189m	86.659ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.379m	246.699ms	50	50	100.00
V2	executable	sram_ctrl_executable	24.004m	206.740ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.622m	2.606ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.525m	177.322ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.815m	6.361ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.771m	11.187ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	28.136m	18.136ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	7.220s	2.577ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.369h	3.600s	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	1.110s	25.293us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	7.500s	141.855us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	7.500s	141.855us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.050s	51.962us	5	5	100.00
		sram_ctrl_csr_rw	1.120s	49.480us	20	20	100.00
		sram_ctrl_csr_aliasing	1.060s	16.859us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.280s	22.566us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.050s	51.962us	5	5	100.00
		sram_ctrl_csr_rw	1.120s	49.480us	20	20	100.00
		sram_ctrl_csr_aliasing	1.060s	16.859us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.280s	22.566us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.567m	22.774ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	5.900s	418.383us	5	5	100.00
		sram_ctrl_tl_intg_err	4.830s	732.660us	19	20	95.00
V2S	prim_count_check	sram_ctrl_sec_cm	5.900s	418.383us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.830s	732.660us	19	20	95.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	28.136m	18.136ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	28.136m	18.136ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.120s	49.480us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	24.004m	206.740ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	24.004m	206.740ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	24.004m	206.740ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.379m	246.699ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.567m	22.774ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	14.270s	6.007ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.613m	1.544ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.613m	1.544ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	24.004m	206.740ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	5.900s	418.383us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.379m	246.699ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	5.900s	418.383us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	5.900s	418.383us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.613m	1.544ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	5.900s	418.383us	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.676m	10.876ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1085	1090	99.54

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.64	99.50	96.05	99.72	100.00	97.34	99.13	98.72

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test sram_ctrl_bijection has 1 failures.
  - 2.sram_ctrl_bijection.74478317064484566597371090374001152461181635538083603930920542012346514599178
    Line 83, in log /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
- Test sram_ctrl_tl_intg_err has 1 failures.
  - 18.sram_ctrl_tl_intg_err.59435100415740523233655388443292676280984957441595451473112051435307040341083
    Line 226, in log /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_tl_intg_err/latest/run.log
```
  UVM_ERROR @ 320798950 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 320798950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 21.sram_ctrl_stress_all_with_rand_reset.26018444141941775133004791640690819711233276703599747458131953193750281421936
    Line 94, in log /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4133906512 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4133906512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 31.sram_ctrl_multiple_keys.9743451369740824655200344352732725855670891375472640257613547173919238987260
    Line 117, in log /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/31.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 174549785299 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x22f466cc
  UVM_INFO @ 174549785299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 41.sram_ctrl_stress_all.88643732475433834559150101023575205827403938911775779205287705310783192752095
    Line 97, in log /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 3272266415068 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xd38a755
  UVM_INFO @ 3272266415068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: 12e3b8572e

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `12e3b8572e`