SRAM_CTRL/MAIN Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: 877a77116

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.213m 474.184us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.640s 52.947us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.710s 22.770us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.860s 637.394us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.710s 46.119us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 13.560s 711.547us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.710s 22.770us 20 20 100.00
sram_ctrl_csr_aliasing 0.710s 46.119us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 5.106m 46.932ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 2.548m 31.096ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 36.705m 30.229ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 8.322m 25.139ms 50 50 100.00
V2 bijection sram_ctrl_bijection 45.971m 479.213ms 48 50 96.00
V2 access_during_key_req sram_ctrl_access_during_key_req 42.263m 48.583ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 5.861m 59.213ms 50 50 100.00
V2 executable sram_ctrl_executable 38.756m 103.790ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.654m 2.037ms 50 50 100.00
sram_ctrl_partial_access_b2b 10.228m 38.868ms 49 50 98.00
V2 max_throughput sram_ctrl_max_throughput 2.997m 785.183us 50 50 100.00
sram_ctrl_throughput_w_partial_write 3.048m 2.789ms 50 50 100.00
V2 regwen sram_ctrl_regwen 37.595m 17.743ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 14.290s 3.043ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.635h 533.786ms 50 50 100.00
V2 alert_test sram_ctrl_alert_test 0.810s 18.832us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.780s 579.394us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.780s 579.394us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.640s 52.947us 5 5 100.00
sram_ctrl_csr_rw 0.710s 22.770us 20 20 100.00
sram_ctrl_csr_aliasing 0.710s 46.119us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.810s 99.936us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.640s 52.947us 5 5 100.00
sram_ctrl_csr_rw 0.710s 22.770us 20 20 100.00
sram_ctrl_csr_aliasing 0.710s 46.119us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.810s 99.936us 20 20 100.00
V2 TOTAL 737 740 99.59
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 4.543m 14.454ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 4.140s 773.262us 5 5 100.00
sram_ctrl_tl_intg_err 2.490s 752.810us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 4.140s 773.262us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.490s 752.810us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 37.595m 17.743ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.710s 22.770us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 38.756m 103.790ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 38.756m 103.790ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 38.756m 103.790ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 5.861m 59.213ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 4.543m 14.454ms 20 20 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.213m 474.184us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.213m 474.184us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 38.756m 103.790ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 4.140s 773.262us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 5.861m 59.213ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 4.140s 773.262us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 4.140s 773.262us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.213m 474.184us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 4.140s 773.262us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 2.036h 4.980ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1037 1040 99.71

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.26 99.16 93.54 100.00 70.00 97.41 99.70 100.00

Failure Buckets

Past Results