Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	293904426	1			T1	227094		T2	301465		T3	41514
instr_valid_dis	272455459	1			T1	227094		T2	301465		T3	41514
instr_en	14959154	1			T6	8208		T29	413502		T51	54906

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9866229	1			T3	21198		T17	74522		T27	43156
sram_ifetch_valid_disable	268882835	1			T1	227094		T2	301465		T5	14762
sram_ifetch_enable	15155362	1			T3	20316		T17	236148		T27	95118

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	293904426	1			T1	227094		T2	301465		T3	41514
hw_debug_en_valid_off	270654943	1			T1	227094		T2	301465		T3	41446
hw_debug_en_on	16051605	1			T17	180136		T27	42376		T28	55748

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	268882835	1			T1	227094		T2	301465		T5	14762
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	260999476	1			T1	227094		T2	301465		T5	14762
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	5157560	1			T29	27236		T8	64186		T58	72
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3335958	1			T3	21198		T17	35104		T29	104486
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1222486	1			T3	21198		T17	35104		T52	70846
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1667876	1			T29	104486		T51	30446		T8	9368
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4870837	1			T17	25242		T6	12058		T29	33492
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	3119563	1			T17	25242		T6	12058		T51	19190
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1360218	1			T29	33492		T8	11192		T127	77002
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	5110730	1			T17	120142		T27	42376		T28	10538
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2059782	1			T17	120142		T27	42376		T28	10538
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2043050	1			T29	78		T8	21548		T131	159376

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	6254856	1			T6	8208		T29	222976		T51	6724
lc_exec_en	6070038	1			T17	34752		T28	45210		T6	10356
valid_exec_dis	267613501	1			T1	227094		T2	301465		T3	20316
invalid_exec_dis	25021591	1			T3	41514		T17	310670		T27	138274