| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.753228475 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1160647988 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1347998181 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3811351651 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3826078944 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1587576315 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1584441325 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3359570538 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4171881112 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2187086778 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2896859608 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1296084072 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3738747535 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.363018421 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.302300064 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2189749395 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.891677733 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3515495830 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3664959984 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4285565025 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.935400677 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2973167360 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3194545032 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2488675577 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2009134698 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2328247626 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2605129758 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.685565563 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1424855948 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3223537053 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3900978694 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1198893183 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2503603751 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.853350892 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.733119996 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.473052804 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2106277428 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3273529222 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2098227429 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.730271750 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1826284747 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2551611589 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2309700703 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1900520943 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.227213772 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.247312846 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3204436442 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1263175673 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.470387198 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.792267912 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4264142722 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.103166580 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1024980113 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.757600602 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3131601499 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1047888017 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.845509542 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2633561802 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.133319477 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3248805434 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3741366182 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2027405465 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3298876059 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1832281847 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3430121587 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1523796201 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.389056302 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3696282182 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3544444641 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4181950088 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1884520779 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3370200089 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.4125876218 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3674433424 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1020091536 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.555751222 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.29924268 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3112277601 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3631606127 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1491870921 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3099527303 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2026987688 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3919089041 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.301771876 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3225194377 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1062733829 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1527148559 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2635219064 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2470637032 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3357458393 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.339026883 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1397455104 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3094628880 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.598728584 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2933276014 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1964085705 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4227311034 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3620156682 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1760877031 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.936128858 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.22268399 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.687966635 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.705193943 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2979496442 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.115314909 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3052548302 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.450676478 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2255262488 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3922029585 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2006255416 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3836010186 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2626606796 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1573530981 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1255989838 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.562875955 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2718516225 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4019091241 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.77951093 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2695098247 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.633498965 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1476110232 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2201514465 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3372711392 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1362674744 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1455555363 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2083418423 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1232147997 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1973638718 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3180328360 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3299982017 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.712495878 |
| /workspace/coverage/default/0.sram_ctrl_bijection.1110814814 |
| /workspace/coverage/default/0.sram_ctrl_executable.1586576196 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.668192256 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.1002021996 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1283131047 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.1057064240 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.2751255681 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.3045509118 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.772507090 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.54535298 |
| /workspace/coverage/default/0.sram_ctrl_regwen.178539577 |
| /workspace/coverage/default/0.sram_ctrl_smoke.3145853056 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.635464043 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2116601561 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.453289265 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1081441388 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2223481239 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.1140682508 |
| /workspace/coverage/default/1.sram_ctrl_bijection.1265570340 |
| /workspace/coverage/default/1.sram_ctrl_executable.1056976141 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.2264614691 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.253831276 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.672312367 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.2289199784 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.2561020395 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.941690970 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.1551227255 |
| /workspace/coverage/default/1.sram_ctrl_regwen.3219848799 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.3815259611 |
| /workspace/coverage/default/1.sram_ctrl_smoke.1269902421 |
| /workspace/coverage/default/1.sram_ctrl_stress_all.1485768015 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3451151836 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.3012580150 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.877444656 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.4240362874 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.1269120280 |
| /workspace/coverage/default/10.sram_ctrl_executable.1202396984 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.4238711723 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.1298177405 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.187189404 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.1518206674 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.341137051 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.1198727824 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2643032554 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.668503378 |
| /workspace/coverage/default/10.sram_ctrl_regwen.3717300083 |
| /workspace/coverage/default/10.sram_ctrl_smoke.180885468 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.3560918103 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2975603988 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.2778313925 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2727777778 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.2262160493 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.1533000008 |
| /workspace/coverage/default/11.sram_ctrl_bijection.1640183812 |
| /workspace/coverage/default/11.sram_ctrl_executable.2167521240 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.2958130309 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.849291588 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.1540792056 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.1566094942 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.1982777693 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.1094034160 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.1304385165 |
| /workspace/coverage/default/11.sram_ctrl_regwen.1886773444 |
| /workspace/coverage/default/11.sram_ctrl_smoke.3834780349 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.3487016416 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.886310231 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.2125120702 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3275028074 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1885142450 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.1559977786 |
| /workspace/coverage/default/12.sram_ctrl_bijection.2703116850 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.1361132048 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.102162345 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3688947718 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.2317748476 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.2914800566 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.1569342780 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3447116441 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.1894938817 |
| /workspace/coverage/default/12.sram_ctrl_regwen.2569795528 |
| /workspace/coverage/default/12.sram_ctrl_smoke.1640159155 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3240240610 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2536364292 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2579280441 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.2153142290 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.813563620 |
| /workspace/coverage/default/13.sram_ctrl_bijection.3241903975 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.4176816216 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.719432021 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.542850740 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.3967803687 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.2061010903 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.2685792844 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.75801129 |
| /workspace/coverage/default/13.sram_ctrl_regwen.797079986 |
| /workspace/coverage/default/13.sram_ctrl_smoke.2030163103 |
| /workspace/coverage/default/13.sram_ctrl_stress_all.3944110470 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1451309228 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3410925245 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.744162383 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2294941906 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.2337737895 |
| /workspace/coverage/default/14.sram_ctrl_bijection.3280580923 |
| /workspace/coverage/default/14.sram_ctrl_executable.2170091288 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.358160288 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.586143069 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3385073036 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.1376539729 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.3807964504 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.2194937990 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.154984062 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.2027937484 |
| /workspace/coverage/default/14.sram_ctrl_regwen.3092534133 |
| /workspace/coverage/default/14.sram_ctrl_smoke.463881021 |
| /workspace/coverage/default/14.sram_ctrl_stress_all.4174005804 |
| /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1190042656 |
| /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2295993982 |
| /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1418802307 |
| /workspace/coverage/default/15.sram_ctrl_access_during_key_req.2999644636 |
| /workspace/coverage/default/15.sram_ctrl_alert_test.2161300336 |
| /workspace/coverage/default/15.sram_ctrl_bijection.2230168952 |
| /workspace/coverage/default/15.sram_ctrl_lc_escalation.1743635531 |
| /workspace/coverage/default/15.sram_ctrl_max_throughput.2586797243 |
| /workspace/coverage/default/15.sram_ctrl_mem_partial_access.2390643508 |
| /workspace/coverage/default/15.sram_ctrl_mem_walk.60507312 |
| /workspace/coverage/default/15.sram_ctrl_multiple_keys.906556064 |
| /workspace/coverage/default/15.sram_ctrl_partial_access.3249975656 |
| /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1090514143 |
| /workspace/coverage/default/15.sram_ctrl_ram_cfg.2191753466 |
| /workspace/coverage/default/15.sram_ctrl_regwen.178202571 |
| /workspace/coverage/default/15.sram_ctrl_smoke.3621138192 |
| /workspace/coverage/default/15.sram_ctrl_stress_all.4263329184 |
| /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.96676112 |
| /workspace/coverage/default/15.sram_ctrl_stress_pipeline.230173509 |
| /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.959133198 |
| /workspace/coverage/default/16.sram_ctrl_access_during_key_req.4032268951 |
| /workspace/coverage/default/16.sram_ctrl_alert_test.2194418133 |
| /workspace/coverage/default/16.sram_ctrl_bijection.1946936670 |
| /workspace/coverage/default/16.sram_ctrl_max_throughput.3761068080 |
| /workspace/coverage/default/16.sram_ctrl_mem_partial_access.1930916296 |
| /workspace/coverage/default/16.sram_ctrl_mem_walk.3321369892 |
| /workspace/coverage/default/16.sram_ctrl_multiple_keys.1079228958 |
| /workspace/coverage/default/16.sram_ctrl_partial_access.567920246 |
| /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.881168784 |
| /workspace/coverage/default/16.sram_ctrl_ram_cfg.3418288301 |
| /workspace/coverage/default/16.sram_ctrl_regwen.2736410810 |
| /workspace/coverage/default/16.sram_ctrl_smoke.560722534 |
| /workspace/coverage/default/16.sram_ctrl_stress_pipeline.3598318438 |
| /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3785984021 |
| /workspace/coverage/default/17.sram_ctrl_access_during_key_req.934747954 |
| /workspace/coverage/default/17.sram_ctrl_alert_test.1560495713 |
| /workspace/coverage/default/17.sram_ctrl_bijection.765030657 |
| /workspace/coverage/default/17.sram_ctrl_executable.2090844259 |
| /workspace/coverage/default/17.sram_ctrl_lc_escalation.281890114 |
| /workspace/coverage/default/17.sram_ctrl_max_throughput.3537284722 |
| /workspace/coverage/default/17.sram_ctrl_mem_partial_access.2181681364 |
| /workspace/coverage/default/17.sram_ctrl_mem_walk.118935208 |
| /workspace/coverage/default/17.sram_ctrl_multiple_keys.102444582 |
| /workspace/coverage/default/17.sram_ctrl_partial_access.4209597242 |
| /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2380948339 |
| /workspace/coverage/default/17.sram_ctrl_ram_cfg.2595961934 |
| /workspace/coverage/default/17.sram_ctrl_regwen.3816427912 |
| /workspace/coverage/default/17.sram_ctrl_smoke.1169773605 |
| /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1742815995 |
| /workspace/coverage/default/17.sram_ctrl_stress_pipeline.4006496015 |
| /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2052829614 |
| /workspace/coverage/default/18.sram_ctrl_access_during_key_req.3164818 |
| /workspace/coverage/default/18.sram_ctrl_alert_test.1629769846 |
| /workspace/coverage/default/18.sram_ctrl_bijection.2759109020 |
| /workspace/coverage/default/18.sram_ctrl_max_throughput.4194132797 |
| /workspace/coverage/default/18.sram_ctrl_mem_partial_access.2168259424 |
| /workspace/coverage/default/18.sram_ctrl_mem_walk.511852295 |
| /workspace/coverage/default/18.sram_ctrl_multiple_keys.1884142569 |
| /workspace/coverage/default/18.sram_ctrl_partial_access.2931025898 |
| /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1777981047 |
| /workspace/coverage/default/18.sram_ctrl_ram_cfg.2264145226 |
| /workspace/coverage/default/18.sram_ctrl_regwen.2492242733 |
| /workspace/coverage/default/18.sram_ctrl_smoke.3257709788 |
| /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1533336453 |
| /workspace/coverage/default/18.sram_ctrl_stress_pipeline.4156631815 |
| /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3301473265 |
| /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3403072161 |
| /workspace/coverage/default/19.sram_ctrl_alert_test.1335599199 |
| /workspace/coverage/default/19.sram_ctrl_bijection.1622393767 |
| /workspace/coverage/default/19.sram_ctrl_lc_escalation.736081228 |
| /workspace/coverage/default/19.sram_ctrl_max_throughput.4110955251 |
| /workspace/coverage/default/19.sram_ctrl_mem_partial_access.2641393233 |
| /workspace/coverage/default/19.sram_ctrl_mem_walk.2891660586 |
| /workspace/coverage/default/19.sram_ctrl_multiple_keys.3874361089 |
| /workspace/coverage/default/19.sram_ctrl_partial_access.1729592766 |
| /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.141180520 |
| /workspace/coverage/default/19.sram_ctrl_ram_cfg.247316540 |
| /workspace/coverage/default/19.sram_ctrl_regwen.2970030883 |
| /workspace/coverage/default/19.sram_ctrl_smoke.862986571 |
| /workspace/coverage/default/19.sram_ctrl_stress_all.3832745570 |
| /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3107335162 |
| /workspace/coverage/default/19.sram_ctrl_stress_pipeline.648898062 |
| /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.805675602 |
| /workspace/coverage/default/2.sram_ctrl_access_during_key_req.2316703344 |
| /workspace/coverage/default/2.sram_ctrl_alert_test.2853256663 |
| /workspace/coverage/default/2.sram_ctrl_bijection.3467726599 |
| /workspace/coverage/default/2.sram_ctrl_lc_escalation.1538660789 |
| /workspace/coverage/default/2.sram_ctrl_max_throughput.2640065018 |
| /workspace/coverage/default/2.sram_ctrl_mem_partial_access.2303850958 |
| /workspace/coverage/default/2.sram_ctrl_mem_walk.152489167 |
| /workspace/coverage/default/2.sram_ctrl_multiple_keys.95174580 |
| /workspace/coverage/default/2.sram_ctrl_partial_access.3027724587 |
| /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.769885209 |
| /workspace/coverage/default/2.sram_ctrl_ram_cfg.1286436324 |
| /workspace/coverage/default/2.sram_ctrl_regwen.2329151431 |
| /workspace/coverage/default/2.sram_ctrl_sec_cm.1097765498 |
| /workspace/coverage/default/2.sram_ctrl_smoke.1148941462 |
| /workspace/coverage/default/2.sram_ctrl_stress_all.3344285518 |
| /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.413064289 |
| /workspace/coverage/default/2.sram_ctrl_stress_pipeline.459916021 |
| /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.231049765 |
| /workspace/coverage/default/20.sram_ctrl_access_during_key_req.2931216474 |
| /workspace/coverage/default/20.sram_ctrl_alert_test.2133080957 |
| /workspace/coverage/default/20.sram_ctrl_bijection.3271502211 |
| /workspace/coverage/default/20.sram_ctrl_executable.2708533788 |
| /workspace/coverage/default/20.sram_ctrl_lc_escalation.639566070 |
| /workspace/coverage/default/20.sram_ctrl_max_throughput.1385898796 |
| /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2244864637 |
| /workspace/coverage/default/20.sram_ctrl_mem_walk.2870782324 |
| /workspace/coverage/default/20.sram_ctrl_multiple_keys.130291948 |
| /workspace/coverage/default/20.sram_ctrl_partial_access.3699447173 |
| /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3608754350 |
| /workspace/coverage/default/20.sram_ctrl_ram_cfg.4284212410 |
| /workspace/coverage/default/20.sram_ctrl_regwen.2993704037 |
| /workspace/coverage/default/20.sram_ctrl_smoke.1374208499 |
| /workspace/coverage/default/20.sram_ctrl_stress_all.1679568310 |
| /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.345510598 |
| /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1126823786 |
| /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.898923479 |
| /workspace/coverage/default/21.sram_ctrl_access_during_key_req.532657222 |
| /workspace/coverage/default/21.sram_ctrl_alert_test.2470608078 |
| /workspace/coverage/default/21.sram_ctrl_bijection.2921344541 |
| /workspace/coverage/default/21.sram_ctrl_executable.1051038271 |
| /workspace/coverage/default/21.sram_ctrl_lc_escalation.1147076668 |
| /workspace/coverage/default/21.sram_ctrl_max_throughput.2461003153 |
| /workspace/coverage/default/21.sram_ctrl_mem_partial_access.3394383561 |
| /workspace/coverage/default/21.sram_ctrl_mem_walk.1962170229 |
| /workspace/coverage/default/21.sram_ctrl_multiple_keys.3841501011 |
| /workspace/coverage/default/21.sram_ctrl_partial_access.2449283438 |
| /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.382742757 |
| /workspace/coverage/default/21.sram_ctrl_ram_cfg.3966786621 |
| /workspace/coverage/default/21.sram_ctrl_regwen.273332014 |
| /workspace/coverage/default/21.sram_ctrl_smoke.3204653911 |
| /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2335918533 |
| /workspace/coverage/default/21.sram_ctrl_stress_pipeline.3503063501 |
| /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.622520369 |
| /workspace/coverage/default/22.sram_ctrl_access_during_key_req.2923628241 |
| /workspace/coverage/default/22.sram_ctrl_alert_test.3153925536 |
| /workspace/coverage/default/22.sram_ctrl_bijection.764827923 |
| /workspace/coverage/default/22.sram_ctrl_lc_escalation.479683409 |
| /workspace/coverage/default/22.sram_ctrl_max_throughput.2696354752 |
| /workspace/coverage/default/22.sram_ctrl_mem_partial_access.271290758 |
| /workspace/coverage/default/22.sram_ctrl_mem_walk.3089665993 |
| /workspace/coverage/default/22.sram_ctrl_multiple_keys.2184826746 |
| /workspace/coverage/default/22.sram_ctrl_partial_access.2898344700 |
| /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2585219346 |
| /workspace/coverage/default/22.sram_ctrl_ram_cfg.1396204156 |
| /workspace/coverage/default/22.sram_ctrl_regwen.724407371 |
| /workspace/coverage/default/22.sram_ctrl_smoke.1541491329 |
| /workspace/coverage/default/22.sram_ctrl_stress_all.9862498 |
| /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1551211743 |
| /workspace/coverage/default/22.sram_ctrl_stress_pipeline.131435997 |
| /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2396149581 |
| /workspace/coverage/default/23.sram_ctrl_access_during_key_req.3672381165 |
| /workspace/coverage/default/23.sram_ctrl_alert_test.953171510 |
| /workspace/coverage/default/23.sram_ctrl_bijection.2884751150 |
| /workspace/coverage/default/23.sram_ctrl_executable.1954560102 |
| /workspace/coverage/default/23.sram_ctrl_lc_escalation.3727303426 |
| /workspace/coverage/default/23.sram_ctrl_max_throughput.2187016553 |
| /workspace/coverage/default/23.sram_ctrl_mem_partial_access.3955074412 |
| /workspace/coverage/default/23.sram_ctrl_mem_walk.2690993186 |
| /workspace/coverage/default/23.sram_ctrl_multiple_keys.3838740289 |
| /workspace/coverage/default/23.sram_ctrl_partial_access.2867765943 |
| /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1453196268 |
| /workspace/coverage/default/23.sram_ctrl_ram_cfg.2742533723 |
| /workspace/coverage/default/23.sram_ctrl_regwen.1397119191 |
| /workspace/coverage/default/23.sram_ctrl_smoke.1823510677 |
| /workspace/coverage/default/23.sram_ctrl_stress_all.3238657206 |
| /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.933498490 |
| /workspace/coverage/default/23.sram_ctrl_stress_pipeline.578965633 |
| /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1668764076 |
| /workspace/coverage/default/24.sram_ctrl_access_during_key_req.2477365368 |
| /workspace/coverage/default/24.sram_ctrl_alert_test.25260082 |
| /workspace/coverage/default/24.sram_ctrl_bijection.459700853 |
| /workspace/coverage/default/24.sram_ctrl_lc_escalation.2114904098 |
| /workspace/coverage/default/24.sram_ctrl_max_throughput.3101873946 |
| /workspace/coverage/default/24.sram_ctrl_mem_partial_access.3363361233 |
| /workspace/coverage/default/24.sram_ctrl_mem_walk.184155505 |
| /workspace/coverage/default/24.sram_ctrl_multiple_keys.1746106616 |
| /workspace/coverage/default/24.sram_ctrl_partial_access.3211970206 |
| /workspace/coverage/default/24.sram_ctrl_ram_cfg.3661959709 |
| /workspace/coverage/default/24.sram_ctrl_regwen.1767578253 |
| /workspace/coverage/default/24.sram_ctrl_smoke.3814305091 |
| /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3244603614 |
| /workspace/coverage/default/24.sram_ctrl_stress_pipeline.2499348550 |
| /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1425115541 |
| /workspace/coverage/default/25.sram_ctrl_access_during_key_req.610020875 |
| /workspace/coverage/default/25.sram_ctrl_alert_test.1776470060 |
| /workspace/coverage/default/25.sram_ctrl_bijection.3605553074 |
| /workspace/coverage/default/25.sram_ctrl_executable.1885222778 |
| /workspace/coverage/default/25.sram_ctrl_lc_escalation.761305511 |
| /workspace/coverage/default/25.sram_ctrl_max_throughput.65521810 |
| /workspace/coverage/default/25.sram_ctrl_mem_partial_access.2737574503 |
| /workspace/coverage/default/25.sram_ctrl_mem_walk.135903371 |
| /workspace/coverage/default/25.sram_ctrl_multiple_keys.61389574 |
| /workspace/coverage/default/25.sram_ctrl_partial_access.782728527 |
| /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3876590080 |
| /workspace/coverage/default/25.sram_ctrl_ram_cfg.2809832436 |
| /workspace/coverage/default/25.sram_ctrl_regwen.2695141137 |
| /workspace/coverage/default/25.sram_ctrl_smoke.3583378687 |
| /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3372625652 |
| /workspace/coverage/default/25.sram_ctrl_stress_pipeline.2606138202 |
| /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3300418849 |
| /workspace/coverage/default/26.sram_ctrl_access_during_key_req.3509810672 |
| /workspace/coverage/default/26.sram_ctrl_alert_test.1550776418 |
| /workspace/coverage/default/26.sram_ctrl_bijection.2267413023 |
| /workspace/coverage/default/26.sram_ctrl_executable.3485762205 |
| /workspace/coverage/default/26.sram_ctrl_lc_escalation.962531968 |
| /workspace/coverage/default/26.sram_ctrl_max_throughput.1748881826 |
| /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1220202064 |
| /workspace/coverage/default/26.sram_ctrl_mem_walk.1212781732 |
| /workspace/coverage/default/26.sram_ctrl_multiple_keys.1184615565 |
| /workspace/coverage/default/26.sram_ctrl_partial_access.346971071 |
| /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.646413018 |
| /workspace/coverage/default/26.sram_ctrl_ram_cfg.3278169180 |
| /workspace/coverage/default/26.sram_ctrl_regwen.2275700570 |
| /workspace/coverage/default/26.sram_ctrl_smoke.4130205271 |
| /workspace/coverage/default/26.sram_ctrl_stress_all.1552734766 |
| /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.473631837 |
| /workspace/coverage/default/26.sram_ctrl_stress_pipeline.405762226 |
| /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.4008940419 |
| /workspace/coverage/default/27.sram_ctrl_access_during_key_req.174663931 |
| /workspace/coverage/default/27.sram_ctrl_alert_test.710493047 |
| /workspace/coverage/default/27.sram_ctrl_bijection.315413125 |
| /workspace/coverage/default/27.sram_ctrl_executable.405148663 |
| /workspace/coverage/default/27.sram_ctrl_lc_escalation.1642713651 |
| /workspace/coverage/default/27.sram_ctrl_max_throughput.4170094236 |
| /workspace/coverage/default/27.sram_ctrl_mem_partial_access.2169983513 |
| /workspace/coverage/default/27.sram_ctrl_mem_walk.1059651453 |
| /workspace/coverage/default/27.sram_ctrl_multiple_keys.4173769302 |
| /workspace/coverage/default/27.sram_ctrl_partial_access.1003035389 |
| /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3119152723 |
| /workspace/coverage/default/27.sram_ctrl_ram_cfg.3832902886 |
| /workspace/coverage/default/27.sram_ctrl_regwen.30883078 |
| /workspace/coverage/default/27.sram_ctrl_smoke.3336815755 |
| /workspace/coverage/default/27.sram_ctrl_stress_all.2531698610 |
| /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2050566829 |
| /workspace/coverage/default/27.sram_ctrl_stress_pipeline.1169922725 |
| /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.820548703 |
| /workspace/coverage/default/28.sram_ctrl_access_during_key_req.3153039453 |
| /workspace/coverage/default/28.sram_ctrl_alert_test.2523355726 |
| /workspace/coverage/default/28.sram_ctrl_bijection.1351634478 |
| /workspace/coverage/default/28.sram_ctrl_max_throughput.2280094137 |
| /workspace/coverage/default/28.sram_ctrl_mem_partial_access.767853114 |
| /workspace/coverage/default/28.sram_ctrl_mem_walk.1699599027 |
| /workspace/coverage/default/28.sram_ctrl_multiple_keys.3797437213 |
| /workspace/coverage/default/28.sram_ctrl_partial_access.1396839908 |
| /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1092451436 |
| /workspace/coverage/default/28.sram_ctrl_ram_cfg.423924480 |
| /workspace/coverage/default/28.sram_ctrl_regwen.3292435767 |
| /workspace/coverage/default/28.sram_ctrl_smoke.3965890155 |
| /workspace/coverage/default/28.sram_ctrl_stress_all.440282643 |
| /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2581265720 |
| /workspace/coverage/default/28.sram_ctrl_stress_pipeline.2814515338 |
| /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2189577608 |
| /workspace/coverage/default/29.sram_ctrl_access_during_key_req.985568730 |
| /workspace/coverage/default/29.sram_ctrl_alert_test.2427390556 |
| /workspace/coverage/default/29.sram_ctrl_bijection.228272851 |
| /workspace/coverage/default/29.sram_ctrl_lc_escalation.3954814481 |
| /workspace/coverage/default/29.sram_ctrl_max_throughput.3902151276 |
| /workspace/coverage/default/29.sram_ctrl_mem_partial_access.3867257771 |
| /workspace/coverage/default/29.sram_ctrl_mem_walk.201052782 |
| /workspace/coverage/default/29.sram_ctrl_multiple_keys.1150498117 |
| /workspace/coverage/default/29.sram_ctrl_partial_access.3451995056 |
| /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2664358779 |
| /workspace/coverage/default/29.sram_ctrl_ram_cfg.775198214 |
| /workspace/coverage/default/29.sram_ctrl_smoke.150701059 |
| /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1889085679 |
| /workspace/coverage/default/29.sram_ctrl_stress_pipeline.196413026 |
| /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.130426997 |
| /workspace/coverage/default/3.sram_ctrl_access_during_key_req.532151440 |
| /workspace/coverage/default/3.sram_ctrl_alert_test.1949052461 |
| /workspace/coverage/default/3.sram_ctrl_bijection.3620634407 |
| /workspace/coverage/default/3.sram_ctrl_lc_escalation.926558594 |
| /workspace/coverage/default/3.sram_ctrl_max_throughput.3478200987 |
| /workspace/coverage/default/3.sram_ctrl_mem_partial_access.3963725945 |
| /workspace/coverage/default/3.sram_ctrl_mem_walk.3869905312 |
| /workspace/coverage/default/3.sram_ctrl_multiple_keys.4180153368 |
| /workspace/coverage/default/3.sram_ctrl_partial_access.3913787631 |
| /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3268532801 |
| /workspace/coverage/default/3.sram_ctrl_ram_cfg.1684516846 |
| /workspace/coverage/default/3.sram_ctrl_regwen.1253248149 |
| /workspace/coverage/default/3.sram_ctrl_sec_cm.2859515421 |
| /workspace/coverage/default/3.sram_ctrl_smoke.2104975930 |
| /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3968409930 |
| /workspace/coverage/default/3.sram_ctrl_stress_pipeline.1219339114 |
| /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3769361350 |
| /workspace/coverage/default/30.sram_ctrl_access_during_key_req.2354768450 |
| /workspace/coverage/default/30.sram_ctrl_alert_test.3711311545 |
| /workspace/coverage/default/30.sram_ctrl_bijection.3267471939 |
| /workspace/coverage/default/30.sram_ctrl_lc_escalation.3723691161 |
| /workspace/coverage/default/30.sram_ctrl_max_throughput.3916166277 |
| /workspace/coverage/default/30.sram_ctrl_mem_partial_access.443733978 |
| /workspace/coverage/default/30.sram_ctrl_mem_walk.1613026055 |
| /workspace/coverage/default/30.sram_ctrl_multiple_keys.1618779386 |
| /workspace/coverage/default/30.sram_ctrl_partial_access.2383385255 |
| /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.482381533 |
| /workspace/coverage/default/30.sram_ctrl_ram_cfg.2860077477 |
| /workspace/coverage/default/30.sram_ctrl_regwen.3035138778 |
| /workspace/coverage/default/30.sram_ctrl_smoke.2028034192 |
| /workspace/coverage/default/30.sram_ctrl_stress_all.2368884330 |
| /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2693367189 |
| /workspace/coverage/default/30.sram_ctrl_stress_pipeline.1759132584 |
| /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2917857713 |
| /workspace/coverage/default/31.sram_ctrl_access_during_key_req.650254470 |
| /workspace/coverage/default/31.sram_ctrl_alert_test.3429983594 |
| /workspace/coverage/default/31.sram_ctrl_bijection.2202095513 |
| /workspace/coverage/default/31.sram_ctrl_executable.1395029973 |
| /workspace/coverage/default/31.sram_ctrl_max_throughput.4032888457 |
| /workspace/coverage/default/31.sram_ctrl_mem_partial_access.1760585681 |
| /workspace/coverage/default/31.sram_ctrl_mem_walk.800463112 |
| /workspace/coverage/default/31.sram_ctrl_multiple_keys.1374780529 |
| /workspace/coverage/default/31.sram_ctrl_partial_access.2170012047 |
| /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1680596890 |
| /workspace/coverage/default/31.sram_ctrl_ram_cfg.3527810642 |
| /workspace/coverage/default/31.sram_ctrl_regwen.3933250625 |
| /workspace/coverage/default/31.sram_ctrl_smoke.434865237 |
| /workspace/coverage/default/31.sram_ctrl_stress_all.291418927 |
| /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2186067536 |
| /workspace/coverage/default/31.sram_ctrl_stress_pipeline.1069569102 |
| /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2901696663 |
| /workspace/coverage/default/32.sram_ctrl_access_during_key_req.1643234205 |
| /workspace/coverage/default/32.sram_ctrl_alert_test.1791697583 |
| /workspace/coverage/default/32.sram_ctrl_bijection.845853362 |
| /workspace/coverage/default/32.sram_ctrl_executable.4246366537 |
| /workspace/coverage/default/32.sram_ctrl_lc_escalation.454085906 |
| /workspace/coverage/default/32.sram_ctrl_max_throughput.1822710832 |
| /workspace/coverage/default/32.sram_ctrl_mem_partial_access.3703445086 |
| /workspace/coverage/default/32.sram_ctrl_mem_walk.2283439490 |
| /workspace/coverage/default/32.sram_ctrl_multiple_keys.3527732483 |
| /workspace/coverage/default/32.sram_ctrl_partial_access.2536341463 |
| /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3114260630 |
| /workspace/coverage/default/32.sram_ctrl_ram_cfg.3522918912 |
| /workspace/coverage/default/32.sram_ctrl_regwen.2575109688 |
| /workspace/coverage/default/32.sram_ctrl_smoke.2465785250 |
| /workspace/coverage/default/32.sram_ctrl_stress_all.1813267363 |
| /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3720190396 |
| /workspace/coverage/default/32.sram_ctrl_stress_pipeline.2421970396 |
| /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3254105164 |
| /workspace/coverage/default/33.sram_ctrl_access_during_key_req.2790112078 |
| /workspace/coverage/default/33.sram_ctrl_alert_test.604444271 |
| /workspace/coverage/default/33.sram_ctrl_bijection.1328414757 |
| /workspace/coverage/default/33.sram_ctrl_lc_escalation.2937185423 |
| /workspace/coverage/default/33.sram_ctrl_max_throughput.2424630770 |
| /workspace/coverage/default/33.sram_ctrl_mem_partial_access.2113050538 |
| /workspace/coverage/default/33.sram_ctrl_mem_walk.1732917141 |
| /workspace/coverage/default/33.sram_ctrl_multiple_keys.1925785546 |
| /workspace/coverage/default/33.sram_ctrl_partial_access.4239513859 |
| /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.3985356664 |
| /workspace/coverage/default/33.sram_ctrl_ram_cfg.826993762 |
| /workspace/coverage/default/33.sram_ctrl_regwen.2953526429 |
| /workspace/coverage/default/33.sram_ctrl_smoke.1779535685 |
| /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.798331926 |
| /workspace/coverage/default/33.sram_ctrl_stress_pipeline.1085841027 |
| /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2457434178 |
| /workspace/coverage/default/34.sram_ctrl_access_during_key_req.4173375548 |
| /workspace/coverage/default/34.sram_ctrl_alert_test.2085221685 |
| /workspace/coverage/default/34.sram_ctrl_bijection.475601340 |
| /workspace/coverage/default/34.sram_ctrl_lc_escalation.913877263 |
| /workspace/coverage/default/34.sram_ctrl_max_throughput.4032128218 |
| /workspace/coverage/default/34.sram_ctrl_mem_partial_access.787081629 |
| /workspace/coverage/default/34.sram_ctrl_mem_walk.1833295534 |
| /workspace/coverage/default/34.sram_ctrl_multiple_keys.2486561164 |
| /workspace/coverage/default/34.sram_ctrl_partial_access.4205009600 |
| /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2094994615 |
| /workspace/coverage/default/34.sram_ctrl_ram_cfg.3506924782 |
| /workspace/coverage/default/34.sram_ctrl_regwen.2262347947 |
| /workspace/coverage/default/34.sram_ctrl_smoke.3486277475 |
| /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.452737168 |
| /workspace/coverage/default/34.sram_ctrl_stress_pipeline.322714021 |
| /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1373654755 |
| /workspace/coverage/default/35.sram_ctrl_access_during_key_req.804231436 |
| /workspace/coverage/default/35.sram_ctrl_alert_test.2546265743 |
| /workspace/coverage/default/35.sram_ctrl_bijection.2128196465 |
| /workspace/coverage/default/35.sram_ctrl_executable.1994240242 |
| /workspace/coverage/default/35.sram_ctrl_lc_escalation.1687475761 |
| /workspace/coverage/default/35.sram_ctrl_max_throughput.672199121 |
| /workspace/coverage/default/35.sram_ctrl_mem_partial_access.798195960 |
| /workspace/coverage/default/35.sram_ctrl_mem_walk.2328681187 |
| /workspace/coverage/default/35.sram_ctrl_multiple_keys.2656280804 |
| /workspace/coverage/default/35.sram_ctrl_partial_access.1759979784 |
| /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2905805779 |
| /workspace/coverage/default/35.sram_ctrl_ram_cfg.2942469612 |
| /workspace/coverage/default/35.sram_ctrl_regwen.2799651802 |
| /workspace/coverage/default/35.sram_ctrl_smoke.2134341942 |
| /workspace/coverage/default/35.sram_ctrl_stress_all.1836490697 |
| /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1116045374 |
| /workspace/coverage/default/35.sram_ctrl_stress_pipeline.792208600 |
| /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3204353006 |
| /workspace/coverage/default/36.sram_ctrl_access_during_key_req.154774829 |
| /workspace/coverage/default/36.sram_ctrl_alert_test.2590649743 |
| /workspace/coverage/default/36.sram_ctrl_bijection.4215336902 |
| /workspace/coverage/default/36.sram_ctrl_lc_escalation.3434564794 |
| /workspace/coverage/default/36.sram_ctrl_max_throughput.3044090683 |
| /workspace/coverage/default/36.sram_ctrl_mem_partial_access.3505546854 |
| /workspace/coverage/default/36.sram_ctrl_mem_walk.2840843816 |
| /workspace/coverage/default/36.sram_ctrl_multiple_keys.3967305248 |
| /workspace/coverage/default/36.sram_ctrl_partial_access.958581524 |
| /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.73999012 |
| /workspace/coverage/default/36.sram_ctrl_ram_cfg.2637367271 |
| /workspace/coverage/default/36.sram_ctrl_regwen.2113386463 |
| /workspace/coverage/default/36.sram_ctrl_smoke.1387132822 |
| /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1517221658 |
| /workspace/coverage/default/36.sram_ctrl_stress_pipeline.2059434858 |
| /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.1958085407 |
| /workspace/coverage/default/37.sram_ctrl_access_during_key_req.2338277582 |
| /workspace/coverage/default/37.sram_ctrl_alert_test.2215257831 |
| /workspace/coverage/default/37.sram_ctrl_bijection.1357261651 |
| /workspace/coverage/default/37.sram_ctrl_executable.1859660399 |
| /workspace/coverage/default/37.sram_ctrl_lc_escalation.871087441 |
| /workspace/coverage/default/37.sram_ctrl_max_throughput.3261430860 |
| /workspace/coverage/default/37.sram_ctrl_mem_partial_access.1677576707 |
| /workspace/coverage/default/37.sram_ctrl_mem_walk.2876434428 |
| /workspace/coverage/default/37.sram_ctrl_multiple_keys.2357989121 |
| /workspace/coverage/default/37.sram_ctrl_partial_access.691324514 |
| /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1236030172 |
| /workspace/coverage/default/37.sram_ctrl_ram_cfg.3359360818 |
| /workspace/coverage/default/37.sram_ctrl_regwen.39900809 |
| /workspace/coverage/default/37.sram_ctrl_smoke.2859440767 |
| /workspace/coverage/default/37.sram_ctrl_stress_all.176595469 |
| /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.926439862 |
| /workspace/coverage/default/37.sram_ctrl_stress_pipeline.2099608407 |
| /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.494099809 |
| /workspace/coverage/default/38.sram_ctrl_access_during_key_req.4156633900 |
| /workspace/coverage/default/38.sram_ctrl_bijection.3570451499 |
| /workspace/coverage/default/38.sram_ctrl_lc_escalation.3728778271 |
| /workspace/coverage/default/38.sram_ctrl_max_throughput.709735056 |
| /workspace/coverage/default/38.sram_ctrl_mem_partial_access.1172604115 |
| /workspace/coverage/default/38.sram_ctrl_mem_walk.1726524257 |
| /workspace/coverage/default/38.sram_ctrl_multiple_keys.832428702 |
| /workspace/coverage/default/38.sram_ctrl_partial_access.1411218361 |
| /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2840136881 |
| /workspace/coverage/default/38.sram_ctrl_ram_cfg.4201651108 |
| /workspace/coverage/default/38.sram_ctrl_regwen.3305667701 |
| /workspace/coverage/default/38.sram_ctrl_smoke.1712926069 |
| /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2432247364 |
| /workspace/coverage/default/38.sram_ctrl_stress_pipeline.75883626 |
| /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3615506322 |
| /workspace/coverage/default/39.sram_ctrl_access_during_key_req.462067284 |
| /workspace/coverage/default/39.sram_ctrl_alert_test.344774071 |
| /workspace/coverage/default/39.sram_ctrl_bijection.4255607420 |
| /workspace/coverage/default/39.sram_ctrl_lc_escalation.2754403369 |
| /workspace/coverage/default/39.sram_ctrl_max_throughput.2457666582 |
| /workspace/coverage/default/39.sram_ctrl_mem_partial_access.980998490 |
| /workspace/coverage/default/39.sram_ctrl_mem_walk.1547342751 |
| /workspace/coverage/default/39.sram_ctrl_multiple_keys.3947253382 |
| /workspace/coverage/default/39.sram_ctrl_partial_access.2798852292 |
| /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2281534597 |
| /workspace/coverage/default/39.sram_ctrl_ram_cfg.42794881 |
| /workspace/coverage/default/39.sram_ctrl_regwen.2455509989 |
| /workspace/coverage/default/39.sram_ctrl_smoke.308101508 |
| /workspace/coverage/default/39.sram_ctrl_stress_all.2738412754 |
| /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3589746409 |
| /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1702417136 |
| /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.4124263670 |
| /workspace/coverage/default/4.sram_ctrl_access_during_key_req.660067381 |
| /workspace/coverage/default/4.sram_ctrl_alert_test.3106785999 |
| /workspace/coverage/default/4.sram_ctrl_bijection.1661615848 |
| /workspace/coverage/default/4.sram_ctrl_executable.3338059166 |
| /workspace/coverage/default/4.sram_ctrl_max_throughput.3165809393 |
| /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2299140942 |
| /workspace/coverage/default/4.sram_ctrl_mem_walk.4138280277 |
| /workspace/coverage/default/4.sram_ctrl_multiple_keys.4080572435 |
| /workspace/coverage/default/4.sram_ctrl_partial_access.2605256078 |
| /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1070790674 |
| /workspace/coverage/default/4.sram_ctrl_ram_cfg.2628030809 |
| /workspace/coverage/default/4.sram_ctrl_regwen.1311614761 |
| /workspace/coverage/default/4.sram_ctrl_sec_cm.1448813951 |
| /workspace/coverage/default/4.sram_ctrl_smoke.3949188229 |
| /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2298052396 |
| /workspace/coverage/default/4.sram_ctrl_stress_pipeline.3762390965 |
| /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1865134168 |
| /workspace/coverage/default/40.sram_ctrl_access_during_key_req.1698627019 |
| /workspace/coverage/default/40.sram_ctrl_alert_test.538587566 |
| /workspace/coverage/default/40.sram_ctrl_bijection.2985152409 |
| /workspace/coverage/default/40.sram_ctrl_executable.964648315 |
| /workspace/coverage/default/40.sram_ctrl_lc_escalation.703434629 |
| /workspace/coverage/default/40.sram_ctrl_max_throughput.2358998045 |
| /workspace/coverage/default/40.sram_ctrl_mem_partial_access.168576204 |
| /workspace/coverage/default/40.sram_ctrl_mem_walk.4200748481 |
| /workspace/coverage/default/40.sram_ctrl_multiple_keys.3975288553 |
| /workspace/coverage/default/40.sram_ctrl_partial_access.2029463861 |
| /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3308858177 |
| /workspace/coverage/default/40.sram_ctrl_ram_cfg.3446340325 |
| /workspace/coverage/default/40.sram_ctrl_regwen.2441327038 |
| /workspace/coverage/default/40.sram_ctrl_smoke.2711029577 |
| /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1907364775 |
| /workspace/coverage/default/40.sram_ctrl_stress_pipeline.1322493231 |
| /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1594149508 |
| /workspace/coverage/default/41.sram_ctrl_access_during_key_req.2765911013 |
| /workspace/coverage/default/41.sram_ctrl_alert_test.1305863741 |
| /workspace/coverage/default/41.sram_ctrl_bijection.4093828592 |
| /workspace/coverage/default/41.sram_ctrl_lc_escalation.1882979349 |
| /workspace/coverage/default/41.sram_ctrl_max_throughput.2084473797 |
| /workspace/coverage/default/41.sram_ctrl_mem_partial_access.1913516022 |
| /workspace/coverage/default/41.sram_ctrl_mem_walk.232136174 |
| /workspace/coverage/default/41.sram_ctrl_multiple_keys.986856994 |
| /workspace/coverage/default/41.sram_ctrl_partial_access.4153860783 |
| /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.285925862 |
| /workspace/coverage/default/41.sram_ctrl_ram_cfg.88131214 |
| /workspace/coverage/default/41.sram_ctrl_regwen.3210079194 |
| /workspace/coverage/default/41.sram_ctrl_smoke.2923609519 |
| /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2614906721 |
| /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3391990626 |
| /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3981309307 |
| /workspace/coverage/default/42.sram_ctrl_access_during_key_req.39044653 |
| /workspace/coverage/default/42.sram_ctrl_alert_test.2323882343 |
| /workspace/coverage/default/42.sram_ctrl_bijection.889691496 |
| /workspace/coverage/default/42.sram_ctrl_executable.1441480185 |
| /workspace/coverage/default/42.sram_ctrl_lc_escalation.174801676 |
| /workspace/coverage/default/42.sram_ctrl_max_throughput.1353132361 |
| /workspace/coverage/default/42.sram_ctrl_mem_partial_access.1543128875 |
| /workspace/coverage/default/42.sram_ctrl_mem_walk.1692755649 |
| /workspace/coverage/default/42.sram_ctrl_multiple_keys.274371533 |
| /workspace/coverage/default/42.sram_ctrl_partial_access.4200447290 |
| /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.4056768241 |
| /workspace/coverage/default/42.sram_ctrl_ram_cfg.1954079034 |
| /workspace/coverage/default/42.sram_ctrl_regwen.2133949399 |
| /workspace/coverage/default/42.sram_ctrl_smoke.408577038 |
| /workspace/coverage/default/42.sram_ctrl_stress_all.1109507913 |
| /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3724354406 |
| /workspace/coverage/default/42.sram_ctrl_stress_pipeline.2648029511 |
| /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1378162294 |
| /workspace/coverage/default/43.sram_ctrl_alert_test.137107912 |
| /workspace/coverage/default/43.sram_ctrl_bijection.2169710221 |
| /workspace/coverage/default/43.sram_ctrl_executable.353320598 |
| /workspace/coverage/default/43.sram_ctrl_lc_escalation.3050894948 |
| /workspace/coverage/default/43.sram_ctrl_max_throughput.710355837 |
| /workspace/coverage/default/43.sram_ctrl_mem_partial_access.150425950 |
| /workspace/coverage/default/43.sram_ctrl_mem_walk.3026916198 |
| /workspace/coverage/default/43.sram_ctrl_multiple_keys.784846384 |
| /workspace/coverage/default/43.sram_ctrl_partial_access.948701113 |
| /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.585112671 |
| /workspace/coverage/default/43.sram_ctrl_ram_cfg.1266059623 |
| /workspace/coverage/default/43.sram_ctrl_regwen.3210101981 |
| /workspace/coverage/default/43.sram_ctrl_smoke.1502356092 |
| /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.561732193 |
| /workspace/coverage/default/43.sram_ctrl_stress_pipeline.100827970 |
| /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1667992256 |
| /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1116701637 |
| /workspace/coverage/default/44.sram_ctrl_alert_test.4258803810 |
| /workspace/coverage/default/44.sram_ctrl_bijection.1647228385 |
| /workspace/coverage/default/44.sram_ctrl_executable.4050840091 |
| /workspace/coverage/default/44.sram_ctrl_lc_escalation.3560242300 |
| /workspace/coverage/default/44.sram_ctrl_max_throughput.2925949019 |
| /workspace/coverage/default/44.sram_ctrl_mem_partial_access.274764548 |
| /workspace/coverage/default/44.sram_ctrl_mem_walk.1108688051 |
| /workspace/coverage/default/44.sram_ctrl_multiple_keys.4251006607 |
| /workspace/coverage/default/44.sram_ctrl_partial_access.2057940593 |
| /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.748812713 |
| /workspace/coverage/default/44.sram_ctrl_ram_cfg.2642821880 |
| /workspace/coverage/default/44.sram_ctrl_regwen.1673505650 |
| /workspace/coverage/default/44.sram_ctrl_smoke.96949372 |
| /workspace/coverage/default/44.sram_ctrl_stress_all.1059628069 |
| /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1587104806 |
| /workspace/coverage/default/44.sram_ctrl_stress_pipeline.1723328088 |
| /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.974461641 |
| /workspace/coverage/default/45.sram_ctrl_access_during_key_req.2630309384 |
| /workspace/coverage/default/45.sram_ctrl_alert_test.4042494942 |
| /workspace/coverage/default/45.sram_ctrl_bijection.435165906 |
| /workspace/coverage/default/45.sram_ctrl_executable.649749795 |
| /workspace/coverage/default/45.sram_ctrl_lc_escalation.3464209345 |
| /workspace/coverage/default/45.sram_ctrl_max_throughput.251838964 |
| /workspace/coverage/default/45.sram_ctrl_mem_partial_access.1039532684 |
| /workspace/coverage/default/45.sram_ctrl_mem_walk.998851576 |
| /workspace/coverage/default/45.sram_ctrl_multiple_keys.619405209 |
| /workspace/coverage/default/45.sram_ctrl_partial_access.2969760525 |
| /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2573891288 |
| /workspace/coverage/default/45.sram_ctrl_ram_cfg.3448673906 |
| /workspace/coverage/default/45.sram_ctrl_regwen.4164103749 |
| /workspace/coverage/default/45.sram_ctrl_smoke.951667527 |
| /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2933607368 |
| /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3560380216 |
| /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2530884981 |
| /workspace/coverage/default/46.sram_ctrl_access_during_key_req.746666877 |
| /workspace/coverage/default/46.sram_ctrl_alert_test.237777277 |
| /workspace/coverage/default/46.sram_ctrl_bijection.367776078 |
| /workspace/coverage/default/46.sram_ctrl_executable.4088806009 |
| /workspace/coverage/default/46.sram_ctrl_lc_escalation.643353752 |
| /workspace/coverage/default/46.sram_ctrl_max_throughput.2748479541 |
| /workspace/coverage/default/46.sram_ctrl_mem_partial_access.2642480522 |
| /workspace/coverage/default/46.sram_ctrl_mem_walk.1321530558 |
| /workspace/coverage/default/46.sram_ctrl_multiple_keys.1076984144 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.1821135677 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3879460121 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.415657883 |
| /workspace/coverage/default/46.sram_ctrl_regwen.3741822224 |
| /workspace/coverage/default/46.sram_ctrl_smoke.852570800 |
| /workspace/coverage/default/46.sram_ctrl_stress_all.3059233257 |
| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2147663675 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.525276102 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3805678971 |
| /workspace/coverage/default/47.sram_ctrl_access_during_key_req.2803623106 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.2048092261 |
| /workspace/coverage/default/47.sram_ctrl_bijection.1761955539 |
| /workspace/coverage/default/47.sram_ctrl_executable.856185251 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.2442351130 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.1833201809 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.2904409486 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.3838217448 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.3009073378 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.2795714531 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1482490980 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.3883557336 |
| /workspace/coverage/default/47.sram_ctrl_regwen.3136124240 |
| /workspace/coverage/default/47.sram_ctrl_smoke.2097942024 |
| /workspace/coverage/default/47.sram_ctrl_stress_all.4242172814 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1338508240 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.4071541461 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.4256104769 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.3027500309 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.720585564 |
| /workspace/coverage/default/48.sram_ctrl_bijection.4289760846 |
| /workspace/coverage/default/48.sram_ctrl_executable.1320104450 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.3690102754 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.1015360963 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.4201893870 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.1057463216 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.3281608322 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.940063731 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2743322263 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.3619385357 |
| /workspace/coverage/default/48.sram_ctrl_regwen.3627720183 |
| /workspace/coverage/default/48.sram_ctrl_smoke.4082836316 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.825409410 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3626382184 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3200748659 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.453339136 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.562312385 |
| /workspace/coverage/default/49.sram_ctrl_bijection.3645251431 |
| /workspace/coverage/default/49.sram_ctrl_executable.1871677574 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.4156688270 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.984480032 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2669865021 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.1860733288 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.2162648813 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.2799957558 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3170303070 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.1781427322 |
| /workspace/coverage/default/49.sram_ctrl_regwen.1571295388 |
| /workspace/coverage/default/49.sram_ctrl_smoke.3846115429 |
| /workspace/coverage/default/49.sram_ctrl_stress_all.2439401743 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2244304365 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.3233490910 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3228605171 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.1619768988 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.3574519921 |
| /workspace/coverage/default/5.sram_ctrl_bijection.2406857257 |
| /workspace/coverage/default/5.sram_ctrl_executable.2036601290 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.1671287035 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.577559479 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2698399892 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.1269842255 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.3349623224 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.2720631756 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.23134584 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.374743956 |
| /workspace/coverage/default/5.sram_ctrl_regwen.4104884923 |
| /workspace/coverage/default/5.sram_ctrl_smoke.2108380837 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.67156539 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.733544886 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.844016809 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2254788155 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.3572147017 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.226158713 |
| /workspace/coverage/default/6.sram_ctrl_bijection.1244642104 |
| /workspace/coverage/default/6.sram_ctrl_executable.4207157787 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.921665849 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.195393277 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2637245058 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.2413725433 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.4126986038 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.1234926190 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2417274145 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.1976685290 |
| /workspace/coverage/default/6.sram_ctrl_regwen.371036110 |
| /workspace/coverage/default/6.sram_ctrl_smoke.581025704 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.632131559 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.596207888 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.4147754243 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.206768031 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.2717188196 |
| /workspace/coverage/default/7.sram_ctrl_bijection.1692266082 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.54464971 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.1910253446 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.2277070553 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.4187226043 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.1763608705 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.1549080351 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2565675840 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.462692565 |
| /workspace/coverage/default/7.sram_ctrl_regwen.2970380881 |
| /workspace/coverage/default/7.sram_ctrl_smoke.3449501208 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.3045617276 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2255990145 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.2075229221 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3236653222 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.162672505 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.3450252967 |
| /workspace/coverage/default/8.sram_ctrl_bijection.271726566 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.3952339177 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.2493330908 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1180010393 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.3342378363 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.1345738986 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.4057797949 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.51460135 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.1626264516 |
| /workspace/coverage/default/8.sram_ctrl_regwen.1492937148 |
| /workspace/coverage/default/8.sram_ctrl_smoke.2281611763 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.244559295 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2269499906 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.336883772 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.3223584146 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.1719239934 |
| /workspace/coverage/default/9.sram_ctrl_bijection.3158462543 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.754912787 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.1090486924 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2638651841 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.2596827516 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.1090262183 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.2312799516 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3676697789 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.2310759726 |
| /workspace/coverage/default/9.sram_ctrl_regwen.898526337 |
| /workspace/coverage/default/9.sram_ctrl_smoke.1090995168 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.576208574 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2239248798 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3014174150 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.3384165477 |
|
|
Dec 20 01:06:41 PM PST 23 |
Dec 20 01:20:36 PM PST 23 |
30036146448 ps |
| T2 |
/workspace/coverage/default/27.sram_ctrl_bijection.315413125 |
|
|
Dec 20 01:06:04 PM PST 23 |
Dec 20 01:46:32 PM PST 23 |
170771397781 ps |
| T3 |
/workspace/coverage/default/12.sram_ctrl_regwen.2569795528 |
|
|
Dec 20 01:05:10 PM PST 23 |
Dec 20 01:08:28 PM PST 23 |
632302223 ps |
| T9 |
/workspace/coverage/default/31.sram_ctrl_alert_test.3429983594 |
|
|
Dec 20 01:06:15 PM PST 23 |
Dec 20 01:06:27 PM PST 23 |
18317227 ps |
| T5 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.1822710832 |
|
|
Dec 20 01:06:11 PM PST 23 |
Dec 20 01:07:49 PM PST 23 |
1510400554 ps |
| T4 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.3963725945 |
|
|
Dec 20 01:04:58 PM PST 23 |
Dec 20 01:08:04 PM PST 23 |
11305668375 ps |
| T10 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3441534564 |
|
|
Dec 20 01:05:15 PM PST 23 |
Dec 20 01:48:22 PM PST 23 |
2312529829 ps |
| T11 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.1833295534 |
|
|
Dec 20 01:06:15 PM PST 23 |
Dec 20 01:10:28 PM PST 23 |
3948232021 ps |
| T12 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.4156633900 |
|
|
Dec 20 01:06:17 PM PST 23 |
Dec 20 01:19:25 PM PST 23 |
6239811682 ps |
| T13 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.3838740289 |
|
|
Dec 20 01:05:30 PM PST 23 |
Dec 20 01:08:07 PM PST 23 |
10016058908 ps |
| T14 |
/workspace/coverage/default/18.sram_ctrl_partial_access.2931025898 |
|
|
Dec 20 01:05:37 PM PST 23 |
Dec 20 01:07:20 PM PST 23 |
2335634440 ps |
| T15 |
/workspace/coverage/default/29.sram_ctrl_partial_access.3451995056 |
|
|
Dec 20 01:06:05 PM PST 23 |
Dec 20 01:08:52 PM PST 23 |
2777609169 ps |
| T16 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.1079228958 |
|
|
Dec 20 01:05:20 PM PST 23 |
Dec 20 01:28:31 PM PST 23 |
50734541474 ps |
| T22 |
/workspace/coverage/default/45.sram_ctrl_alert_test.4042494942 |
|
|
Dec 20 01:06:52 PM PST 23 |
Dec 20 01:07:16 PM PST 23 |
64234648 ps |
| T17 |
/workspace/coverage/default/21.sram_ctrl_regwen.273332014 |
|
|
Dec 20 01:05:41 PM PST 23 |
Dec 20 01:30:05 PM PST 23 |
40548324648 ps |
| T18 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.805675602 |
|
|
Dec 20 01:05:39 PM PST 23 |
Dec 20 01:06:59 PM PST 23 |
763756345 ps |
| T49 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.784901869 |
|
|
Dec 20 01:05:24 PM PST 23 |
Dec 20 01:12:40 PM PST 23 |
25523202212 ps |
| T50 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.1913516022 |
|
|
Dec 20 01:06:45 PM PST 23 |
Dec 20 01:08:32 PM PST 23 |
5049229008 ps |
| T98 |
/workspace/coverage/default/26.sram_ctrl_smoke.4130205271 |
|
|
Dec 20 01:05:58 PM PST 23 |
Dec 20 01:07:35 PM PST 23 |
2414787908 ps |
| T99 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.596207888 |
|
|
Dec 20 01:05:13 PM PST 23 |
Dec 20 01:10:02 PM PST 23 |
17984725610 ps |
| T133 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.3321369892 |
|
|
Dec 20 01:05:24 PM PST 23 |
Dec 20 01:07:36 PM PST 23 |
1980167342 ps |
| T134 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.2457666582 |
|
|
Dec 20 01:06:15 PM PST 23 |
Dec 20 01:06:56 PM PST 23 |
1389239809 ps |
| T27 |
/workspace/coverage/default/30.sram_ctrl_stress_all.2368884330 |
|
|
Dec 20 01:06:02 PM PST 23 |
Dec 20 01:41:17 PM PST 23 |
19024336684 ps |
| T28 |
/workspace/coverage/default/39.sram_ctrl_regwen.2455509989 |
|
|
Dec 20 01:06:17 PM PST 23 |
Dec 20 01:11:11 PM PST 23 |
3193323754 ps |
| T135 |
/workspace/coverage/default/47.sram_ctrl_bijection.1761955539 |
|
|
Dec 20 01:07:07 PM PST 23 |
Dec 20 01:29:02 PM PST 23 |
60044525280 ps |
| T100 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.141180520 |
|
|
Dec 20 01:05:36 PM PST 23 |
Dec 20 01:13:20 PM PST 23 |
8356090437 ps |
| T101 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1418802307 |
|
|
Dec 20 01:05:23 PM PST 23 |
Dec 20 01:06:20 PM PST 23 |
745048531 ps |
| T102 |
/workspace/coverage/default/37.sram_ctrl_bijection.1357261651 |
|
|
Dec 20 01:06:11 PM PST 23 |
Dec 20 01:21:44 PM PST 23 |
41608266556 ps |
| T6 |
/workspace/coverage/default/28.sram_ctrl_stress_all.440282643 |
|
|
Dec 20 01:06:00 PM PST 23 |
Dec 20 02:03:40 PM PST 23 |
48784205640 ps |
| T29 |
/workspace/coverage/default/29.sram_ctrl_regwen.1559530797 |
|
|
Dec 20 01:06:10 PM PST 23 |
Dec 20 01:25:21 PM PST 23 |
38030782985 ps |
| T103 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.2413725433 |
|
|
Dec 20 01:05:03 PM PST 23 |
Dec 20 01:08:01 PM PST 23 |
10764467074 ps |
| T136 |
/workspace/coverage/default/26.sram_ctrl_bijection.2267413023 |
|
|
Dec 20 01:06:04 PM PST 23 |
Dec 20 01:26:56 PM PST 23 |
77635571601 ps |
| T105 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3608754350 |
|
|
Dec 20 01:05:50 PM PST 23 |
Dec 20 01:16:37 PM PST 23 |
25199467716 ps |
| T106 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.2421970396 |
|
|
Dec 20 01:06:15 PM PST 23 |
Dec 20 01:09:17 PM PST 23 |
2617881865 ps |
| T137 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3981309307 |
|
|
Dec 20 01:06:44 PM PST 23 |
Dec 20 01:09:31 PM PST 23 |
7780380617 ps |
| T138 |
/workspace/coverage/default/0.sram_ctrl_partial_access.3045509118 |
|
|
Dec 20 01:05:02 PM PST 23 |
Dec 20 01:05:54 PM PST 23 |
4925414194 ps |
| T20 |
/workspace/coverage/default/7.sram_ctrl_alert_test.2717188196 |
|
|
Dec 20 01:05:17 PM PST 23 |
Dec 20 01:05:39 PM PST 23 |
47405693 ps |
| T139 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.4032128218 |
|
|
Dec 20 01:06:13 PM PST 23 |
Dec 20 01:07:26 PM PST 23 |
1481835902 ps |
| T140 |
/workspace/coverage/default/24.sram_ctrl_bijection.459700853 |
|
|
Dec 20 01:06:07 PM PST 23 |
Dec 20 01:30:28 PM PST 23 |
67263399924 ps |
| T19 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.154774829 |
|
|
Dec 20 01:06:05 PM PST 23 |
Dec 20 01:22:15 PM PST 23 |
77369048497 ps |
| T141 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2289199784 |
|
|
Dec 20 01:05:07 PM PST 23 |
Dec 20 01:09:44 PM PST 23 |
19947392342 ps |
| T35 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.1781427322 |
|
|
Dec 20 01:07:19 PM PST 23 |
Dec 20 01:07:39 PM PST 23 |
1469784790 ps |
| T51 |
/workspace/coverage/default/49.sram_ctrl_executable.1871677574 |
|
|
Dec 20 01:07:20 PM PST 23 |
Dec 20 01:12:42 PM PST 23 |
39493917954 ps |
| T142 |
/workspace/coverage/default/5.sram_ctrl_bijection.2406857257 |
|
|
Dec 20 01:05:13 PM PST 23 |
Dec 20 01:33:52 PM PST 23 |
104612790365 ps |
| T143 |
/workspace/coverage/default/41.sram_ctrl_regwen.3210079194 |
|
|
Dec 20 01:06:44 PM PST 23 |
Dec 20 01:13:28 PM PST 23 |
4682360830 ps |
| T76 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2262160493 |
|
|
Dec 20 01:05:21 PM PST 23 |
Dec 20 01:19:19 PM PST 23 |
13094304108 ps |
| T144 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.2914800566 |
|
|
Dec 20 01:05:20 PM PST 23 |
Dec 20 01:14:20 PM PST 23 |
77172120978 ps |
| T145 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.4147754243 |
|
|
Dec 20 01:05:08 PM PST 23 |
Dec 20 01:06:06 PM PST 23 |
9766400226 ps |
| T107 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.1126823786 |
|
|
Dec 20 01:05:38 PM PST 23 |
Dec 20 01:13:42 PM PST 23 |
25444031069 ps |
| T146 |
/workspace/coverage/default/1.sram_ctrl_smoke.1269902421 |
|
|
Dec 20 01:05:03 PM PST 23 |
Dec 20 01:05:45 PM PST 23 |
2721348840 ps |
| T7 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.3727303426 |
|
|
Dec 20 01:05:34 PM PST 23 |
Dec 20 01:06:19 PM PST 23 |
2410963285 ps |
| T8 |
/workspace/coverage/default/40.sram_ctrl_stress_all.660729827 |
|
|
Dec 20 01:06:34 PM PST 23 |
Dec 20 01:31:39 PM PST 23 |
64250547525 ps |
| T147 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.2840843816 |
|
|
Dec 20 01:06:11 PM PST 23 |
Dec 20 01:08:57 PM PST 23 |
15987033888 ps |
| T21 |
/workspace/coverage/default/30.sram_ctrl_alert_test.3711311545 |
|
|
Dec 20 01:06:06 PM PST 23 |
Dec 20 01:06:16 PM PST 23 |
16344730 ps |
| T148 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1425115541 |
|
|
Dec 20 01:05:55 PM PST 23 |
Dec 20 01:07:31 PM PST 23 |
1528616181 ps |
| T149 |
/workspace/coverage/default/4.sram_ctrl_bijection.1661615848 |
|
|
Dec 20 01:05:10 PM PST 23 |
Dec 20 01:27:01 PM PST 23 |
77878662956 ps |
| T32 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3720190396 |
|
|
Dec 20 01:06:06 PM PST 23 |
Dec 20 02:11:11 PM PST 23 |
757521513 ps |
| T150 |
/workspace/coverage/default/17.sram_ctrl_smoke.1169773605 |
|
|
Dec 20 01:05:25 PM PST 23 |
Dec 20 01:06:09 PM PST 23 |
3897267354 ps |
| T34 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.853350892 |
|
|
Dec 20 12:24:03 PM PST 23 |
Dec 20 12:24:44 PM PST 23 |
53771225 ps |
| T65 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3900978694 |
|
|
Dec 20 12:23:51 PM PST 23 |
Dec 20 12:24:33 PM PST 23 |
42348775 ps |
| T104 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1476110232 |
|
|
Dec 20 12:24:06 PM PST 23 |
Dec 20 12:24:44 PM PST 23 |
30954936 ps |
| T33 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3028608864 |
|
|
Dec 20 12:23:30 PM PST 23 |
Dec 20 12:24:09 PM PST 23 |
185316973 ps |
| T66 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1024980113 |
|
|
Dec 20 12:24:58 PM PST 23 |
Dec 20 12:29:54 PM PST 23 |
7343108459 ps |
| T67 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1832281847 |
|
|
Dec 20 12:23:41 PM PST 23 |
Dec 20 12:24:20 PM PST 23 |
66142447 ps |
| T55 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.473052804 |
|
|
Dec 20 12:23:41 PM PST 23 |
Dec 20 12:24:32 PM PST 23 |
351942929 ps |
| T56 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3515495830 |
|
|
Dec 20 12:23:47 PM PST 23 |
Dec 20 12:24:33 PM PST 23 |
1400126104 ps |
| T53 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3836010186 |
|
|
Dec 20 12:25:03 PM PST 23 |
Dec 20 12:25:26 PM PST 23 |
264130108 ps |
| T68 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2695098247 |
|
|
Dec 20 12:26:02 PM PST 23 |
Dec 20 12:26:25 PM PST 23 |
149352681 ps |
| T57 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3298876059 |
|
|
Dec 20 12:23:49 PM PST 23 |
Dec 20 12:24:36 PM PST 23 |
711517627 ps |
| T54 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3674433424 |
|
|
Dec 20 12:24:13 PM PST 23 |
Dec 20 12:24:51 PM PST 23 |
262643111 ps |
| T58 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4147210052 |
|
|
Dec 20 12:23:47 PM PST 23 |
Dec 20 12:24:30 PM PST 23 |
224249204 ps |
| T90 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3631606127 |
|
|
Dec 20 12:23:30 PM PST 23 |
Dec 20 12:24:08 PM PST 23 |
14473410 ps |
| T59 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3112277601 |
|
|
Dec 20 12:23:29 PM PST 23 |
Dec 20 12:24:13 PM PST 23 |
2143885041 ps |
| T69 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3737740503 |
|
|
Dec 20 12:24:05 PM PST 23 |
Dec 20 12:25:40 PM PST 23 |
7539707348 ps |
| T60 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2973167360 |
|
|
Dec 20 12:23:40 PM PST 23 |
Dec 20 12:24:20 PM PST 23 |
212836590 ps |
| T70 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2605129758 |
|
|
Dec 20 12:23:40 PM PST 23 |
Dec 20 12:24:20 PM PST 23 |
46940079 ps |
| T62 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3180328360 |
|
|
Dec 20 12:23:42 PM PST 23 |
Dec 20 12:24:22 PM PST 23 |
90004809 ps |
| T112 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2635219064 |
|
|
Dec 20 12:23:37 PM PST 23 |
Dec 20 12:24:16 PM PST 23 |
14104238 ps |
| T61 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.4125876218 |
|
|
Dec 20 12:24:06 PM PST 23 |
Dec 20 12:24:46 PM PST 23 |
43695479 ps |
| T119 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.936128858 |
|
|
Dec 20 12:23:27 PM PST 23 |
Dec 20 12:24:04 PM PST 23 |
74846572 ps |
| T71 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.935400677 |
|
|
Dec 20 12:25:06 PM PST 23 |
Dec 20 12:25:27 PM PST 23 |
22249845 ps |
| T72 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2083418423 |
|
|
Dec 20 12:23:40 PM PST 23 |
Dec 20 12:28:43 PM PST 23 |
7114945806 ps |
| T63 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3372711392 |
|
|
Dec 20 12:23:57 PM PST 23 |
Dec 20 12:24:38 PM PST 23 |
533082119 ps |
| T73 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.302300064 |
|
|
Dec 20 12:23:29 PM PST 23 |
Dec 20 12:24:07 PM PST 23 |
17120210 ps |
| T151 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4264142722 |
|
|
Dec 20 12:23:37 PM PST 23 |
Dec 20 12:24:28 PM PST 23 |
364307632 ps |
| T152 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1527148559 |
|
|
Dec 20 12:23:35 PM PST 23 |
Dec 20 12:24:23 PM PST 23 |
721720869 ps |
| T74 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2328247626 |
|
|
Dec 20 12:26:06 PM PST 23 |
Dec 20 12:27:32 PM PST 23 |
3720645541 ps |
| T75 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3811351651 |
|
|
Dec 20 12:23:25 PM PST 23 |
Dec 20 12:24:00 PM PST 23 |
24953104 ps |
| T153 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.705193943 |
|
|
Dec 20 12:24:10 PM PST 23 |
Dec 20 12:24:49 PM PST 23 |
37200054 ps |
| T77 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2551611589 |
|
|
Dec 20 12:26:01 PM PST 23 |
Dec 20 12:26:24 PM PST 23 |
14232030 ps |
| T114 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3052548302 |
|
|
Dec 20 12:23:48 PM PST 23 |
Dec 20 12:24:34 PM PST 23 |
1424385596 ps |
| T64 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2026987688 |
|
|
Dec 20 12:23:34 PM PST 23 |
Dec 20 12:24:12 PM PST 23 |
218160801 ps |
| T78 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4171881112 |
|
|
Dec 20 12:23:35 PM PST 23 |
Dec 20 12:24:13 PM PST 23 |
41907664 ps |
| T154 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1491870921 |
|
|
Dec 20 12:23:19 PM PST 23 |
Dec 20 12:25:45 PM PST 23 |
7998113736 ps |
| T155 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.247312846 |
|
|
Dec 20 12:23:48 PM PST 23 |
Dec 20 12:24:35 PM PST 23 |
648081298 ps |
| T156 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.598728584 |
|
|
Dec 20 12:23:38 PM PST 23 |
Dec 20 12:24:16 PM PST 23 |
16431653 ps |
| T157 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.792267912 |
|
|
Dec 20 12:26:12 PM PST 23 |
Dec 20 12:26:44 PM PST 23 |
451717666 ps |
| T158 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1760877031 |
|
|
Dec 20 12:23:38 PM PST 23 |
Dec 20 12:24:17 PM PST 23 |
82154633 ps |
| T79 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1062733829 |
|
|
Dec 20 12:23:25 PM PST 23 |
Dec 20 12:24:00 PM PST 23 |
25727327 ps |
| T159 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2979496442 |
|
|
Dec 20 12:24:50 PM PST 23 |
Dec 20 12:25:22 PM PST 23 |
31496337 ps |
| T115 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1047888017 |
|
|
Dec 20 12:23:39 PM PST 23 |
Dec 20 12:24:19 PM PST 23 |
169521136 ps |
| T87 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2470637032 |
|
|
Dec 20 12:23:32 PM PST 23 |
Dec 20 12:26:33 PM PST 23 |
24614517679 ps |
| T160 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3357458393 |
|
|
Dec 20 12:23:39 PM PST 23 |
Dec 20 12:24:17 PM PST 23 |
115396282 ps |
| T161 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2009134698 |
|
|
Dec 20 12:25:24 PM PST 23 |
Dec 20 12:25:49 PM PST 23 |
12945601 ps |
| T162 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2503603751 |
|
|
Dec 20 12:24:01 PM PST 23 |
Dec 20 12:24:41 PM PST 23 |
76457468 ps |
| T163 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.22268399 |
|
|
Dec 20 12:23:40 PM PST 23 |
Dec 20 12:24:31 PM PST 23 |
363514010 ps |
| T164 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.555751222 |
|
|
Dec 20 12:23:30 PM PST 23 |
Dec 20 12:24:09 PM PST 23 |
74797933 ps |
| T165 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1523796201 |
|
|
Dec 20 12:23:49 PM PST 23 |
Dec 20 12:24:32 PM PST 23 |
34028794 ps |
| T166 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2626606796 |
|
|
Dec 20 12:23:56 PM PST 23 |
Dec 20 12:24:51 PM PST 23 |
1293440498 ps |
| T88 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.301771876 |
|
|
Dec 20 12:23:25 PM PST 23 |
Dec 20 12:24:00 PM PST 23 |
17474545 ps |
| T167 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3099527303 |
|
|
Dec 20 12:23:40 PM PST 23 |
Dec 20 12:24:19 PM PST 23 |
125151325 ps |
| T168 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1584441325 |
|
|
Dec 20 12:23:31 PM PST 23 |
Dec 20 12:24:12 PM PST 23 |
491308992 ps |
| T121 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1756378352 |
|
|
Dec 20 12:26:01 PM PST 23 |
Dec 20 12:26:26 PM PST 23 |
365991707 ps |
| T89 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1198893183 |
|
|
Dec 20 12:25:17 PM PST 23 |
Dec 20 12:27:25 PM PST 23 |
32011877687 ps |
| T97 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4285565025 |
|
|
Dec 20 12:26:08 PM PST 23 |
Dec 20 12:28:35 PM PST 23 |
25267841351 ps |
| T169 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.133319477 |
|
|
Dec 20 12:26:27 PM PST 23 |
Dec 20 12:27:51 PM PST 23 |
3857020632 ps |
| T170 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.685565563 |
|
|
Dec 20 12:25:54 PM PST 23 |
Dec 20 12:26:20 PM PST 23 |
178402671 ps |
| T171 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1397455104 |
|
|
Dec 20 12:24:00 PM PST 23 |
Dec 20 12:24:41 PM PST 23 |
44558940 ps |
| T122 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1424855948 |
|
|
Dec 20 12:23:54 PM PST 23 |
Dec 20 12:24:36 PM PST 23 |
181156460 ps |
| T172 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1900520943 |
|
|
Dec 20 12:23:38 PM PST 23 |
Dec 20 12:24:29 PM PST 23 |
58018314 ps |
| T173 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2633561802 |
|
|
Dec 20 12:26:17 PM PST 23 |
Dec 20 12:26:49 PM PST 23 |
13930752 ps |
| T174 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3430121587 |
|
|
Dec 20 12:26:06 PM PST 23 |
Dec 20 12:27:35 PM PST 23 |
30702741208 ps |
| T175 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.470387198 |
|
|
Dec 20 12:23:46 PM PST 23 |
Dec 20 12:24:27 PM PST 23 |
34859801 ps |
| T176 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4181950088 |
|
|
Dec 20 12:23:58 PM PST 23 |
Dec 20 12:24:39 PM PST 23 |
56564609 ps |
| T177 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3370200089 |
|
|
Dec 20 12:25:09 PM PST 23 |
Dec 20 12:25:29 PM PST 23 |
30174563 ps |
| T178 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1160647988 |
|
|
Dec 20 12:23:46 PM PST 23 |
Dec 20 12:24:27 PM PST 23 |
121764519 ps |
| T179 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2255262488 |
|
|
Dec 20 12:24:32 PM PST 23 |
Dec 20 12:26:06 PM PST 23 |
3890338030 ps |
| T180 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.733119996 |
|
|
Dec 20 12:23:45 PM PST 23 |
Dec 20 12:24:27 PM PST 23 |
106315845 ps |
| T181 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3544444641 |
|
|
Dec 20 12:25:31 PM PST 23 |
Dec 20 12:26:04 PM PST 23 |
1353798568 ps |
| T182 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1455555363 |
|
|
Dec 20 12:23:45 PM PST 23 |
Dec 20 12:24:25 PM PST 23 |
14958050 ps |
| T183 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1587576315 |
|
|
Dec 20 12:23:37 PM PST 23 |
Dec 20 12:24:16 PM PST 23 |
121591470 ps |
| T91 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2896859608 |
|
|
Dec 20 12:23:40 PM PST 23 |
Dec 20 12:24:19 PM PST 23 |
63831169 ps |
| T120 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2027405465 |
|
|
Dec 20 12:23:55 PM PST 23 |
Dec 20 12:24:37 PM PST 23 |
3450088374 ps |
| T184 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.389056302 |
|
|
Dec 20 12:23:39 PM PST 23 |
Dec 20 12:24:23 PM PST 23 |
39515388 ps |
| T185 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1232147997 |
|
|
Dec 20 12:24:05 PM PST 23 |
Dec 20 12:24:44 PM PST 23 |
15522585 ps |
| T186 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2718516225 |
|
|
Dec 20 12:25:16 PM PST 23 |
Dec 20 12:25:40 PM PST 23 |
276814978 ps |
| T124 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.115314909 |
|
|
Dec 20 12:24:11 PM PST 23 |
Dec 20 12:24:52 PM PST 23 |
808848835 ps |
| T187 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3696282182 |
|
|
Dec 20 12:25:18 PM PST 23 |
Dec 20 12:25:41 PM PST 23 |
104437989 ps |
| T188 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.562875955 |
|
|
Dec 20 12:25:13 PM PST 23 |
Dec 20 12:25:32 PM PST 23 |
81295930 ps |
| T189 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3273529222 |
|
|
Dec 20 12:23:40 PM PST 23 |
Dec 20 12:25:22 PM PST 23 |
14799991264 ps |
| T190 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3359570538 |
|
|
Dec 20 12:23:42 PM PST 23 |
Dec 20 12:24:22 PM PST 23 |
220289072 ps |
| T191 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3094628880 |
|
|
Dec 20 12:23:41 PM PST 23 |
Dec 20 12:24:21 PM PST 23 |
98176680 ps |
| T92 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1964085705 |
|
|
Dec 20 12:24:12 PM PST 23 |
Dec 20 12:24:50 PM PST 23 |
15686714 ps |
| T93 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1255989838 |
|
|
Dec 20 12:24:33 PM PST 23 |
Dec 20 12:27:31 PM PST 23 |
7379609193 ps |
| T192 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2201514465 |
|
|
Dec 20 12:24:09 PM PST 23 |
Dec 20 12:24:49 PM PST 23 |
145048822 ps |
| T193 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.633498965 |
|
|
Dec 20 12:24:11 PM PST 23 |
Dec 20 12:25:49 PM PST 23 |
3746571636 ps |
| T194 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1573530981 |
|
|
Dec 20 12:23:37 PM PST 23 |
Dec 20 12:24:16 PM PST 23 |
42386282 ps |
| T195 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3248805434 |
|
|
Dec 20 12:23:45 PM PST 23 |
Dec 20 12:24:26 PM PST 23 |
39307470 ps |
| T123 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1588010477 |
|
|
Dec 20 12:24:06 PM PST 23 |
Dec 20 12:24:45 PM PST 23 |
140537546 ps |
| T196 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3620156682 |
|
|
Dec 20 12:23:22 PM PST 23 |
Dec 20 12:23:55 PM PST 23 |
17500441 ps |
| T197 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3204436442 |
|
|
Dec 20 12:24:29 PM PST 23 |
Dec 20 12:25:02 PM PST 23 |
47958939 ps |
| T198 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2189749395 |
|
|
Dec 20 12:23:26 PM PST 23 |
Dec 20 12:24:06 PM PST 23 |
523787930 ps |
| T199 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1973638718 |
|
|
Dec 20 12:23:50 PM PST 23 |
Dec 20 12:24:33 PM PST 23 |
54177790 ps |
| T200 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.730271750 |
|
|
Dec 20 12:24:11 PM PST 23 |
Dec 20 12:24:50 PM PST 23 |
72319518 ps |
| T201 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2309700703 |
|
|
Dec 20 12:24:09 PM PST 23 |
Dec 20 12:27:05 PM PST 23 |
3837826207 ps |
| T202 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.687966635 |
|
|
Dec 20 12:23:47 PM PST 23 |
Dec 20 12:24:28 PM PST 23 |
38021969 ps |
| T203 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1826284747 |
|
|
Dec 20 12:26:15 PM PST 23 |
Dec 20 12:26:50 PM PST 23 |
699086378 ps |
| T204 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.339026883 |
|
|
Dec 20 12:23:29 PM PST 23 |
Dec 20 12:24:08 PM PST 23 |
72356552 ps |
| T205 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.891677733 |
|
|
Dec 20 12:23:22 PM PST 23 |
Dec 20 12:23:56 PM PST 23 |
791009314 ps |
| T206 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2933276014 |
|
|
Dec 20 12:24:10 PM PST 23 |
Dec 20 12:24:52 PM PST 23 |
356391760 ps |
| T207 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.757600602 |
|
|
Dec 20 12:24:05 PM PST 23 |
Dec 20 12:24:43 PM PST 23 |
18886488 ps |
| T208 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1347998181 |
|
|
Dec 20 12:23:20 PM PST 23 |
Dec 20 12:23:55 PM PST 23 |
755767266 ps |
| T209 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1884520779 |
|
|
Dec 20 12:26:04 PM PST 23 |
Dec 20 12:27:35 PM PST 23 |
61486537123 ps |
| T94 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1370239610 |
|
|
Dec 20 12:23:57 PM PST 23 |
Dec 20 12:24:38 PM PST 23 |
15990934 ps |
| T125 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3919089041 |
|
|
Dec 20 12:23:16 PM PST 23 |
Dec 20 12:23:44 PM PST 23 |
202174018 ps |
| T210 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.227213772 |
|
|
Dec 20 12:26:12 PM PST 23 |
Dec 20 12:26:43 PM PST 23 |
177141388 ps |
| T211 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.77951093 |
|
|
Dec 20 12:23:41 PM PST 23 |
Dec 20 12:24:26 PM PST 23 |
2799850064 ps |
| T95 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4227311034 |
|
|
Dec 20 12:23:21 PM PST 23 |
Dec 20 12:26:07 PM PST 23 |
7740701305 ps |
| T96 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3664959984 |
|
|
Dec 20 12:25:18 PM PST 23 |
Dec 20 12:25:40 PM PST 23 |
17389136 ps |
| T212 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1296084072 |
|
|
Dec 20 12:23:23 PM PST 23 |
Dec 20 12:24:01 PM PST 23 |
354200034 ps |
| T213 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1020091536 |
|
|
Dec 20 12:23:30 PM PST 23 |
Dec 20 12:24:08 PM PST 23 |
12164023 ps |
| T214 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3826078944 |
|
|
Dec 20 12:23:40 PM PST 23 |
Dec 20 12:26:18 PM PST 23 |
28469043230 ps |
| T215 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2488675577 |
|
|
Dec 20 12:23:40 PM PST 23 |
Dec 20 12:24:24 PM PST 23 |
1580795473 ps |
| T216 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3738747535 |
|
|
Dec 20 12:23:30 PM PST 23 |
Dec 20 12:24:08 PM PST 23 |
40101098 ps |
| T217 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3741366182 |
|
|
Dec 20 12:23:41 PM PST 23 |
Dec 20 12:24:24 PM PST 23 |
76351141 ps |
| T218 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1263175673 |
|
|
Dec 20 12:23:36 PM PST 23 |
Dec 20 12:28:46 PM PST 23 |
63898273306 ps |
| T219 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3225194377 |
|
|
Dec 20 12:24:13 PM PST 23 |
Dec 20 12:24:52 PM PST 23 |
148410424 ps |
| T220 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3922029585 |
|
|
Dec 20 12:25:09 PM PST 23 |
Dec 20 12:25:29 PM PST 23 |
44860720 ps |
| T221 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.29924268 |
|
|
Dec 20 12:23:42 PM PST 23 |
Dec 20 12:24:28 PM PST 23 |
106619466 ps |
| T222 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4019091241 |
|
|
Dec 20 12:23:41 PM PST 23 |
Dec 20 12:24:21 PM PST 23 |
97969043 ps |
| T223 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2106277428 |
|
|
Dec 20 12:23:40 PM PST 23 |
Dec 20 12:24:18 PM PST 23 |
20038838 ps |
| T224 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3194545032 |
|
|
Dec 20 12:24:07 PM PST 23 |
Dec 20 12:24:47 PM PST 23 |
602680005 ps |
| T225 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3131601499 |
|
|
Dec 20 12:24:00 PM PST 23 |
Dec 20 12:24:42 PM PST 23 |
60738665 ps |
| T226 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.363018421 |
|
|
Dec 20 12:26:12 PM PST 23 |
Dec 20 12:30:59 PM PST 23 |
35239504272 ps |
| T227 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.103166580 |
|
|
Dec 20 12:24:04 PM PST 23 |
Dec 20 12:24:43 PM PST 23 |
42881470 ps |
| T228 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.450676478 |
|
|
Dec 20 12:23:42 PM PST 23 |
Dec 20 12:24:21 PM PST 23 |
17356134 ps |
| T229 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2098227429 |
|
|
Dec 20 12:26:00 PM PST 23 |
Dec 20 12:26:24 PM PST 23 |
27766469 ps |
| T230 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.753228475 |
|
|
Dec 20 12:24:57 PM PST 23 |
Dec 20 12:25:24 PM PST 23 |
152397761 ps |
| T231 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2006255416 |
|
|
Dec 20 12:23:28 PM PST 23 |
Dec 20 12:24:09 PM PST 23 |
428204859 ps |
| T232 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2187086778 |
|
|
Dec 20 12:23:28 PM PST 23 |
Dec 20 12:24:06 PM PST 23 |
69038726 ps |
| T233 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1362674744 |
|
|
Dec 20 12:23:46 PM PST 23 |
Dec 20 12:24:30 PM PST 23 |
1399183057 ps |
| T234 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.845509542 |
|
|
Dec 20 12:24:16 PM PST 23 |
Dec 20 12:25:06 PM PST 23 |
1584860478 ps |
| T235 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3223537053 |
|
|
Dec 20 12:24:03 PM PST 23 |
Dec 20 12:24:48 PM PST 23 |
6850488985 ps |
| T52 |
/workspace/coverage/default/6.sram_ctrl_regwen.371036110 |
|
|
Dec 20 01:05:12 PM PST 23 |
Dec 20 01:27:32 PM PST 23 |
19394059539 ps |
| T236 |
/workspace/coverage/default/49.sram_ctrl_alert_test.562312385 |
|
|
Dec 20 01:07:19 PM PST 23 |
Dec 20 01:07:33 PM PST 23 |
18261276 ps |
| T237 |
/workspace/coverage/default/39.sram_ctrl_bijection.4255607420 |
|
|
Dec 20 01:06:17 PM PST 23 |
Dec 20 01:31:10 PM PST 23 |
277304067956 ps |
| T238 |
/workspace/coverage/default/40.sram_ctrl_bijection.2985152409 |
|
|
Dec 20 01:06:09 PM PST 23 |
Dec 20 01:41:14 PM PST 23 |
197363929047 ps |
| T239 |
/workspace/coverage/default/38.sram_ctrl_alert_test.400229594 |
|
|
Dec 20 01:06:12 PM PST 23 |
Dec 20 01:06:23 PM PST 23 |
41095510 ps |
| T113 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.345510598 |
|
|
Dec 20 01:05:34 PM PST 23 |
Dec 20 02:01:36 PM PST 23 |
4706427750 ps |
| T108 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3268532801 |
|
|
Dec 20 01:04:58 PM PST 23 |
Dec 20 01:14:00 PM PST 23 |
34404722330 ps |
| T240 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2727777778 |
|
|
Dec 20 01:05:26 PM PST 23 |
Dec 20 01:08:21 PM PST 23 |
1567541404 ps |
| T241 |
/workspace/coverage/default/36.sram_ctrl_bijection.4215336902 |
|
|
Dec 20 01:06:17 PM PST 23 |
Dec 20 01:20:20 PM PST 23 |
50825179792 ps |
| T131 |
/workspace/coverage/default/36.sram_ctrl_regwen.2113386463 |
|
|
Dec 20 01:06:14 PM PST 23 |
Dec 20 01:23:50 PM PST 23 |
73866663049 ps |
| T242 |
/workspace/coverage/default/42.sram_ctrl_partial_access.4200447290 |
|
|
Dec 20 01:06:45 PM PST 23 |
Dec 20 01:07:54 PM PST 23 |
2900385192 ps |
| T127 |
/workspace/coverage/default/44.sram_ctrl_regwen.1673505650 |
|
|
Dec 20 01:06:42 PM PST 23 |
Dec 20 01:22:49 PM PST 23 |
20981577129 ps |
| T243 |
/workspace/coverage/default/13.sram_ctrl_bijection.3241903975 |
|
|
Dec 20 01:05:30 PM PST 23 |
Dec 20 01:26:46 PM PST 23 |
240602693125 ps |
| T244 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1081441388 |
|
|
Dec 20 01:04:56 PM PST 23 |
Dec 20 01:06:22 PM PST 23 |
3153727771 ps |
| T245 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.4180153368 |
|
|
Dec 20 01:04:57 PM PST 23 |
Dec 20 01:25:07 PM PST 23 |
15290427499 ps |
| T246 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.201052782 |
|
|
Dec 20 01:06:09 PM PST 23 |
Dec 20 01:08:25 PM PST 23 |
13150835234 ps |
| T247 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.4124263670 |
|
|
Dec 20 01:06:13 PM PST 23 |
Dec 20 01:06:51 PM PST 23 |
1446643396 ps |
| T248 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1742815995 |
|
|
Dec 20 01:05:41 PM PST 23 |
Dec 20 01:33:48 PM PST 23 |
3248384573 ps |
| T80 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.746666877 |
|
|
Dec 20 01:06:58 PM PST 23 |
Dec 20 01:08:46 PM PST 23 |
33615990233 ps |
| T109 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.4056768241 |
|
|
Dec 20 01:06:52 PM PST 23 |
Dec 20 01:11:30 PM PST 23 |
32177445271 ps |
| T249 |
/workspace/coverage/default/20.sram_ctrl_partial_access.3699447173 |
|
|
Dec 20 01:05:38 PM PST 23 |
Dec 20 01:06:17 PM PST 23 |
6915976870 ps |
| T250 |
/workspace/coverage/default/28.sram_ctrl_bijection.1351634478 |
|
|
Dec 20 01:06:06 PM PST 23 |
Dec 20 01:20:35 PM PST 23 |
50568730688 ps |
| T251 |
/workspace/coverage/default/31.sram_ctrl_partial_access.2170012047 |
|
|
Dec 20 01:06:11 PM PST 23 |
Dec 20 01:07:22 PM PST 23 |
3284912470 ps |
| T252 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.733544886 |
|
|
Dec 20 01:04:54 PM PST 23 |
Dec 20 01:32:35 PM PST 23 |
303286981 ps |
| T253 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3769361350 |
|
|
Dec 20 01:05:05 PM PST 23 |
Dec 20 01:06:45 PM PST 23 |
748976919 ps |
| T254 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.2891660586 |
|
|
Dec 20 01:05:41 PM PST 23 |
Dec 20 01:08:05 PM PST 23 |
7892112760 ps |
| T36 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.1347214237 |
|
|
Dec 20 01:05:28 PM PST 23 |
Dec 20 01:05:53 PM PST 23 |
353580797 ps |
| T255 |
/workspace/coverage/default/26.sram_ctrl_regwen.2275700570 |
|
|
Dec 20 01:05:47 PM PST 23 |
Dec 20 01:23:44 PM PST 23 |
15890645037 ps |
| T81 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.1540792056 |
|
|
Dec 20 01:05:17 PM PST 23 |
Dec 20 01:08:25 PM PST 23 |
13082124290 ps |
| T256 |
/workspace/coverage/default/14.sram_ctrl_partial_access.2194937990 |
|
|
Dec 20 01:05:25 PM PST 23 |
Dec 20 01:05:52 PM PST 23 |
1393156158 ps |
| T257 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.3527732483 |
|
|
Dec 20 01:06:11 PM PST 23 |
Dec 20 01:13:52 PM PST 23 |
7724253471 ps |
| T258 |
/workspace/coverage/default/41.sram_ctrl_alert_test.1305863741 |
|
|
Dec 20 01:06:49 PM PST 23 |
Dec 20 01:07:15 PM PST 23 |
78429885 ps |
| T37 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.4201651108 |
|
|
Dec 20 01:06:17 PM PST 23 |
Dec 20 01:06:41 PM PST 23 |
364227973 ps |
| T259 |
/workspace/coverage/default/29.sram_ctrl_bijection.228272851 |
|
|
Dec 20 01:06:11 PM PST 23 |
Dec 20 01:41:26 PM PST 23 |
368542107985 ps |
| T110 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.75883626 |
|
|
Dec 20 01:06:17 PM PST 23 |
Dec 20 01:13:16 PM PST 23 |
6356715789 ps |
| T260 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1533336453 |
|
|
Dec 20 01:05:31 PM PST 23 |
Dec 20 01:47:15 PM PST 23 |
1176517283 ps |
| T261 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1763608705 |
|
|
Dec 20 01:05:26 PM PST 23 |
Dec 20 01:12:34 PM PST 23 |
5049416658 ps |
| T262 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.709735056 |
|
|
Dec 20 01:06:14 PM PST 23 |
Dec 20 01:07:15 PM PST 23 |
743951331 ps |
| T126 |
/workspace/coverage/default/27.sram_ctrl_executable.405148663 |
|
|
Dec 20 01:06:05 PM PST 23 |
Dec 20 01:30:20 PM PST 23 |
265041489694 ps |
| T263 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.877444656 |
|
|
Dec 20 01:04:58 PM PST 23 |
Dec 20 01:05:58 PM PST 23 |
3159593828 ps |
| T264 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.4284212410 |
|
|
Dec 20 01:05:45 PM PST 23 |
Dec 20 01:06:14 PM PST 23 |
359116709 ps |
| T265 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.413064289 |
|
|
Dec 20 01:04:56 PM PST 23 |
Dec 20 01:36:55 PM PST 23 |
1497987436 ps |
| T266 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.1150498117 |
|
|
Dec 20 01:06:08 PM PST 23 |
Dec 20 01:22:11 PM PST 23 |
18354066163 ps |
| T267 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3228605171 |
|
|
Dec 20 01:07:22 PM PST 23 |
Dec 20 01:09:29 PM PST 23 |
3162184970 ps |
| T82 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.934747954 |
|
|
Dec 20 01:05:42 PM PST 23 |
Dec 20 01:23:16 PM PST 23 |
9297626039 ps |
| T26 |
/workspace/coverage/default/46.sram_ctrl_stress_all.3059233257 |
|
|
Dec 20 01:07:00 PM PST 23 |
Dec 20 01:41:07 PM PST 23 |
512486667060 ps |
| T268 |
/workspace/coverage/default/0.sram_ctrl_stress_all.635464043 |
|
|
Dec 20 01:05:03 PM PST 23 |
Dec 20 01:37:19 PM PST 23 |
36994254283 ps |
| T269 |
/workspace/coverage/default/8.sram_ctrl_smoke.2281611763 |
|
|
Dec 20 01:05:13 PM PST 23 |
Dec 20 01:05:50 PM PST 23 |
1494884237 ps |
| T83 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2669865021 |
|
|
Dec 20 01:07:21 PM PST 23 |
Dec 20 01:09:59 PM PST 23 |
4570310672 ps |
| T270 |
/workspace/coverage/default/23.sram_ctrl_alert_test.953171510 |
|
|
Dec 20 01:05:59 PM PST 23 |
Dec 20 01:06:11 PM PST 23 |
14590413 ps |
| T271 |
/workspace/coverage/default/42.sram_ctrl_alert_test.2323882343 |
|
|
Dec 20 01:06:41 PM PST 23 |
Dec 20 01:07:05 PM PST 23 |
41728945 ps |
| T111 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.3385073036 |
|
|
Dec 20 01:05:28 PM PST 23 |
Dec 20 01:06:58 PM PST 23 |
957114517 ps |
| T272 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.374743956 |
|
|
Dec 20 01:05:14 PM PST 23 |
Dec 20 01:05:44 PM PST 23 |
3361676188 ps |
| T273 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.3359360818 |
|
|
Dec 20 01:06:13 PM PST 23 |
Dec 20 01:06:31 PM PST 23 |
1408338723 ps |
| T274 |
/workspace/coverage/default/41.sram_ctrl_smoke.2923609519 |
|
|
Dec 20 01:06:42 PM PST 23 |
Dec 20 01:08:13 PM PST 23 |
8289480781 ps |
| T275 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.1748881826 |
|
|
Dec 20 01:05:48 PM PST 23 |
Dec 20 01:06:35 PM PST 23 |
1359479347 ps |
| T276 |
/workspace/coverage/default/1.sram_ctrl_regwen.3219848799 |
|
|
Dec 20 01:04:58 PM PST 23 |
Dec 20 01:18:17 PM PST 23 |
52058286779 ps |