Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	121846082	1			T1	103307		T2	150732		T3	7577
triple_byte_access	2830039	1			T1	2013		T3	134		T4	7078
halfword_access	4334285	1			T1	3048		T3	228		T4	12928
byte_access	6044297	1			T1	4130		T3	297		T4	24649
zero_access	1811977	1			T1	1049		T3	81		T4	14752

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67871753

1

T1

56786

T2

753664

T3

4083

auto[1]

68994927

1

T1

56761

T2

753664

T3

4234

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	60260723	1			T1	51633		T2	753664		T3	3713
auto[0]	triple_byte_access	1347070	1			T1	1035		T3	76		T4	1366
auto[0]	halfword_access	2112632	1			T1	1536		T3	106		T4	4484
auto[0]	byte_access	3080989	1			T1	2057		T3	150		T4	13245
auto[0]	zero_access	1070339	1			T1	525		T3	38		T4	11824
auto[1]	word_access	61585359	1			T1	51674		T2	753664		T3	3864
auto[1]	triple_byte_access	1482969	1			T1	978		T3	58		T4	5712
auto[1]	halfword_access	2221653	1			T1	1512		T3	122		T4	8444
auto[1]	byte_access	2963308	1			T1	2073		T3	147		T4	11404
auto[1]	zero_access	741638	1			T1	524		T3	43		T4	2928