Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	283936400	1			T1	76318		T2	108712		T3	4734
instr_valid_dis	260271804	1			T1	75796		T2	108712		T3	4734
instr_en	17321707	1			T1	522		T27	122086		T115	236490

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	14438268	1			T1	42042		T10	39494		T27	29320
sram_ifetch_valid_disable	250915894	1			T1	34276		T2	108712		T3	4734
sram_ifetch_enable	18582238	1			T10	158174		T27	59362		T115	256424

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	283936400	1			T1	76318		T2	108712		T3	4734
hw_debug_en_valid_off	259485937	1			T1	34276		T2	108712		T3	4734
hw_debug_en_on	16706916	1			T1	42042		T10	202488		T27	28696

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	250915894	1			T1	34276		T2	108712		T3	4734
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	243408422	1			T1	34276		T2	108712		T3	4734
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	5445889	1			T27	38234		T115	12890		T60	5
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	8723144	1			T10	39494		T27	17862		T115	12380
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	4593220	1			T10	39494		T115	12380		T28	46024
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2885156	1			T27	17862		T116	11422		T29	21072
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3181074	1			T1	42042		T27	11458		T115	3128
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1296598	1			T1	41520		T28	20000		T126	45018
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1349728	1			T1	522		T27	11458		T115	3128
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	5008302	1			T10	148056		T27	17238		T28	47234
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	1875156	1			T10	148056		T27	17238		T28	47234
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2360390	1			T116	11360		T29	15674		T129	109946

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	5813974	1			T27	54532		T115	220472		T28	74
lc_exec_en	8517540	1			T10	54432		T115	143984		T28	30910
valid_exec_dis	253853237	1			T1	34276		T2	108712		T3	4734
invalid_exec_dis	33020506	1			T1	42042		T10	197668		T27	88682