| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.767638080 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.5772230 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1185756587 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2867415994 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4275085290 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1932395615 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.154535019 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2931315104 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1406443083 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.521827401 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.108494335 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4144442484 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2135668668 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3203042784 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2966447026 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2671045425 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2815456430 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3180797406 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.505985397 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.759831694 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1769728108 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3479260496 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1996999048 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3959133574 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.443064663 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1627277896 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4160760271 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2664416328 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1588475056 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3582402566 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3154593471 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3393420944 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.823918461 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2930537233 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1394235345 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3882171617 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2026579507 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2516140501 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3003578946 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1776462894 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.217484765 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3797808836 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1024652423 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.612463002 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2767047142 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.755657631 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3999886779 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.613162331 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2966640109 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2211097211 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4115051370 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1499555300 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1159248387 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1217446344 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4011476609 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1978696704 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3706204380 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.656278784 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2679942790 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.462260641 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.787146997 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1511912231 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1088957040 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1457569108 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.753649946 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.11392502 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.735656510 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3085852140 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1886448693 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.404924892 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.692359110 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2718191489 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2164711224 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.537706320 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3233937865 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2492793021 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1814951675 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.140076441 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.950199220 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3905254914 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.348664482 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.373708116 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2573693135 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2229261312 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.218113361 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3905479798 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1414604546 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2905726676 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3565841526 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2306337286 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2934123743 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1520341199 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3662099092 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2310235443 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3189569290 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.923848394 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1680584555 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3673287340 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2324426131 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3705539474 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.901727870 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2978907607 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3015034961 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2660920634 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3256326528 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2680226144 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4076887818 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2225741145 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.4221608006 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1646147016 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1954676897 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1408596477 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4090104106 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2271293893 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3806343108 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3159911150 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1424881901 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1231953789 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.721359110 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.4070495503 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2302359920 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1549660898 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4269349255 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3091710005 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2049394619 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3637532718 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2876257479 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.726500161 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1603924157 |
| /workspace/coverage/default/0.sram_ctrl_bijection.427792910 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.2441557702 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.4006782653 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.67723935 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.3585255568 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.2089310581 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1175725206 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.745524202 |
| /workspace/coverage/default/0.sram_ctrl_regwen.4185326964 |
| /workspace/coverage/default/0.sram_ctrl_sec_cm.3782452828 |
| /workspace/coverage/default/0.sram_ctrl_smoke.804477768 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.1107471384 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2910753399 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.4212511650 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1829756780 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.1557927102 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.979858587 |
| /workspace/coverage/default/1.sram_ctrl_bijection.1405934525 |
| /workspace/coverage/default/1.sram_ctrl_executable.3932993101 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.255671855 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.2005068534 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.2192778118 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.198220058 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.1963789072 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.3556891403 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3581108741 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.2772812599 |
| /workspace/coverage/default/1.sram_ctrl_regwen.2610364875 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.566471931 |
| /workspace/coverage/default/1.sram_ctrl_smoke.429038186 |
| /workspace/coverage/default/1.sram_ctrl_stress_all.1263606587 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1154961165 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1447470865 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1561180821 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.1382439679 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.1400246347 |
| /workspace/coverage/default/10.sram_ctrl_bijection.547994275 |
| /workspace/coverage/default/10.sram_ctrl_executable.2699425511 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.1087610300 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.712016104 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1360949725 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.2501429590 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.1206070086 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.1074959898 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.4027638636 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.1494718447 |
| /workspace/coverage/default/10.sram_ctrl_regwen.3716132079 |
| /workspace/coverage/default/10.sram_ctrl_smoke.728912308 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2784151312 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.199599943 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.762816943 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3504004981 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.218774096 |
| /workspace/coverage/default/11.sram_ctrl_bijection.1506877909 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.1525878916 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.2228126221 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.1310941948 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.1757929879 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.3438430591 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.1026716887 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1015660967 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.1645678344 |
| /workspace/coverage/default/11.sram_ctrl_regwen.326509445 |
| /workspace/coverage/default/11.sram_ctrl_smoke.2306461257 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.185404048 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3595954610 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.3234435449 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.66799103 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.3903094393 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.450502570 |
| /workspace/coverage/default/12.sram_ctrl_bijection.2993257929 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.3374923673 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.2931619241 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.881420637 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.985526650 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.2803236487 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.3178914857 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3322809190 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.3479914012 |
| /workspace/coverage/default/12.sram_ctrl_regwen.3095586421 |
| /workspace/coverage/default/12.sram_ctrl_smoke.1739167161 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.1120270046 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3746392452 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.1749086321 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.755862316 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.3622038048 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.3189310210 |
| /workspace/coverage/default/13.sram_ctrl_bijection.1472270784 |
| /workspace/coverage/default/13.sram_ctrl_executable.669858042 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.3288978168 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.3182159337 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.607189063 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.2297013640 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.785656623 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.4254042376 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2341511762 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.2124835689 |
| /workspace/coverage/default/13.sram_ctrl_regwen.558936621 |
| /workspace/coverage/default/13.sram_ctrl_smoke.3337438971 |
| /workspace/coverage/default/13.sram_ctrl_stress_all.1881056906 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1772594614 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2128785203 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2862144079 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2459363746 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.1097669359 |
| /workspace/coverage/default/14.sram_ctrl_bijection.1894403840 |
| /workspace/coverage/default/14.sram_ctrl_executable.1739998752 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.199581893 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.2985432011 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.2274889439 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.3882500874 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.1930423271 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.2090254628 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.508502940 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.1509079597 |
| /workspace/coverage/default/14.sram_ctrl_smoke.3026559985 |
| /workspace/coverage/default/14.sram_ctrl_stress_pipeline.807191073 |
| /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.4228549030 |
| /workspace/coverage/default/15.sram_ctrl_access_during_key_req.468137362 |
| /workspace/coverage/default/15.sram_ctrl_alert_test.3491607276 |
| /workspace/coverage/default/15.sram_ctrl_bijection.2976945088 |
| /workspace/coverage/default/15.sram_ctrl_lc_escalation.1384434425 |
| /workspace/coverage/default/15.sram_ctrl_max_throughput.2592011424 |
| /workspace/coverage/default/15.sram_ctrl_mem_partial_access.3021590730 |
| /workspace/coverage/default/15.sram_ctrl_mem_walk.1643764842 |
| /workspace/coverage/default/15.sram_ctrl_multiple_keys.2195466231 |
| /workspace/coverage/default/15.sram_ctrl_partial_access.3383724070 |
| /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2524430275 |
| /workspace/coverage/default/15.sram_ctrl_ram_cfg.160852802 |
| /workspace/coverage/default/15.sram_ctrl_regwen.2160056100 |
| /workspace/coverage/default/15.sram_ctrl_smoke.1770519994 |
| /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2237297257 |
| /workspace/coverage/default/15.sram_ctrl_stress_pipeline.845406958 |
| /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.4212253362 |
| /workspace/coverage/default/16.sram_ctrl_access_during_key_req.3677842709 |
| /workspace/coverage/default/16.sram_ctrl_alert_test.1248915276 |
| /workspace/coverage/default/16.sram_ctrl_bijection.2726389537 |
| /workspace/coverage/default/16.sram_ctrl_max_throughput.1921647836 |
| /workspace/coverage/default/16.sram_ctrl_mem_partial_access.110185759 |
| /workspace/coverage/default/16.sram_ctrl_mem_walk.4014349050 |
| /workspace/coverage/default/16.sram_ctrl_multiple_keys.96225875 |
| /workspace/coverage/default/16.sram_ctrl_partial_access.3240563159 |
| /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2812819113 |
| /workspace/coverage/default/16.sram_ctrl_ram_cfg.617905545 |
| /workspace/coverage/default/16.sram_ctrl_regwen.460945744 |
| /workspace/coverage/default/16.sram_ctrl_smoke.1617866092 |
| /workspace/coverage/default/16.sram_ctrl_stress_all.52403178 |
| /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.886008481 |
| /workspace/coverage/default/16.sram_ctrl_stress_pipeline.3386300690 |
| /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.677050565 |
| /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2284838917 |
| /workspace/coverage/default/17.sram_ctrl_alert_test.205645066 |
| /workspace/coverage/default/17.sram_ctrl_bijection.2038709222 |
| /workspace/coverage/default/17.sram_ctrl_executable.3091910510 |
| /workspace/coverage/default/17.sram_ctrl_lc_escalation.2809811432 |
| /workspace/coverage/default/17.sram_ctrl_max_throughput.1199312218 |
| /workspace/coverage/default/17.sram_ctrl_mem_partial_access.3353796234 |
| /workspace/coverage/default/17.sram_ctrl_mem_walk.159508466 |
| /workspace/coverage/default/17.sram_ctrl_multiple_keys.1785060200 |
| /workspace/coverage/default/17.sram_ctrl_partial_access.2548854138 |
| /workspace/coverage/default/17.sram_ctrl_ram_cfg.884124696 |
| /workspace/coverage/default/17.sram_ctrl_regwen.2839628614 |
| /workspace/coverage/default/17.sram_ctrl_smoke.93103374 |
| /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1013987154 |
| /workspace/coverage/default/17.sram_ctrl_stress_pipeline.3059624049 |
| /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.4288848365 |
| /workspace/coverage/default/18.sram_ctrl_access_during_key_req.1148763064 |
| /workspace/coverage/default/18.sram_ctrl_alert_test.3818484770 |
| /workspace/coverage/default/18.sram_ctrl_bijection.3263930636 |
| /workspace/coverage/default/18.sram_ctrl_executable.1120707125 |
| /workspace/coverage/default/18.sram_ctrl_lc_escalation.1660325506 |
| /workspace/coverage/default/18.sram_ctrl_max_throughput.3096425567 |
| /workspace/coverage/default/18.sram_ctrl_mem_partial_access.2045530120 |
| /workspace/coverage/default/18.sram_ctrl_mem_walk.3380233038 |
| /workspace/coverage/default/18.sram_ctrl_multiple_keys.986989154 |
| /workspace/coverage/default/18.sram_ctrl_partial_access.1719047720 |
| /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1599239223 |
| /workspace/coverage/default/18.sram_ctrl_ram_cfg.472995212 |
| /workspace/coverage/default/18.sram_ctrl_regwen.1394604919 |
| /workspace/coverage/default/18.sram_ctrl_smoke.3148745864 |
| /workspace/coverage/default/18.sram_ctrl_stress_all.3290977576 |
| /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1187059635 |
| /workspace/coverage/default/18.sram_ctrl_stress_pipeline.1059907068 |
| /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.595936836 |
| /workspace/coverage/default/19.sram_ctrl_alert_test.3012933666 |
| /workspace/coverage/default/19.sram_ctrl_bijection.3625264296 |
| /workspace/coverage/default/19.sram_ctrl_executable.3883543957 |
| /workspace/coverage/default/19.sram_ctrl_max_throughput.1503418486 |
| /workspace/coverage/default/19.sram_ctrl_mem_partial_access.2708940754 |
| /workspace/coverage/default/19.sram_ctrl_mem_walk.1425866576 |
| /workspace/coverage/default/19.sram_ctrl_multiple_keys.3026473880 |
| /workspace/coverage/default/19.sram_ctrl_partial_access.2880547747 |
| /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2167244944 |
| /workspace/coverage/default/19.sram_ctrl_ram_cfg.3030078117 |
| /workspace/coverage/default/19.sram_ctrl_regwen.2736256311 |
| /workspace/coverage/default/19.sram_ctrl_smoke.1878954820 |
| /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1495508963 |
| /workspace/coverage/default/19.sram_ctrl_stress_pipeline.1684638429 |
| /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1951663735 |
| /workspace/coverage/default/2.sram_ctrl_access_during_key_req.118131934 |
| /workspace/coverage/default/2.sram_ctrl_alert_test.2015046752 |
| /workspace/coverage/default/2.sram_ctrl_bijection.2841614138 |
| /workspace/coverage/default/2.sram_ctrl_lc_escalation.2641820059 |
| /workspace/coverage/default/2.sram_ctrl_max_throughput.3836278708 |
| /workspace/coverage/default/2.sram_ctrl_mem_partial_access.2152262194 |
| /workspace/coverage/default/2.sram_ctrl_mem_walk.3989584146 |
| /workspace/coverage/default/2.sram_ctrl_multiple_keys.2932043844 |
| /workspace/coverage/default/2.sram_ctrl_partial_access.2922548991 |
| /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.272056389 |
| /workspace/coverage/default/2.sram_ctrl_ram_cfg.144717842 |
| /workspace/coverage/default/2.sram_ctrl_regwen.1110285327 |
| /workspace/coverage/default/2.sram_ctrl_smoke.2626837688 |
| /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.4285675195 |
| /workspace/coverage/default/2.sram_ctrl_stress_pipeline.3561941587 |
| /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3748920436 |
| /workspace/coverage/default/20.sram_ctrl_access_during_key_req.3460051874 |
| /workspace/coverage/default/20.sram_ctrl_alert_test.1601323190 |
| /workspace/coverage/default/20.sram_ctrl_bijection.2619431256 |
| /workspace/coverage/default/20.sram_ctrl_lc_escalation.122574920 |
| /workspace/coverage/default/20.sram_ctrl_max_throughput.3243742602 |
| /workspace/coverage/default/20.sram_ctrl_mem_partial_access.3465023825 |
| /workspace/coverage/default/20.sram_ctrl_mem_walk.168376192 |
| /workspace/coverage/default/20.sram_ctrl_multiple_keys.1419196656 |
| /workspace/coverage/default/20.sram_ctrl_partial_access.1873407559 |
| /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3334600918 |
| /workspace/coverage/default/20.sram_ctrl_ram_cfg.3465865685 |
| /workspace/coverage/default/20.sram_ctrl_smoke.1737537986 |
| /workspace/coverage/default/20.sram_ctrl_stress_all.446954627 |
| /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3035080644 |
| /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1621582130 |
| /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3686246539 |
| /workspace/coverage/default/21.sram_ctrl_access_during_key_req.4265762550 |
| /workspace/coverage/default/21.sram_ctrl_alert_test.1543371081 |
| /workspace/coverage/default/21.sram_ctrl_bijection.3691061110 |
| /workspace/coverage/default/21.sram_ctrl_executable.3056202185 |
| /workspace/coverage/default/21.sram_ctrl_max_throughput.3417484245 |
| /workspace/coverage/default/21.sram_ctrl_mem_partial_access.4196837802 |
| /workspace/coverage/default/21.sram_ctrl_mem_walk.3062751476 |
| /workspace/coverage/default/21.sram_ctrl_multiple_keys.2327305255 |
| /workspace/coverage/default/21.sram_ctrl_partial_access.3684192921 |
| /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2885731403 |
| /workspace/coverage/default/21.sram_ctrl_ram_cfg.3972497056 |
| /workspace/coverage/default/21.sram_ctrl_regwen.1908904991 |
| /workspace/coverage/default/21.sram_ctrl_smoke.4012429079 |
| /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1358647529 |
| /workspace/coverage/default/21.sram_ctrl_stress_pipeline.850314890 |
| /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1353338785 |
| /workspace/coverage/default/22.sram_ctrl_access_during_key_req.700363818 |
| /workspace/coverage/default/22.sram_ctrl_alert_test.1052675243 |
| /workspace/coverage/default/22.sram_ctrl_bijection.4045177168 |
| /workspace/coverage/default/22.sram_ctrl_executable.1945458186 |
| /workspace/coverage/default/22.sram_ctrl_max_throughput.3971362471 |
| /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2043656055 |
| /workspace/coverage/default/22.sram_ctrl_mem_walk.2963952839 |
| /workspace/coverage/default/22.sram_ctrl_multiple_keys.1517372137 |
| /workspace/coverage/default/22.sram_ctrl_partial_access.3726473391 |
| /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.289992887 |
| /workspace/coverage/default/22.sram_ctrl_ram_cfg.2246802534 |
| /workspace/coverage/default/22.sram_ctrl_regwen.3726843224 |
| /workspace/coverage/default/22.sram_ctrl_smoke.3785099976 |
| /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.4147087387 |
| /workspace/coverage/default/22.sram_ctrl_stress_pipeline.977352368 |
| /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2355982516 |
| /workspace/coverage/default/23.sram_ctrl_access_during_key_req.662925771 |
| /workspace/coverage/default/23.sram_ctrl_alert_test.1085438487 |
| /workspace/coverage/default/23.sram_ctrl_bijection.2054620301 |
| /workspace/coverage/default/23.sram_ctrl_lc_escalation.2684359724 |
| /workspace/coverage/default/23.sram_ctrl_max_throughput.974788226 |
| /workspace/coverage/default/23.sram_ctrl_mem_partial_access.1362086056 |
| /workspace/coverage/default/23.sram_ctrl_mem_walk.1623787794 |
| /workspace/coverage/default/23.sram_ctrl_multiple_keys.1011571376 |
| /workspace/coverage/default/23.sram_ctrl_partial_access.2164554431 |
| /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3793324423 |
| /workspace/coverage/default/23.sram_ctrl_ram_cfg.445634793 |
| /workspace/coverage/default/23.sram_ctrl_regwen.872531335 |
| /workspace/coverage/default/23.sram_ctrl_smoke.1023704842 |
| /workspace/coverage/default/23.sram_ctrl_stress_all.666388826 |
| /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1456960443 |
| /workspace/coverage/default/23.sram_ctrl_stress_pipeline.806254048 |
| /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3974781558 |
| /workspace/coverage/default/24.sram_ctrl_access_during_key_req.1631200480 |
| /workspace/coverage/default/24.sram_ctrl_alert_test.292343226 |
| /workspace/coverage/default/24.sram_ctrl_bijection.1304085843 |
| /workspace/coverage/default/24.sram_ctrl_executable.3922557054 |
| /workspace/coverage/default/24.sram_ctrl_lc_escalation.1061451698 |
| /workspace/coverage/default/24.sram_ctrl_max_throughput.2514956018 |
| /workspace/coverage/default/24.sram_ctrl_mem_partial_access.3934656449 |
| /workspace/coverage/default/24.sram_ctrl_mem_walk.2499373909 |
| /workspace/coverage/default/24.sram_ctrl_multiple_keys.2934730606 |
| /workspace/coverage/default/24.sram_ctrl_partial_access.802632602 |
| /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.613197654 |
| /workspace/coverage/default/24.sram_ctrl_ram_cfg.558327497 |
| /workspace/coverage/default/24.sram_ctrl_regwen.302114974 |
| /workspace/coverage/default/24.sram_ctrl_smoke.3408498109 |
| /workspace/coverage/default/24.sram_ctrl_stress_all.1417842385 |
| /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2080514658 |
| /workspace/coverage/default/24.sram_ctrl_stress_pipeline.3665030855 |
| /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1256904508 |
| /workspace/coverage/default/25.sram_ctrl_access_during_key_req.1912404984 |
| /workspace/coverage/default/25.sram_ctrl_alert_test.1869113373 |
| /workspace/coverage/default/25.sram_ctrl_bijection.2819424810 |
| /workspace/coverage/default/25.sram_ctrl_lc_escalation.1982678891 |
| /workspace/coverage/default/25.sram_ctrl_max_throughput.2792610010 |
| /workspace/coverage/default/25.sram_ctrl_mem_partial_access.3761732625 |
| /workspace/coverage/default/25.sram_ctrl_mem_walk.430880271 |
| /workspace/coverage/default/25.sram_ctrl_multiple_keys.2265966345 |
| /workspace/coverage/default/25.sram_ctrl_partial_access.3764249363 |
| /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3875976839 |
| /workspace/coverage/default/25.sram_ctrl_ram_cfg.2380107362 |
| /workspace/coverage/default/25.sram_ctrl_regwen.3243402472 |
| /workspace/coverage/default/25.sram_ctrl_smoke.612029509 |
| /workspace/coverage/default/25.sram_ctrl_stress_all.3530615083 |
| /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.517560447 |
| /workspace/coverage/default/25.sram_ctrl_stress_pipeline.2076071808 |
| /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.551118629 |
| /workspace/coverage/default/26.sram_ctrl_access_during_key_req.3355288097 |
| /workspace/coverage/default/26.sram_ctrl_alert_test.945443206 |
| /workspace/coverage/default/26.sram_ctrl_bijection.244063196 |
| /workspace/coverage/default/26.sram_ctrl_lc_escalation.3725069881 |
| /workspace/coverage/default/26.sram_ctrl_max_throughput.1228664076 |
| /workspace/coverage/default/26.sram_ctrl_mem_partial_access.409493396 |
| /workspace/coverage/default/26.sram_ctrl_mem_walk.63097409 |
| /workspace/coverage/default/26.sram_ctrl_multiple_keys.343507287 |
| /workspace/coverage/default/26.sram_ctrl_partial_access.1493680936 |
| /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3407230704 |
| /workspace/coverage/default/26.sram_ctrl_ram_cfg.959683552 |
| /workspace/coverage/default/26.sram_ctrl_regwen.3187107753 |
| /workspace/coverage/default/26.sram_ctrl_smoke.521602580 |
| /workspace/coverage/default/26.sram_ctrl_stress_all.3841972006 |
| /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.348567733 |
| /workspace/coverage/default/26.sram_ctrl_stress_pipeline.1671489793 |
| /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.819825437 |
| /workspace/coverage/default/27.sram_ctrl_access_during_key_req.1688577229 |
| /workspace/coverage/default/27.sram_ctrl_alert_test.1525818045 |
| /workspace/coverage/default/27.sram_ctrl_bijection.4043569179 |
| /workspace/coverage/default/27.sram_ctrl_lc_escalation.272219944 |
| /workspace/coverage/default/27.sram_ctrl_max_throughput.553251263 |
| /workspace/coverage/default/27.sram_ctrl_mem_partial_access.2690898589 |
| /workspace/coverage/default/27.sram_ctrl_mem_walk.2668826816 |
| /workspace/coverage/default/27.sram_ctrl_multiple_keys.3035859122 |
| /workspace/coverage/default/27.sram_ctrl_partial_access.2962019001 |
| /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2282320364 |
| /workspace/coverage/default/27.sram_ctrl_ram_cfg.3711375685 |
| /workspace/coverage/default/27.sram_ctrl_regwen.192120421 |
| /workspace/coverage/default/27.sram_ctrl_smoke.657710738 |
| /workspace/coverage/default/27.sram_ctrl_stress_all.1577015620 |
| /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3263716595 |
| /workspace/coverage/default/27.sram_ctrl_stress_pipeline.689783817 |
| /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.4181505424 |
| /workspace/coverage/default/28.sram_ctrl_access_during_key_req.2730300917 |
| /workspace/coverage/default/28.sram_ctrl_alert_test.3092101172 |
| /workspace/coverage/default/28.sram_ctrl_bijection.4286544882 |
| /workspace/coverage/default/28.sram_ctrl_executable.1617332382 |
| /workspace/coverage/default/28.sram_ctrl_lc_escalation.3493655733 |
| /workspace/coverage/default/28.sram_ctrl_max_throughput.1712010471 |
| /workspace/coverage/default/28.sram_ctrl_mem_partial_access.1025399201 |
| /workspace/coverage/default/28.sram_ctrl_mem_walk.4029865834 |
| /workspace/coverage/default/28.sram_ctrl_multiple_keys.1716781796 |
| /workspace/coverage/default/28.sram_ctrl_partial_access.3311526411 |
| /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.127367620 |
| /workspace/coverage/default/28.sram_ctrl_regwen.4009786541 |
| /workspace/coverage/default/28.sram_ctrl_smoke.3541133142 |
| /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.282163630 |
| /workspace/coverage/default/28.sram_ctrl_stress_pipeline.1683798988 |
| /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2583094349 |
| /workspace/coverage/default/29.sram_ctrl_access_during_key_req.3954096053 |
| /workspace/coverage/default/29.sram_ctrl_alert_test.4250863075 |
| /workspace/coverage/default/29.sram_ctrl_bijection.2032185459 |
| /workspace/coverage/default/29.sram_ctrl_lc_escalation.2811762666 |
| /workspace/coverage/default/29.sram_ctrl_max_throughput.728315717 |
| /workspace/coverage/default/29.sram_ctrl_mem_partial_access.3862490165 |
| /workspace/coverage/default/29.sram_ctrl_mem_walk.559866385 |
| /workspace/coverage/default/29.sram_ctrl_multiple_keys.2917408215 |
| /workspace/coverage/default/29.sram_ctrl_partial_access.3257685688 |
| /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.313832332 |
| /workspace/coverage/default/29.sram_ctrl_ram_cfg.2274662170 |
| /workspace/coverage/default/29.sram_ctrl_regwen.827859519 |
| /workspace/coverage/default/29.sram_ctrl_smoke.2068325789 |
| /workspace/coverage/default/29.sram_ctrl_stress_all.3180375620 |
| /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.157806254 |
| /workspace/coverage/default/29.sram_ctrl_stress_pipeline.1200398792 |
| /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1747283937 |
| /workspace/coverage/default/3.sram_ctrl_access_during_key_req.1458678178 |
| /workspace/coverage/default/3.sram_ctrl_alert_test.3644351109 |
| /workspace/coverage/default/3.sram_ctrl_bijection.4218705960 |
| /workspace/coverage/default/3.sram_ctrl_executable.3808657840 |
| /workspace/coverage/default/3.sram_ctrl_max_throughput.3741402444 |
| /workspace/coverage/default/3.sram_ctrl_mem_partial_access.2387864514 |
| /workspace/coverage/default/3.sram_ctrl_mem_walk.2164151390 |
| /workspace/coverage/default/3.sram_ctrl_multiple_keys.2266749389 |
| /workspace/coverage/default/3.sram_ctrl_partial_access.1590233031 |
| /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3412768539 |
| /workspace/coverage/default/3.sram_ctrl_ram_cfg.2502942117 |
| /workspace/coverage/default/3.sram_ctrl_regwen.2212549556 |
| /workspace/coverage/default/3.sram_ctrl_sec_cm.4089603100 |
| /workspace/coverage/default/3.sram_ctrl_smoke.3909944595 |
| /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.721958015 |
| /workspace/coverage/default/3.sram_ctrl_stress_pipeline.915836824 |
| /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.388805583 |
| /workspace/coverage/default/30.sram_ctrl_access_during_key_req.4099726546 |
| /workspace/coverage/default/30.sram_ctrl_alert_test.3418876639 |
| /workspace/coverage/default/30.sram_ctrl_bijection.1340069775 |
| /workspace/coverage/default/30.sram_ctrl_executable.2896577908 |
| /workspace/coverage/default/30.sram_ctrl_lc_escalation.2497962771 |
| /workspace/coverage/default/30.sram_ctrl_max_throughput.1090307430 |
| /workspace/coverage/default/30.sram_ctrl_mem_partial_access.3684786581 |
| /workspace/coverage/default/30.sram_ctrl_mem_walk.2748668659 |
| /workspace/coverage/default/30.sram_ctrl_multiple_keys.2583961787 |
| /workspace/coverage/default/30.sram_ctrl_partial_access.3762811044 |
| /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2125727662 |
| /workspace/coverage/default/30.sram_ctrl_ram_cfg.3070989204 |
| /workspace/coverage/default/30.sram_ctrl_regwen.3988074542 |
| /workspace/coverage/default/30.sram_ctrl_smoke.2511238734 |
| /workspace/coverage/default/30.sram_ctrl_stress_all.1294821191 |
| /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.398061209 |
| /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2887769335 |
| /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1282039074 |
| /workspace/coverage/default/31.sram_ctrl_access_during_key_req.1203103023 |
| /workspace/coverage/default/31.sram_ctrl_alert_test.1993772903 |
| /workspace/coverage/default/31.sram_ctrl_bijection.1645669127 |
| /workspace/coverage/default/31.sram_ctrl_executable.1288440858 |
| /workspace/coverage/default/31.sram_ctrl_lc_escalation.1917857104 |
| /workspace/coverage/default/31.sram_ctrl_max_throughput.3577945382 |
| /workspace/coverage/default/31.sram_ctrl_mem_partial_access.1488989147 |
| /workspace/coverage/default/31.sram_ctrl_mem_walk.2627547393 |
| /workspace/coverage/default/31.sram_ctrl_multiple_keys.656827450 |
| /workspace/coverage/default/31.sram_ctrl_partial_access.1661618363 |
| /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2139575922 |
| /workspace/coverage/default/31.sram_ctrl_ram_cfg.750526869 |
| /workspace/coverage/default/31.sram_ctrl_regwen.3492836131 |
| /workspace/coverage/default/31.sram_ctrl_smoke.3523382799 |
| /workspace/coverage/default/31.sram_ctrl_stress_all.3525492016 |
| /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2851828425 |
| /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2269496417 |
| /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1181934150 |
| /workspace/coverage/default/32.sram_ctrl_access_during_key_req.2536313184 |
| /workspace/coverage/default/32.sram_ctrl_alert_test.3027281189 |
| /workspace/coverage/default/32.sram_ctrl_bijection.2522953756 |
| /workspace/coverage/default/32.sram_ctrl_lc_escalation.1819241452 |
| /workspace/coverage/default/32.sram_ctrl_max_throughput.2429395081 |
| /workspace/coverage/default/32.sram_ctrl_mem_partial_access.2304411066 |
| /workspace/coverage/default/32.sram_ctrl_mem_walk.3400255133 |
| /workspace/coverage/default/32.sram_ctrl_partial_access.510300857 |
| /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2459269362 |
| /workspace/coverage/default/32.sram_ctrl_ram_cfg.221658915 |
| /workspace/coverage/default/32.sram_ctrl_regwen.2074791375 |
| /workspace/coverage/default/32.sram_ctrl_smoke.2103587874 |
| /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1008880673 |
| /workspace/coverage/default/32.sram_ctrl_stress_pipeline.65227840 |
| /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1499346233 |
| /workspace/coverage/default/33.sram_ctrl_access_during_key_req.1921623507 |
| /workspace/coverage/default/33.sram_ctrl_alert_test.982974853 |
| /workspace/coverage/default/33.sram_ctrl_bijection.2385673247 |
| /workspace/coverage/default/33.sram_ctrl_lc_escalation.4015640790 |
| /workspace/coverage/default/33.sram_ctrl_max_throughput.1013019973 |
| /workspace/coverage/default/33.sram_ctrl_mem_partial_access.2909811083 |
| /workspace/coverage/default/33.sram_ctrl_mem_walk.4039038805 |
| /workspace/coverage/default/33.sram_ctrl_multiple_keys.3552076039 |
| /workspace/coverage/default/33.sram_ctrl_partial_access.2658784558 |
| /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1550894590 |
| /workspace/coverage/default/33.sram_ctrl_ram_cfg.2866176633 |
| /workspace/coverage/default/33.sram_ctrl_regwen.359835592 |
| /workspace/coverage/default/33.sram_ctrl_smoke.415445271 |
| /workspace/coverage/default/33.sram_ctrl_stress_all.3781491889 |
| /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1662497597 |
| /workspace/coverage/default/33.sram_ctrl_stress_pipeline.411012613 |
| /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.517620531 |
| /workspace/coverage/default/34.sram_ctrl_access_during_key_req.605057980 |
| /workspace/coverage/default/34.sram_ctrl_alert_test.4268090722 |
| /workspace/coverage/default/34.sram_ctrl_bijection.3373366176 |
| /workspace/coverage/default/34.sram_ctrl_executable.3461816001 |
| /workspace/coverage/default/34.sram_ctrl_max_throughput.3681649507 |
| /workspace/coverage/default/34.sram_ctrl_mem_partial_access.3869833093 |
| /workspace/coverage/default/34.sram_ctrl_mem_walk.1689540520 |
| /workspace/coverage/default/34.sram_ctrl_multiple_keys.217001312 |
| /workspace/coverage/default/34.sram_ctrl_partial_access.1849941159 |
| /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1934257220 |
| /workspace/coverage/default/34.sram_ctrl_ram_cfg.1730182998 |
| /workspace/coverage/default/34.sram_ctrl_regwen.3651707952 |
| /workspace/coverage/default/34.sram_ctrl_smoke.1901497039 |
| /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.413102386 |
| /workspace/coverage/default/34.sram_ctrl_stress_pipeline.4213230422 |
| /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3235825566 |
| /workspace/coverage/default/35.sram_ctrl_access_during_key_req.3535045283 |
| /workspace/coverage/default/35.sram_ctrl_alert_test.2936152754 |
| /workspace/coverage/default/35.sram_ctrl_bijection.1654707195 |
| /workspace/coverage/default/35.sram_ctrl_max_throughput.335680707 |
| /workspace/coverage/default/35.sram_ctrl_mem_partial_access.3954271906 |
| /workspace/coverage/default/35.sram_ctrl_mem_walk.425760351 |
| /workspace/coverage/default/35.sram_ctrl_partial_access.3430352081 |
| /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.910225541 |
| /workspace/coverage/default/35.sram_ctrl_ram_cfg.3496124005 |
| /workspace/coverage/default/35.sram_ctrl_smoke.3948318098 |
| /workspace/coverage/default/35.sram_ctrl_stress_all.62822635 |
| /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.221807550 |
| /workspace/coverage/default/35.sram_ctrl_stress_pipeline.3739980497 |
| /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.4009084615 |
| /workspace/coverage/default/36.sram_ctrl_access_during_key_req.945623350 |
| /workspace/coverage/default/36.sram_ctrl_alert_test.1316422126 |
| /workspace/coverage/default/36.sram_ctrl_bijection.3507432777 |
| /workspace/coverage/default/36.sram_ctrl_executable.26382413 |
| /workspace/coverage/default/36.sram_ctrl_max_throughput.410387399 |
| /workspace/coverage/default/36.sram_ctrl_mem_partial_access.2104486000 |
| /workspace/coverage/default/36.sram_ctrl_mem_walk.4254699039 |
| /workspace/coverage/default/36.sram_ctrl_multiple_keys.1733175862 |
| /workspace/coverage/default/36.sram_ctrl_partial_access.909039458 |
| /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3382042705 |
| /workspace/coverage/default/36.sram_ctrl_ram_cfg.785804904 |
| /workspace/coverage/default/36.sram_ctrl_regwen.3668115857 |
| /workspace/coverage/default/36.sram_ctrl_smoke.4184452375 |
| /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.664483993 |
| /workspace/coverage/default/36.sram_ctrl_stress_pipeline.3714175986 |
| /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.3312187471 |
| /workspace/coverage/default/37.sram_ctrl_access_during_key_req.2375543862 |
| /workspace/coverage/default/37.sram_ctrl_alert_test.1453094778 |
| /workspace/coverage/default/37.sram_ctrl_bijection.2990069686 |
| /workspace/coverage/default/37.sram_ctrl_lc_escalation.3176773731 |
| /workspace/coverage/default/37.sram_ctrl_max_throughput.4013104064 |
| /workspace/coverage/default/37.sram_ctrl_mem_partial_access.390688770 |
| /workspace/coverage/default/37.sram_ctrl_mem_walk.2084188023 |
| /workspace/coverage/default/37.sram_ctrl_multiple_keys.4196247663 |
| /workspace/coverage/default/37.sram_ctrl_partial_access.3326415669 |
| /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.894976122 |
| /workspace/coverage/default/37.sram_ctrl_ram_cfg.1007739048 |
| /workspace/coverage/default/37.sram_ctrl_regwen.3337113167 |
| /workspace/coverage/default/37.sram_ctrl_smoke.497866888 |
| /workspace/coverage/default/37.sram_ctrl_stress_all.3817641901 |
| /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2694970619 |
| /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1001601917 |
| /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3756092448 |
| /workspace/coverage/default/38.sram_ctrl_access_during_key_req.2083604985 |
| /workspace/coverage/default/38.sram_ctrl_alert_test.3924590820 |
| /workspace/coverage/default/38.sram_ctrl_bijection.2173137218 |
| /workspace/coverage/default/38.sram_ctrl_executable.3301312656 |
| /workspace/coverage/default/38.sram_ctrl_lc_escalation.3758771179 |
| /workspace/coverage/default/38.sram_ctrl_max_throughput.3711839081 |
| /workspace/coverage/default/38.sram_ctrl_mem_partial_access.560408552 |
| /workspace/coverage/default/38.sram_ctrl_mem_walk.3388368146 |
| /workspace/coverage/default/38.sram_ctrl_multiple_keys.1878460661 |
| /workspace/coverage/default/38.sram_ctrl_partial_access.3991148267 |
| /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1659818908 |
| /workspace/coverage/default/38.sram_ctrl_ram_cfg.1968717061 |
| /workspace/coverage/default/38.sram_ctrl_regwen.2327732835 |
| /workspace/coverage/default/38.sram_ctrl_smoke.42515451 |
| /workspace/coverage/default/38.sram_ctrl_stress_all.1980348616 |
| /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.204932823 |
| /workspace/coverage/default/38.sram_ctrl_stress_pipeline.3137626821 |
| /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2973498590 |
| /workspace/coverage/default/39.sram_ctrl_access_during_key_req.483723805 |
| /workspace/coverage/default/39.sram_ctrl_alert_test.3241659177 |
| /workspace/coverage/default/39.sram_ctrl_bijection.699752055 |
| /workspace/coverage/default/39.sram_ctrl_executable.4262107223 |
| /workspace/coverage/default/39.sram_ctrl_lc_escalation.2707998946 |
| /workspace/coverage/default/39.sram_ctrl_max_throughput.4151216145 |
| /workspace/coverage/default/39.sram_ctrl_mem_partial_access.3467484785 |
| /workspace/coverage/default/39.sram_ctrl_mem_walk.464612743 |
| /workspace/coverage/default/39.sram_ctrl_multiple_keys.3157225199 |
| /workspace/coverage/default/39.sram_ctrl_partial_access.433889923 |
| /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3450760331 |
| /workspace/coverage/default/39.sram_ctrl_ram_cfg.2899169448 |
| /workspace/coverage/default/39.sram_ctrl_regwen.950674122 |
| /workspace/coverage/default/39.sram_ctrl_smoke.3436357733 |
| /workspace/coverage/default/39.sram_ctrl_stress_all.2876449275 |
| /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3898756100 |
| /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1844087603 |
| /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.274385650 |
| /workspace/coverage/default/4.sram_ctrl_access_during_key_req.1132084907 |
| /workspace/coverage/default/4.sram_ctrl_alert_test.2130681792 |
| /workspace/coverage/default/4.sram_ctrl_bijection.2699322184 |
| /workspace/coverage/default/4.sram_ctrl_executable.3116758167 |
| /workspace/coverage/default/4.sram_ctrl_lc_escalation.1093104476 |
| /workspace/coverage/default/4.sram_ctrl_max_throughput.2045939117 |
| /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2726496664 |
| /workspace/coverage/default/4.sram_ctrl_mem_walk.2450532092 |
| /workspace/coverage/default/4.sram_ctrl_multiple_keys.509764148 |
| /workspace/coverage/default/4.sram_ctrl_partial_access.2858932030 |
| /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2945612535 |
| /workspace/coverage/default/4.sram_ctrl_ram_cfg.287934574 |
| /workspace/coverage/default/4.sram_ctrl_regwen.681070009 |
| /workspace/coverage/default/4.sram_ctrl_sec_cm.2565391798 |
| /workspace/coverage/default/4.sram_ctrl_smoke.533094210 |
| /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1622037090 |
| /workspace/coverage/default/4.sram_ctrl_stress_pipeline.351012709 |
| /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1051332817 |
| /workspace/coverage/default/40.sram_ctrl_access_during_key_req.3757360536 |
| /workspace/coverage/default/40.sram_ctrl_alert_test.1944982561 |
| /workspace/coverage/default/40.sram_ctrl_bijection.2645413260 |
| /workspace/coverage/default/40.sram_ctrl_executable.555213065 |
| /workspace/coverage/default/40.sram_ctrl_lc_escalation.217394880 |
| /workspace/coverage/default/40.sram_ctrl_max_throughput.798546 |
| /workspace/coverage/default/40.sram_ctrl_mem_partial_access.295585266 |
| /workspace/coverage/default/40.sram_ctrl_mem_walk.3180939990 |
| /workspace/coverage/default/40.sram_ctrl_multiple_keys.1834083698 |
| /workspace/coverage/default/40.sram_ctrl_partial_access.3113545317 |
| /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.4070987501 |
| /workspace/coverage/default/40.sram_ctrl_ram_cfg.4086858169 |
| /workspace/coverage/default/40.sram_ctrl_regwen.3327887488 |
| /workspace/coverage/default/40.sram_ctrl_smoke.3736619777 |
| /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2743186262 |
| /workspace/coverage/default/40.sram_ctrl_stress_pipeline.3524271936 |
| /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3310535252 |
| /workspace/coverage/default/41.sram_ctrl_access_during_key_req.1855955531 |
| /workspace/coverage/default/41.sram_ctrl_alert_test.3774230592 |
| /workspace/coverage/default/41.sram_ctrl_bijection.317422862 |
| /workspace/coverage/default/41.sram_ctrl_lc_escalation.3635908716 |
| /workspace/coverage/default/41.sram_ctrl_max_throughput.3122505421 |
| /workspace/coverage/default/41.sram_ctrl_mem_partial_access.658110152 |
| /workspace/coverage/default/41.sram_ctrl_mem_walk.667064604 |
| /workspace/coverage/default/41.sram_ctrl_multiple_keys.156855447 |
| /workspace/coverage/default/41.sram_ctrl_partial_access.3563966228 |
| /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.767820603 |
| /workspace/coverage/default/41.sram_ctrl_ram_cfg.4013344743 |
| /workspace/coverage/default/41.sram_ctrl_regwen.1966386328 |
| /workspace/coverage/default/41.sram_ctrl_smoke.542677828 |
| /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3583179082 |
| /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3510343169 |
| /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1033233903 |
| /workspace/coverage/default/42.sram_ctrl_access_during_key_req.321350068 |
| /workspace/coverage/default/42.sram_ctrl_alert_test.1032352619 |
| /workspace/coverage/default/42.sram_ctrl_bijection.3083258054 |
| /workspace/coverage/default/42.sram_ctrl_lc_escalation.776396471 |
| /workspace/coverage/default/42.sram_ctrl_max_throughput.2874894870 |
| /workspace/coverage/default/42.sram_ctrl_mem_partial_access.4123838927 |
| /workspace/coverage/default/42.sram_ctrl_mem_walk.1503632258 |
| /workspace/coverage/default/42.sram_ctrl_multiple_keys.3688366363 |
| /workspace/coverage/default/42.sram_ctrl_partial_access.327931546 |
| /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2538807390 |
| /workspace/coverage/default/42.sram_ctrl_ram_cfg.586071017 |
| /workspace/coverage/default/42.sram_ctrl_regwen.46290062 |
| /workspace/coverage/default/42.sram_ctrl_smoke.1400298771 |
| /workspace/coverage/default/42.sram_ctrl_stress_all.1739145769 |
| /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3615251507 |
| /workspace/coverage/default/42.sram_ctrl_stress_pipeline.359527666 |
| /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.4175215341 |
| /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2835883515 |
| /workspace/coverage/default/43.sram_ctrl_alert_test.658962690 |
| /workspace/coverage/default/43.sram_ctrl_bijection.2700621655 |
| /workspace/coverage/default/43.sram_ctrl_lc_escalation.2481962702 |
| /workspace/coverage/default/43.sram_ctrl_max_throughput.1249364287 |
| /workspace/coverage/default/43.sram_ctrl_mem_partial_access.2329686456 |
| /workspace/coverage/default/43.sram_ctrl_mem_walk.332001899 |
| /workspace/coverage/default/43.sram_ctrl_partial_access.973343370 |
| /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1636569873 |
| /workspace/coverage/default/43.sram_ctrl_ram_cfg.2881811237 |
| /workspace/coverage/default/43.sram_ctrl_regwen.3471178905 |
| /workspace/coverage/default/43.sram_ctrl_smoke.350493544 |
| /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.62410163 |
| /workspace/coverage/default/43.sram_ctrl_stress_pipeline.21686135 |
| /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1240945162 |
| /workspace/coverage/default/44.sram_ctrl_access_during_key_req.167685642 |
| /workspace/coverage/default/44.sram_ctrl_alert_test.2829740831 |
| /workspace/coverage/default/44.sram_ctrl_bijection.2502870928 |
| /workspace/coverage/default/44.sram_ctrl_lc_escalation.2182271096 |
| /workspace/coverage/default/44.sram_ctrl_max_throughput.4092613249 |
| /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3598663609 |
| /workspace/coverage/default/44.sram_ctrl_mem_walk.1154932788 |
| /workspace/coverage/default/44.sram_ctrl_multiple_keys.1017270714 |
| /workspace/coverage/default/44.sram_ctrl_partial_access.844287469 |
| /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1261737973 |
| /workspace/coverage/default/44.sram_ctrl_ram_cfg.3870942184 |
| /workspace/coverage/default/44.sram_ctrl_smoke.2703299460 |
| /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1777344551 |
| /workspace/coverage/default/44.sram_ctrl_stress_pipeline.585378237 |
| /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1437104083 |
| /workspace/coverage/default/45.sram_ctrl_access_during_key_req.2688746298 |
| /workspace/coverage/default/45.sram_ctrl_alert_test.1063683146 |
| /workspace/coverage/default/45.sram_ctrl_bijection.717659000 |
| /workspace/coverage/default/45.sram_ctrl_executable.2948858329 |
| /workspace/coverage/default/45.sram_ctrl_lc_escalation.1580123071 |
| /workspace/coverage/default/45.sram_ctrl_max_throughput.818325344 |
| /workspace/coverage/default/45.sram_ctrl_mem_partial_access.597913719 |
| /workspace/coverage/default/45.sram_ctrl_mem_walk.429298072 |
| /workspace/coverage/default/45.sram_ctrl_multiple_keys.1480778570 |
| /workspace/coverage/default/45.sram_ctrl_partial_access.3785614307 |
| /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.130400660 |
| /workspace/coverage/default/45.sram_ctrl_ram_cfg.1639296248 |
| /workspace/coverage/default/45.sram_ctrl_regwen.3412861188 |
| /workspace/coverage/default/45.sram_ctrl_smoke.383929492 |
| /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3482537005 |
| /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3928407240 |
| /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.4038170503 |
| /workspace/coverage/default/46.sram_ctrl_access_during_key_req.3713397957 |
| /workspace/coverage/default/46.sram_ctrl_alert_test.1762960266 |
| /workspace/coverage/default/46.sram_ctrl_bijection.1963747813 |
| /workspace/coverage/default/46.sram_ctrl_executable.3961146136 |
| /workspace/coverage/default/46.sram_ctrl_lc_escalation.2979867510 |
| /workspace/coverage/default/46.sram_ctrl_max_throughput.2496325571 |
| /workspace/coverage/default/46.sram_ctrl_mem_partial_access.3986105022 |
| /workspace/coverage/default/46.sram_ctrl_mem_walk.2927315574 |
| /workspace/coverage/default/46.sram_ctrl_multiple_keys.3705729648 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.37497382 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.4224067273 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.2867810163 |
| /workspace/coverage/default/46.sram_ctrl_regwen.1172112073 |
| /workspace/coverage/default/46.sram_ctrl_smoke.3206819795 |
| /workspace/coverage/default/46.sram_ctrl_stress_all.2657433594 |
| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3399350681 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2534442575 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1922952504 |
| /workspace/coverage/default/47.sram_ctrl_access_during_key_req.471380452 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.1590816290 |
| /workspace/coverage/default/47.sram_ctrl_bijection.3025375018 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.4215504009 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.588188778 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.2046566437 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.2186211930 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.2332066134 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1586274918 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.764000163 |
| /workspace/coverage/default/47.sram_ctrl_regwen.3667875852 |
| /workspace/coverage/default/47.sram_ctrl_smoke.1306045703 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.124803744 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.4159182041 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1737472657 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1429540761 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.1925022185 |
| /workspace/coverage/default/48.sram_ctrl_bijection.2975826572 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.1633389816 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.3689005476 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.1903743818 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.1806676709 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.3876131884 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.1616694004 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1822631849 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.3374505429 |
| /workspace/coverage/default/48.sram_ctrl_regwen.256091041 |
| /workspace/coverage/default/48.sram_ctrl_smoke.2938076176 |
| /workspace/coverage/default/48.sram_ctrl_stress_all.974253805 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2755358735 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.850406025 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.179117839 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.162688339 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.1162924501 |
| /workspace/coverage/default/49.sram_ctrl_bijection.3192791350 |
| /workspace/coverage/default/49.sram_ctrl_executable.2301160767 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.1739321477 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.171358386 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.3790193245 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.2136606525 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.4001567483 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.4039254352 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3147713798 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.145896980 |
| /workspace/coverage/default/49.sram_ctrl_regwen.873782492 |
| /workspace/coverage/default/49.sram_ctrl_smoke.3566496970 |
| /workspace/coverage/default/49.sram_ctrl_stress_all.3332939857 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1604078296 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.259912619 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2678074430 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.4238030069 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.180194423 |
| /workspace/coverage/default/5.sram_ctrl_bijection.4095825685 |
| /workspace/coverage/default/5.sram_ctrl_executable.2730831696 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.779925977 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.4240601842 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.348849883 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.2680208261 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.1548938312 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1944823627 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.2865647400 |
| /workspace/coverage/default/5.sram_ctrl_regwen.3767564910 |
| /workspace/coverage/default/5.sram_ctrl_smoke.274928277 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1182528040 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1534621921 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3851122356 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.2550197031 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.1539672756 |
| /workspace/coverage/default/6.sram_ctrl_bijection.1511940181 |
| /workspace/coverage/default/6.sram_ctrl_executable.451514136 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.2775386276 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.4285206441 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.4213933722 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.2881930435 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.1843976474 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.1935338067 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.4001789411 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.3979199484 |
| /workspace/coverage/default/6.sram_ctrl_regwen.3232781854 |
| /workspace/coverage/default/6.sram_ctrl_smoke.864288689 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.583640082 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3355628582 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3596894519 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3509710863 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3088247568 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.3304921326 |
| /workspace/coverage/default/7.sram_ctrl_bijection.1880601721 |
| /workspace/coverage/default/7.sram_ctrl_executable.791706312 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.265485374 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.3346807417 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.346673714 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.3661142822 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.3363615203 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.2761628136 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.416580344 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.224856340 |
| /workspace/coverage/default/7.sram_ctrl_regwen.2921958398 |
| /workspace/coverage/default/7.sram_ctrl_smoke.474186014 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1904920959 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1149683854 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.582891419 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.3983226811 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.3550368239 |
| /workspace/coverage/default/8.sram_ctrl_bijection.3192257304 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.3280419806 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.1790806492 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.3664418923 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.2980000428 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.2505982733 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.3979945184 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.4279038391 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.3099488848 |
| /workspace/coverage/default/8.sram_ctrl_regwen.2385478695 |
| /workspace/coverage/default/8.sram_ctrl_smoke.2672618108 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.336545757 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2214635930 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.4158411102 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.3307131328 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.1435121278 |
| /workspace/coverage/default/9.sram_ctrl_bijection.3214118575 |
| /workspace/coverage/default/9.sram_ctrl_executable.1010924123 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.3296060788 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.4228018197 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.187444809 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.658324180 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.124578064 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.3596433264 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1759558730 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.1153591760 |
| /workspace/coverage/default/9.sram_ctrl_regwen.3920308295 |
| /workspace/coverage/default/9.sram_ctrl_smoke.1617725538 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.542965654 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1474607654 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.4090113050 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.488200220 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1751399663 |
|
|
Dec 27 12:44:47 PM PST 23 |
Dec 27 01:31:14 PM PST 23 |
6582133000 ps |
| T2 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3363615203 |
|
|
Dec 27 12:44:16 PM PST 23 |
Dec 27 12:50:34 PM PST 23 |
23826151790 ps |
| T3 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.3786283771 |
|
|
Dec 27 12:45:00 PM PST 23 |
Dec 27 12:46:23 PM PST 23 |
7292156314 ps |
| T4 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.2668826816 |
|
|
Dec 27 12:44:53 PM PST 23 |
Dec 27 12:47:05 PM PST 23 |
8233339266 ps |
| T9 |
/workspace/coverage/default/16.sram_ctrl_bijection.2726389537 |
|
|
Dec 27 12:44:37 PM PST 23 |
Dec 27 12:56:46 PM PST 23 |
11648407402 ps |
| T10 |
/workspace/coverage/default/25.sram_ctrl_regwen.3243402472 |
|
|
Dec 27 12:44:54 PM PST 23 |
Dec 27 01:20:25 PM PST 23 |
3366706367 ps |
| T11 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.2688746298 |
|
|
Dec 27 12:45:16 PM PST 23 |
Dec 27 01:08:42 PM PST 23 |
9194719369 ps |
| T12 |
/workspace/coverage/default/12.sram_ctrl_alert_test.450502570 |
|
|
Dec 27 12:44:27 PM PST 23 |
Dec 27 12:44:36 PM PST 23 |
178480067 ps |
| T13 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.3021590730 |
|
|
Dec 27 12:44:38 PM PST 23 |
Dec 27 12:47:03 PM PST 23 |
13027422448 ps |
| T14 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.4230837992 |
|
|
Dec 27 12:45:43 PM PST 23 |
Dec 27 12:47:19 PM PST 23 |
22010600256 ps |
| T17 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3263716595 |
|
|
Dec 27 12:45:06 PM PST 23 |
Dec 27 01:41:40 PM PST 23 |
812009205 ps |
| T59 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.985526650 |
|
|
Dec 27 12:44:42 PM PST 23 |
Dec 27 12:48:47 PM PST 23 |
19695198596 ps |
| T18 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.3869833093 |
|
|
Dec 27 12:45:15 PM PST 23 |
Dec 27 12:47:32 PM PST 23 |
6438260837 ps |
| T19 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.3422000110 |
|
|
Dec 27 12:44:30 PM PST 23 |
Dec 27 01:06:22 PM PST 23 |
8728786157 ps |
| T20 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.2887769335 |
|
|
Dec 27 12:45:23 PM PST 23 |
Dec 27 12:49:15 PM PST 23 |
3501773750 ps |
| T31 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3355628582 |
|
|
Dec 27 12:45:08 PM PST 23 |
Dec 27 01:44:10 PM PST 23 |
1067579557 ps |
| T93 |
/workspace/coverage/default/36.sram_ctrl_bijection.3507432777 |
|
|
Dec 27 12:45:30 PM PST 23 |
Dec 27 01:19:41 PM PST 23 |
625081005281 ps |
| T15 |
/workspace/coverage/default/10.sram_ctrl_smoke.728912308 |
|
|
Dec 27 12:45:09 PM PST 23 |
Dec 27 12:47:36 PM PST 23 |
5882196239 ps |
| T102 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1747283937 |
|
|
Dec 27 12:45:10 PM PST 23 |
Dec 27 12:46:21 PM PST 23 |
9099750730 ps |
| T103 |
/workspace/coverage/default/25.sram_ctrl_smoke.612029509 |
|
|
Dec 27 12:44:58 PM PST 23 |
Dec 27 12:47:45 PM PST 23 |
1788407456 ps |
| T130 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.798546 |
|
|
Dec 27 12:45:32 PM PST 23 |
Dec 27 12:46:11 PM PST 23 |
693454693 ps |
| T34 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.3716989585 |
|
|
Dec 27 12:44:38 PM PST 23 |
Dec 27 12:44:51 PM PST 23 |
349522659 ps |
| T95 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3581108741 |
|
|
Dec 27 12:44:10 PM PST 23 |
Dec 27 12:50:57 PM PST 23 |
60329618524 ps |
| T21 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.605057980 |
|
|
Dec 27 12:45:29 PM PST 23 |
Dec 27 12:58:19 PM PST 23 |
44744520393 ps |
| T96 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.351012709 |
|
|
Dec 27 12:44:16 PM PST 23 |
Dec 27 12:49:16 PM PST 23 |
10183453149 ps |
| T131 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.728315717 |
|
|
Dec 27 12:45:09 PM PST 23 |
Dec 27 12:47:12 PM PST 23 |
2982993476 ps |
| T7 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.2979867510 |
|
|
Dec 27 12:45:38 PM PST 23 |
Dec 27 12:46:14 PM PST 23 |
2789984361 ps |
| T16 |
/workspace/coverage/default/5.sram_ctrl_smoke.274928277 |
|
|
Dec 27 12:44:47 PM PST 23 |
Dec 27 12:45:48 PM PST 23 |
2246653170 ps |
| T52 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1358647529 |
|
|
Dec 27 12:44:47 PM PST 23 |
Dec 27 01:28:21 PM PST 23 |
1303323812 ps |
| T27 |
/workspace/coverage/default/16.sram_ctrl_regwen.460945744 |
|
|
Dec 27 12:44:19 PM PST 23 |
Dec 27 12:50:08 PM PST 23 |
19163295700 ps |
| T132 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.559866385 |
|
|
Dec 27 12:45:01 PM PST 23 |
Dec 27 12:49:03 PM PST 23 |
4068392436 ps |
| T97 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.2076071808 |
|
|
Dec 27 12:44:56 PM PST 23 |
Dec 27 12:50:51 PM PST 23 |
47524965189 ps |
| T35 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.2380107362 |
|
|
Dec 27 12:45:06 PM PST 23 |
Dec 27 12:45:25 PM PST 23 |
699318370 ps |
| T69 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.1458678178 |
|
|
Dec 27 12:44:23 PM PST 23 |
Dec 27 01:17:39 PM PST 23 |
13176601902 ps |
| T115 |
/workspace/coverage/default/36.sram_ctrl_executable.26382413 |
|
|
Dec 27 12:45:50 PM PST 23 |
Dec 27 01:03:31 PM PST 23 |
11978611446 ps |
| T133 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1033233903 |
|
|
Dec 27 12:45:42 PM PST 23 |
Dec 27 12:47:54 PM PST 23 |
771127244 ps |
| T134 |
/workspace/coverage/default/44.sram_ctrl_bijection.2502870928 |
|
|
Dec 27 12:45:35 PM PST 23 |
Dec 27 01:10:12 PM PST 23 |
21333573814 ps |
| T135 |
/workspace/coverage/default/35.sram_ctrl_bijection.1654707195 |
|
|
Dec 27 12:45:27 PM PST 23 |
Dec 27 01:24:31 PM PST 23 |
575074949063 ps |
| T136 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3748920436 |
|
|
Dec 27 12:44:22 PM PST 23 |
Dec 27 12:45:02 PM PST 23 |
1019213875 ps |
| T137 |
/workspace/coverage/default/49.sram_ctrl_bijection.3192791350 |
|
|
Dec 27 12:45:44 PM PST 23 |
Dec 27 01:14:20 PM PST 23 |
478575300396 ps |
| T138 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.3661142822 |
|
|
Dec 27 12:44:38 PM PST 23 |
Dec 27 12:47:35 PM PST 23 |
73747588825 ps |
| T73 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1603924157 |
|
|
Dec 27 12:44:13 PM PST 23 |
Dec 27 12:59:23 PM PST 23 |
35734332388 ps |
| T139 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.179117839 |
|
|
Dec 27 12:45:13 PM PST 23 |
Dec 27 12:47:05 PM PST 23 |
806575123 ps |
| T74 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.295585266 |
|
|
Dec 27 12:45:24 PM PST 23 |
Dec 27 12:47:58 PM PST 23 |
5198453394 ps |
| T53 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2237297257 |
|
|
Dec 27 12:44:56 PM PST 23 |
Dec 27 01:19:26 PM PST 23 |
8428068537 ps |
| T140 |
/workspace/coverage/default/21.sram_ctrl_partial_access.3684192921 |
|
|
Dec 27 12:44:42 PM PST 23 |
Dec 27 12:45:06 PM PST 23 |
2419058780 ps |
| T98 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.1671489793 |
|
|
Dec 27 12:44:55 PM PST 23 |
Dec 27 12:50:10 PM PST 23 |
4174317942 ps |
| T32 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1185756587 |
|
|
Dec 27 12:32:12 PM PST 23 |
Dec 27 12:32:57 PM PST 23 |
64025388 ps |
| T54 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3189569290 |
|
|
Dec 27 12:32:57 PM PST 23 |
Dec 27 12:33:36 PM PST 23 |
353973478 ps |
| T33 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2026579507 |
|
|
Dec 27 12:32:39 PM PST 23 |
Dec 27 12:35:39 PM PST 23 |
3799238116 ps |
| T60 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.505985397 |
|
|
Dec 27 12:33:12 PM PST 23 |
Dec 27 12:34:43 PM PST 23 |
15784762328 ps |
| T55 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3256326528 |
|
|
Dec 27 12:33:03 PM PST 23 |
Dec 27 12:33:39 PM PST 23 |
277943865 ps |
| T56 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1549660898 |
|
|
Dec 27 12:32:57 PM PST 23 |
Dec 27 12:33:34 PM PST 23 |
85707600 ps |
| T57 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.348664482 |
|
|
Dec 27 12:32:41 PM PST 23 |
Dec 27 12:33:20 PM PST 23 |
134899301 ps |
| T49 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.4117111410 |
|
|
Dec 27 12:32:44 PM PST 23 |
Dec 27 12:33:22 PM PST 23 |
348185522 ps |
| T58 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1978696704 |
|
|
Dec 27 12:33:18 PM PST 23 |
Dec 27 12:33:49 PM PST 23 |
142813006 ps |
| T61 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4011476609 |
|
|
Dec 27 12:32:18 PM PST 23 |
Dec 27 12:33:02 PM PST 23 |
58095345 ps |
| T50 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3705539474 |
|
|
Dec 27 12:33:18 PM PST 23 |
Dec 27 12:33:46 PM PST 23 |
118775547 ps |
| T141 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1588475056 |
|
|
Dec 27 12:32:53 PM PST 23 |
Dec 27 12:33:40 PM PST 23 |
789220422 ps |
| T94 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4090104106 |
|
|
Dec 27 12:32:17 PM PST 23 |
Dec 27 12:33:01 PM PST 23 |
21545783 ps |
| T142 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1414604546 |
|
|
Dec 27 12:33:00 PM PST 23 |
Dec 27 12:33:33 PM PST 23 |
12528619 ps |
| T62 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.613162331 |
|
|
Dec 27 12:33:22 PM PST 23 |
Dec 27 12:34:40 PM PST 23 |
3879431118 ps |
| T63 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1511769039 |
|
|
Dec 27 12:33:01 PM PST 23 |
Dec 27 12:34:30 PM PST 23 |
7390252680 ps |
| T64 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3637532718 |
|
|
Dec 27 12:33:29 PM PST 23 |
Dec 27 12:35:36 PM PST 23 |
29389867227 ps |
| T65 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3393420944 |
|
|
Dec 27 12:33:42 PM PST 23 |
Dec 27 12:33:58 PM PST 23 |
16183305 ps |
| T66 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2049394619 |
|
|
Dec 27 12:33:20 PM PST 23 |
Dec 27 12:33:50 PM PST 23 |
13106345 ps |
| T67 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3673287340 |
|
|
Dec 27 12:33:09 PM PST 23 |
Dec 27 12:33:40 PM PST 23 |
13194333 ps |
| T68 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.759831694 |
|
|
Dec 27 12:33:21 PM PST 23 |
Dec 27 12:33:47 PM PST 23 |
13674971 ps |
| T51 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2680226144 |
|
|
Dec 27 12:32:54 PM PST 23 |
Dec 27 12:33:31 PM PST 23 |
758999181 ps |
| T84 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2573693135 |
|
|
Dec 27 12:32:23 PM PST 23 |
Dec 27 12:33:05 PM PST 23 |
28489601 ps |
| T90 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2671045425 |
|
|
Dec 27 12:32:54 PM PST 23 |
Dec 27 12:33:30 PM PST 23 |
896781883 ps |
| T91 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2931315104 |
|
|
Dec 27 12:33:20 PM PST 23 |
Dec 27 12:33:48 PM PST 23 |
61579579 ps |
| T143 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.140076441 |
|
|
Dec 27 12:32:35 PM PST 23 |
Dec 27 12:33:15 PM PST 23 |
42308981 ps |
| T104 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1424881901 |
|
|
Dec 27 12:32:57 PM PST 23 |
Dec 27 12:33:33 PM PST 23 |
405468092 ps |
| T70 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.753649946 |
|
|
Dec 27 12:32:56 PM PST 23 |
Dec 27 12:33:30 PM PST 23 |
39058304 ps |
| T144 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1511912231 |
|
|
Dec 27 12:32:24 PM PST 23 |
Dec 27 12:33:11 PM PST 23 |
360967796 ps |
| T145 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1814951675 |
|
|
Dec 27 12:32:10 PM PST 23 |
Dec 27 12:32:59 PM PST 23 |
1423167420 ps |
| T71 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1886448693 |
|
|
Dec 27 12:32:17 PM PST 23 |
Dec 27 12:33:01 PM PST 23 |
14222315 ps |
| T146 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.692359110 |
|
|
Dec 27 12:32:39 PM PST 23 |
Dec 27 12:33:17 PM PST 23 |
14523057 ps |
| T147 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2229261312 |
|
|
Dec 27 12:32:16 PM PST 23 |
Dec 27 12:33:01 PM PST 23 |
547882074 ps |
| T148 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3159911150 |
|
|
Dec 27 12:32:13 PM PST 23 |
Dec 27 12:33:01 PM PST 23 |
40844531 ps |
| T149 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.154535019 |
|
|
Dec 27 12:32:13 PM PST 23 |
Dec 27 12:32:57 PM PST 23 |
22341519 ps |
| T72 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3806343108 |
|
|
Dec 27 12:32:52 PM PST 23 |
Dec 27 12:33:28 PM PST 23 |
96880932 ps |
| T150 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.108494335 |
|
|
Dec 27 12:32:29 PM PST 23 |
Dec 27 12:33:10 PM PST 23 |
30868961 ps |
| T151 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1088957040 |
|
|
Dec 27 12:32:40 PM PST 23 |
Dec 27 12:33:18 PM PST 23 |
11644313 ps |
| T75 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1217446344 |
|
|
Dec 27 12:33:10 PM PST 23 |
Dec 27 12:35:26 PM PST 23 |
20145735683 ps |
| T76 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1159248387 |
|
|
Dec 27 12:32:54 PM PST 23 |
Dec 27 12:33:29 PM PST 23 |
34498340 ps |
| T152 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.472556511 |
|
|
Dec 27 12:33:13 PM PST 23 |
Dec 27 12:33:46 PM PST 23 |
734541175 ps |
| T153 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.901727870 |
|
|
Dec 27 12:32:51 PM PST 23 |
Dec 27 12:33:32 PM PST 23 |
1452369023 ps |
| T154 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2211097211 |
|
|
Dec 27 12:33:11 PM PST 23 |
Dec 27 12:33:44 PM PST 23 |
36641714 ps |
| T155 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2225741145 |
|
|
Dec 27 12:32:37 PM PST 23 |
Dec 27 12:33:16 PM PST 23 |
13156529 ps |
| T77 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4275085290 |
|
|
Dec 27 12:32:40 PM PST 23 |
Dec 27 12:33:18 PM PST 23 |
13779583 ps |
| T156 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2302359920 |
|
|
Dec 27 12:32:48 PM PST 23 |
Dec 27 12:33:32 PM PST 23 |
15742887 ps |
| T157 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3797808836 |
|
|
Dec 27 12:33:10 PM PST 23 |
Dec 27 12:33:41 PM PST 23 |
47066374 ps |
| T158 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.950199220 |
|
|
Dec 27 12:32:18 PM PST 23 |
Dec 27 12:34:02 PM PST 23 |
14761086314 ps |
| T78 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1680584555 |
|
|
Dec 27 12:33:22 PM PST 23 |
Dec 27 12:38:10 PM PST 23 |
7114743846 ps |
| T159 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1996999048 |
|
|
Dec 27 12:33:11 PM PST 23 |
Dec 27 12:33:46 PM PST 23 |
1547091478 ps |
| T79 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3959133574 |
|
|
Dec 27 12:32:52 PM PST 23 |
Dec 27 12:33:34 PM PST 23 |
30588138 ps |
| T160 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1627277896 |
|
|
Dec 27 12:35:09 PM PST 23 |
Dec 27 12:35:27 PM PST 23 |
33128468 ps |
| T161 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3882171617 |
|
|
Dec 27 12:32:35 PM PST 23 |
Dec 27 12:33:15 PM PST 23 |
20372792 ps |
| T162 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3203042784 |
|
|
Dec 27 12:33:00 PM PST 23 |
Dec 27 12:33:33 PM PST 23 |
21706630 ps |
| T163 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1394235345 |
|
|
Dec 27 12:33:23 PM PST 23 |
Dec 27 12:34:00 PM PST 23 |
1436658160 ps |
| T82 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.443064663 |
|
|
Dec 27 12:33:10 PM PST 23 |
Dec 27 12:38:23 PM PST 23 |
87895665384 ps |
| T164 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3091710005 |
|
|
Dec 27 12:32:58 PM PST 23 |
Dec 27 12:33:44 PM PST 23 |
354375853 ps |
| T165 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3180797406 |
|
|
Dec 27 12:32:40 PM PST 23 |
Dec 27 12:33:18 PM PST 23 |
14591271 ps |
| T166 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1769728108 |
|
|
Dec 27 12:32:30 PM PST 23 |
Dec 27 12:33:14 PM PST 23 |
466791040 ps |
| T83 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.767638080 |
|
|
Dec 27 12:32:11 PM PST 23 |
Dec 27 12:32:56 PM PST 23 |
13439017 ps |
| T167 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3905479798 |
|
|
Dec 27 12:32:51 PM PST 23 |
Dec 27 12:33:31 PM PST 23 |
349139394 ps |
| T168 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.923848394 |
|
|
Dec 27 12:33:11 PM PST 23 |
Dec 27 12:33:42 PM PST 23 |
16539087 ps |
| T169 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2876257479 |
|
|
Dec 27 12:32:58 PM PST 23 |
Dec 27 12:33:32 PM PST 23 |
12252696 ps |
| T170 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2660920634 |
|
|
Dec 27 12:32:28 PM PST 23 |
Dec 27 12:33:08 PM PST 23 |
27112072 ps |
| T171 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2306337286 |
|
|
Dec 27 12:32:22 PM PST 23 |
Dec 27 12:33:06 PM PST 23 |
49511657 ps |
| T172 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2930537233 |
|
|
Dec 27 12:32:56 PM PST 23 |
Dec 27 12:33:31 PM PST 23 |
139916886 ps |
| T173 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.656278784 |
|
|
Dec 27 12:32:48 PM PST 23 |
Dec 27 12:33:24 PM PST 23 |
40913214 ps |
| T92 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.4070495503 |
|
|
Dec 27 12:32:58 PM PST 23 |
Dec 27 12:35:48 PM PST 23 |
7692185489 ps |
| T174 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.755657631 |
|
|
Dec 27 12:33:07 PM PST 23 |
Dec 27 12:33:44 PM PST 23 |
363487547 ps |
| T109 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.735656510 |
|
|
Dec 27 12:32:34 PM PST 23 |
Dec 27 12:33:16 PM PST 23 |
361046727 ps |
| T175 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4076887818 |
|
|
Dec 27 12:32:59 PM PST 23 |
Dec 27 12:33:38 PM PST 23 |
1517848392 ps |
| T176 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.5772230 |
|
|
Dec 27 12:33:29 PM PST 23 |
Dec 27 12:33:50 PM PST 23 |
152194101 ps |
| T112 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2664416328 |
|
|
Dec 27 12:33:07 PM PST 23 |
Dec 27 12:33:40 PM PST 23 |
117461030 ps |
| T177 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2324426131 |
|
|
Dec 27 12:32:56 PM PST 23 |
Dec 27 12:33:34 PM PST 23 |
2763397113 ps |
| T113 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3479260496 |
|
|
Dec 27 12:32:41 PM PST 23 |
Dec 27 12:33:20 PM PST 23 |
99457788 ps |
| T178 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3085852140 |
|
|
Dec 27 12:32:57 PM PST 23 |
Dec 27 12:33:36 PM PST 23 |
1512188299 ps |
| T179 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1406443083 |
|
|
Dec 27 12:32:30 PM PST 23 |
Dec 27 12:33:11 PM PST 23 |
25354693 ps |
| T85 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3154593471 |
|
|
Dec 27 12:32:43 PM PST 23 |
Dec 27 12:37:49 PM PST 23 |
29510113991 ps |
| T180 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.462260641 |
|
|
Dec 27 12:32:47 PM PST 23 |
Dec 27 12:33:26 PM PST 23 |
807519682 ps |
| T181 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4144442484 |
|
|
Dec 27 12:32:24 PM PST 23 |
Dec 27 12:33:06 PM PST 23 |
14265712 ps |
| T182 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2492793021 |
|
|
Dec 27 12:32:57 PM PST 23 |
Dec 27 12:33:31 PM PST 23 |
36081502 ps |
| T183 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3003578946 |
|
|
Dec 27 12:32:54 PM PST 23 |
Dec 27 12:33:32 PM PST 23 |
582151528 ps |
| T184 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1499555300 |
|
|
Dec 27 12:32:38 PM PST 23 |
Dec 27 12:33:22 PM PST 23 |
2838697205 ps |
| T185 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3999886779 |
|
|
Dec 27 12:33:09 PM PST 23 |
Dec 27 12:33:40 PM PST 23 |
15780578 ps |
| T186 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.373708116 |
|
|
Dec 27 12:32:32 PM PST 23 |
Dec 27 12:33:14 PM PST 23 |
190368209 ps |
| T187 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.537706320 |
|
|
Dec 27 12:32:50 PM PST 23 |
Dec 27 12:33:25 PM PST 23 |
12994196 ps |
| T188 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3582402566 |
|
|
Dec 27 12:33:09 PM PST 23 |
Dec 27 12:33:40 PM PST 23 |
14208902 ps |
| T189 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.823918461 |
|
|
Dec 27 12:32:57 PM PST 23 |
Dec 27 12:33:32 PM PST 23 |
71740663 ps |
| T190 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2966447026 |
|
|
Dec 27 12:32:15 PM PST 23 |
Dec 27 12:33:07 PM PST 23 |
144403458 ps |
| T191 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2934123743 |
|
|
Dec 27 12:32:21 PM PST 23 |
Dec 27 12:33:05 PM PST 23 |
256482095 ps |
| T86 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1932395615 |
|
|
Dec 27 12:32:41 PM PST 23 |
Dec 27 12:37:54 PM PST 23 |
8043029483 ps |
| T192 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1520341199 |
|
|
Dec 27 12:33:38 PM PST 23 |
Dec 27 12:33:54 PM PST 23 |
45555271 ps |
| T87 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2905726676 |
|
|
Dec 27 12:32:20 PM PST 23 |
Dec 27 12:34:43 PM PST 23 |
7224891972 ps |
| T193 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1776462894 |
|
|
Dec 27 12:32:19 PM PST 23 |
Dec 27 12:33:03 PM PST 23 |
289152891 ps |
| T88 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3015034961 |
|
|
Dec 27 12:33:18 PM PST 23 |
Dec 27 12:38:12 PM PST 23 |
7046199661 ps |
| T194 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.721359110 |
|
|
Dec 27 12:33:01 PM PST 23 |
Dec 27 12:33:34 PM PST 23 |
33549293 ps |
| T107 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4115051370 |
|
|
Dec 27 12:33:03 PM PST 23 |
Dec 27 12:33:37 PM PST 23 |
135364500 ps |
| T195 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2679942790 |
|
|
Dec 27 12:33:00 PM PST 23 |
Dec 27 12:33:33 PM PST 23 |
27902330 ps |
| T196 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3233937865 |
|
|
Dec 27 12:32:08 PM PST 23 |
Dec 27 12:32:55 PM PST 23 |
498718107 ps |
| T197 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1457569108 |
|
|
Dec 27 12:32:53 PM PST 23 |
Dec 27 12:34:26 PM PST 23 |
5824771854 ps |
| T198 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.612463002 |
|
|
Dec 27 12:33:16 PM PST 23 |
Dec 27 12:33:45 PM PST 23 |
33865205 ps |
| T199 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1231953789 |
|
|
Dec 27 12:32:28 PM PST 23 |
Dec 27 12:33:13 PM PST 23 |
1405642782 ps |
| T200 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.11392502 |
|
|
Dec 27 12:32:45 PM PST 23 |
Dec 27 12:33:23 PM PST 23 |
24468440 ps |
| T201 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.4221608006 |
|
|
Dec 27 12:32:56 PM PST 23 |
Dec 27 12:35:28 PM PST 23 |
7350897593 ps |
| T105 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2737192450 |
|
|
Dec 27 12:34:47 PM PST 23 |
Dec 27 12:35:10 PM PST 23 |
186762778 ps |
| T89 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2310235443 |
|
|
Dec 27 12:32:29 PM PST 23 |
Dec 27 12:33:10 PM PST 23 |
20033959 ps |
| T202 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2516140501 |
|
|
Dec 27 12:32:53 PM PST 23 |
Dec 27 12:33:28 PM PST 23 |
20362818 ps |
| T203 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.521827401 |
|
|
Dec 27 12:34:17 PM PST 23 |
Dec 27 12:34:34 PM PST 23 |
59742838 ps |
| T204 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3905254914 |
|
|
Dec 27 12:32:22 PM PST 23 |
Dec 27 12:33:05 PM PST 23 |
42884526 ps |
| T106 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3256608578 |
|
|
Dec 27 12:32:57 PM PST 23 |
Dec 27 12:33:32 PM PST 23 |
687208278 ps |
| T108 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1736425478 |
|
|
Dec 27 12:32:19 PM PST 23 |
Dec 27 12:33:04 PM PST 23 |
286777938 ps |
| T205 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2978907607 |
|
|
Dec 27 12:33:02 PM PST 23 |
Dec 27 12:33:35 PM PST 23 |
23157864 ps |
| T206 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2135668668 |
|
|
Dec 27 12:32:57 PM PST 23 |
Dec 27 12:35:37 PM PST 23 |
32057283917 ps |
| T207 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2867415994 |
|
|
Dec 27 12:32:17 PM PST 23 |
Dec 27 12:33:13 PM PST 23 |
356817350 ps |
| T208 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1408596477 |
|
|
Dec 27 12:32:48 PM PST 23 |
Dec 27 12:33:37 PM PST 23 |
360488595 ps |
| T209 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3706204380 |
|
|
Dec 27 12:32:51 PM PST 23 |
Dec 27 12:33:31 PM PST 23 |
2812110300 ps |
| T210 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3662099092 |
|
|
Dec 27 12:32:27 PM PST 23 |
Dec 27 12:33:09 PM PST 23 |
545191837 ps |
| T114 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3033792522 |
|
|
Dec 27 12:32:12 PM PST 23 |
Dec 27 12:32:58 PM PST 23 |
224538076 ps |
| T211 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2966640109 |
|
|
Dec 27 12:33:39 PM PST 23 |
Dec 27 12:33:55 PM PST 23 |
124199300 ps |
| T212 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.726500161 |
|
|
Dec 27 12:32:41 PM PST 23 |
Dec 27 12:33:20 PM PST 23 |
32217652 ps |
| T213 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2815456430 |
|
|
Dec 27 12:33:05 PM PST 23 |
Dec 27 12:33:50 PM PST 23 |
360020982 ps |
| T111 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2164711224 |
|
|
Dec 27 12:32:52 PM PST 23 |
Dec 27 12:33:29 PM PST 23 |
728179905 ps |
| T214 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.218113361 |
|
|
Dec 27 12:32:30 PM PST 23 |
Dec 27 12:33:10 PM PST 23 |
53400428 ps |
| T215 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.404924892 |
|
|
Dec 27 12:32:51 PM PST 23 |
Dec 27 12:37:55 PM PST 23 |
7548101028 ps |
| T216 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3565841526 |
|
|
Dec 27 12:33:06 PM PST 23 |
Dec 27 12:33:39 PM PST 23 |
14636702 ps |
| T217 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2718191489 |
|
|
Dec 27 12:32:20 PM PST 23 |
Dec 27 12:33:06 PM PST 23 |
119725528 ps |
| T110 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.787146997 |
|
|
Dec 27 12:32:30 PM PST 23 |
Dec 27 12:33:12 PM PST 23 |
270098740 ps |
| T218 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1024652423 |
|
|
Dec 27 12:32:19 PM PST 23 |
Dec 27 12:33:54 PM PST 23 |
26410429786 ps |
| T219 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1646147016 |
|
|
Dec 27 12:32:47 PM PST 23 |
Dec 27 12:33:23 PM PST 23 |
24853721 ps |
| T220 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2271293893 |
|
|
Dec 27 12:33:31 PM PST 23 |
Dec 27 12:35:34 PM PST 23 |
32063988247 ps |
| T221 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4269349255 |
|
|
Dec 27 12:32:39 PM PST 23 |
Dec 27 12:33:23 PM PST 23 |
295967166 ps |
| T222 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.217484765 |
|
|
Dec 27 12:33:44 PM PST 23 |
Dec 27 12:34:12 PM PST 23 |
361894251 ps |
| T223 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1954676897 |
|
|
Dec 27 12:32:40 PM PST 23 |
Dec 27 12:33:20 PM PST 23 |
187538501 ps |
| T224 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2767047142 |
|
|
Dec 27 12:33:13 PM PST 23 |
Dec 27 12:33:45 PM PST 23 |
77364400 ps |
| T225 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4160760271 |
|
|
Dec 27 12:33:01 PM PST 23 |
Dec 27 12:33:36 PM PST 23 |
68593785 ps |
| T28 |
/workspace/coverage/default/45.sram_ctrl_regwen.3412861188 |
|
|
Dec 27 12:45:30 PM PST 23 |
Dec 27 01:07:58 PM PST 23 |
5183206661 ps |
| T226 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.1834083698 |
|
|
Dec 27 12:45:37 PM PST 23 |
Dec 27 01:05:17 PM PST 23 |
44142003544 ps |
| T36 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.472995212 |
|
|
Dec 27 12:44:32 PM PST 23 |
Dec 27 12:44:47 PM PST 23 |
683763025 ps |
| T227 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.617905545 |
|
|
Dec 27 12:44:32 PM PST 23 |
Dec 27 12:44:54 PM PST 23 |
360042623 ps |
| T228 |
/workspace/coverage/default/7.sram_ctrl_smoke.474186014 |
|
|
Dec 27 12:45:02 PM PST 23 |
Dec 27 12:45:31 PM PST 23 |
1344666240 ps |
| T229 |
/workspace/coverage/default/14.sram_ctrl_smoke.3026559985 |
|
|
Dec 27 12:44:45 PM PST 23 |
Dec 27 12:45:04 PM PST 23 |
734509771 ps |
| T230 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.2502942117 |
|
|
Dec 27 12:44:21 PM PST 23 |
Dec 27 12:44:35 PM PST 23 |
367860540 ps |
| T231 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.2927315574 |
|
|
Dec 27 12:45:26 PM PST 23 |
Dec 27 12:47:38 PM PST 23 |
3950791786 ps |
| T232 |
/workspace/coverage/default/8.sram_ctrl_partial_access.3979945184 |
|
|
Dec 27 12:44:12 PM PST 23 |
Dec 27 12:44:56 PM PST 23 |
814288010 ps |
| T233 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1282039074 |
|
|
Dec 27 12:45:13 PM PST 23 |
Dec 27 12:46:35 PM PST 23 |
2990199888 ps |
| T234 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.145896980 |
|
|
Dec 27 12:45:38 PM PST 23 |
Dec 27 12:45:59 PM PST 23 |
686555319 ps |
| T235 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1256904508 |
|
|
Dec 27 12:44:54 PM PST 23 |
Dec 27 12:47:21 PM PST 23 |
780161172 ps |
| T127 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3585255568 |
|
|
Dec 27 12:44:15 PM PST 23 |
Dec 27 01:02:26 PM PST 23 |
31461862731 ps |
| T22 |
/workspace/coverage/default/20.sram_ctrl_alert_test.1601323190 |
|
|
Dec 27 12:44:48 PM PST 23 |
Dec 27 12:44:55 PM PST 23 |
28328850 ps |
| T23 |
/workspace/coverage/default/0.sram_ctrl_alert_test.954434544 |
|
|
Dec 27 12:44:29 PM PST 23 |
Dec 27 12:44:38 PM PST 23 |
12597998 ps |
| T99 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2139575922 |
|
|
Dec 27 12:44:52 PM PST 23 |
Dec 27 12:52:00 PM PST 23 |
34615966476 ps |
| T236 |
/workspace/coverage/default/24.sram_ctrl_partial_access.802632602 |
|
|
Dec 27 12:45:10 PM PST 23 |
Dec 27 12:45:39 PM PST 23 |
6364133473 ps |
| T100 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1456111259 |
|
|
Dec 27 12:44:34 PM PST 23 |
Dec 27 12:53:29 PM PST 23 |
95016763177 ps |
| T237 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1008880673 |
|
|
Dec 27 12:45:23 PM PST 23 |
Dec 27 01:30:05 PM PST 23 |
206453348 ps |
| T8 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.217394880 |
|
|
Dec 27 12:45:22 PM PST 23 |
Dec 27 12:46:17 PM PST 23 |
13833186756 ps |
| T238 |
/workspace/coverage/default/28.sram_ctrl_bijection.4286544882 |
|
|
Dec 27 12:45:01 PM PST 23 |
Dec 27 01:04:43 PM PST 23 |
31697592634 ps |
| T101 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.1749086321 |
|
|
Dec 27 12:44:12 PM PST 23 |
Dec 27 12:49:44 PM PST 23 |
14960511247 ps |
| T239 |
/workspace/coverage/default/1.sram_ctrl_bijection.1405934525 |
|
|
Dec 27 12:44:16 PM PST 23 |
Dec 27 01:07:13 PM PST 23 |
124986995244 ps |
| T5 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.3288978168 |
|
|
Dec 27 12:44:32 PM PST 23 |
Dec 27 12:47:03 PM PST 23 |
14238861622 ps |
| T240 |
/workspace/coverage/default/27.sram_ctrl_smoke.657710738 |
|
|
Dec 27 12:45:13 PM PST 23 |
Dec 27 12:45:48 PM PST 23 |
1403980631 ps |
| T241 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.3243742602 |
|
|
Dec 27 12:44:47 PM PST 23 |
Dec 27 12:45:26 PM PST 23 |
697844204 ps |
| T242 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3147713798 |
|
|
Dec 27 12:45:31 PM PST 23 |
Dec 27 12:49:51 PM PST 23 |
8718222200 ps |
| T80 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.483723805 |
|
|
Dec 27 12:45:35 PM PST 23 |
Dec 27 01:02:12 PM PST 23 |
31496881738 ps |
| T243 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.425760351 |
|
|
Dec 27 12:45:19 PM PST 23 |
Dec 27 12:49:27 PM PST 23 |
3945632695 ps |
| T116 |
/workspace/coverage/default/34.sram_ctrl_executable.3461816001 |
|
|
Dec 27 12:45:18 PM PST 23 |
Dec 27 12:56:58 PM PST 23 |
56488270222 ps |
| T244 |
/workspace/coverage/default/47.sram_ctrl_alert_test.1590816290 |
|
|
Dec 27 12:45:53 PM PST 23 |
Dec 27 12:46:02 PM PST 23 |
47831339 ps |
| T29 |
/workspace/coverage/default/35.sram_ctrl_regwen.1603481622 |
|
|
Dec 27 12:45:44 PM PST 23 |
Dec 27 01:06:30 PM PST 23 |
49524132595 ps |
| T245 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.2835883515 |
|
|
Dec 27 12:45:44 PM PST 23 |
Dec 27 12:55:07 PM PST 23 |
2596956252 ps |
| T246 |
/workspace/coverage/default/36.sram_ctrl_partial_access.909039458 |
|
|
Dec 27 12:45:27 PM PST 23 |
Dec 27 12:45:56 PM PST 23 |
2470687715 ps |
| T247 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.517560447 |
|
|
Dec 27 12:45:06 PM PST 23 |
Dec 27 01:54:53 PM PST 23 |
5970551044 ps |
| T248 |
/workspace/coverage/default/38.sram_ctrl_regwen.2327732835 |
|
|
Dec 27 12:45:14 PM PST 23 |
Dec 27 12:46:17 PM PST 23 |
4600685710 ps |
| T249 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.3862490165 |
|
|
Dec 27 12:45:17 PM PST 23 |
Dec 27 12:46:32 PM PST 23 |
948140598 ps |
| T250 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.700363818 |
|
|
Dec 27 12:45:04 PM PST 23 |
Dec 27 01:13:56 PM PST 23 |
16782415964 ps |
| T251 |
/workspace/coverage/default/26.sram_ctrl_partial_access.1493680936 |
|
|
Dec 27 12:44:48 PM PST 23 |
Dec 27 12:46:17 PM PST 23 |
511760531 ps |
| T252 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3876131884 |
|
|
Dec 27 12:45:39 PM PST 23 |
Dec 27 12:55:51 PM PST 23 |
9118071411 ps |
| T253 |
/workspace/coverage/default/22.sram_ctrl_alert_test.1052675243 |
|
|
Dec 27 12:44:57 PM PST 23 |
Dec 27 12:45:06 PM PST 23 |
33978136 ps |
| T254 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.2499373909 |
|
|
Dec 27 12:44:41 PM PST 23 |
Dec 27 12:47:16 PM PST 23 |
10553175437 ps |
| T129 |
/workspace/coverage/default/6.sram_ctrl_regwen.3232781854 |
|
|
Dec 27 12:44:33 PM PST 23 |
Dec 27 12:52:45 PM PST 23 |
13444149465 ps |
| T255 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.348849883 |
|
|
Dec 27 12:44:53 PM PST 23 |
Dec 27 12:47:29 PM PST 23 |
8951373528 ps |
| T256 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.762816943 |
|
|
Dec 27 12:44:46 PM PST 23 |
Dec 27 12:45:24 PM PST 23 |
1963373763 ps |
| T257 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.1757929879 |
|
|
Dec 27 12:44:16 PM PST 23 |
Dec 27 12:46:59 PM PST 23 |
15658044791 ps |
| T258 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.1963789072 |
|
|
Dec 27 12:44:19 PM PST 23 |
Dec 27 12:55:26 PM PST 23 |
23166057780 ps |
| T259 |
/workspace/coverage/default/18.sram_ctrl_regwen.1394604919 |
|
|
Dec 27 12:44:43 PM PST 23 |
Dec 27 12:55:15 PM PST 23 |
6550487696 ps |
| T260 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1737472657 |
|
|
Dec 27 12:45:26 PM PST 23 |
Dec 27 12:46:18 PM PST 23 |
2077335223 ps |
| T48 |
/workspace/coverage/default/28.sram_ctrl_executable.1617332382 |
|
|
Dec 27 12:44:46 PM PST 23 |
Dec 27 12:48:36 PM PST 23 |
8339087962 ps |
| T128 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.4224067273 |
|
|
Dec 27 12:45:30 PM PST 23 |
Dec 27 12:54:47 PM PST 23 |
245730601867 ps |
| T6 |
/workspace/coverage/default/30.sram_ctrl_stress_all.1294821191 |
|
|
Dec 27 12:44:48 PM PST 23 |
Dec 27 12:55:08 PM PST 23 |
84632765316 ps |
| T261 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.488200220 |
|
|
Dec 27 12:44:25 PM PST 23 |
Dec 27 12:45:49 PM PST 23 |
10621243236 ps |
| T262 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.3182159337 |
|
|
Dec 27 12:44:30 PM PST 23 |
Dec 27 12:45:06 PM PST 23 |
698781126 ps |
| T263 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.1688577229 |
|
|
Dec 27 12:45:04 PM PST 23 |
Dec 27 01:06:29 PM PST 23 |
11366010098 ps |
| T264 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.2327305255 |
|
|
Dec 27 12:44:49 PM PST 23 |
Dec 27 12:55:26 PM PST 23 |
20702690724 ps |
| T265 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3979199484 |
|
|
Dec 27 12:44:47 PM PST 23 |
Dec 27 12:45:00 PM PST 23 |
1399786143 ps |
| T266 |
/workspace/coverage/default/9.sram_ctrl_bijection.3214118575 |
|
|
Dec 27 12:44:35 PM PST 23 |
Dec 27 01:04:04 PM PST 23 |
768682979927 ps |
| T267 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.199599943 |
|
|
Dec 27 12:44:57 PM PST 23 |
Dec 27 12:49:20 PM PST 23 |
8053775941 ps |
| T268 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3234435449 |
|
|
Dec 27 12:44:23 PM PST 23 |
Dec 27 12:52:13 PM PST 23 |
6361662186 ps |
| T269 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.4212253362 |
|
|
Dec 27 12:44:48 PM PST 23 |
Dec 27 12:45:23 PM PST 23 |
1594895049 ps |
| T270 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1639296248 |
|
|
Dec 27 12:45:26 PM PST 23 |
Dec 27 12:45:40 PM PST 23 |
707597521 ps |
| T271 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.1013019973 |
|
|
Dec 27 12:45:18 PM PST 23 |
Dec 27 12:46:39 PM PST 23 |
3063326436 ps |
| T272 |
/workspace/coverage/default/23.sram_ctrl_alert_test.1085438487 |
|
|
Dec 27 12:45:05 PM PST 23 |
Dec 27 12:45:12 PM PST 23 |
42345518 ps |
| T273 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.3577945382 |
|
|
Dec 27 12:45:06 PM PST 23 |
Dec 27 12:47:34 PM PST 23 |
1187425124 ps |
| T30 |
/workspace/coverage/default/11.sram_ctrl_stress_all.185404048 |
|
|
Dec 27 12:44:19 PM PST 23 |
Dec 27 02:00:05 PM PST 23 |
878525127544 ps |
| T274 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.2583961787 |
|
|
Dec 27 12:45:07 PM PST 23 |
Dec 27 12:51:19 PM PST 23 |
4093161288 ps |
| T275 |
/workspace/coverage/default/36.sram_ctrl_alert_test.1316422126 |
|
|
Dec 27 12:45:22 PM PST 23 |
Dec 27 12:45:32 PM PST 23 |
16938853 ps |