Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	118273614	1			T1	9801		T2	49237		T3	111
triple_byte_access	2630787	1			T1	186		T2	973		T3	4
halfword_access	4049988	1			T1	295		T2	1488		T3	5
byte_access	5693064	1			T1	362		T2	2107		T3	2
zero_access	1762882	1			T1	113		T2	551		T10	875

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65608277

1

T1

7092

T2

27266

T3

60

auto[1]

66802058

1

T1

3665

T2

27090

T3

62

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	58430951	1			T1	6482		T2	24753		T3	52
auto[0]	triple_byte_access	1238575	1			T1	105		T2	465		T3	3
auto[0]	halfword_access	1963116	1			T1	189		T2	752		T3	3
auto[0]	byte_access	2909778	1			T1	235		T2	1038		T3	2
auto[0]	zero_access	1065857	1			T1	81		T2	258		T10	495
auto[1]	word_access	59842663	1			T1	3319		T2	24484		T3	59
auto[1]	triple_byte_access	1392212	1			T1	81		T2	508		T3	1
auto[1]	halfword_access	2086872	1			T1	106		T2	736		T3	2
auto[1]	byte_access	2783286	1			T1	127		T2	1069		T10	1568
auto[1]	zero_access	697025	1			T1	32		T2	293		T10	380