Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	309990258	1			T1	4348		T2	124630		T3	322120
instr_valid_dis	288289870	1			T1	4348		T2	124630		T3	322120
instr_en	15965835	1			T6	42518		T18	14738		T7	129506

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	6407519	1			T6	47612		T44	56294		T45	9332
sram_ifetch_valid_disable	290455103	1			T1	4348		T2	124630		T3	322120
sram_ifetch_enable	13127636	1			T6	20000		T7	205780		T44	94794

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	309990258	1			T1	4348		T2	124630		T3	322120
hw_debug_en_valid_off	287603275	1			T1	4348		T2	124630		T3	322120
hw_debug_en_on	14637668	1			T6	35508		T18	98		T7	307272

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	290455103	1			T1	4348		T2	124630		T3	322120
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	279458614	1			T1	4348		T2	124630		T3	322120
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8694426	1			T6	10414		T18	14738		T7	27370
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	2767646	1			T44	20456		T45	9332		T28	70452
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1141644	1			T44	20456		T28	70452		T130	9838
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1032552	1			T45	9332		T109	13302		T126	11514
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	2216904	1			T6	15508		T28	21750		T127	28274
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	915786	1			T6	15508		T28	21750		T127	28274
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	886502	1			T109	18086		T132	15970		T137	195226
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7654148	1			T18	98		T7	264918		T44	81040
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2312026	1			T7	246836		T44	81040		T28	68602
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4428230	1			T18	98		T7	18082		T45	52966

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	4853700	1			T7	102136		T45	201048		T127	19226
lc_exec_en	4766616	1			T6	20000		T7	42354		T44	8230
valid_exec_dis	286399209	1			T1	4348		T2	124630		T3	322120
invalid_exec_dis	19535155	1			T6	67612		T7	205780		T44	151088