| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.509014845 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2234491142 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.285842736 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4167759442 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3269718302 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4120831145 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2127395635 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.522489648 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1385893839 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3356717420 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2256607454 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2076854166 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.701472062 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3239530245 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3393566972 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2030676828 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1031831967 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1549660097 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.649034705 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2767917918 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3785382488 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.129045338 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3786959949 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2180145492 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3652478695 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.412454416 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.799181033 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1094705388 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.848437820 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.252796584 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2023458192 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.633459085 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2822043621 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2066850733 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2517677269 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1016354524 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3187008596 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.499288953 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.449735324 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1233648944 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.497130470 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2796038735 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.121270921 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.183566485 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4091182025 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4230664930 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3226835580 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2661123375 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2359882564 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1020348451 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3372322918 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1927125440 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2565509140 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1773362323 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3267353679 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.176359358 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2357066039 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2737944466 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3795864781 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3668047758 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2279113543 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1117034420 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1037135334 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3692353364 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2281992478 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.362787303 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.308526616 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3328512450 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1833923425 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1919713113 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1391287503 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1127274449 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1353667359 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3597784699 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3270075034 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4044734494 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2445875922 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1311980125 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3275797881 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4105747192 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.905127262 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2635458641 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.429207131 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2143552437 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.679812184 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3995764353 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3629029925 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2029345734 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1107346269 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2335320115 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.917211389 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.271039936 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4176758253 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1492525735 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1347971952 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3202539249 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3419415800 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1865654508 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1252463734 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2607181082 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1108635342 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4046241117 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2298942759 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1957987955 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3968215916 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2857381688 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4117254875 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.647273600 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.323209924 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2769070927 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2298741193 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.171169628 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2848518163 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.168348502 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2786942368 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.135363451 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3267000656 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.953800623 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.120411807 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1994060351 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.337145015 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4203153331 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3578420049 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2151724741 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3553611370 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.864273588 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3123418553 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3557851366 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2195376670 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.2522785056 |
| /workspace/coverage/default/0.sram_ctrl_bijection.884579827 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.2351440756 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.3809513028 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2803743503 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.2432579483 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.3620673127 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.418014868 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1523027849 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.4000500283 |
| /workspace/coverage/default/0.sram_ctrl_smoke.4252374967 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.1198595413 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.290630308 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.3018208023 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3366778748 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.616170047 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.819701896 |
| /workspace/coverage/default/1.sram_ctrl_bijection.2860954042 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.1631142127 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.1824946883 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1612354065 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.3697312811 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.2055996800 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.2680693865 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2715950463 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.1235651444 |
| /workspace/coverage/default/1.sram_ctrl_regwen.3930050819 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.2439199723 |
| /workspace/coverage/default/1.sram_ctrl_smoke.3131758997 |
| /workspace/coverage/default/1.sram_ctrl_stress_all.4036945868 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2417999016 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2215243522 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2320296613 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2916785734 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.2448120277 |
| /workspace/coverage/default/10.sram_ctrl_bijection.3889024882 |
| /workspace/coverage/default/10.sram_ctrl_executable.3008663931 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.3348403066 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.2203958932 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.682099802 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.459352353 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.1825223130 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.4008164224 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2715848252 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.1013437857 |
| /workspace/coverage/default/10.sram_ctrl_regwen.1797225906 |
| /workspace/coverage/default/10.sram_ctrl_smoke.1896221245 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.582885851 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.2994912856 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3512071808 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.1413709269 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.2575512789 |
| /workspace/coverage/default/11.sram_ctrl_bijection.2989949246 |
| /workspace/coverage/default/11.sram_ctrl_executable.557981286 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.474199679 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.1070842206 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.983339544 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.661671051 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.2936083036 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.811625315 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.452882274 |
| /workspace/coverage/default/11.sram_ctrl_regwen.423706257 |
| /workspace/coverage/default/11.sram_ctrl_smoke.2632947936 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.760124735 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1192948284 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.2977948078 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.827220544 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.2201512385 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.3649619625 |
| /workspace/coverage/default/12.sram_ctrl_bijection.208138537 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.2595880797 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.1030990369 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2109987706 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.2873162326 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.2416235090 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.2715254794 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2444474239 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.1361510230 |
| /workspace/coverage/default/12.sram_ctrl_regwen.2470969131 |
| /workspace/coverage/default/12.sram_ctrl_smoke.1171824110 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.3345118045 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2617920653 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2644049939 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.974883562 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.2619072635 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.4276893576 |
| /workspace/coverage/default/13.sram_ctrl_bijection.2063658878 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.3221591869 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1818978579 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.997839759 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.1674903013 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.2608548623 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2027362446 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.4254601354 |
| /workspace/coverage/default/13.sram_ctrl_regwen.407431141 |
| /workspace/coverage/default/13.sram_ctrl_smoke.1844523884 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3189074501 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.1640721417 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.353850758 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2303182617 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.2510031378 |
| /workspace/coverage/default/14.sram_ctrl_bijection.2940596260 |
| /workspace/coverage/default/14.sram_ctrl_executable.822879347 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.4058780005 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.2826423491 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.1166603457 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.3095688192 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.4117613060 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.909341412 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3212760920 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.2155476051 |
| /workspace/coverage/default/14.sram_ctrl_regwen.3224426547 |
| /workspace/coverage/default/14.sram_ctrl_smoke.727059951 |
| /workspace/coverage/default/14.sram_ctrl_stress_all.1579304008 |
| /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2902492025 |
| /workspace/coverage/default/14.sram_ctrl_stress_pipeline.4128973575 |
| /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2229743834 |
| /workspace/coverage/default/15.sram_ctrl_access_during_key_req.3809176905 |
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| /workspace/coverage/default/44.sram_ctrl_stress_all.4236770805 |
| /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1708459921 |
| /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3613658259 |
| /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2548685395 |
| /workspace/coverage/default/45.sram_ctrl_access_during_key_req.2533317367 |
| /workspace/coverage/default/45.sram_ctrl_alert_test.567944776 |
| /workspace/coverage/default/45.sram_ctrl_bijection.3900560508 |
| /workspace/coverage/default/45.sram_ctrl_executable.816180875 |
| /workspace/coverage/default/45.sram_ctrl_lc_escalation.2795901030 |
| /workspace/coverage/default/45.sram_ctrl_max_throughput.2599133709 |
| /workspace/coverage/default/45.sram_ctrl_mem_partial_access.3938028936 |
| /workspace/coverage/default/45.sram_ctrl_mem_walk.3369584616 |
| /workspace/coverage/default/45.sram_ctrl_multiple_keys.4224910395 |
| /workspace/coverage/default/45.sram_ctrl_partial_access.4134317372 |
| /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1984848822 |
| /workspace/coverage/default/45.sram_ctrl_ram_cfg.2640987096 |
| /workspace/coverage/default/45.sram_ctrl_regwen.439659625 |
| /workspace/coverage/default/45.sram_ctrl_smoke.1515977267 |
| /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3641807694 |
| /workspace/coverage/default/45.sram_ctrl_stress_pipeline.129071488 |
| /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2514803670 |
| /workspace/coverage/default/46.sram_ctrl_access_during_key_req.3391342531 |
| /workspace/coverage/default/46.sram_ctrl_alert_test.3917543214 |
| /workspace/coverage/default/46.sram_ctrl_bijection.3798980020 |
| /workspace/coverage/default/46.sram_ctrl_lc_escalation.1178939928 |
| /workspace/coverage/default/46.sram_ctrl_max_throughput.497532274 |
| /workspace/coverage/default/46.sram_ctrl_mem_partial_access.2306340413 |
| /workspace/coverage/default/46.sram_ctrl_mem_walk.1218764762 |
| /workspace/coverage/default/46.sram_ctrl_multiple_keys.2157045265 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.1641263213 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1956961173 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.3122286212 |
| /workspace/coverage/default/46.sram_ctrl_regwen.821270018 |
| /workspace/coverage/default/46.sram_ctrl_smoke.2899043071 |
| /workspace/coverage/default/46.sram_ctrl_stress_all.1267502698 |
| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3670457808 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1864955986 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2604339198 |
| /workspace/coverage/default/47.sram_ctrl_access_during_key_req.533387805 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.425560971 |
| /workspace/coverage/default/47.sram_ctrl_bijection.2167208562 |
| /workspace/coverage/default/47.sram_ctrl_executable.3349627453 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.3909336537 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.3503116098 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3488994473 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.812961872 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.3184052239 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.738824633 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.644414331 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.4114073089 |
| /workspace/coverage/default/47.sram_ctrl_regwen.687049416 |
| /workspace/coverage/default/47.sram_ctrl_smoke.3464282795 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3135852101 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2931423302 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.901589572 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1833701955 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.2428520832 |
| /workspace/coverage/default/48.sram_ctrl_bijection.246837763 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.4187725372 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.878683623 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3421589072 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.4238603079 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.1946759790 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.2248494187 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1024072409 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.2866494768 |
| /workspace/coverage/default/48.sram_ctrl_regwen.1932549808 |
| /workspace/coverage/default/48.sram_ctrl_smoke.3387247304 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2347427857 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.941733837 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.792656379 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2138802398 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.70856187 |
| /workspace/coverage/default/49.sram_ctrl_bijection.234615957 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.4138635303 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.3833223201 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.4097620835 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.38551576 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.3548371181 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.11471344 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.866330097 |
| /workspace/coverage/default/49.sram_ctrl_regwen.3369913912 |
| /workspace/coverage/default/49.sram_ctrl_smoke.752608168 |
| /workspace/coverage/default/49.sram_ctrl_stress_all.3233108731 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.362360899 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2709946866 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3650508472 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.4005448888 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.781021549 |
| /workspace/coverage/default/5.sram_ctrl_bijection.721818719 |
| /workspace/coverage/default/5.sram_ctrl_executable.881610133 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.3239139486 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3598799205 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.502800679 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.1432873574 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.1979890937 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3004517733 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.1548362380 |
| /workspace/coverage/default/5.sram_ctrl_regwen.76016233 |
| /workspace/coverage/default/5.sram_ctrl_smoke.1234773967 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.2770977118 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3872675701 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.2875821309 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3609535518 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.1549443025 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.2721083437 |
| /workspace/coverage/default/6.sram_ctrl_bijection.4107724138 |
| /workspace/coverage/default/6.sram_ctrl_executable.944786660 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.880060458 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.2620424061 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.882326926 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.3405331073 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.1927549725 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.3634451647 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2558772781 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.532844586 |
| /workspace/coverage/default/6.sram_ctrl_regwen.1845544618 |
| /workspace/coverage/default/6.sram_ctrl_smoke.376350278 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.1647650738 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3461560152 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2455634254 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3337277544 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.69428566 |
| /workspace/coverage/default/7.sram_ctrl_bijection.2087420109 |
| /workspace/coverage/default/7.sram_ctrl_executable.663556590 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.1783912423 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.628496441 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1689286413 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.3262204853 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.4177168258 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.1468218505 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1488541325 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.173705285 |
| /workspace/coverage/default/7.sram_ctrl_regwen.829767869 |
| /workspace/coverage/default/7.sram_ctrl_smoke.3456007949 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.3787119658 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.206905465 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.570357788 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1405426644 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2707324713 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.1858280879 |
| /workspace/coverage/default/8.sram_ctrl_bijection.2027793270 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.370922849 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.2637862703 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1258762087 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.1023484422 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.67541070 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.3810751218 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2161812393 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.1944158471 |
| /workspace/coverage/default/8.sram_ctrl_regwen.1094465279 |
| /workspace/coverage/default/8.sram_ctrl_smoke.3983731847 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3595636594 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.864021073 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2847275003 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.860300124 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.1576339274 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.411487541 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.2133971847 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.3217372285 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.2129753028 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.3955041499 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.2214610330 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.4067384044 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.3495681310 |
| /workspace/coverage/default/9.sram_ctrl_regwen.712536593 |
| /workspace/coverage/default/9.sram_ctrl_smoke.920187762 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.565888547 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1105028953 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3826816841 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.2785668258 |
|
|
Jan 03 01:40:16 PM PST 24 |
Jan 03 01:43:15 PM PST 24 |
6074552499 ps |
| T2 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.2803743503 |
|
|
Jan 03 01:40:02 PM PST 24 |
Jan 03 01:42:48 PM PST 24 |
9943780123 ps |
| T3 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.1674903013 |
|
|
Jan 03 01:42:08 PM PST 24 |
Jan 03 01:56:30 PM PST 24 |
36892399986 ps |
| T4 |
/workspace/coverage/default/28.sram_ctrl_bijection.2099811147 |
|
|
Jan 03 01:45:27 PM PST 24 |
Jan 03 02:08:41 PM PST 24 |
331532291621 ps |
| T5 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3609535518 |
|
|
Jan 03 01:40:48 PM PST 24 |
Jan 03 01:42:53 PM PST 24 |
3208484092 ps |
| T6 |
/workspace/coverage/default/38.sram_ctrl_stress_all.283890192 |
|
|
Jan 03 01:45:25 PM PST 24 |
Jan 03 04:06:50 PM PST 24 |
224436970696 ps |
| T8 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.3952161819 |
|
|
Jan 03 01:42:51 PM PST 24 |
Jan 03 01:42:59 PM PST 24 |
1351868427 ps |
| T9 |
/workspace/coverage/default/13.sram_ctrl_bijection.2063658878 |
|
|
Jan 03 01:42:07 PM PST 24 |
Jan 03 02:26:31 PM PST 24 |
170634111854 ps |
| T10 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3826816841 |
|
|
Jan 03 01:40:48 PM PST 24 |
Jan 03 01:43:44 PM PST 24 |
827179749 ps |
| T11 |
/workspace/coverage/default/44.sram_ctrl_alert_test.3894479284 |
|
|
Jan 03 01:46:30 PM PST 24 |
Jan 03 01:46:37 PM PST 24 |
15270812 ps |
| T13 |
/workspace/coverage/default/16.sram_ctrl_smoke.1991866308 |
|
|
Jan 03 01:42:25 PM PST 24 |
Jan 03 01:44:18 PM PST 24 |
3036642882 ps |
| T14 |
/workspace/coverage/default/5.sram_ctrl_partial_access.1979890937 |
|
|
Jan 03 01:41:10 PM PST 24 |
Jan 03 01:41:39 PM PST 24 |
1380117375 ps |
| T30 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.442273535 |
|
|
Jan 03 01:40:50 PM PST 24 |
Jan 03 01:41:03 PM PST 24 |
346192528 ps |
| T15 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1105028953 |
|
|
Jan 03 01:40:46 PM PST 24 |
Jan 03 01:47:36 PM PST 24 |
12037791688 ps |
| T17 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3506588183 |
|
|
Jan 03 01:43:35 PM PST 24 |
Jan 03 02:49:42 PM PST 24 |
887676114 ps |
| T16 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.1818655438 |
|
|
Jan 03 01:45:00 PM PST 24 |
Jan 03 01:48:44 PM PST 24 |
34778846755 ps |
| T12 |
/workspace/coverage/default/20.sram_ctrl_stress_all.2089887861 |
|
|
Jan 03 01:42:32 PM PST 24 |
Jan 03 02:24:02 PM PST 24 |
382632526419 ps |
| T18 |
/workspace/coverage/default/24.sram_ctrl_regwen.2392196641 |
|
|
Jan 03 01:43:34 PM PST 24 |
Jan 03 01:44:38 PM PST 24 |
2970205141 ps |
| T58 |
/workspace/coverage/default/16.sram_ctrl_bijection.2832590303 |
|
|
Jan 03 01:42:31 PM PST 24 |
Jan 03 02:00:55 PM PST 24 |
192608237613 ps |
| T59 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.4219671036 |
|
|
Jan 03 01:43:39 PM PST 24 |
Jan 03 01:45:27 PM PST 24 |
5047445538 ps |
| T7 |
/workspace/coverage/default/3.sram_ctrl_stress_all.4102315474 |
|
|
Jan 03 01:40:20 PM PST 24 |
Jan 03 02:48:37 PM PST 24 |
937048231170 ps |
| T70 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.4143158245 |
|
|
Jan 03 01:42:37 PM PST 24 |
Jan 03 01:45:52 PM PST 24 |
14105437750 ps |
| T34 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3495681310 |
|
|
Jan 03 01:41:14 PM PST 24 |
Jan 03 01:41:24 PM PST 24 |
1468698697 ps |
| T71 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3938028936 |
|
|
Jan 03 01:46:33 PM PST 24 |
Jan 03 01:48:54 PM PST 24 |
3171295275 ps |
| T139 |
/workspace/coverage/default/10.sram_ctrl_smoke.1896221245 |
|
|
Jan 03 01:41:52 PM PST 24 |
Jan 03 01:42:13 PM PST 24 |
845890566 ps |
| T44 |
/workspace/coverage/default/39.sram_ctrl_regwen.1798747032 |
|
|
Jan 03 01:46:28 PM PST 24 |
Jan 03 01:58:23 PM PST 24 |
12971072917 ps |
| T103 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3018208023 |
|
|
Jan 03 01:39:50 PM PST 24 |
Jan 03 01:47:55 PM PST 24 |
6329616290 ps |
| T45 |
/workspace/coverage/default/49.sram_ctrl_regwen.3369913912 |
|
|
Jan 03 01:46:59 PM PST 24 |
Jan 03 02:00:41 PM PST 24 |
71648977405 ps |
| T140 |
/workspace/coverage/default/42.sram_ctrl_partial_access.1793365052 |
|
|
Jan 03 01:46:34 PM PST 24 |
Jan 03 01:47:09 PM PST 24 |
1051698635 ps |
| T141 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.1681887155 |
|
|
Jan 03 01:45:25 PM PST 24 |
Jan 03 01:45:42 PM PST 24 |
1416068145 ps |
| T142 |
/workspace/coverage/default/20.sram_ctrl_smoke.1130812157 |
|
|
Jan 03 01:43:29 PM PST 24 |
Jan 03 01:43:52 PM PST 24 |
1924842052 ps |
| T19 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.376413455 |
|
|
Jan 03 01:41:14 PM PST 24 |
Jan 03 01:59:36 PM PST 24 |
8596698532 ps |
| T28 |
/workspace/coverage/default/4.sram_ctrl_regwen.1424406378 |
|
|
Jan 03 01:40:33 PM PST 24 |
Jan 03 01:53:56 PM PST 24 |
28416782397 ps |
| T143 |
/workspace/coverage/default/46.sram_ctrl_bijection.3798980020 |
|
|
Jan 03 01:46:33 PM PST 24 |
Jan 03 02:16:58 PM PST 24 |
27585275258 ps |
| T27 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.1379348219 |
|
|
Jan 03 01:44:58 PM PST 24 |
Jan 03 01:49:47 PM PST 24 |
11295963189 ps |
| T104 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2444474239 |
|
|
Jan 03 01:41:59 PM PST 24 |
Jan 03 01:48:01 PM PST 24 |
62073758720 ps |
| T72 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1612354065 |
|
|
Jan 03 01:39:53 PM PST 24 |
Jan 03 01:42:31 PM PST 24 |
18051411557 ps |
| T144 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.2873162326 |
|
|
Jan 03 01:42:28 PM PST 24 |
Jan 03 01:46:40 PM PST 24 |
4109784070 ps |
| T127 |
/workspace/coverage/default/32.sram_ctrl_stress_all.2757860093 |
|
|
Jan 03 01:45:21 PM PST 24 |
Jan 03 03:35:26 PM PST 24 |
728126102627 ps |
| T20 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.586816740 |
|
|
Jan 03 01:46:35 PM PST 24 |
Jan 03 01:52:47 PM PST 24 |
16043125224 ps |
| T145 |
/workspace/coverage/default/28.sram_ctrl_partial_access.1257930195 |
|
|
Jan 03 01:45:27 PM PST 24 |
Jan 03 01:46:10 PM PST 24 |
2681101901 ps |
| T146 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1298189757 |
|
|
Jan 03 01:46:33 PM PST 24 |
Jan 03 01:47:32 PM PST 24 |
1149629869 ps |
| T31 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2238628524 |
|
|
Jan 03 01:46:31 PM PST 24 |
Jan 03 02:28:22 PM PST 24 |
670683898 ps |
| T32 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1480357493 |
|
|
Jan 03 01:45:00 PM PST 24 |
Jan 03 02:25:04 PM PST 24 |
2951868420 ps |
| T60 |
/workspace/coverage/default/14.sram_ctrl_smoke.727059951 |
|
|
Jan 03 01:41:14 PM PST 24 |
Jan 03 01:41:40 PM PST 24 |
1005560296 ps |
| T61 |
/workspace/coverage/default/26.sram_ctrl_bijection.1230806167 |
|
|
Jan 03 01:43:45 PM PST 24 |
Jan 03 02:07:32 PM PST 24 |
239939950362 ps |
| T105 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2875821309 |
|
|
Jan 03 01:41:12 PM PST 24 |
Jan 03 01:48:51 PM PST 24 |
5793807499 ps |
| T106 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1242281983 |
|
|
Jan 03 01:46:28 PM PST 24 |
Jan 03 01:54:17 PM PST 24 |
70269842763 ps |
| T46 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1558137134 |
|
|
Jan 03 01:45:26 PM PST 24 |
Jan 03 02:21:36 PM PST 24 |
905837704 ps |
| T109 |
/workspace/coverage/default/5.sram_ctrl_stress_all.2770977118 |
|
|
Jan 03 01:40:54 PM PST 24 |
Jan 03 03:27:09 PM PST 24 |
1136615332978 ps |
| T110 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2331075256 |
|
|
Jan 03 01:45:01 PM PST 24 |
Jan 03 01:45:36 PM PST 24 |
3863663377 ps |
| T22 |
/workspace/coverage/default/35.sram_ctrl_alert_test.2994067317 |
|
|
Jan 03 01:45:26 PM PST 24 |
Jan 03 01:45:37 PM PST 24 |
38607196 ps |
| T33 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2143552437 |
|
|
Jan 03 01:01:28 PM PST 24 |
Jan 03 01:02:38 PM PST 24 |
14495096 ps |
| T63 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1007095577 |
|
|
Jan 03 01:01:18 PM PST 24 |
Jan 03 01:04:14 PM PST 24 |
7070349140 ps |
| T50 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.252796584 |
|
|
Jan 03 01:01:28 PM PST 24 |
Jan 03 01:02:52 PM PST 24 |
363258980 ps |
| T101 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3275797881 |
|
|
Jan 03 01:01:22 PM PST 24 |
Jan 03 01:02:29 PM PST 24 |
43375888 ps |
| T64 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1492525735 |
|
|
Jan 03 01:01:28 PM PST 24 |
Jan 03 01:02:41 PM PST 24 |
150205071 ps |
| T65 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4105747192 |
|
|
Jan 03 01:01:20 PM PST 24 |
Jan 03 01:04:48 PM PST 24 |
7471622119 ps |
| T51 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1016354524 |
|
|
Jan 03 01:01:18 PM PST 24 |
Jan 03 01:02:31 PM PST 24 |
663789768 ps |
| T52 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2195376670 |
|
|
Jan 03 01:01:17 PM PST 24 |
Jan 03 01:02:29 PM PST 24 |
2321969122 ps |
| T102 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.362787303 |
|
|
Jan 03 01:01:29 PM PST 24 |
Jan 03 01:02:41 PM PST 24 |
23029153 ps |
| T66 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4203153331 |
|
|
Jan 03 01:01:14 PM PST 24 |
Jan 03 01:02:21 PM PST 24 |
24241296 ps |
| T53 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1311980125 |
|
|
Jan 03 01:01:29 PM PST 24 |
Jan 03 01:02:52 PM PST 24 |
352113870 ps |
| T67 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2786942368 |
|
|
Jan 03 01:01:25 PM PST 24 |
Jan 03 01:02:35 PM PST 24 |
29795954 ps |
| T68 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3995764353 |
|
|
Jan 03 01:01:22 PM PST 24 |
Jan 03 01:02:29 PM PST 24 |
37931575 ps |
| T54 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2607181082 |
|
|
Jan 03 01:01:25 PM PST 24 |
Jan 03 01:02:36 PM PST 24 |
223765872 ps |
| T69 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3187008596 |
|
|
Jan 03 01:01:18 PM PST 24 |
Jan 03 01:02:25 PM PST 24 |
49901110 ps |
| T55 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4046241117 |
|
|
Jan 03 01:01:25 PM PST 24 |
Jan 03 01:02:47 PM PST 24 |
1365632832 ps |
| T73 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2796038735 |
|
|
Jan 03 01:01:34 PM PST 24 |
Jan 03 01:02:47 PM PST 24 |
44268860 ps |
| T47 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3397768680 |
|
|
Jan 03 01:01:27 PM PST 24 |
Jan 03 01:02:39 PM PST 24 |
899819530 ps |
| T74 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.337145015 |
|
|
Jan 03 01:01:26 PM PST 24 |
Jan 03 01:03:29 PM PST 24 |
3857728193 ps |
| T56 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.917211389 |
|
|
Jan 03 01:01:19 PM PST 24 |
Jan 03 01:02:26 PM PST 24 |
79160308 ps |
| T76 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1919713113 |
|
|
Jan 03 01:01:35 PM PST 24 |
Jan 03 01:02:48 PM PST 24 |
21783484 ps |
| T77 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2661123375 |
|
|
Jan 03 01:01:27 PM PST 24 |
Jan 03 01:02:38 PM PST 24 |
21042680 ps |
| T57 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.953800623 |
|
|
Jan 03 01:01:27 PM PST 24 |
Jan 03 01:02:40 PM PST 24 |
33917744 ps |
| T78 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3629029925 |
|
|
Jan 03 01:01:30 PM PST 24 |
Jan 03 01:02:53 PM PST 24 |
354223776 ps |
| T62 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4091182025 |
|
|
Jan 03 01:01:24 PM PST 24 |
Jan 03 01:02:36 PM PST 24 |
80422056 ps |
| T75 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3123418553 |
|
|
Jan 03 01:01:21 PM PST 24 |
Jan 03 01:07:02 PM PST 24 |
14356613420 ps |
| T90 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.701472062 |
|
|
Jan 03 01:01:25 PM PST 24 |
Jan 03 01:02:47 PM PST 24 |
5670656641 ps |
| T95 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2279113543 |
|
|
Jan 03 01:01:33 PM PST 24 |
Jan 03 01:02:48 PM PST 24 |
175900858 ps |
| T147 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3393566972 |
|
|
Jan 03 01:01:13 PM PST 24 |
Jan 03 01:02:19 PM PST 24 |
40767575 ps |
| T148 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3785382488 |
|
|
Jan 03 01:01:26 PM PST 24 |
Jan 03 01:02:37 PM PST 24 |
66741775 ps |
| T48 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4117254875 |
|
|
Jan 03 01:01:29 PM PST 24 |
Jan 03 01:02:42 PM PST 24 |
247436377 ps |
| T149 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2445875922 |
|
|
Jan 03 01:01:24 PM PST 24 |
Jan 03 01:02:32 PM PST 24 |
43212424 ps |
| T150 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2335320115 |
|
|
Jan 03 01:01:34 PM PST 24 |
Jan 03 01:02:47 PM PST 24 |
32842380 ps |
| T151 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3239530245 |
|
|
Jan 03 01:01:20 PM PST 24 |
Jan 03 01:02:27 PM PST 24 |
17272836 ps |
| T152 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.308526616 |
|
|
Jan 03 01:01:29 PM PST 24 |
Jan 03 01:02:42 PM PST 24 |
59380290 ps |
| T153 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2127395635 |
|
|
Jan 03 01:01:13 PM PST 24 |
Jan 03 01:02:20 PM PST 24 |
28509969 ps |
| T79 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2281992478 |
|
|
Jan 03 01:01:29 PM PST 24 |
Jan 03 01:03:32 PM PST 24 |
3766385115 ps |
| T49 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3597784699 |
|
|
Jan 03 01:01:43 PM PST 24 |
Jan 03 01:02:58 PM PST 24 |
1320192434 ps |
| T96 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3795864781 |
|
|
Jan 03 01:01:29 PM PST 24 |
Jan 03 01:04:41 PM PST 24 |
26088499845 ps |
| T97 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3202539249 |
|
|
Jan 03 01:01:26 PM PST 24 |
Jan 03 01:02:40 PM PST 24 |
1352150800 ps |
| T154 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2635458641 |
|
|
Jan 03 01:01:17 PM PST 24 |
Jan 03 01:02:26 PM PST 24 |
63512268 ps |
| T115 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.429207131 |
|
|
Jan 03 01:01:27 PM PST 24 |
Jan 03 01:02:39 PM PST 24 |
591166944 ps |
| T155 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2030676828 |
|
|
Jan 03 01:01:28 PM PST 24 |
Jan 03 01:02:39 PM PST 24 |
57648478 ps |
| T80 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1391287503 |
|
|
Jan 03 01:01:15 PM PST 24 |
Jan 03 01:04:08 PM PST 24 |
117472386042 ps |
| T156 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1252463734 |
|
|
Jan 03 01:01:15 PM PST 24 |
Jan 03 01:02:27 PM PST 24 |
48657420 ps |
| T157 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3557851366 |
|
|
Jan 03 01:01:16 PM PST 24 |
Jan 03 01:02:23 PM PST 24 |
16410987 ps |
| T158 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2822043621 |
|
|
Jan 03 01:01:22 PM PST 24 |
Jan 03 01:02:29 PM PST 24 |
41951424 ps |
| T113 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3317465098 |
|
|
Jan 03 01:01:18 PM PST 24 |
Jan 03 01:02:26 PM PST 24 |
248701257 ps |
| T159 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3968215916 |
|
|
Jan 03 01:01:16 PM PST 24 |
Jan 03 01:02:23 PM PST 24 |
21280775 ps |
| T81 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.135363451 |
|
|
Jan 03 01:01:25 PM PST 24 |
Jan 03 01:03:31 PM PST 24 |
15409254628 ps |
| T160 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.679812184 |
|
|
Jan 03 01:01:21 PM PST 24 |
Jan 03 01:02:29 PM PST 24 |
367380113 ps |
| T161 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.799181033 |
|
|
Jan 03 01:01:22 PM PST 24 |
Jan 03 01:02:30 PM PST 24 |
29754612 ps |
| T162 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.120411807 |
|
|
Jan 03 01:01:19 PM PST 24 |
Jan 03 01:02:31 PM PST 24 |
1370298855 ps |
| T163 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1549660097 |
|
|
Jan 03 01:01:18 PM PST 24 |
Jan 03 01:02:29 PM PST 24 |
1762969419 ps |
| T164 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3356717420 |
|
|
Jan 03 01:01:19 PM PST 24 |
Jan 03 01:02:26 PM PST 24 |
21800344 ps |
| T165 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.323209924 |
|
|
Jan 03 01:01:30 PM PST 24 |
Jan 03 01:02:41 PM PST 24 |
20849522 ps |
| T114 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2151724741 |
|
|
Jan 03 01:01:16 PM PST 24 |
Jan 03 01:02:23 PM PST 24 |
328140687 ps |
| T166 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2066850733 |
|
|
Jan 03 01:01:17 PM PST 24 |
Jan 03 01:02:27 PM PST 24 |
73262266 ps |
| T121 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1385893839 |
|
|
Jan 03 01:01:20 PM PST 24 |
Jan 03 01:02:29 PM PST 24 |
136653464 ps |
| T167 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.412454416 |
|
|
Jan 03 01:01:14 PM PST 24 |
Jan 03 01:04:23 PM PST 24 |
27221823319 ps |
| T168 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2029345734 |
|
|
Jan 03 01:01:19 PM PST 24 |
Jan 03 01:02:27 PM PST 24 |
45919646 ps |
| T169 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.905127262 |
|
|
Jan 03 01:01:26 PM PST 24 |
Jan 03 01:02:35 PM PST 24 |
45315820 ps |
| T170 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4044734494 |
|
|
Jan 03 01:01:27 PM PST 24 |
Jan 03 01:02:39 PM PST 24 |
208410252 ps |
| T82 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2359882564 |
|
|
Jan 03 01:01:27 PM PST 24 |
Jan 03 01:03:27 PM PST 24 |
7368603732 ps |
| T171 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2857381688 |
|
|
Jan 03 01:01:26 PM PST 24 |
Jan 03 01:02:38 PM PST 24 |
30881722 ps |
| T172 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.449735324 |
|
|
Jan 03 01:01:34 PM PST 24 |
Jan 03 01:02:47 PM PST 24 |
117734530 ps |
| T173 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.522489648 |
|
|
Jan 03 01:01:14 PM PST 24 |
Jan 03 01:02:22 PM PST 24 |
63605527 ps |
| T174 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3668047758 |
|
|
Jan 03 01:01:24 PM PST 24 |
Jan 03 01:02:32 PM PST 24 |
31112659 ps |
| T175 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.647273600 |
|
|
Jan 03 01:01:29 PM PST 24 |
Jan 03 01:02:45 PM PST 24 |
1800057928 ps |
| T176 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1031831967 |
|
|
Jan 03 01:01:16 PM PST 24 |
Jan 03 01:02:25 PM PST 24 |
206551256 ps |
| T177 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3267353679 |
|
|
Jan 03 01:01:27 PM PST 24 |
Jan 03 01:02:38 PM PST 24 |
136264832 ps |
| T178 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.183566485 |
|
|
Jan 03 01:01:13 PM PST 24 |
Jan 03 01:02:19 PM PST 24 |
27592781 ps |
| T179 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2023458192 |
|
|
Jan 03 01:01:23 PM PST 24 |
Jan 03 01:02:31 PM PST 24 |
43242747 ps |
| T180 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2565509140 |
|
|
Jan 03 01:01:45 PM PST 24 |
Jan 03 01:02:58 PM PST 24 |
70358414 ps |
| T181 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2298942759 |
|
|
Jan 03 01:01:20 PM PST 24 |
Jan 03 01:02:27 PM PST 24 |
31159768 ps |
| T122 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1108635342 |
|
|
Jan 03 01:01:25 PM PST 24 |
Jan 03 01:02:36 PM PST 24 |
158536793 ps |
| T118 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4230664930 |
|
|
Jan 03 01:01:25 PM PST 24 |
Jan 03 01:02:36 PM PST 24 |
161781671 ps |
| T182 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.129045338 |
|
|
Jan 03 01:01:22 PM PST 24 |
Jan 03 01:02:33 PM PST 24 |
455286571 ps |
| T183 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.497130470 |
|
|
Jan 03 01:01:28 PM PST 24 |
Jan 03 01:02:42 PM PST 24 |
1367999297 ps |
| T184 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1927125440 |
|
|
Jan 03 01:01:28 PM PST 24 |
Jan 03 01:02:50 PM PST 24 |
702486560 ps |
| T83 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1107346269 |
|
|
Jan 03 01:01:25 PM PST 24 |
Jan 03 01:07:21 PM PST 24 |
32008526703 ps |
| T185 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2180145492 |
|
|
Jan 03 01:01:26 PM PST 24 |
Jan 03 01:02:47 PM PST 24 |
358348426 ps |
| T186 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3267000656 |
|
|
Jan 03 01:01:16 PM PST 24 |
Jan 03 01:02:22 PM PST 24 |
59506089 ps |
| T187 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2076854166 |
|
|
Jan 03 01:01:13 PM PST 24 |
Jan 03 01:02:19 PM PST 24 |
15530188 ps |
| T188 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1127274449 |
|
|
Jan 03 01:01:40 PM PST 24 |
Jan 03 01:02:53 PM PST 24 |
46131920 ps |
| T119 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3786959949 |
|
|
Jan 03 01:01:34 PM PST 24 |
Jan 03 01:02:47 PM PST 24 |
392399040 ps |
| T98 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.499288953 |
|
|
Jan 03 01:01:22 PM PST 24 |
Jan 03 01:04:19 PM PST 24 |
26111237070 ps |
| T189 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.168348502 |
|
|
Jan 03 01:01:15 PM PST 24 |
Jan 03 01:02:26 PM PST 24 |
512120091 ps |
| T190 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.171169628 |
|
|
Jan 03 01:01:33 PM PST 24 |
Jan 03 01:02:48 PM PST 24 |
72417325 ps |
| T191 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2357066039 |
|
|
Jan 03 01:01:26 PM PST 24 |
Jan 03 01:02:47 PM PST 24 |
473498014 ps |
| T116 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2517677269 |
|
|
Jan 03 01:01:28 PM PST 24 |
Jan 03 01:02:39 PM PST 24 |
133649222 ps |
| T192 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2256607454 |
|
|
Jan 03 01:01:20 PM PST 24 |
Jan 03 01:02:29 PM PST 24 |
68876638 ps |
| T193 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4176758253 |
|
|
Jan 03 01:01:19 PM PST 24 |
Jan 03 01:02:27 PM PST 24 |
18055821 ps |
| T91 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1773362323 |
|
|
Jan 03 01:01:25 PM PST 24 |
Jan 03 01:07:03 PM PST 24 |
7220318022 ps |
| T194 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2848518163 |
|
|
Jan 03 01:01:31 PM PST 24 |
Jan 03 01:02:42 PM PST 24 |
160111857 ps |
| T92 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2769070927 |
|
|
Jan 03 01:01:42 PM PST 24 |
Jan 03 01:05:24 PM PST 24 |
19393215020 ps |
| T195 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3372322918 |
|
|
Jan 03 01:01:34 PM PST 24 |
Jan 03 01:02:48 PM PST 24 |
26914875 ps |
| T196 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.509014845 |
|
|
Jan 03 01:01:16 PM PST 24 |
Jan 03 01:02:23 PM PST 24 |
18877568 ps |
| T93 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.121270921 |
|
|
Jan 03 01:01:34 PM PST 24 |
Jan 03 01:05:19 PM PST 24 |
11991625817 ps |
| T197 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.864273588 |
|
|
Jan 03 01:01:24 PM PST 24 |
Jan 03 01:02:32 PM PST 24 |
15429169 ps |
| T198 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2298741193 |
|
|
Jan 03 01:01:38 PM PST 24 |
Jan 03 01:02:50 PM PST 24 |
18685938 ps |
| T117 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1494642100 |
|
|
Jan 03 01:01:18 PM PST 24 |
Jan 03 01:02:26 PM PST 24 |
386964075 ps |
| T199 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3652478695 |
|
|
Jan 03 01:01:16 PM PST 24 |
Jan 03 01:02:23 PM PST 24 |
12800559 ps |
| T200 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.633459085 |
|
|
Jan 03 01:01:20 PM PST 24 |
Jan 03 01:04:27 PM PST 24 |
10867388873 ps |
| T201 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.649034705 |
|
|
Jan 03 01:01:19 PM PST 24 |
Jan 03 01:02:25 PM PST 24 |
19236859 ps |
| T99 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3270075034 |
|
|
Jan 03 01:01:23 PM PST 24 |
Jan 03 01:02:31 PM PST 24 |
13088553 ps |
| T202 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.176359358 |
|
|
Jan 03 01:01:28 PM PST 24 |
Jan 03 01:02:39 PM PST 24 |
32840426 ps |
| T203 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3578420049 |
|
|
Jan 03 01:01:23 PM PST 24 |
Jan 03 01:02:34 PM PST 24 |
40645904 ps |
| T123 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2388897426 |
|
|
Jan 03 01:01:35 PM PST 24 |
Jan 03 01:02:48 PM PST 24 |
285611504 ps |
| T204 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2234491142 |
|
|
Jan 03 01:01:10 PM PST 24 |
Jan 03 01:02:18 PM PST 24 |
521270251 ps |
| T205 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4167759442 |
|
|
Jan 03 01:01:18 PM PST 24 |
Jan 03 01:02:29 PM PST 24 |
379707998 ps |
| T206 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3553611370 |
|
|
Jan 03 01:01:27 PM PST 24 |
Jan 03 01:02:50 PM PST 24 |
364899511 ps |
| T207 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1094705388 |
|
|
Jan 03 01:01:15 PM PST 24 |
Jan 03 01:02:24 PM PST 24 |
798533789 ps |
| T208 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1037135334 |
|
|
Jan 03 01:01:29 PM PST 24 |
Jan 03 01:02:45 PM PST 24 |
1428768887 ps |
| T209 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1994060351 |
|
|
Jan 03 01:01:24 PM PST 24 |
Jan 03 01:02:33 PM PST 24 |
15615654 ps |
| T210 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.848437820 |
|
|
Jan 03 01:01:18 PM PST 24 |
Jan 03 01:02:25 PM PST 24 |
135015925 ps |
| T94 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2767917918 |
|
|
Jan 03 01:01:17 PM PST 24 |
Jan 03 01:07:08 PM PST 24 |
28154496248 ps |
| T211 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1833923425 |
|
|
Jan 03 01:01:25 PM PST 24 |
Jan 03 01:02:40 PM PST 24 |
1366618593 ps |
| T212 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3692353364 |
|
|
Jan 03 01:01:30 PM PST 24 |
Jan 03 01:02:41 PM PST 24 |
62734159 ps |
| T125 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3328512450 |
|
|
Jan 03 01:01:31 PM PST 24 |
Jan 03 01:02:44 PM PST 24 |
196989097 ps |
| T213 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1865654508 |
|
|
Jan 03 01:01:40 PM PST 24 |
Jan 03 01:04:44 PM PST 24 |
7539649712 ps |
| T214 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1233648944 |
|
|
Jan 03 01:01:24 PM PST 24 |
Jan 03 01:02:34 PM PST 24 |
212999484 ps |
| T120 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1777252612 |
|
|
Jan 03 01:01:33 PM PST 24 |
Jan 03 01:02:47 PM PST 24 |
154058808 ps |
| T215 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3226835580 |
|
|
Jan 03 01:01:25 PM PST 24 |
Jan 03 01:02:47 PM PST 24 |
351216920 ps |
| T216 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4120831145 |
|
|
Jan 03 01:01:21 PM PST 24 |
Jan 03 01:04:52 PM PST 24 |
4343162073 ps |
| T124 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.271039936 |
|
|
Jan 03 01:01:21 PM PST 24 |
Jan 03 01:02:29 PM PST 24 |
334190046 ps |
| T217 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1347971952 |
|
|
Jan 03 01:01:25 PM PST 24 |
Jan 03 01:02:35 PM PST 24 |
35563040 ps |
| T218 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1353667359 |
|
|
Jan 03 01:01:20 PM PST 24 |
Jan 03 01:02:30 PM PST 24 |
142910522 ps |
| T219 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3269718302 |
|
|
Jan 03 01:01:19 PM PST 24 |
Jan 03 01:02:25 PM PST 24 |
28630972 ps |
| T220 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1957987955 |
|
|
Jan 03 01:01:18 PM PST 24 |
Jan 03 01:03:17 PM PST 24 |
7740828876 ps |
| T221 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1117034420 |
|
|
Jan 03 01:01:24 PM PST 24 |
Jan 03 01:02:33 PM PST 24 |
187330500 ps |
| T222 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.285842736 |
|
|
Jan 03 01:01:15 PM PST 24 |
Jan 03 01:02:22 PM PST 24 |
15755470 ps |
| T223 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2737944466 |
|
|
Jan 03 01:01:24 PM PST 24 |
Jan 03 01:02:33 PM PST 24 |
41104877 ps |
| T224 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1020348451 |
|
|
Jan 03 01:01:27 PM PST 24 |
Jan 03 01:02:38 PM PST 24 |
14421390 ps |
| T225 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3419415800 |
|
|
Jan 03 01:01:27 PM PST 24 |
Jan 03 01:02:38 PM PST 24 |
17369812 ps |
| T226 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.4284555447 |
|
|
Jan 03 01:40:15 PM PST 24 |
Jan 03 01:45:03 PM PST 24 |
14358897769 ps |
| T107 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3809220206 |
|
|
Jan 03 01:39:44 PM PST 24 |
Jan 03 01:45:07 PM PST 24 |
22600641895 ps |
| T227 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.3341185046 |
|
|
Jan 03 01:40:32 PM PST 24 |
Jan 03 01:40:51 PM PST 24 |
709366597 ps |
| T228 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1877174766 |
|
|
Jan 03 01:45:45 PM PST 24 |
Jan 03 01:46:46 PM PST 24 |
1499327986 ps |
| T229 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.3687907828 |
|
|
Jan 03 01:43:35 PM PST 24 |
Jan 03 01:44:06 PM PST 24 |
2698464925 ps |
| T29 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.2913938654 |
|
|
Jan 03 01:43:40 PM PST 24 |
Jan 03 01:47:06 PM PST 24 |
36862640053 ps |
| T230 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.3239139486 |
|
|
Jan 03 01:40:48 PM PST 24 |
Jan 03 01:42:49 PM PST 24 |
3890911294 ps |
| T84 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.1519763685 |
|
|
Jan 03 01:42:50 PM PST 24 |
Jan 03 01:45:28 PM PST 24 |
13252528625 ps |
| T231 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3337277544 |
|
|
Jan 03 01:40:14 PM PST 24 |
Jan 03 01:41:01 PM PST 24 |
2800485497 ps |
| T232 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.2932788412 |
|
|
Jan 03 01:44:56 PM PST 24 |
Jan 03 01:46:59 PM PST 24 |
1999790685 ps |
| T233 |
/workspace/coverage/default/37.sram_ctrl_partial_access.2531492330 |
|
|
Jan 03 01:45:00 PM PST 24 |
Jan 03 01:45:38 PM PST 24 |
3943845104 ps |
| T108 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.2736615811 |
|
|
Jan 03 01:46:26 PM PST 24 |
Jan 03 01:53:36 PM PST 24 |
5734109995 ps |
| T234 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.3155421994 |
|
|
Jan 03 01:45:16 PM PST 24 |
Jan 03 01:54:01 PM PST 24 |
2860420894 ps |
| T235 |
/workspace/coverage/default/8.sram_ctrl_partial_access.3810751218 |
|
|
Jan 03 01:40:20 PM PST 24 |
Jan 03 01:41:11 PM PST 24 |
974466423 ps |
| T236 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3857196423 |
|
|
Jan 03 01:46:35 PM PST 24 |
Jan 03 01:49:05 PM PST 24 |
3290444676 ps |
| T237 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.1361510230 |
|
|
Jan 03 01:41:47 PM PST 24 |
Jan 03 01:42:14 PM PST 24 |
681603831 ps |
| T238 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1660970369 |
|
|
Jan 03 01:44:15 PM PST 24 |
Jan 03 01:44:52 PM PST 24 |
2754378213 ps |
| T85 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.1855724734 |
|
|
Jan 03 01:47:00 PM PST 24 |
Jan 03 01:48:26 PM PST 24 |
974038013 ps |
| T239 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.699290422 |
|
|
Jan 03 01:45:41 PM PST 24 |
Jan 03 01:53:11 PM PST 24 |
27963192145 ps |
| T23 |
/workspace/coverage/default/39.sram_ctrl_alert_test.83601441 |
|
|
Jan 03 01:46:30 PM PST 24 |
Jan 03 01:46:36 PM PST 24 |
13472736 ps |
| T86 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2109987706 |
|
|
Jan 03 01:41:57 PM PST 24 |
Jan 03 01:44:23 PM PST 24 |
11154195316 ps |
| T240 |
/workspace/coverage/default/3.sram_ctrl_alert_test.3621287834 |
|
|
Jan 03 01:40:28 PM PST 24 |
Jan 03 01:40:30 PM PST 24 |
85731852 ps |
| T241 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3012269489 |
|
|
Jan 03 01:44:56 PM PST 24 |
Jan 03 01:45:39 PM PST 24 |
5847769454 ps |
| T242 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.3425987013 |
|
|
Jan 03 01:43:44 PM PST 24 |
Jan 03 01:46:16 PM PST 24 |
41383673424 ps |
| T243 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.880060458 |
|
|
Jan 03 01:40:32 PM PST 24 |
Jan 03 01:41:21 PM PST 24 |
6051669692 ps |
| T128 |
/workspace/coverage/default/37.sram_ctrl_regwen.3347889239 |
|
|
Jan 03 01:45:24 PM PST 24 |
Jan 03 02:05:29 PM PST 24 |
11227000658 ps |
| T138 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1516220843 |
|
|
Jan 03 01:46:37 PM PST 24 |
Jan 03 01:52:11 PM PST 24 |
18089248398 ps |
| T244 |
/workspace/coverage/default/10.sram_ctrl_alert_test.2448120277 |
|
|
Jan 03 01:40:28 PM PST 24 |
Jan 03 01:40:30 PM PST 24 |
24840025 ps |
| T245 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.603231295 |
|
|
Jan 03 01:43:40 PM PST 24 |
Jan 03 01:44:13 PM PST 24 |
13666319980 ps |
| T130 |
/workspace/coverage/default/15.sram_ctrl_regwen.3169554385 |
|
|
Jan 03 01:41:57 PM PST 24 |
Jan 03 02:03:19 PM PST 24 |
89426844659 ps |
| T246 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.749705341 |
|
|
Jan 03 01:45:16 PM PST 24 |
Jan 03 01:48:42 PM PST 24 |
3872790715 ps |
| T247 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.82607235 |
|
|
Jan 03 01:42:59 PM PST 24 |
Jan 03 01:47:40 PM PST 24 |
17902663047 ps |
| T21 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2916785734 |
|
|
Jan 03 01:42:06 PM PST 24 |
Jan 03 02:06:55 PM PST 24 |
16910136217 ps |
| T248 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.1047505421 |
|
|
Jan 03 01:45:00 PM PST 24 |
Jan 03 02:00:16 PM PST 24 |
149343736254 ps |
| T249 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2333781012 |
|
|
Jan 03 01:46:33 PM PST 24 |
Jan 03 01:47:28 PM PST 24 |
3769611828 ps |
| T250 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3872675701 |
|
|
Jan 03 01:40:51 PM PST 24 |
Jan 03 02:57:21 PM PST 24 |
12283919755 ps |
| T112 |
/workspace/coverage/default/39.sram_ctrl_stress_all.406143155 |
|
|
Jan 03 01:46:33 PM PST 24 |
Jan 03 02:38:21 PM PST 24 |
30624626138 ps |
| T135 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3847829909 |
|
|
Jan 03 01:46:36 PM PST 24 |
Jan 03 01:55:10 PM PST 24 |
118697697666 ps |
| T251 |
/workspace/coverage/default/47.sram_ctrl_partial_access.738824633 |
|
|
Jan 03 01:46:59 PM PST 24 |
Jan 03 01:47:52 PM PST 24 |
3757329040 ps |
| T252 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1548362380 |
|
|
Jan 03 01:40:50 PM PST 24 |
Jan 03 01:41:01 PM PST 24 |
4823040250 ps |
| T253 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.4142444295 |
|
|
Jan 03 01:46:32 PM PST 24 |
Jan 03 01:51:10 PM PST 24 |
15354497743 ps |
| T87 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.1992663837 |
|
|
Jan 03 01:46:28 PM PST 24 |
Jan 03 02:14:04 PM PST 24 |
57433507680 ps |
| T254 |
/workspace/coverage/default/11.sram_ctrl_partial_access.811625315 |
|
|
Jan 03 01:42:32 PM PST 24 |
Jan 03 01:43:07 PM PST 24 |
1617145086 ps |
| T255 |
/workspace/coverage/default/36.sram_ctrl_alert_test.1491227883 |
|
|
Jan 03 01:44:59 PM PST 24 |
Jan 03 01:45:02 PM PST 24 |
22132906 ps |
| T256 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.451991849 |
|
|
Jan 03 01:45:23 PM PST 24 |
Jan 03 01:53:13 PM PST 24 |
7428041730 ps |
| T257 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.4061313783 |
|
|
Jan 03 01:44:55 PM PST 24 |
Jan 03 01:45:11 PM PST 24 |
1534047636 ps |
| T258 |
/workspace/coverage/default/20.sram_ctrl_alert_test.3542203747 |
|
|
Jan 03 01:42:48 PM PST 24 |
Jan 03 01:42:50 PM PST 24 |
14903820 ps |
| T259 |
/workspace/coverage/default/48.sram_ctrl_smoke.3387247304 |
|
|
Jan 03 01:46:55 PM PST 24 |
Jan 03 01:49:37 PM PST 24 |
5483479860 ps |
| T260 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.153533456 |
|
|
Jan 03 01:42:28 PM PST 24 |
Jan 03 01:44:31 PM PST 24 |
799986043 ps |
| T261 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2078329222 |
|
|
Jan 03 01:43:11 PM PST 24 |
Jan 03 02:51:37 PM PST 24 |
1485477111 ps |
| T126 |
/workspace/coverage/default/14.sram_ctrl_regwen.3224426547 |
|
|
Jan 03 01:41:50 PM PST 24 |
Jan 03 01:57:24 PM PST 24 |
17744632483 ps |
| T262 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.1218764762 |
|
|
Jan 03 01:46:35 PM PST 24 |
Jan 03 01:51:26 PM PST 24 |
14338471666 ps |
| T263 |
/workspace/coverage/default/0.sram_ctrl_alert_test.1009910950 |
|
|
Jan 03 01:39:58 PM PST 24 |
Jan 03 01:40:07 PM PST 24 |
19118864 ps |
| T100 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.1216730635 |
|
|
Jan 03 01:40:15 PM PST 24 |
Jan 03 01:42:56 PM PST 24 |
8582559544 ps |
| T264 |
/workspace/coverage/default/21.sram_ctrl_alert_test.54426900 |
|
|
Jan 03 01:42:50 PM PST 24 |
Jan 03 01:42:52 PM PST 24 |
121554254 ps |
| T265 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.2198293717 |
|
|
Jan 03 01:45:40 PM PST 24 |
Jan 03 01:45:56 PM PST 24 |
1398866437 ps |
| T134 |
/workspace/coverage/default/6.sram_ctrl_regwen.1845544618 |
|
|
Jan 03 01:40:14 PM PST 24 |
Jan 03 01:55:54 PM PST 24 |
11177859767 ps |
| T266 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.2115521825 |
|
|
Jan 03 01:45:27 PM PST 24 |
Jan 03 01:46:58 PM PST 24 |
730710626 ps |
| T267 |
/workspace/coverage/default/35.sram_ctrl_bijection.3589704637 |
|
|
Jan 03 01:45:17 PM PST 24 |
Jan 03 01:59:45 PM PST 24 |
52752067933 ps |
| T268 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.834519561 |
|
|
Jan 03 01:40:18 PM PST 24 |
Jan 03 02:11:57 PM PST 24 |
966350892 ps |
| T269 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1432873574 |
|
|
Jan 03 01:40:48 PM PST 24 |
Jan 03 01:58:50 PM PST 24 |
20025376107 ps |
| T270 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.474991351 |
|
|
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