Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	131206985	1			T1	587		T2	3121		T3	146318
triple_byte_access	2801683	1			T1	9		T2	6910		T3	2951
halfword_access	4306348	1			T1	19		T2	13146		T3	4387
byte_access	6027851	1			T1	15		T2	24628		T3	5887
zero_access	1830043	1			T1	4		T2	14510		T3	1517

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72431872

1

T1

319

T2

30922

T3

80225

auto[1]

73741038

1

T1

315

T2

31393

T3

80835

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	64850300	1			T1	299		T2	240		T3	72795
auto[0]	triple_byte_access	1325583	1			T1	1		T2	1318		T3	1461
auto[0]	halfword_access	2090872	1			T1	9		T2	4454		T3	2257
auto[0]	byte_access	3072872	1			T1	8		T2	13289		T3	2948
auto[0]	zero_access	1092245	1			T1	2		T2	11621		T3	764
auto[1]	word_access	66356685	1			T1	288		T2	2881		T3	73523
auto[1]	triple_byte_access	1476100	1			T1	8		T2	5592		T3	1490
auto[1]	halfword_access	2215476	1			T1	10		T2	8692		T3	2130
auto[1]	byte_access	2954979	1			T1	7		T2	11339		T3	2939
auto[1]	zero_access	737798	1			T1	2		T2	2889		T3	753