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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 100.00 98.27 100.00 100.00 99.71 99.70 100.00


Total test records in report: 987
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T753 /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1260117768 Jan 03 01:45:31 PM PST 24 Jan 03 01:46:09 PM PST 24 7462222812 ps
T754 /workspace/coverage/default/11.sram_ctrl_mem_walk.661671051 Jan 03 01:41:10 PM PST 24 Jan 03 01:45:26 PM PST 24 7886121850 ps
T755 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.1262320056 Jan 03 01:45:20 PM PST 24 Jan 03 01:48:08 PM PST 24 18248243458 ps
T756 /workspace/coverage/default/0.sram_ctrl_mem_walk.2432579483 Jan 03 01:39:56 PM PST 24 Jan 03 01:42:06 PM PST 24 8970158720 ps
T757 /workspace/coverage/default/2.sram_ctrl_partial_access.1891911080 Jan 03 01:39:50 PM PST 24 Jan 03 01:40:55 PM PST 24 2831627752 ps
T758 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.71041624 Jan 03 01:40:18 PM PST 24 Jan 03 01:40:56 PM PST 24 699394067 ps
T759 /workspace/coverage/default/9.sram_ctrl_mem_walk.2129753028 Jan 03 01:41:37 PM PST 24 Jan 03 01:44:10 PM PST 24 11480072885 ps
T760 /workspace/coverage/default/8.sram_ctrl_ram_cfg.1944158471 Jan 03 01:40:22 PM PST 24 Jan 03 01:40:34 PM PST 24 1406218737 ps
T761 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3488994473 Jan 03 01:46:59 PM PST 24 Jan 03 01:48:21 PM PST 24 3939445498 ps
T762 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.2131500969 Jan 03 01:44:59 PM PST 24 Jan 03 01:48:52 PM PST 24 6979688404 ps
T763 /workspace/coverage/default/31.sram_ctrl_mem_walk.4223174006 Jan 03 01:44:55 PM PST 24 Jan 03 01:47:04 PM PST 24 2074888621 ps
T764 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2707324713 Jan 03 01:40:32 PM PST 24 Jan 03 01:53:37 PM PST 24 5845825376 ps
T765 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.882326926 Jan 03 01:40:17 PM PST 24 Jan 03 01:41:46 PM PST 24 4610296963 ps
T766 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1258762087 Jan 03 01:41:13 PM PST 24 Jan 03 01:43:51 PM PST 24 4561949954 ps
T767 /workspace/coverage/default/29.sram_ctrl_alert_test.3707376512 Jan 03 01:45:16 PM PST 24 Jan 03 01:45:28 PM PST 24 15106103 ps
T768 /workspace/coverage/default/3.sram_ctrl_mem_walk.1133413470 Jan 03 01:40:15 PM PST 24 Jan 03 01:45:51 PM PST 24 18666433196 ps
T769 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3613658259 Jan 03 01:46:37 PM PST 24 Jan 03 01:52:03 PM PST 24 15861642862 ps
T770 /workspace/coverage/default/49.sram_ctrl_ram_cfg.866330097 Jan 03 01:46:58 PM PST 24 Jan 03 01:47:12 PM PST 24 1307958699 ps
T771 /workspace/coverage/default/48.sram_ctrl_lc_escalation.4187725372 Jan 03 01:46:57 PM PST 24 Jan 03 01:48:29 PM PST 24 31334235557 ps
T772 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.510973040 Jan 03 01:43:45 PM PST 24 Jan 03 01:44:54 PM PST 24 777287371 ps
T773 /workspace/coverage/default/4.sram_ctrl_max_throughput.206718363 Jan 03 01:40:18 PM PST 24 Jan 03 01:41:51 PM PST 24 1550769481 ps
T774 /workspace/coverage/default/23.sram_ctrl_partial_access.715802562 Jan 03 01:44:01 PM PST 24 Jan 03 01:44:23 PM PST 24 2086930237 ps
T775 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2038653154 Jan 03 01:44:57 PM PST 24 Jan 03 01:45:59 PM PST 24 758742198 ps
T776 /workspace/coverage/default/24.sram_ctrl_ram_cfg.4019917318 Jan 03 01:43:16 PM PST 24 Jan 03 01:43:23 PM PST 24 355937362 ps
T777 /workspace/coverage/default/15.sram_ctrl_smoke.711374985 Jan 03 01:41:46 PM PST 24 Jan 03 01:43:39 PM PST 24 2552222877 ps
T778 /workspace/coverage/default/11.sram_ctrl_max_throughput.1070842206 Jan 03 01:42:34 PM PST 24 Jan 03 01:43:23 PM PST 24 1474003850 ps
T779 /workspace/coverage/default/8.sram_ctrl_mem_walk.1023484422 Jan 03 01:40:47 PM PST 24 Jan 03 01:44:59 PM PST 24 15767053619 ps
T780 /workspace/coverage/default/5.sram_ctrl_alert_test.781021549 Jan 03 01:41:35 PM PST 24 Jan 03 01:41:41 PM PST 24 21668882 ps
T781 /workspace/coverage/default/6.sram_ctrl_alert_test.2721083437 Jan 03 01:40:16 PM PST 24 Jan 03 01:40:26 PM PST 24 55449294 ps
T782 /workspace/coverage/default/20.sram_ctrl_regwen.3675468739 Jan 03 01:42:27 PM PST 24 Jan 03 01:56:50 PM PST 24 16715437236 ps
T783 /workspace/coverage/default/32.sram_ctrl_bijection.1892242021 Jan 03 01:44:54 PM PST 24 Jan 03 02:30:50 PM PST 24 689679837995 ps
T784 /workspace/coverage/default/1.sram_ctrl_multiple_keys.2055996800 Jan 03 01:39:58 PM PST 24 Jan 03 01:49:41 PM PST 24 9143574184 ps
T785 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.2544719607 Jan 03 01:42:08 PM PST 24 Jan 03 01:48:26 PM PST 24 5002503548 ps
T786 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.3917948617 Jan 03 01:45:27 PM PST 24 Jan 03 01:52:19 PM PST 24 5193153041 ps
T787 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.3581417234 Jan 03 01:44:32 PM PST 24 Jan 03 01:45:51 PM PST 24 2645253405 ps
T788 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.3336972410 Jan 03 01:40:30 PM PST 24 Jan 03 01:54:34 PM PST 24 15263714928 ps
T789 /workspace/coverage/default/26.sram_ctrl_max_throughput.2377089153 Jan 03 01:44:31 PM PST 24 Jan 03 01:45:07 PM PST 24 2973331551 ps
T790 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.682099802 Jan 03 01:42:28 PM PST 24 Jan 03 01:44:52 PM PST 24 1615249959 ps
T791 /workspace/coverage/default/4.sram_ctrl_mem_walk.731149057 Jan 03 01:40:32 PM PST 24 Jan 03 01:43:27 PM PST 24 43005243656 ps
T792 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.820748005 Jan 03 01:42:56 PM PST 24 Jan 03 01:46:57 PM PST 24 3240399452 ps
T793 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.911792643 Jan 03 01:46:25 PM PST 24 Jan 03 01:48:13 PM PST 24 788788630 ps
T794 /workspace/coverage/default/31.sram_ctrl_bijection.4279859003 Jan 03 01:45:40 PM PST 24 Jan 03 02:28:09 PM PST 24 309555653671 ps
T795 /workspace/coverage/default/16.sram_ctrl_multiple_keys.1034784578 Jan 03 01:42:25 PM PST 24 Jan 03 01:58:13 PM PST 24 12830639453 ps
T796 /workspace/coverage/default/3.sram_ctrl_stress_pipeline.1076784317 Jan 03 01:40:14 PM PST 24 Jan 03 01:44:20 PM PST 24 22498930293 ps
T797 /workspace/coverage/default/19.sram_ctrl_lc_escalation.1520434502 Jan 03 01:43:11 PM PST 24 Jan 03 01:44:28 PM PST 24 8679016520 ps
T798 /workspace/coverage/default/36.sram_ctrl_regwen.2145352737 Jan 03 01:45:41 PM PST 24 Jan 03 01:50:46 PM PST 24 22982448463 ps
T799 /workspace/coverage/default/37.sram_ctrl_bijection.1903809550 Jan 03 01:45:18 PM PST 24 Jan 03 02:17:03 PM PST 24 60593264022 ps
T800 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.2619072635 Jan 03 01:42:26 PM PST 24 Jan 03 01:44:02 PM PST 24 6925516545 ps
T801 /workspace/coverage/default/34.sram_ctrl_smoke.2224102973 Jan 03 01:45:41 PM PST 24 Jan 03 01:45:51 PM PST 24 1599368193 ps
T802 /workspace/coverage/default/23.sram_ctrl_executable.2769159287 Jan 03 01:44:28 PM PST 24 Jan 03 01:52:09 PM PST 24 26659280529 ps
T803 /workspace/coverage/default/10.sram_ctrl_executable.3008663931 Jan 03 01:42:28 PM PST 24 Jan 03 02:11:17 PM PST 24 264703202817 ps
T804 /workspace/coverage/default/2.sram_ctrl_alert_test.1992984981 Jan 03 01:40:22 PM PST 24 Jan 03 01:40:28 PM PST 24 13121259 ps
T805 /workspace/coverage/default/44.sram_ctrl_stress_all.4236770805 Jan 03 01:46:28 PM PST 24 Jan 03 02:27:00 PM PST 24 25372317131 ps
T806 /workspace/coverage/default/3.sram_ctrl_partial_access.449265961 Jan 03 01:40:17 PM PST 24 Jan 03 01:41:02 PM PST 24 2950187393 ps
T807 /workspace/coverage/default/11.sram_ctrl_smoke.2632947936 Jan 03 01:41:55 PM PST 24 Jan 03 01:44:21 PM PST 24 1349021212 ps
T808 /workspace/coverage/default/15.sram_ctrl_max_throughput.1664571819 Jan 03 01:42:24 PM PST 24 Jan 03 01:44:08 PM PST 24 774289288 ps
T809 /workspace/coverage/default/2.sram_ctrl_multiple_keys.3112056885 Jan 03 01:39:52 PM PST 24 Jan 03 01:50:25 PM PST 24 36582551841 ps
T810 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1818978579 Jan 03 01:41:11 PM PST 24 Jan 03 01:43:43 PM PST 24 3102714289 ps
T811 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2617920653 Jan 03 01:42:21 PM PST 24 Jan 03 02:06:07 PM PST 24 3278463181 ps
T812 /workspace/coverage/default/47.sram_ctrl_alert_test.425560971 Jan 03 01:46:58 PM PST 24 Jan 03 01:47:07 PM PST 24 20969016 ps
T813 /workspace/coverage/default/40.sram_ctrl_ram_cfg.2510574698 Jan 03 01:46:28 PM PST 24 Jan 03 01:46:37 PM PST 24 1349303809 ps
T814 /workspace/coverage/default/1.sram_ctrl_max_throughput.1824946883 Jan 03 01:39:59 PM PST 24 Jan 03 01:41:41 PM PST 24 3049041998 ps
T815 /workspace/coverage/default/1.sram_ctrl_lc_escalation.1631142127 Jan 03 01:39:51 PM PST 24 Jan 03 01:40:09 PM PST 24 1396328292 ps
T816 /workspace/coverage/default/13.sram_ctrl_partial_access.2608548623 Jan 03 01:41:57 PM PST 24 Jan 03 01:43:17 PM PST 24 6454421846 ps
T817 /workspace/coverage/default/45.sram_ctrl_ram_cfg.2640987096 Jan 03 01:46:36 PM PST 24 Jan 03 01:47:00 PM PST 24 369721236 ps
T818 /workspace/coverage/default/30.sram_ctrl_alert_test.3883099440 Jan 03 01:45:40 PM PST 24 Jan 03 01:45:44 PM PST 24 81810126 ps
T819 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.31109691 Jan 03 01:44:16 PM PST 24 Jan 03 02:12:50 PM PST 24 42710970861 ps
T820 /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1863617593 Jan 03 01:46:37 PM PST 24 Jan 03 02:37:29 PM PST 24 5320773310 ps
T821 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1665682964 Jan 03 01:45:01 PM PST 24 Jan 03 01:48:00 PM PST 24 9750487120 ps
T822 /workspace/coverage/default/30.sram_ctrl_executable.2644517247 Jan 03 01:45:03 PM PST 24 Jan 03 01:51:03 PM PST 24 2893499624 ps
T823 /workspace/coverage/default/24.sram_ctrl_smoke.3726698777 Jan 03 01:43:06 PM PST 24 Jan 03 01:43:24 PM PST 24 1517669519 ps
T824 /workspace/coverage/default/20.sram_ctrl_max_throughput.310055923 Jan 03 01:43:14 PM PST 24 Jan 03 01:43:55 PM PST 24 702772779 ps
T825 /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2347427857 Jan 03 01:46:58 PM PST 24 Jan 03 02:54:07 PM PST 24 14539979446 ps
T826 /workspace/coverage/default/18.sram_ctrl_smoke.1644828903 Jan 03 01:42:31 PM PST 24 Jan 03 01:44:28 PM PST 24 4101689454 ps
T827 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.3212305425 Jan 03 01:42:49 PM PST 24 Jan 03 01:45:29 PM PST 24 4475307928 ps
T828 /workspace/coverage/default/25.sram_ctrl_mem_partial_access.240661695 Jan 03 01:43:41 PM PST 24 Jan 03 01:46:04 PM PST 24 6243379150 ps
T829 /workspace/coverage/default/46.sram_ctrl_stress_all.1267502698 Jan 03 01:46:58 PM PST 24 Jan 03 02:27:54 PM PST 24 81335328166 ps
T830 /workspace/coverage/default/40.sram_ctrl_alert_test.435222322 Jan 03 01:46:32 PM PST 24 Jan 03 01:46:39 PM PST 24 48120176 ps
T831 /workspace/coverage/default/12.sram_ctrl_regwen.2470969131 Jan 03 01:41:48 PM PST 24 Jan 03 02:00:17 PM PST 24 21669941808 ps
T832 /workspace/coverage/default/39.sram_ctrl_access_during_key_req.2317127223 Jan 03 01:46:27 PM PST 24 Jan 03 02:16:16 PM PST 24 9953913287 ps
T833 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1405426644 Jan 03 01:41:39 PM PST 24 Jan 03 01:42:33 PM PST 24 2075806044 ps
T834 /workspace/coverage/default/7.sram_ctrl_lc_escalation.1783912423 Jan 03 01:41:14 PM PST 24 Jan 03 01:43:09 PM PST 24 6926315547 ps
T835 /workspace/coverage/default/14.sram_ctrl_alert_test.2510031378 Jan 03 01:41:57 PM PST 24 Jan 03 01:42:06 PM PST 24 33500860 ps
T836 /workspace/coverage/default/29.sram_ctrl_bijection.951378350 Jan 03 01:44:16 PM PST 24 Jan 03 02:22:40 PM PST 24 244256856869 ps
T837 /workspace/coverage/default/48.sram_ctrl_regwen.1932549808 Jan 03 01:46:59 PM PST 24 Jan 03 02:01:36 PM PST 24 38873396765 ps
T838 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.1413709269 Jan 03 01:40:47 PM PST 24 Jan 03 01:45:36 PM PST 24 4774886293 ps
T839 /workspace/coverage/default/46.sram_ctrl_regwen.821270018 Jan 03 01:46:58 PM PST 24 Jan 03 01:52:43 PM PST 24 12160909703 ps
T840 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1526621673 Jan 03 01:43:33 PM PST 24 Jan 03 01:52:43 PM PST 24 28061759995 ps
T841 /workspace/coverage/default/47.sram_ctrl_bijection.2167208562 Jan 03 01:46:56 PM PST 24 Jan 03 01:58:22 PM PST 24 25715267129 ps
T842 /workspace/coverage/default/26.sram_ctrl_multiple_keys.3818593466 Jan 03 01:43:42 PM PST 24 Jan 03 01:56:10 PM PST 24 28564834614 ps
T843 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.4263238943 Jan 03 01:44:54 PM PST 24 Jan 03 02:14:04 PM PST 24 9347391716 ps
T844 /workspace/coverage/default/2.sram_ctrl_lc_escalation.2848632564 Jan 03 01:40:31 PM PST 24 Jan 03 01:43:06 PM PST 24 18762687893 ps
T845 /workspace/coverage/default/14.sram_ctrl_bijection.2940596260 Jan 03 01:41:13 PM PST 24 Jan 03 01:57:18 PM PST 24 249085316635 ps
T846 /workspace/coverage/default/49.sram_ctrl_alert_test.70856187 Jan 03 01:46:58 PM PST 24 Jan 03 01:47:07 PM PST 24 14585605 ps
T847 /workspace/coverage/default/23.sram_ctrl_bijection.1563134631 Jan 03 01:43:44 PM PST 24 Jan 03 02:20:31 PM PST 24 33143119470 ps
T848 /workspace/coverage/default/35.sram_ctrl_max_throughput.4053561308 Jan 03 01:45:24 PM PST 24 Jan 03 01:46:40 PM PST 24 2684401348 ps
T849 /workspace/coverage/default/28.sram_ctrl_mem_walk.431158795 Jan 03 01:45:29 PM PST 24 Jan 03 01:49:42 PM PST 24 4106560901 ps
T850 /workspace/coverage/default/7.sram_ctrl_stress_all.3787119658 Jan 03 01:41:50 PM PST 24 Jan 03 02:47:43 PM PST 24 236683047720 ps
T851 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2215243522 Jan 03 01:39:54 PM PST 24 Jan 03 01:44:27 PM PST 24 7135152630 ps
T852 /workspace/coverage/default/22.sram_ctrl_mem_walk.3738460389 Jan 03 01:43:42 PM PST 24 Jan 03 01:46:27 PM PST 24 43098228638 ps
T853 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3650508472 Jan 03 01:46:59 PM PST 24 Jan 03 01:48:29 PM PST 24 1521638206 ps
T854 /workspace/coverage/default/27.sram_ctrl_regwen.2746452046 Jan 03 01:43:39 PM PST 24 Jan 03 01:46:17 PM PST 24 1752725420 ps
T855 /workspace/coverage/default/47.sram_ctrl_regwen.687049416 Jan 03 01:46:57 PM PST 24 Jan 03 01:55:30 PM PST 24 34377754029 ps
T856 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.2533317367 Jan 03 01:46:33 PM PST 24 Jan 03 01:52:24 PM PST 24 2040230994 ps
T857 /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3641807694 Jan 03 01:46:31 PM PST 24 Jan 03 02:28:16 PM PST 24 313035424 ps
T858 /workspace/coverage/default/8.sram_ctrl_regwen.1094465279 Jan 03 01:40:33 PM PST 24 Jan 03 01:47:06 PM PST 24 12981857647 ps
T859 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.565888547 Jan 03 01:41:38 PM PST 24 Jan 03 02:32:54 PM PST 24 1992556023 ps
T860 /workspace/coverage/default/15.sram_ctrl_bijection.2750720333 Jan 03 01:41:58 PM PST 24 Jan 03 02:24:57 PM PST 24 967611350726 ps
T861 /workspace/coverage/default/25.sram_ctrl_alert_test.2386869088 Jan 03 01:43:42 PM PST 24 Jan 03 01:43:46 PM PST 24 26956146 ps
T862 /workspace/coverage/default/33.sram_ctrl_alert_test.687692314 Jan 03 01:45:42 PM PST 24 Jan 03 01:45:44 PM PST 24 16860863 ps
T863 /workspace/coverage/default/29.sram_ctrl_smoke.2585983300 Jan 03 01:44:53 PM PST 24 Jan 03 01:45:20 PM PST 24 2761821867 ps
T864 /workspace/coverage/default/11.sram_ctrl_alert_test.2575512789 Jan 03 01:40:46 PM PST 24 Jan 03 01:40:52 PM PST 24 20124606 ps
T865 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.488846647 Jan 03 01:46:29 PM PST 24 Jan 03 01:54:38 PM PST 24 132890031900 ps
T866 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2731910027 Jan 03 01:45:14 PM PST 24 Jan 03 01:49:03 PM PST 24 7431425788 ps
T867 /workspace/coverage/default/31.sram_ctrl_multiple_keys.209823157 Jan 03 01:45:50 PM PST 24 Jan 03 02:01:09 PM PST 24 67578427232 ps
T868 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.4187991670 Jan 03 01:45:25 PM PST 24 Jan 03 01:54:36 PM PST 24 83979742388 ps
T869 /workspace/coverage/default/38.sram_ctrl_executable.179072846 Jan 03 01:45:25 PM PST 24 Jan 03 01:48:41 PM PST 24 5922991999 ps
T870 /workspace/coverage/default/45.sram_ctrl_bijection.3900560508 Jan 03 01:46:29 PM PST 24 Jan 03 02:07:04 PM PST 24 923038766904 ps
T871 /workspace/coverage/default/33.sram_ctrl_bijection.2473661308 Jan 03 01:45:05 PM PST 24 Jan 03 02:01:49 PM PST 24 271448785430 ps
T872 /workspace/coverage/default/0.sram_ctrl_stress_all.1198595413 Jan 03 01:39:52 PM PST 24 Jan 03 02:33:05 PM PST 24 421557099791 ps
T873 /workspace/coverage/default/26.sram_ctrl_partial_access.327936577 Jan 03 01:43:59 PM PST 24 Jan 03 01:44:22 PM PST 24 2294294639 ps
T874 /workspace/coverage/default/19.sram_ctrl_alert_test.2404452753 Jan 03 01:43:13 PM PST 24 Jan 03 01:43:16 PM PST 24 55803044 ps
T875 /workspace/coverage/default/38.sram_ctrl_alert_test.2993114516 Jan 03 01:45:25 PM PST 24 Jan 03 01:45:37 PM PST 24 63509023 ps
T876 /workspace/coverage/default/9.sram_ctrl_mem_partial_access.3217372285 Jan 03 01:41:38 PM PST 24 Jan 03 01:44:07 PM PST 24 8889556721 ps
T877 /workspace/coverage/default/29.sram_ctrl_partial_access.1185535431 Jan 03 01:44:52 PM PST 24 Jan 03 01:45:11 PM PST 24 1442942267 ps
T878 /workspace/coverage/default/49.sram_ctrl_stress_all.3233108731 Jan 03 01:46:58 PM PST 24 Jan 03 02:33:15 PM PST 24 20776759916 ps
T879 /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2149936146 Jan 03 01:42:49 PM PST 24 Jan 03 01:43:19 PM PST 24 2815236255 ps
T880 /workspace/coverage/default/21.sram_ctrl_partial_access.4049009060 Jan 03 01:42:34 PM PST 24 Jan 03 01:43:07 PM PST 24 2670407411 ps
T881 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2435052535 Jan 03 01:41:55 PM PST 24 Jan 03 01:44:07 PM PST 24 3243956941 ps
T882 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3808980927 Jan 03 01:40:24 PM PST 24 Jan 03 02:52:02 PM PST 24 880170901 ps
T883 /workspace/coverage/default/30.sram_ctrl_partial_access.1301083134 Jan 03 01:44:58 PM PST 24 Jan 03 01:45:19 PM PST 24 840589959 ps
T884 /workspace/coverage/default/42.sram_ctrl_smoke.360131198 Jan 03 01:46:27 PM PST 24 Jan 03 01:46:44 PM PST 24 355540963 ps
T885 /workspace/coverage/default/49.sram_ctrl_smoke.752608168 Jan 03 01:46:58 PM PST 24 Jan 03 01:47:59 PM PST 24 2994082443 ps
T886 /workspace/coverage/default/42.sram_ctrl_mem_walk.647751536 Jan 03 01:46:32 PM PST 24 Jan 03 01:50:45 PM PST 24 16417343410 ps
T887 /workspace/coverage/default/40.sram_ctrl_partial_access.3674447666 Jan 03 01:46:26 PM PST 24 Jan 03 01:46:44 PM PST 24 1012095545 ps
T888 /workspace/coverage/default/18.sram_ctrl_stress_all.328785523 Jan 03 01:42:59 PM PST 24 Jan 03 02:39:47 PM PST 24 34259698683 ps
T889 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2715848252 Jan 03 01:41:42 PM PST 24 Jan 03 01:45:56 PM PST 24 4057714918 ps
T890 /workspace/coverage/default/16.sram_ctrl_access_during_key_req.3468411871 Jan 03 01:41:57 PM PST 24 Jan 03 02:02:49 PM PST 24 23788479318 ps
T891 /workspace/coverage/default/41.sram_ctrl_regwen.4286053962 Jan 03 01:46:58 PM PST 24 Jan 03 01:55:23 PM PST 24 7756367695 ps
T892 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1061557085 Jan 03 01:46:35 PM PST 24 Jan 03 01:50:07 PM PST 24 2960313130 ps
T893 /workspace/coverage/default/40.sram_ctrl_smoke.1968982194 Jan 03 01:46:27 PM PST 24 Jan 03 01:46:45 PM PST 24 796992270 ps
T894 /workspace/coverage/default/29.sram_ctrl_multiple_keys.3625053497 Jan 03 01:44:33 PM PST 24 Jan 03 01:55:23 PM PST 24 133788900219 ps
T895 /workspace/coverage/default/27.sram_ctrl_smoke.3694986147 Jan 03 01:44:58 PM PST 24 Jan 03 01:45:13 PM PST 24 1416904779 ps
T896 /workspace/coverage/default/4.sram_ctrl_multiple_keys.1301063103 Jan 03 01:40:24 PM PST 24 Jan 03 02:10:03 PM PST 24 72781035000 ps
T897 /workspace/coverage/default/13.sram_ctrl_alert_test.4276893576 Jan 03 01:41:39 PM PST 24 Jan 03 01:41:43 PM PST 24 23100520 ps
T898 /workspace/coverage/default/25.sram_ctrl_regwen.86645424 Jan 03 01:43:40 PM PST 24 Jan 03 01:54:49 PM PST 24 20086904499 ps
T899 /workspace/coverage/default/43.sram_ctrl_ram_cfg.1274901546 Jan 03 01:46:33 PM PST 24 Jan 03 01:46:48 PM PST 24 695703711 ps
T900 /workspace/coverage/default/29.sram_ctrl_mem_walk.1201641091 Jan 03 01:44:57 PM PST 24 Jan 03 01:47:39 PM PST 24 20681656895 ps
T901 /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.11471344 Jan 03 01:46:55 PM PST 24 Jan 03 01:54:15 PM PST 24 14558143779 ps
T902 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.1192557102 Jan 03 01:45:27 PM PST 24 Jan 03 01:58:35 PM PST 24 15912283303 ps
T903 /workspace/coverage/default/15.sram_ctrl_executable.4162154170 Jan 03 01:42:27 PM PST 24 Jan 03 02:01:50 PM PST 24 95575346980 ps
T904 /workspace/coverage/default/31.sram_ctrl_smoke.4243482236 Jan 03 01:45:40 PM PST 24 Jan 03 01:45:54 PM PST 24 700205573 ps
T905 /workspace/coverage/default/46.sram_ctrl_smoke.2899043071 Jan 03 01:46:33 PM PST 24 Jan 03 01:47:11 PM PST 24 3707667512 ps
T906 /workspace/coverage/default/14.sram_ctrl_max_throughput.2826423491 Jan 03 01:41:16 PM PST 24 Jan 03 01:41:50 PM PST 24 2800647382 ps
T907 /workspace/coverage/default/26.sram_ctrl_stress_all.1819533310 Jan 03 01:44:59 PM PST 24 Jan 03 02:23:45 PM PST 24 35727303472 ps
T908 /workspace/coverage/default/7.sram_ctrl_max_throughput.628496441 Jan 03 01:41:38 PM PST 24 Jan 03 01:43:43 PM PST 24 753400483 ps
T909 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2627045948 Jan 03 01:45:23 PM PST 24 Jan 03 01:46:54 PM PST 24 2450348405 ps
T910 /workspace/coverage/default/34.sram_ctrl_stress_all.234211110 Jan 03 01:45:19 PM PST 24 Jan 03 03:12:25 PM PST 24 994860844344 ps
T911 /workspace/coverage/default/49.sram_ctrl_mem_walk.4097620835 Jan 03 01:46:58 PM PST 24 Jan 03 01:49:34 PM PST 24 13524523250 ps
T912 /workspace/coverage/default/42.sram_ctrl_regwen.1437761061 Jan 03 01:46:33 PM PST 24 Jan 03 01:54:12 PM PST 24 4447365220 ps
T913 /workspace/coverage/default/16.sram_ctrl_alert_test.742251912 Jan 03 01:42:28 PM PST 24 Jan 03 01:42:31 PM PST 24 27613327 ps
T914 /workspace/coverage/default/25.sram_ctrl_multiple_keys.3741404047 Jan 03 01:43:15 PM PST 24 Jan 03 02:01:37 PM PST 24 19453773959 ps
T915 /workspace/coverage/default/19.sram_ctrl_partial_access.1505975146 Jan 03 01:42:58 PM PST 24 Jan 03 01:43:28 PM PST 24 1493377600 ps
T916 /workspace/coverage/default/12.sram_ctrl_stress_all.3345118045 Jan 03 01:41:58 PM PST 24 Jan 03 03:45:58 PM PST 24 439547559435 ps
T917 /workspace/coverage/default/14.sram_ctrl_stress_all.1579304008 Jan 03 01:42:25 PM PST 24 Jan 03 03:27:09 PM PST 24 815741851801 ps
T918 /workspace/coverage/default/7.sram_ctrl_multiple_keys.4177168258 Jan 03 01:40:16 PM PST 24 Jan 03 01:59:22 PM PST 24 123961723550 ps
T919 /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3512071808 Jan 03 01:41:58 PM PST 24 Jan 03 01:42:48 PM PST 24 2944479267 ps
T920 /workspace/coverage/default/48.sram_ctrl_partial_access.2248494187 Jan 03 01:46:57 PM PST 24 Jan 03 01:47:16 PM PST 24 1355287700 ps
T921 /workspace/coverage/default/45.sram_ctrl_regwen.439659625 Jan 03 01:46:32 PM PST 24 Jan 03 01:50:08 PM PST 24 22540982800 ps
T922 /workspace/coverage/default/34.sram_ctrl_ram_cfg.1866079178 Jan 03 01:45:43 PM PST 24 Jan 03 01:45:52 PM PST 24 365700196 ps
T923 /workspace/coverage/default/8.sram_ctrl_smoke.3983731847 Jan 03 01:42:25 PM PST 24 Jan 03 01:42:42 PM PST 24 758862478 ps
T924 /workspace/coverage/default/17.sram_ctrl_partial_access.1978626993 Jan 03 01:42:52 PM PST 24 Jan 03 01:43:25 PM PST 24 673750170 ps
T925 /workspace/coverage/default/33.sram_ctrl_smoke.2435756974 Jan 03 01:45:27 PM PST 24 Jan 03 01:46:05 PM PST 24 3031253061 ps
T926 /workspace/coverage/default/41.sram_ctrl_executable.1566800301 Jan 03 01:46:55 PM PST 24 Jan 03 01:51:16 PM PST 24 5056830411 ps
T927 /workspace/coverage/default/39.sram_ctrl_partial_access.2021085247 Jan 03 01:45:26 PM PST 24 Jan 03 01:46:19 PM PST 24 3989516063 ps
T36 /workspace/coverage/default/0.sram_ctrl_sec_cm.247004029 Jan 03 01:40:01 PM PST 24 Jan 03 01:40:15 PM PST 24 310646048 ps
T928 /workspace/coverage/default/13.sram_ctrl_ram_cfg.4254601354 Jan 03 01:41:12 PM PST 24 Jan 03 01:41:22 PM PST 24 349947861 ps
T929 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1609090013 Jan 03 01:42:50 PM PST 24 Jan 03 02:50:37 PM PST 24 4068450271 ps
T930 /workspace/coverage/default/34.sram_ctrl_regwen.3326837815 Jan 03 01:45:43 PM PST 24 Jan 03 02:02:42 PM PST 24 43160823235 ps
T931 /workspace/coverage/default/9.sram_ctrl_lc_escalation.411487541 Jan 03 01:40:51 PM PST 24 Jan 03 01:43:46 PM PST 24 8222032518 ps
T932 /workspace/coverage/default/35.sram_ctrl_ram_cfg.3025029426 Jan 03 01:45:24 PM PST 24 Jan 03 01:45:40 PM PST 24 350381441 ps
T933 /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1651721510 Jan 03 01:42:27 PM PST 24 Jan 03 01:46:46 PM PST 24 41569116969 ps
T934 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.775135014 Jan 03 01:45:47 PM PST 24 Jan 03 01:50:33 PM PST 24 13771278824 ps
T935 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.1971702032 Jan 03 01:45:41 PM PST 24 Jan 03 01:54:12 PM PST 24 12101052453 ps
T936 /workspace/coverage/default/19.sram_ctrl_smoke.1485122561 Jan 03 01:42:54 PM PST 24 Jan 03 01:43:27 PM PST 24 788386302 ps
T937 /workspace/coverage/default/7.sram_ctrl_executable.663556590 Jan 03 01:41:42 PM PST 24 Jan 03 02:03:55 PM PST 24 83131781650 ps
T938 /workspace/coverage/default/19.sram_ctrl_multiple_keys.8918636 Jan 03 01:42:50 PM PST 24 Jan 03 02:02:58 PM PST 24 36460556155 ps
T939 /workspace/coverage/default/32.sram_ctrl_ram_cfg.4131612268 Jan 03 01:45:21 PM PST 24 Jan 03 01:45:35 PM PST 24 1347105084 ps
T940 /workspace/coverage/default/46.sram_ctrl_alert_test.3917543214 Jan 03 01:46:56 PM PST 24 Jan 03 01:47:03 PM PST 24 20248678 ps
T941 /workspace/coverage/default/23.sram_ctrl_regwen.3643017924 Jan 03 01:43:39 PM PST 24 Jan 03 02:03:25 PM PST 24 15710142028 ps
T942 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2704881458 Jan 03 01:42:01 PM PST 24 Jan 03 02:12:07 PM PST 24 4949266911 ps
T943 /workspace/coverage/default/2.sram_ctrl_access_during_key_req.2632469666 Jan 03 01:40:14 PM PST 24 Jan 03 01:53:25 PM PST 24 10698484114 ps
T944 /workspace/coverage/default/41.sram_ctrl_lc_escalation.3174556050 Jan 03 01:46:38 PM PST 24 Jan 03 01:47:51 PM PST 24 22989076724 ps
T945 /workspace/coverage/default/13.sram_ctrl_smoke.1844523884 Jan 03 01:41:57 PM PST 24 Jan 03 01:42:12 PM PST 24 823342029 ps
T946 /workspace/coverage/default/14.sram_ctrl_partial_access.909341412 Jan 03 01:41:15 PM PST 24 Jan 03 01:41:29 PM PST 24 1803790799 ps
T947 /workspace/coverage/default/15.sram_ctrl_stress_all.3820690223 Jan 03 01:41:52 PM PST 24 Jan 03 02:44:33 PM PST 24 980208744299 ps
T948 /workspace/coverage/default/48.sram_ctrl_alert_test.2428520832 Jan 03 01:46:58 PM PST 24 Jan 03 01:47:07 PM PST 24 60548305 ps
T949 /workspace/coverage/default/21.sram_ctrl_ram_cfg.292880223 Jan 03 01:42:50 PM PST 24 Jan 03 01:42:57 PM PST 24 3060598648 ps
T950 /workspace/coverage/default/25.sram_ctrl_smoke.2137252537 Jan 03 01:43:39 PM PST 24 Jan 03 01:44:02 PM PST 24 1146882226 ps
T951 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3510778535 Jan 03 01:42:28 PM PST 24 Jan 03 01:51:27 PM PST 24 285320687901 ps
T952 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2377312512 Jan 03 01:44:59 PM PST 24 Jan 03 01:50:37 PM PST 24 20557471453 ps
T89 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.2230490137 Jan 03 01:44:30 PM PST 24 Jan 03 01:45:57 PM PST 24 39171193036 ps
T953 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1058327531 Jan 03 01:40:18 PM PST 24 Jan 03 01:45:43 PM PST 24 47387664759 ps
T954 /workspace/coverage/default/3.sram_ctrl_smoke.925387433 Jan 03 01:40:13 PM PST 24 Jan 03 01:40:43 PM PST 24 889949168 ps
T955 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.716860372 Jan 03 01:45:14 PM PST 24 Jan 03 01:52:50 PM PST 24 26426837777 ps
T956 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2320296613 Jan 03 01:39:59 PM PST 24 Jan 03 01:41:44 PM PST 24 784306057 ps
T957 /workspace/coverage/default/8.sram_ctrl_bijection.2027793270 Jan 03 01:42:07 PM PST 24 Jan 03 01:54:28 PM PST 24 135120543269 ps
T958 /workspace/coverage/default/23.sram_ctrl_smoke.4048157845 Jan 03 01:43:38 PM PST 24 Jan 03 01:44:16 PM PST 24 3275426161 ps
T959 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.570357788 Jan 03 01:41:09 PM PST 24 Jan 03 01:46:24 PM PST 24 29945132297 ps
T960 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2644049939 Jan 03 01:41:41 PM PST 24 Jan 03 01:46:58 PM PST 24 4477575826 ps
T961 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2306181136 Jan 03 01:45:43 PM PST 24 Jan 03 02:25:25 PM PST 24 166636842 ps
T962 /workspace/coverage/default/32.sram_ctrl_regwen.2580809021 Jan 03 01:45:01 PM PST 24 Jan 03 01:54:44 PM PST 24 10049978274 ps
T963 /workspace/coverage/default/33.sram_ctrl_mem_walk.2228343929 Jan 03 01:45:38 PM PST 24 Jan 03 01:53:00 PM PST 24 413464393500 ps
T964 /workspace/coverage/default/47.sram_ctrl_mem_walk.812961872 Jan 03 01:46:55 PM PST 24 Jan 03 01:49:13 PM PST 24 17955428675 ps
T965 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3676132056 Jan 03 01:44:55 PM PST 24 Jan 03 02:51:00 PM PST 24 2397778989 ps
T966 /workspace/coverage/default/38.sram_ctrl_max_throughput.2569537864 Jan 03 01:45:23 PM PST 24 Jan 03 01:48:26 PM PST 24 824812065 ps
T967 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.860319205 Jan 03 01:44:56 PM PST 24 Jan 03 02:29:59 PM PST 24 3190510166 ps
T968 /workspace/coverage/default/44.sram_ctrl_max_throughput.2171100829 Jan 03 01:46:38 PM PST 24 Jan 03 01:49:14 PM PST 24 12592162791 ps
T969 /workspace/coverage/default/16.sram_ctrl_stress_all.1233753711 Jan 03 01:42:29 PM PST 24 Jan 03 03:42:13 PM PST 24 175814347812 ps
T970 /workspace/coverage/default/27.sram_ctrl_bijection.346729792 Jan 03 01:43:37 PM PST 24 Jan 03 01:54:44 PM PST 24 15342941539 ps
T971 /workspace/coverage/default/28.sram_ctrl_smoke.2005344693 Jan 03 01:43:44 PM PST 24 Jan 03 01:44:53 PM PST 24 1471158367 ps
T972 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2640637041 Jan 03 01:45:20 PM PST 24 Jan 03 01:47:19 PM PST 24 834917077 ps
T973 /workspace/coverage/default/8.sram_ctrl_max_throughput.2637862703 Jan 03 01:40:30 PM PST 24 Jan 03 01:43:22 PM PST 24 3177292435 ps
T974 /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2815903515 Jan 03 01:42:33 PM PST 24 Jan 03 01:52:19 PM PST 24 35817017988 ps
T975 /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1708459921 Jan 03 01:46:27 PM PST 24 Jan 03 02:40:34 PM PST 24 1094879962 ps
T976 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2303182617 Jan 03 01:41:40 PM PST 24 Jan 03 02:07:02 PM PST 24 8776135586 ps
T977 /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3670457808 Jan 03 01:46:39 PM PST 24 Jan 03 02:55:14 PM PST 24 2343869386 ps
T978 /workspace/coverage/default/48.sram_ctrl_ram_cfg.2866494768 Jan 03 01:46:58 PM PST 24 Jan 03 01:47:17 PM PST 24 1348730840 ps
T979 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2120863091 Jan 03 01:46:26 PM PST 24 Jan 03 01:47:50 PM PST 24 21756953407 ps
T980 /workspace/coverage/default/1.sram_ctrl_smoke.3131758997 Jan 03 01:39:55 PM PST 24 Jan 03 01:41:56 PM PST 24 925735162 ps
T981 /workspace/coverage/default/29.sram_ctrl_regwen.2466036902 Jan 03 01:44:56 PM PST 24 Jan 03 01:54:22 PM PST 24 10668556778 ps
T982 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2988661047 Jan 03 01:44:53 PM PST 24 Jan 03 01:52:10 PM PST 24 623299054 ps
T983 /workspace/coverage/default/43.sram_ctrl_mem_partial_access.3320303785 Jan 03 01:46:37 PM PST 24 Jan 03 01:49:15 PM PST 24 5171199975 ps
T984 /workspace/coverage/default/1.sram_ctrl_partial_access.2680693865 Jan 03 01:39:52 PM PST 24 Jan 03 01:42:36 PM PST 24 567872284 ps
T985 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2033736357 Jan 03 01:40:44 PM PST 24 Jan 03 03:26:28 PM PST 24 16958298521 ps
T986 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.3249048887 Jan 03 01:44:27 PM PST 24 Jan 03 01:50:03 PM PST 24 4880529939 ps
T987 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2186865451 Jan 03 01:45:25 PM PST 24 Jan 03 01:51:32 PM PST 24 48450097522 ps

Test location /workspace/coverage/default/38.sram_ctrl_stress_all.283890192
Short name T6
Test name
Test status
Simulation time 224436970696 ps
CPU time 8473.77 seconds
Started Jan 03 01:45:25 PM PST 24
Finished Jan 03 04:06:50 PM PST 24
Peak memory 381108 kb
Host smart-aead2be0-4ac0-4806-957c-db499dc695de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283890192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.sram_ctrl_stress_all.283890192
Directory /workspace/38.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all.4102315474
Short name T7
Test name
Test status
Simulation time 937048231170 ps
CPU time 4090.02 seconds
Started Jan 03 01:40:20 PM PST 24
Finished Jan 03 02:48:37 PM PST 24
Peak memory 388180 kb
Host smart-5d6cb3b4-ca94-489e-8d01-87be38ca1f39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102315474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.sram_ctrl_stress_all.4102315474
Directory /workspace/3.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3506588183
Short name T17
Test name
Test status
Simulation time 887676114 ps
CPU time 3965.77 seconds
Started Jan 03 01:43:35 PM PST 24
Finished Jan 03 02:49:42 PM PST 24
Peak memory 676284 kb
Host smart-b299ebdf-f807-417c-9936-afbb01038279
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3506588183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.3506588183
Directory /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3397768680
Short name T47
Test name
Test status
Simulation time 899819530 ps
CPU time 1.7 seconds
Started Jan 03 01:01:27 PM PST 24
Finished Jan 03 01:02:39 PM PST 24
Peak memory 202480 kb
Host smart-0904a754-f0b7-47d1-b151-6c2c70f891b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397768680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 16.sram_ctrl_tl_intg_err.3397768680
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.247004029
Short name T36
Test name
Test status
Simulation time 310646048 ps
CPU time 1.74 seconds
Started Jan 03 01:40:01 PM PST 24
Finished Jan 03 01:40:15 PM PST 24
Peak memory 220968 kb
Host smart-050714e0-20a5-4f63-8d10-d7063bc797ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247004029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_sec_cm.247004029
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3809220206
Short name T107
Test name
Test status
Simulation time 22600641895 ps
CPU time 317.68 seconds
Started Jan 03 01:39:44 PM PST 24
Finished Jan 03 01:45:07 PM PST 24
Peak memory 202200 kb
Host smart-5b1f8d32-1da3-47d3-b7ae-4609fe66f7fd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809220206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.sram_ctrl_partial_access_b2b.3809220206
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1007095577
Short name T63
Test name
Test status
Simulation time 7070349140 ps
CPU time 109.86 seconds
Started Jan 03 01:01:18 PM PST 24
Finished Jan 03 01:04:14 PM PST 24
Peak memory 202844 kb
Host smart-0e7d9fa9-b60e-4f48-a337-4f302f4fd0c2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007095577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.1007095577
Directory /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.376413455
Short name T19
Test name
Test status
Simulation time 8596698532 ps
CPU time 1097.57 seconds
Started Jan 03 01:41:14 PM PST 24
Finished Jan 03 01:59:36 PM PST 24
Peak memory 372924 kb
Host smart-8287e160-2263-4a07-b9e2-eeee6ccf882d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376413455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 7.sram_ctrl_access_during_key_req.376413455
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3317465098
Short name T113
Test name
Test status
Simulation time 248701257 ps
CPU time 1.96 seconds
Started Jan 03 01:01:18 PM PST 24
Finished Jan 03 01:02:26 PM PST 24
Peak memory 202444 kb
Host smart-b346180d-b0d1-44bd-a12b-141f3e1bc947
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317465098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.sram_ctrl_tl_intg_err.3317465098
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.2442142434
Short name T341
Test name
Test status
Simulation time 4694501680 ps
CPU time 1111.94 seconds
Started Jan 03 01:39:53 PM PST 24
Finished Jan 03 01:58:27 PM PST 24
Peak memory 378068 kb
Host smart-548e3441-b3de-4f3d-93a7-ffdab32b8787
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442142434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.2442142434
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.442273535
Short name T30
Test name
Test status
Simulation time 346192528 ps
CPU time 6.84 seconds
Started Jan 03 01:40:50 PM PST 24
Finished Jan 03 01:41:03 PM PST 24
Peak memory 202400 kb
Host smart-fce111a6-58e5-4275-9728-f9fa3a5bbc8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442273535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.442273535
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all.2684093456
Short name T132
Test name
Test status
Simulation time 769681399550 ps
CPU time 5725.1 seconds
Started Jan 03 01:41:14 PM PST 24
Finished Jan 03 03:16:45 PM PST 24
Peak memory 381172 kb
Host smart-76eda5cd-ef9a-4356-ae07-f3217f84b917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684093456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.sram_ctrl_stress_all.2684093456
Directory /workspace/13.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1777252612
Short name T120
Test name
Test status
Simulation time 154058808 ps
CPU time 1.98 seconds
Started Jan 03 01:01:33 PM PST 24
Finished Jan 03 01:02:47 PM PST 24
Peak memory 202432 kb
Host smart-2d2f0492-a97c-433d-a8d6-77c056280836
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777252612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 9.sram_ctrl_tl_intg_err.1777252612
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1494642100
Short name T117
Test name
Test status
Simulation time 386964075 ps
CPU time 2.02 seconds
Started Jan 03 01:01:18 PM PST 24
Finished Jan 03 01:02:26 PM PST 24
Peak memory 202388 kb
Host smart-89fe1c67-5617-4f23-a8bb-4b48f3e12659
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494642100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 15.sram_ctrl_tl_intg_err.1494642100
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.1009910950
Short name T263
Test name
Test status
Simulation time 19118864 ps
CPU time 0.68 seconds
Started Jan 03 01:39:58 PM PST 24
Finished Jan 03 01:40:07 PM PST 24
Peak memory 201368 kb
Host smart-b3ece5aa-f128-43ea-ae3b-392f805edc0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009910950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.1009910950
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.2976525247
Short name T329
Test name
Test status
Simulation time 11893625095 ps
CPU time 132.77 seconds
Started Jan 03 01:42:32 PM PST 24
Finished Jan 03 01:44:47 PM PST 24
Peak memory 202116 kb
Host smart-e4492e0d-ed21-4904-a75c-ac22e4bda394
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976525247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es
calation.2976525247
Directory /workspace/17.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2388897426
Short name T123
Test name
Test status
Simulation time 285611504 ps
CPU time 1.38 seconds
Started Jan 03 01:01:35 PM PST 24
Finished Jan 03 01:02:48 PM PST 24
Peak memory 202472 kb
Host smart-986ffe12-0738-457e-ac5b-b618ffa1ef61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388897426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_tl_intg_err.2388897426
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.sram_ctrl_executable.4091906082
Short name T420
Test name
Test status
Simulation time 23677918779 ps
CPU time 1383.43 seconds
Started Jan 03 01:42:05 PM PST 24
Finished Jan 03 02:05:15 PM PST 24
Peak memory 376100 kb
Host smart-d1f1bceb-2a1d-4454-89c7-aca518e40730
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091906082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab
le.4091906082
Directory /workspace/16.sram_ctrl_executable/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.509014845
Short name T196
Test name
Test status
Simulation time 18877568 ps
CPU time 0.69 seconds
Started Jan 03 01:01:16 PM PST 24
Finished Jan 03 01:02:23 PM PST 24
Peak memory 202064 kb
Host smart-f715c360-5047-409e-9878-4877148a010a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509014845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.sram_ctrl_csr_aliasing.509014845
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2234491142
Short name T204
Test name
Test status
Simulation time 521270251 ps
CPU time 1.58 seconds
Started Jan 03 01:01:10 PM PST 24
Finished Jan 03 01:02:18 PM PST 24
Peak memory 202352 kb
Host smart-3063f3a7-3afa-4dbd-be8e-2b675ec6e942
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234491142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_bit_bash.2234491142
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.285842736
Short name T222
Test name
Test status
Simulation time 15755470 ps
CPU time 0.68 seconds
Started Jan 03 01:01:15 PM PST 24
Finished Jan 03 01:02:22 PM PST 24
Peak memory 201520 kb
Host smart-aae16947-8526-4fee-951e-7ea3d81f8b35
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285842736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.sram_ctrl_csr_hw_reset.285842736
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4167759442
Short name T205
Test name
Test status
Simulation time 379707998 ps
CPU time 5.22 seconds
Started Jan 03 01:01:18 PM PST 24
Finished Jan 03 01:02:29 PM PST 24
Peak memory 202468 kb
Host smart-c15f2a82-f66a-4253-bf76-fff279a4c80b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167759442 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.4167759442
Directory /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3269718302
Short name T219
Test name
Test status
Simulation time 28630972 ps
CPU time 0.69 seconds
Started Jan 03 01:01:19 PM PST 24
Finished Jan 03 01:02:25 PM PST 24
Peak memory 201796 kb
Host smart-cb34c1cf-6dc3-435a-9087-5c16e0d79814
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269718302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_csr_rw.3269718302
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4120831145
Short name T216
Test name
Test status
Simulation time 4343162073 ps
CPU time 144.28 seconds
Started Jan 03 01:01:21 PM PST 24
Finished Jan 03 01:04:52 PM PST 24
Peak memory 202568 kb
Host smart-9efa6de4-0f46-4dd6-9666-c7b93ffbd6db
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120831145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.4120831145
Directory /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2127395635
Short name T153
Test name
Test status
Simulation time 28509969 ps
CPU time 0.69 seconds
Started Jan 03 01:01:13 PM PST 24
Finished Jan 03 01:02:20 PM PST 24
Peak memory 202212 kb
Host smart-afdfdac0-68f5-4373-bc22-e58a22e4fca1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127395635 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.2127395635
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.522489648
Short name T173
Test name
Test status
Simulation time 63605527 ps
CPU time 2.99 seconds
Started Jan 03 01:01:14 PM PST 24
Finished Jan 03 01:02:22 PM PST 24
Peak memory 202440 kb
Host smart-7955ccce-dd7a-4a70-8bb1-fa1dbecf6194
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522489648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_tl_errors.522489648
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1385893839
Short name T121
Test name
Test status
Simulation time 136653464 ps
CPU time 1.88 seconds
Started Jan 03 01:01:20 PM PST 24
Finished Jan 03 01:02:29 PM PST 24
Peak memory 202464 kb
Host smart-625756d7-f019-498f-bb25-90d4ee889903
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385893839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.sram_ctrl_tl_intg_err.1385893839
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3356717420
Short name T164
Test name
Test status
Simulation time 21800344 ps
CPU time 0.63 seconds
Started Jan 03 01:01:19 PM PST 24
Finished Jan 03 01:02:26 PM PST 24
Peak memory 201300 kb
Host smart-dc8b4a75-cf6f-47b1-987a-d0d90d1fdcf4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356717420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_aliasing.3356717420
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2256607454
Short name T192
Test name
Test status
Simulation time 68876638 ps
CPU time 1.63 seconds
Started Jan 03 01:01:20 PM PST 24
Finished Jan 03 01:02:29 PM PST 24
Peak memory 201672 kb
Host smart-cada42c9-0de5-46cc-a7de-d7d6e8405c55
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256607454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_bit_bash.2256607454
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2076854166
Short name T187
Test name
Test status
Simulation time 15530188 ps
CPU time 0.66 seconds
Started Jan 03 01:01:13 PM PST 24
Finished Jan 03 01:02:19 PM PST 24
Peak memory 201364 kb
Host smart-abbb0858-2294-4c0f-8c1e-0023fa6c0817
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076854166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_hw_reset.2076854166
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.701472062
Short name T90
Test name
Test status
Simulation time 5670656641 ps
CPU time 12.82 seconds
Started Jan 03 01:01:25 PM PST 24
Finished Jan 03 01:02:47 PM PST 24
Peak memory 210668 kb
Host smart-70e2615d-fc8a-431f-8b62-8ca521e6ea7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701472062 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.701472062
Directory /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3239530245
Short name T151
Test name
Test status
Simulation time 17272836 ps
CPU time 0.63 seconds
Started Jan 03 01:01:20 PM PST 24
Finished Jan 03 01:02:27 PM PST 24
Peak memory 201560 kb
Host smart-0302c9c4-cdf2-43d2-a298-542176b14c84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239530245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_csr_rw.3239530245
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3393566972
Short name T147
Test name
Test status
Simulation time 40767575 ps
CPU time 0.73 seconds
Started Jan 03 01:01:13 PM PST 24
Finished Jan 03 01:02:19 PM PST 24
Peak memory 202196 kb
Host smart-7f3bb258-2140-4af5-9736-15aa10cc85de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393566972 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.3393566972
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2030676828
Short name T155
Test name
Test status
Simulation time 57648478 ps
CPU time 2.09 seconds
Started Jan 03 01:01:28 PM PST 24
Finished Jan 03 01:02:39 PM PST 24
Peak memory 202448 kb
Host smart-7ae7b198-0deb-4404-b2b1-d511846c05f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030676828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.sram_ctrl_tl_errors.2030676828
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1031831967
Short name T176
Test name
Test status
Simulation time 206551256 ps
CPU time 2.39 seconds
Started Jan 03 01:01:16 PM PST 24
Finished Jan 03 01:02:25 PM PST 24
Peak memory 202504 kb
Host smart-8ed53b0e-5369-40cb-b787-d57aa56cedc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031831967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.sram_ctrl_tl_intg_err.1031831967
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1549660097
Short name T163
Test name
Test status
Simulation time 1762969419 ps
CPU time 5.14 seconds
Started Jan 03 01:01:18 PM PST 24
Finished Jan 03 01:02:29 PM PST 24
Peak memory 210624 kb
Host smart-60a23fa4-0dcd-4c98-b817-19f9f74fd595
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549660097 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.1549660097
Directory /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.649034705
Short name T201
Test name
Test status
Simulation time 19236859 ps
CPU time 0.62 seconds
Started Jan 03 01:01:19 PM PST 24
Finished Jan 03 01:02:25 PM PST 24
Peak memory 201332 kb
Host smart-75e8f6ff-7f5e-4921-975c-3e88b467ab4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649034705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 10.sram_ctrl_csr_rw.649034705
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2767917918
Short name T94
Test name
Test status
Simulation time 28154496248 ps
CPU time 281.9 seconds
Started Jan 03 01:01:17 PM PST 24
Finished Jan 03 01:07:08 PM PST 24
Peak memory 202600 kb
Host smart-eed8211a-21da-49b4-8e21-5454640b7a9b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767917918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.2767917918
Directory /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3785382488
Short name T148
Test name
Test status
Simulation time 66741775 ps
CPU time 0.71 seconds
Started Jan 03 01:01:26 PM PST 24
Finished Jan 03 01:02:37 PM PST 24
Peak memory 202260 kb
Host smart-410a9010-ab33-45e6-b3bf-f6bb184849e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785382488 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.3785382488
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.129045338
Short name T182
Test name
Test status
Simulation time 455286571 ps
CPU time 3.64 seconds
Started Jan 03 01:01:22 PM PST 24
Finished Jan 03 01:02:33 PM PST 24
Peak memory 202428 kb
Host smart-6e731cce-fbcc-4e47-90c1-61726cb3bcc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129045338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_tl_errors.129045338
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3786959949
Short name T119
Test name
Test status
Simulation time 392399040 ps
CPU time 1.42 seconds
Started Jan 03 01:01:34 PM PST 24
Finished Jan 03 01:02:47 PM PST 24
Peak memory 202452 kb
Host smart-ca91b1f0-67ef-422b-ac00-3fbe08b18a4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786959949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 10.sram_ctrl_tl_intg_err.3786959949
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2180145492
Short name T185
Test name
Test status
Simulation time 358348426 ps
CPU time 12.36 seconds
Started Jan 03 01:01:26 PM PST 24
Finished Jan 03 01:02:47 PM PST 24
Peak memory 210676 kb
Host smart-a8918aef-f376-4d91-bd89-e4cbb23927fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180145492 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.2180145492
Directory /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3652478695
Short name T199
Test name
Test status
Simulation time 12800559 ps
CPU time 0.62 seconds
Started Jan 03 01:01:16 PM PST 24
Finished Jan 03 01:02:23 PM PST 24
Peak memory 202128 kb
Host smart-2e54f254-bd69-473e-9bb5-14534d97776d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652478695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_csr_rw.3652478695
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.412454416
Short name T167
Test name
Test status
Simulation time 27221823319 ps
CPU time 122.34 seconds
Started Jan 03 01:01:14 PM PST 24
Finished Jan 03 01:04:23 PM PST 24
Peak memory 202492 kb
Host smart-e262a274-b3f5-4e62-8ebb-f9e5511f5ce5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412454416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.412454416
Directory /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.799181033
Short name T161
Test name
Test status
Simulation time 29754612 ps
CPU time 0.67 seconds
Started Jan 03 01:01:22 PM PST 24
Finished Jan 03 01:02:30 PM PST 24
Peak memory 202216 kb
Host smart-4ea93d69-f88e-491b-82c9-13063f6bba50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799181033 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.799181033
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1094705388
Short name T207
Test name
Test status
Simulation time 798533789 ps
CPU time 2.86 seconds
Started Jan 03 01:01:15 PM PST 24
Finished Jan 03 01:02:24 PM PST 24
Peak memory 210724 kb
Host smart-385820f1-f8f5-4007-aff2-4d2d08b03a4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094705388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.sram_ctrl_tl_errors.1094705388
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.848437820
Short name T210
Test name
Test status
Simulation time 135015925 ps
CPU time 1.31 seconds
Started Jan 03 01:01:18 PM PST 24
Finished Jan 03 01:02:25 PM PST 24
Peak memory 202452 kb
Host smart-dab30f4c-0473-4649-a1f3-059ebdb1aa1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848437820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 11.sram_ctrl_tl_intg_err.848437820
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.252796584
Short name T50
Test name
Test status
Simulation time 363258980 ps
CPU time 13.98 seconds
Started Jan 03 01:01:28 PM PST 24
Finished Jan 03 01:02:52 PM PST 24
Peak memory 210656 kb
Host smart-199d0ba2-9487-4caa-b502-b16aba87e69b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252796584 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.252796584
Directory /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2023458192
Short name T179
Test name
Test status
Simulation time 43242747 ps
CPU time 0.64 seconds
Started Jan 03 01:01:23 PM PST 24
Finished Jan 03 01:02:31 PM PST 24
Peak memory 202164 kb
Host smart-dc4c5569-1611-42cd-954a-5751947f6175
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023458192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_csr_rw.2023458192
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.633459085
Short name T200
Test name
Test status
Simulation time 10867388873 ps
CPU time 120.19 seconds
Started Jan 03 01:01:20 PM PST 24
Finished Jan 03 01:04:27 PM PST 24
Peak memory 202476 kb
Host smart-1861af78-ff82-4a77-a59f-0a8abba2c8f6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633459085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.633459085
Directory /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2822043621
Short name T158
Test name
Test status
Simulation time 41951424 ps
CPU time 0.68 seconds
Started Jan 03 01:01:22 PM PST 24
Finished Jan 03 01:02:29 PM PST 24
Peak memory 202296 kb
Host smart-8f637363-4715-4ed3-986b-ff6c536bf554
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822043621 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.2822043621
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2066850733
Short name T166
Test name
Test status
Simulation time 73262266 ps
CPU time 2.59 seconds
Started Jan 03 01:01:17 PM PST 24
Finished Jan 03 01:02:27 PM PST 24
Peak memory 202356 kb
Host smart-9595edcb-9c92-43e6-8936-eac51f6b1124
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066850733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.sram_ctrl_tl_errors.2066850733
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2517677269
Short name T116
Test name
Test status
Simulation time 133649222 ps
CPU time 1.33 seconds
Started Jan 03 01:01:28 PM PST 24
Finished Jan 03 01:02:39 PM PST 24
Peak memory 202308 kb
Host smart-244f0474-2a37-4b8e-9d06-db8c91651409
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517677269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 12.sram_ctrl_tl_intg_err.2517677269
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1016354524
Short name T51
Test name
Test status
Simulation time 663789768 ps
CPU time 5.25 seconds
Started Jan 03 01:01:18 PM PST 24
Finished Jan 03 01:02:31 PM PST 24
Peak memory 202380 kb
Host smart-026f4053-fe6f-48eb-8088-987400163d27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016354524 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.1016354524
Directory /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3187008596
Short name T69
Test name
Test status
Simulation time 49901110 ps
CPU time 0.66 seconds
Started Jan 03 01:01:18 PM PST 24
Finished Jan 03 01:02:25 PM PST 24
Peak memory 201424 kb
Host smart-e2fa27cc-db4f-4524-b5f8-a849e36d1895
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187008596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_csr_rw.3187008596
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.499288953
Short name T98
Test name
Test status
Simulation time 26111237070 ps
CPU time 109.55 seconds
Started Jan 03 01:01:22 PM PST 24
Finished Jan 03 01:04:19 PM PST 24
Peak memory 210648 kb
Host smart-b8d10d09-e517-498e-bf5b-37703dcd00b2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499288953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.499288953
Directory /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.449735324
Short name T172
Test name
Test status
Simulation time 117734530 ps
CPU time 0.68 seconds
Started Jan 03 01:01:34 PM PST 24
Finished Jan 03 01:02:47 PM PST 24
Peak memory 202260 kb
Host smart-0dcecf78-1ef4-4977-ba90-0e5541bf406f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449735324 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.449735324
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1233648944
Short name T214
Test name
Test status
Simulation time 212999484 ps
CPU time 2.05 seconds
Started Jan 03 01:01:24 PM PST 24
Finished Jan 03 01:02:34 PM PST 24
Peak memory 202328 kb
Host smart-26d2c913-6048-4d58-a9ff-a5b8e539a68e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233648944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.sram_ctrl_tl_errors.1233648944
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.497130470
Short name T183
Test name
Test status
Simulation time 1367999297 ps
CPU time 4.82 seconds
Started Jan 03 01:01:28 PM PST 24
Finished Jan 03 01:02:42 PM PST 24
Peak memory 202372 kb
Host smart-b60cdc35-8f60-46ee-b58a-dc6b3de26097
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497130470 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.497130470
Directory /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2796038735
Short name T73
Test name
Test status
Simulation time 44268860 ps
CPU time 0.65 seconds
Started Jan 03 01:01:34 PM PST 24
Finished Jan 03 01:02:47 PM PST 24
Peak memory 201364 kb
Host smart-9926db15-33b9-4b62-a723-5f297b92eb15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796038735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_csr_rw.2796038735
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.121270921
Short name T93
Test name
Test status
Simulation time 11991625817 ps
CPU time 152.83 seconds
Started Jan 03 01:01:34 PM PST 24
Finished Jan 03 01:05:19 PM PST 24
Peak memory 210740 kb
Host smart-a9d1c877-b481-4777-ac7e-0b550dfc9861
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121270921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.121270921
Directory /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.183566485
Short name T178
Test name
Test status
Simulation time 27592781 ps
CPU time 0.69 seconds
Started Jan 03 01:01:13 PM PST 24
Finished Jan 03 01:02:19 PM PST 24
Peak memory 202076 kb
Host smart-024cfada-0f92-4798-a50d-e802aee61b43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183566485 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.183566485
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4091182025
Short name T62
Test name
Test status
Simulation time 80422056 ps
CPU time 2.72 seconds
Started Jan 03 01:01:24 PM PST 24
Finished Jan 03 01:02:36 PM PST 24
Peak memory 202404 kb
Host smart-7af06e4e-5473-43e7-8b73-1e98df3c6ed7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091182025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.sram_ctrl_tl_errors.4091182025
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4230664930
Short name T118
Test name
Test status
Simulation time 161781671 ps
CPU time 1.99 seconds
Started Jan 03 01:01:25 PM PST 24
Finished Jan 03 01:02:36 PM PST 24
Peak memory 202432 kb
Host smart-d8afc7d0-2df1-4540-bb69-d378da99a86d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230664930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 14.sram_ctrl_tl_intg_err.4230664930
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3226835580
Short name T215
Test name
Test status
Simulation time 351216920 ps
CPU time 13.27 seconds
Started Jan 03 01:01:25 PM PST 24
Finished Jan 03 01:02:47 PM PST 24
Peak memory 210760 kb
Host smart-bdb216ed-12a5-4122-96b6-ab74a3ee709c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226835580 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.3226835580
Directory /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2661123375
Short name T77
Test name
Test status
Simulation time 21042680 ps
CPU time 0.73 seconds
Started Jan 03 01:01:27 PM PST 24
Finished Jan 03 01:02:38 PM PST 24
Peak memory 202124 kb
Host smart-f9ff4dec-a283-45b9-b161-bf5b3d93e23a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661123375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_csr_rw.2661123375
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2359882564
Short name T82
Test name
Test status
Simulation time 7368603732 ps
CPU time 50.43 seconds
Started Jan 03 01:01:27 PM PST 24
Finished Jan 03 01:03:27 PM PST 24
Peak memory 202480 kb
Host smart-89f3c770-3426-4d17-b1a0-cbdc71b54b98
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359882564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.2359882564
Directory /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1020348451
Short name T224
Test name
Test status
Simulation time 14421390 ps
CPU time 0.65 seconds
Started Jan 03 01:01:27 PM PST 24
Finished Jan 03 01:02:38 PM PST 24
Peak memory 202180 kb
Host smart-ca9fdbed-531a-4a02-bd21-38784a64aa03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020348451 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.1020348451
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3372322918
Short name T195
Test name
Test status
Simulation time 26914875 ps
CPU time 2.37 seconds
Started Jan 03 01:01:34 PM PST 24
Finished Jan 03 01:02:48 PM PST 24
Peak memory 202384 kb
Host smart-fa719c65-3c0e-4253-92f4-eb5e975bf279
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372322918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.sram_ctrl_tl_errors.3372322918
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1927125440
Short name T184
Test name
Test status
Simulation time 702486560 ps
CPU time 12.91 seconds
Started Jan 03 01:01:28 PM PST 24
Finished Jan 03 01:02:50 PM PST 24
Peak memory 210760 kb
Host smart-faa7a874-ea1e-4bd5-a514-e49d74a3faf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927125440 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.1927125440
Directory /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2565509140
Short name T180
Test name
Test status
Simulation time 70358414 ps
CPU time 0.68 seconds
Started Jan 03 01:01:45 PM PST 24
Finished Jan 03 01:02:58 PM PST 24
Peak memory 201332 kb
Host smart-2db62a8f-a054-43c2-a440-d39dd51d81fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565509140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_csr_rw.2565509140
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1773362323
Short name T91
Test name
Test status
Simulation time 7220318022 ps
CPU time 268.87 seconds
Started Jan 03 01:01:25 PM PST 24
Finished Jan 03 01:07:03 PM PST 24
Peak memory 210716 kb
Host smart-dbd7da48-9313-4c2c-a6f0-c6df6b382c9e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773362323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.1773362323
Directory /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3267353679
Short name T177
Test name
Test status
Simulation time 136264832 ps
CPU time 0.71 seconds
Started Jan 03 01:01:27 PM PST 24
Finished Jan 03 01:02:38 PM PST 24
Peak memory 201884 kb
Host smart-3ca81cac-5b67-442c-b3c3-e837c68b964b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267353679 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.3267353679
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.176359358
Short name T202
Test name
Test status
Simulation time 32840426 ps
CPU time 2.17 seconds
Started Jan 03 01:01:28 PM PST 24
Finished Jan 03 01:02:39 PM PST 24
Peak memory 202492 kb
Host smart-c3aa8386-543e-47b0-9da0-90254c0e4353
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176359358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_tl_errors.176359358
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2357066039
Short name T191
Test name
Test status
Simulation time 473498014 ps
CPU time 12.3 seconds
Started Jan 03 01:01:26 PM PST 24
Finished Jan 03 01:02:47 PM PST 24
Peak memory 210572 kb
Host smart-f9fc45f2-bb68-4b3d-a1ed-e829aa413cea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357066039 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.2357066039
Directory /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2737944466
Short name T223
Test name
Test status
Simulation time 41104877 ps
CPU time 0.63 seconds
Started Jan 03 01:01:24 PM PST 24
Finished Jan 03 01:02:33 PM PST 24
Peak memory 201400 kb
Host smart-55ba7076-cdc6-4135-8110-df11c8ebf749
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737944466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_csr_rw.2737944466
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3795864781
Short name T96
Test name
Test status
Simulation time 26088499845 ps
CPU time 120.46 seconds
Started Jan 03 01:01:29 PM PST 24
Finished Jan 03 01:04:41 PM PST 24
Peak memory 210736 kb
Host smart-38807136-e2cf-41cb-80c1-8bee16754438
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795864781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.3795864781
Directory /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3668047758
Short name T174
Test name
Test status
Simulation time 31112659 ps
CPU time 0.65 seconds
Started Jan 03 01:01:24 PM PST 24
Finished Jan 03 01:02:32 PM PST 24
Peak memory 202212 kb
Host smart-5423db08-450b-4e6f-8779-7a59e3c7dbbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668047758 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.3668047758
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2279113543
Short name T95
Test name
Test status
Simulation time 175900858 ps
CPU time 3.5 seconds
Started Jan 03 01:01:33 PM PST 24
Finished Jan 03 01:02:48 PM PST 24
Peak memory 202480 kb
Host smart-14b805ab-4970-4b66-9780-44616e6f0c16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279113543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.sram_ctrl_tl_errors.2279113543
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1117034420
Short name T221
Test name
Test status
Simulation time 187330500 ps
CPU time 1.54 seconds
Started Jan 03 01:01:24 PM PST 24
Finished Jan 03 01:02:33 PM PST 24
Peak memory 202308 kb
Host smart-9e3af0c6-b19e-4441-80fd-4f09e31fe2a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117034420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 17.sram_ctrl_tl_intg_err.1117034420
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1037135334
Short name T208
Test name
Test status
Simulation time 1428768887 ps
CPU time 5.18 seconds
Started Jan 03 01:01:29 PM PST 24
Finished Jan 03 01:02:45 PM PST 24
Peak memory 210640 kb
Host smart-8eed4191-99d8-48b1-8305-15ab1ff1702e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037135334 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.1037135334
Directory /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3692353364
Short name T212
Test name
Test status
Simulation time 62734159 ps
CPU time 0.62 seconds
Started Jan 03 01:01:30 PM PST 24
Finished Jan 03 01:02:41 PM PST 24
Peak memory 202144 kb
Host smart-5676aab7-2074-4c8a-b11d-398c68b7c2d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692353364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_csr_rw.3692353364
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2281992478
Short name T79
Test name
Test status
Simulation time 3766385115 ps
CPU time 51.77 seconds
Started Jan 03 01:01:29 PM PST 24
Finished Jan 03 01:03:32 PM PST 24
Peak memory 202400 kb
Host smart-9bcf95a8-a959-4217-bd39-87a487605f6a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281992478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.2281992478
Directory /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.362787303
Short name T102
Test name
Test status
Simulation time 23029153 ps
CPU time 0.71 seconds
Started Jan 03 01:01:29 PM PST 24
Finished Jan 03 01:02:41 PM PST 24
Peak memory 202280 kb
Host smart-c0359748-1863-4b8c-99a6-82c83db0f6cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362787303 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.362787303
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.308526616
Short name T152
Test name
Test status
Simulation time 59380290 ps
CPU time 2.16 seconds
Started Jan 03 01:01:29 PM PST 24
Finished Jan 03 01:02:42 PM PST 24
Peak memory 202416 kb
Host smart-f920218a-6712-4462-ae12-cc3f649d0a8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308526616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_tl_errors.308526616
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3328512450
Short name T125
Test name
Test status
Simulation time 196989097 ps
CPU time 1.44 seconds
Started Jan 03 01:01:31 PM PST 24
Finished Jan 03 01:02:44 PM PST 24
Peak memory 202408 kb
Host smart-e5b9fe78-fc29-44b3-87a2-b8e36a34e799
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328512450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 18.sram_ctrl_tl_intg_err.3328512450
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1833923425
Short name T211
Test name
Test status
Simulation time 1366618593 ps
CPU time 6.26 seconds
Started Jan 03 01:01:25 PM PST 24
Finished Jan 03 01:02:40 PM PST 24
Peak memory 202380 kb
Host smart-95f25826-bfa6-4eb6-b573-4cc2c401ec48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833923425 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.1833923425
Directory /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1919713113
Short name T76
Test name
Test status
Simulation time 21783484 ps
CPU time 0.67 seconds
Started Jan 03 01:01:35 PM PST 24
Finished Jan 03 01:02:48 PM PST 24
Peak memory 202100 kb
Host smart-2f567db7-70b5-4cf1-bcc1-0f0aed134458
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919713113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_csr_rw.1919713113
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1391287503
Short name T80
Test name
Test status
Simulation time 117472386042 ps
CPU time 107.48 seconds
Started Jan 03 01:01:15 PM PST 24
Finished Jan 03 01:04:08 PM PST 24
Peak memory 202564 kb
Host smart-502e5fd8-b190-4c08-a485-caa29a6ca387
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391287503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.1391287503
Directory /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1127274449
Short name T188
Test name
Test status
Simulation time 46131920 ps
CPU time 0.72 seconds
Started Jan 03 01:01:40 PM PST 24
Finished Jan 03 01:02:53 PM PST 24
Peak memory 202236 kb
Host smart-1779500d-1046-4f6c-9a4b-d2809fa5ca92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127274449 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.1127274449
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1353667359
Short name T218
Test name
Test status
Simulation time 142910522 ps
CPU time 3.43 seconds
Started Jan 03 01:01:20 PM PST 24
Finished Jan 03 01:02:30 PM PST 24
Peak memory 202488 kb
Host smart-e8136aa3-dfb6-491a-9150-ec88cb1906f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353667359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.sram_ctrl_tl_errors.1353667359
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3597784699
Short name T49
Test name
Test status
Simulation time 1320192434 ps
CPU time 2.02 seconds
Started Jan 03 01:01:43 PM PST 24
Finished Jan 03 01:02:58 PM PST 24
Peak memory 202520 kb
Host smart-eb4d2d4c-355e-45e3-8ef0-39b91b9f03fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597784699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_tl_intg_err.3597784699
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3270075034
Short name T99
Test name
Test status
Simulation time 13088553 ps
CPU time 0.65 seconds
Started Jan 03 01:01:23 PM PST 24
Finished Jan 03 01:02:31 PM PST 24
Peak memory 201220 kb
Host smart-d54e8f5f-f992-4a89-bf7f-0b2428e988c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270075034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_aliasing.3270075034
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4044734494
Short name T170
Test name
Test status
Simulation time 208410252 ps
CPU time 2.08 seconds
Started Jan 03 01:01:27 PM PST 24
Finished Jan 03 01:02:39 PM PST 24
Peak memory 202052 kb
Host smart-093a3ec4-b9f8-4119-b65b-34bff9fd9048
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044734494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_bit_bash.4044734494
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2445875922
Short name T149
Test name
Test status
Simulation time 43212424 ps
CPU time 0.65 seconds
Started Jan 03 01:01:24 PM PST 24
Finished Jan 03 01:02:32 PM PST 24
Peak memory 201788 kb
Host smart-ede85ebc-83de-42a0-a969-e67fe225823a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445875922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_hw_reset.2445875922
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1311980125
Short name T53
Test name
Test status
Simulation time 352113870 ps
CPU time 12.28 seconds
Started Jan 03 01:01:29 PM PST 24
Finished Jan 03 01:02:52 PM PST 24
Peak memory 210612 kb
Host smart-c5cc3089-dc8b-4a71-86f2-d95e01765a8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311980125 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.1311980125
Directory /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3275797881
Short name T101
Test name
Test status
Simulation time 43375888 ps
CPU time 0.64 seconds
Started Jan 03 01:01:22 PM PST 24
Finished Jan 03 01:02:29 PM PST 24
Peak memory 202156 kb
Host smart-9f620fbf-6b56-4062-8f40-b88ff300263c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275797881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_csr_rw.3275797881
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4105747192
Short name T65
Test name
Test status
Simulation time 7471622119 ps
CPU time 140.89 seconds
Started Jan 03 01:01:20 PM PST 24
Finished Jan 03 01:04:48 PM PST 24
Peak memory 202564 kb
Host smart-ee287a13-1381-42a8-81dd-7b4a50045130
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105747192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.4105747192
Directory /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.905127262
Short name T169
Test name
Test status
Simulation time 45315820 ps
CPU time 0.69 seconds
Started Jan 03 01:01:26 PM PST 24
Finished Jan 03 01:02:35 PM PST 24
Peak memory 201968 kb
Host smart-6e946927-f146-487d-8f9b-bd4700bce52d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905127262 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.905127262
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2635458641
Short name T154
Test name
Test status
Simulation time 63512268 ps
CPU time 2.25 seconds
Started Jan 03 01:01:17 PM PST 24
Finished Jan 03 01:02:26 PM PST 24
Peak memory 202404 kb
Host smart-3405c597-2d90-431d-879b-8dc91d78faca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635458641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.sram_ctrl_tl_errors.2635458641
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.429207131
Short name T115
Test name
Test status
Simulation time 591166944 ps
CPU time 2.17 seconds
Started Jan 03 01:01:27 PM PST 24
Finished Jan 03 01:02:39 PM PST 24
Peak memory 202340 kb
Host smart-b57c5a08-635f-40f1-bf54-db296785c102
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429207131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 2.sram_ctrl_tl_intg_err.429207131
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2143552437
Short name T33
Test name
Test status
Simulation time 14495096 ps
CPU time 0.65 seconds
Started Jan 03 01:01:28 PM PST 24
Finished Jan 03 01:02:38 PM PST 24
Peak memory 202164 kb
Host smart-5b877ad4-2e7e-4f57-b30f-bbe5fa6e97a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143552437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_aliasing.2143552437
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.679812184
Short name T160
Test name
Test status
Simulation time 367380113 ps
CPU time 1.35 seconds
Started Jan 03 01:01:21 PM PST 24
Finished Jan 03 01:02:29 PM PST 24
Peak memory 202312 kb
Host smart-5dcfa75f-7e73-4d91-ace5-9f298afc9172
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679812184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.sram_ctrl_csr_bit_bash.679812184
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3995764353
Short name T68
Test name
Test status
Simulation time 37931575 ps
CPU time 0.61 seconds
Started Jan 03 01:01:22 PM PST 24
Finished Jan 03 01:02:29 PM PST 24
Peak memory 201340 kb
Host smart-3fdfbd16-c03a-4522-bd6c-f47fadd243ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995764353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_hw_reset.3995764353
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3629029925
Short name T78
Test name
Test status
Simulation time 354223776 ps
CPU time 12.42 seconds
Started Jan 03 01:01:30 PM PST 24
Finished Jan 03 01:02:53 PM PST 24
Peak memory 210660 kb
Host smart-bc62ec82-2bb3-4c37-b52d-be8459e1122c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629029925 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.3629029925
Directory /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2029345734
Short name T168
Test name
Test status
Simulation time 45919646 ps
CPU time 0.63 seconds
Started Jan 03 01:01:19 PM PST 24
Finished Jan 03 01:02:27 PM PST 24
Peak memory 201360 kb
Host smart-a406afe7-7cb1-422a-b0d2-595ade4637ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029345734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_csr_rw.2029345734
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1107346269
Short name T83
Test name
Test status
Simulation time 32008526703 ps
CPU time 286.8 seconds
Started Jan 03 01:01:25 PM PST 24
Finished Jan 03 01:07:21 PM PST 24
Peak memory 202552 kb
Host smart-f7563c0a-7aeb-4c14-9988-d12e6e6978ec
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107346269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.1107346269
Directory /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2335320115
Short name T150
Test name
Test status
Simulation time 32842380 ps
CPU time 0.7 seconds
Started Jan 03 01:01:34 PM PST 24
Finished Jan 03 01:02:47 PM PST 24
Peak memory 202272 kb
Host smart-946fdda3-5b90-49dd-8220-fe5732668db6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335320115 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.2335320115
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.917211389
Short name T56
Test name
Test status
Simulation time 79160308 ps
CPU time 1.81 seconds
Started Jan 03 01:01:19 PM PST 24
Finished Jan 03 01:02:26 PM PST 24
Peak memory 202388 kb
Host smart-03e29121-2965-4c00-b7db-e8aabdabe9ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917211389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_tl_errors.917211389
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.271039936
Short name T124
Test name
Test status
Simulation time 334190046 ps
CPU time 2.12 seconds
Started Jan 03 01:01:21 PM PST 24
Finished Jan 03 01:02:29 PM PST 24
Peak memory 202456 kb
Host smart-df2cda6b-bf36-41cf-9f41-80d0ce582b1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271039936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.sram_ctrl_tl_intg_err.271039936
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4176758253
Short name T193
Test name
Test status
Simulation time 18055821 ps
CPU time 0.7 seconds
Started Jan 03 01:01:19 PM PST 24
Finished Jan 03 01:02:27 PM PST 24
Peak memory 202100 kb
Host smart-8f11cb86-28d7-469e-91ef-4c9ce8051ce8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176758253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_aliasing.4176758253
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1492525735
Short name T64
Test name
Test status
Simulation time 150205071 ps
CPU time 1.9 seconds
Started Jan 03 01:01:28 PM PST 24
Finished Jan 03 01:02:41 PM PST 24
Peak memory 202356 kb
Host smart-fa5da575-22c0-4dae-878a-c61bf18bda9d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492525735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_bit_bash.1492525735
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1347971952
Short name T217
Test name
Test status
Simulation time 35563040 ps
CPU time 0.62 seconds
Started Jan 03 01:01:25 PM PST 24
Finished Jan 03 01:02:35 PM PST 24
Peak memory 201604 kb
Host smart-96d9adc3-53fe-4772-9002-3ee62981abed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347971952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_hw_reset.1347971952
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3202539249
Short name T97
Test name
Test status
Simulation time 1352150800 ps
CPU time 5.99 seconds
Started Jan 03 01:01:26 PM PST 24
Finished Jan 03 01:02:40 PM PST 24
Peak memory 202440 kb
Host smart-9244be61-8fe5-45ed-aaad-bbb6dd67b539
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202539249 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.3202539249
Directory /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3419415800
Short name T225
Test name
Test status
Simulation time 17369812 ps
CPU time 0.66 seconds
Started Jan 03 01:01:27 PM PST 24
Finished Jan 03 01:02:38 PM PST 24
Peak memory 202140 kb
Host smart-b7c51d8d-fc2a-4182-a5c3-be71dd9407a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419415800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.3419415800
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1865654508
Short name T213
Test name
Test status
Simulation time 7539649712 ps
CPU time 111.23 seconds
Started Jan 03 01:01:40 PM PST 24
Finished Jan 03 01:04:44 PM PST 24
Peak memory 202540 kb
Host smart-1e0461df-e97f-499e-9476-94d656d2f362
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865654508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.1865654508
Directory /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1252463734
Short name T156
Test name
Test status
Simulation time 48657420 ps
CPU time 0.76 seconds
Started Jan 03 01:01:15 PM PST 24
Finished Jan 03 01:02:27 PM PST 24
Peak memory 202108 kb
Host smart-41c670c1-126e-4330-a017-6b47c1084ba3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252463734 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.1252463734
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2607181082
Short name T54
Test name
Test status
Simulation time 223765872 ps
CPU time 2.24 seconds
Started Jan 03 01:01:25 PM PST 24
Finished Jan 03 01:02:36 PM PST 24
Peak memory 202328 kb
Host smart-99f975ba-1f6b-48d1-9050-1fa385d03577
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607181082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.sram_ctrl_tl_errors.2607181082
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1108635342
Short name T122
Test name
Test status
Simulation time 158536793 ps
CPU time 1.56 seconds
Started Jan 03 01:01:25 PM PST 24
Finished Jan 03 01:02:36 PM PST 24
Peak memory 202356 kb
Host smart-73997b99-9746-4ba6-b1a2-d587d2d39d34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108635342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.sram_ctrl_tl_intg_err.1108635342
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4046241117
Short name T55
Test name
Test status
Simulation time 1365632832 ps
CPU time 13.1 seconds
Started Jan 03 01:01:25 PM PST 24
Finished Jan 03 01:02:47 PM PST 24
Peak memory 210620 kb
Host smart-62f25fc7-ef74-4ff8-aa35-712ec7642b28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046241117 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.4046241117
Directory /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2298942759
Short name T181
Test name
Test status
Simulation time 31159768 ps
CPU time 0.6 seconds
Started Jan 03 01:01:20 PM PST 24
Finished Jan 03 01:02:27 PM PST 24
Peak memory 202224 kb
Host smart-0a3fb1a9-c556-4cf1-8b7f-3435a7334814
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298942759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_csr_rw.2298942759
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1957987955
Short name T220
Test name
Test status
Simulation time 7740828876 ps
CPU time 52.72 seconds
Started Jan 03 01:01:18 PM PST 24
Finished Jan 03 01:03:17 PM PST 24
Peak memory 210692 kb
Host smart-598927b1-93f5-4bd0-a62e-b9dbe4e1bdff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957987955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.1957987955
Directory /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3968215916
Short name T159
Test name
Test status
Simulation time 21280775 ps
CPU time 0.74 seconds
Started Jan 03 01:01:16 PM PST 24
Finished Jan 03 01:02:23 PM PST 24
Peak memory 202220 kb
Host smart-39213a5b-fd4a-41fd-83af-27629c8260aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968215916 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.3968215916
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2857381688
Short name T171
Test name
Test status
Simulation time 30881722 ps
CPU time 2.74 seconds
Started Jan 03 01:01:26 PM PST 24
Finished Jan 03 01:02:38 PM PST 24
Peak memory 202440 kb
Host smart-4131cc91-6419-4b04-b05e-025eccd3d630
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857381688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.sram_ctrl_tl_errors.2857381688
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4117254875
Short name T48
Test name
Test status
Simulation time 247436377 ps
CPU time 2.21 seconds
Started Jan 03 01:01:29 PM PST 24
Finished Jan 03 01:02:42 PM PST 24
Peak memory 202396 kb
Host smart-bddda660-6347-4d03-ba6c-099e6dc5e7d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117254875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.sram_ctrl_tl_intg_err.4117254875
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.647273600
Short name T175
Test name
Test status
Simulation time 1800057928 ps
CPU time 5.21 seconds
Started Jan 03 01:01:29 PM PST 24
Finished Jan 03 01:02:45 PM PST 24
Peak memory 202400 kb
Host smart-092efe97-9cad-4540-bc62-b6253c0643fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647273600 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.647273600
Directory /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.323209924
Short name T165
Test name
Test status
Simulation time 20849522 ps
CPU time 0.64 seconds
Started Jan 03 01:01:30 PM PST 24
Finished Jan 03 01:02:41 PM PST 24
Peak memory 201496 kb
Host smart-deaeb61f-4ba8-42e2-be29-394082469b27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323209924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 6.sram_ctrl_csr_rw.323209924
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2769070927
Short name T92
Test name
Test status
Simulation time 19393215020 ps
CPU time 148.82 seconds
Started Jan 03 01:01:42 PM PST 24
Finished Jan 03 01:05:24 PM PST 24
Peak memory 202516 kb
Host smart-4941e038-7543-46e6-8f90-3cc50acf81ea
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769070927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.2769070927
Directory /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2298741193
Short name T198
Test name
Test status
Simulation time 18685938 ps
CPU time 0.71 seconds
Started Jan 03 01:01:38 PM PST 24
Finished Jan 03 01:02:50 PM PST 24
Peak memory 202088 kb
Host smart-fbdd5dd7-75fa-4289-811a-e989ca0f27ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298741193 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.2298741193
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.171169628
Short name T190
Test name
Test status
Simulation time 72417325 ps
CPU time 3.62 seconds
Started Jan 03 01:01:33 PM PST 24
Finished Jan 03 01:02:48 PM PST 24
Peak memory 202360 kb
Host smart-6f9b02d3-8a3d-4c7a-94f6-57b0840def3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171169628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_tl_errors.171169628
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2848518163
Short name T194
Test name
Test status
Simulation time 160111857 ps
CPU time 1.29 seconds
Started Jan 03 01:01:31 PM PST 24
Finished Jan 03 01:02:42 PM PST 24
Peak memory 202536 kb
Host smart-8c617586-13f0-4b11-ae65-df0c33686132
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848518163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.sram_ctrl_tl_intg_err.2848518163
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.168348502
Short name T189
Test name
Test status
Simulation time 512120091 ps
CPU time 4.67 seconds
Started Jan 03 01:01:15 PM PST 24
Finished Jan 03 01:02:26 PM PST 24
Peak memory 202356 kb
Host smart-f4febf72-c6fa-4b0d-8674-1e527856ca2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168348502 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.168348502
Directory /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2786942368
Short name T67
Test name
Test status
Simulation time 29795954 ps
CPU time 0.63 seconds
Started Jan 03 01:01:25 PM PST 24
Finished Jan 03 01:02:35 PM PST 24
Peak memory 202084 kb
Host smart-45848cff-0691-450f-ba8a-a3a2a81d2bc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786942368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_csr_rw.2786942368
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.135363451
Short name T81
Test name
Test status
Simulation time 15409254628 ps
CPU time 56.85 seconds
Started Jan 03 01:01:25 PM PST 24
Finished Jan 03 01:03:31 PM PST 24
Peak memory 202516 kb
Host smart-06927473-ca0b-453b-a94f-748b76caaa54
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135363451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.135363451
Directory /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3267000656
Short name T186
Test name
Test status
Simulation time 59506089 ps
CPU time 0.7 seconds
Started Jan 03 01:01:16 PM PST 24
Finished Jan 03 01:02:22 PM PST 24
Peak memory 202308 kb
Host smart-cc23d809-8331-4a2a-8a95-917792cecc1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267000656 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.3267000656
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.953800623
Short name T57
Test name
Test status
Simulation time 33917744 ps
CPU time 2.87 seconds
Started Jan 03 01:01:27 PM PST 24
Finished Jan 03 01:02:40 PM PST 24
Peak memory 202436 kb
Host smart-117aed37-bc09-4a7a-be31-48a45264264e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953800623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_tl_errors.953800623
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.120411807
Short name T162
Test name
Test status
Simulation time 1370298855 ps
CPU time 5.05 seconds
Started Jan 03 01:01:19 PM PST 24
Finished Jan 03 01:02:31 PM PST 24
Peak memory 202436 kb
Host smart-bcb82018-714c-4604-8e22-f31634d785e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120411807 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.120411807
Directory /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1994060351
Short name T209
Test name
Test status
Simulation time 15615654 ps
CPU time 0.62 seconds
Started Jan 03 01:01:24 PM PST 24
Finished Jan 03 01:02:33 PM PST 24
Peak memory 201324 kb
Host smart-5dd178c8-cc29-4b1a-883c-d81b1d20a68c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994060351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_csr_rw.1994060351
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.337145015
Short name T74
Test name
Test status
Simulation time 3857728193 ps
CPU time 53.89 seconds
Started Jan 03 01:01:26 PM PST 24
Finished Jan 03 01:03:29 PM PST 24
Peak memory 202620 kb
Host smart-839d087c-aec1-4bdc-8f71-915143c091ff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337145015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.337145015
Directory /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4203153331
Short name T66
Test name
Test status
Simulation time 24241296 ps
CPU time 0.68 seconds
Started Jan 03 01:01:14 PM PST 24
Finished Jan 03 01:02:21 PM PST 24
Peak memory 202192 kb
Host smart-48cd3912-8bda-440f-a6c6-c1b380e0bd1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203153331 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.4203153331
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3578420049
Short name T203
Test name
Test status
Simulation time 40645904 ps
CPU time 3.13 seconds
Started Jan 03 01:01:23 PM PST 24
Finished Jan 03 01:02:34 PM PST 24
Peak memory 202424 kb
Host smart-f7ffd89a-2000-4c2f-b638-0711b0f4cc20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578420049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.sram_ctrl_tl_errors.3578420049
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2151724741
Short name T114
Test name
Test status
Simulation time 328140687 ps
CPU time 1.46 seconds
Started Jan 03 01:01:16 PM PST 24
Finished Jan 03 01:02:23 PM PST 24
Peak memory 210680 kb
Host smart-108b0eee-7e0d-4d14-adf8-a1e0c83bcd51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151724741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.sram_ctrl_tl_intg_err.2151724741
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3553611370
Short name T206
Test name
Test status
Simulation time 364899511 ps
CPU time 13.35 seconds
Started Jan 03 01:01:27 PM PST 24
Finished Jan 03 01:02:50 PM PST 24
Peak memory 210628 kb
Host smart-40fb9f28-cc0f-462d-8d3b-5ca75e0b1802
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553611370 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.3553611370
Directory /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.864273588
Short name T197
Test name
Test status
Simulation time 15429169 ps
CPU time 0.64 seconds
Started Jan 03 01:01:24 PM PST 24
Finished Jan 03 01:02:32 PM PST 24
Peak memory 201352 kb
Host smart-d3e95b3f-5e67-4890-b46b-0a97c4353c20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864273588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 9.sram_ctrl_csr_rw.864273588
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3123418553
Short name T75
Test name
Test status
Simulation time 14356613420 ps
CPU time 274.06 seconds
Started Jan 03 01:01:21 PM PST 24
Finished Jan 03 01:07:02 PM PST 24
Peak memory 211356 kb
Host smart-324bacb8-9707-4f96-a269-5995d90c0445
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123418553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.3123418553
Directory /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3557851366
Short name T157
Test name
Test status
Simulation time 16410987 ps
CPU time 0.71 seconds
Started Jan 03 01:01:16 PM PST 24
Finished Jan 03 01:02:23 PM PST 24
Peak memory 202148 kb
Host smart-49199048-56be-4edf-94ad-bd73a151105e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557851366 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.3557851366
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2195376670
Short name T52
Test name
Test status
Simulation time 2321969122 ps
CPU time 5.21 seconds
Started Jan 03 01:01:17 PM PST 24
Finished Jan 03 01:02:29 PM PST 24
Peak memory 202440 kb
Host smart-8ab15bcc-9bc0-4838-85cf-b97f366eee04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195376670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.sram_ctrl_tl_errors.2195376670
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.2522785056
Short name T365
Test name
Test status
Simulation time 36404545681 ps
CPU time 1021.1 seconds
Started Jan 03 01:39:53 PM PST 24
Finished Jan 03 01:56:56 PM PST 24
Peak memory 367908 kb
Host smart-bdd0da93-5f71-43b0-934c-2036dc0e8192
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522785056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_access_during_key_req.2522785056
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.884579827
Short name T473
Test name
Test status
Simulation time 441228361474 ps
CPU time 1596.14 seconds
Started Jan 03 01:39:51 PM PST 24
Finished Jan 03 02:06:29 PM PST 24
Peak memory 202164 kb
Host smart-001b3e3e-ecd7-46c8-8a96-8852b9a41045
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884579827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.884579827
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.2351440756
Short name T380
Test name
Test status
Simulation time 8099766602 ps
CPU time 80.67 seconds
Started Jan 03 01:39:51 PM PST 24
Finished Jan 03 01:41:14 PM PST 24
Peak memory 202228 kb
Host smart-488757c8-3b6a-4b58-8e37-4c87c013ab16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351440756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc
alation.2351440756
Directory /workspace/0.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.3809513028
Short name T323
Test name
Test status
Simulation time 716893681 ps
CPU time 46.85 seconds
Started Jan 03 01:39:53 PM PST 24
Finished Jan 03 01:40:42 PM PST 24
Peak memory 268596 kb
Host smart-7bb6c01f-1add-417e-bcbd-cf721aee160d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809513028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_max_throughput.3809513028
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2803743503
Short name T2
Test name
Test status
Simulation time 9943780123 ps
CPU time 153.64 seconds
Started Jan 03 01:40:02 PM PST 24
Finished Jan 03 01:42:48 PM PST 24
Peak memory 211676 kb
Host smart-5ce9d19d-3587-49c8-bb69-448f722c6e8f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803743503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_mem_partial_access.2803743503
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.2432579483
Short name T756
Test name
Test status
Simulation time 8970158720 ps
CPU time 127.31 seconds
Started Jan 03 01:39:56 PM PST 24
Finished Jan 03 01:42:06 PM PST 24
Peak memory 202244 kb
Host smart-d732676d-cc73-4a22-936e-b15e12dc91a3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432579483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl
_mem_walk.2432579483
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.3620673127
Short name T526
Test name
Test status
Simulation time 32525547210 ps
CPU time 796.77 seconds
Started Jan 03 01:39:46 PM PST 24
Finished Jan 03 01:53:06 PM PST 24
Peak memory 379152 kb
Host smart-df6ec0ef-e52b-4161-a3ea-553956aa1803
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620673127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip
le_keys.3620673127
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.418014868
Short name T504
Test name
Test status
Simulation time 2498304647 ps
CPU time 13.15 seconds
Started Jan 03 01:39:57 PM PST 24
Finished Jan 03 01:40:14 PM PST 24
Peak memory 202212 kb
Host smart-12487fcb-5245-4f2d-a57f-1f44f009b2d0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418014868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sr
am_ctrl_partial_access.418014868
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1523027849
Short name T41
Test name
Test status
Simulation time 6693456849 ps
CPU time 449.94 seconds
Started Jan 03 01:40:00 PM PST 24
Finished Jan 03 01:47:40 PM PST 24
Peak memory 202244 kb
Host smart-a2f3eab5-f950-4c6c-99b2-f1fac3889aaa
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523027849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.sram_ctrl_partial_access_b2b.1523027849
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.4000500283
Short name T579
Test name
Test status
Simulation time 358318452 ps
CPU time 6.65 seconds
Started Jan 03 01:39:56 PM PST 24
Finished Jan 03 01:40:05 PM PST 24
Peak memory 202396 kb
Host smart-ed9db34f-ed95-42de-bf7b-f8bf5187a4dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000500283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.4000500283
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.4252374967
Short name T301
Test name
Test status
Simulation time 701007146 ps
CPU time 12.02 seconds
Started Jan 03 01:39:46 PM PST 24
Finished Jan 03 01:40:02 PM PST 24
Peak memory 202112 kb
Host smart-a9d0e989-5b88-42f1-9f7c-1a28cce850ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252374967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.4252374967
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all.1198595413
Short name T872
Test name
Test status
Simulation time 421557099791 ps
CPU time 3191.4 seconds
Started Jan 03 01:39:52 PM PST 24
Finished Jan 03 02:33:05 PM PST 24
Peak memory 383148 kb
Host smart-76303fab-6fdf-4167-9bbb-7fde40717ccb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198595413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.sram_ctrl_stress_all.1198595413
Directory /workspace/0.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.290630308
Short name T636
Test name
Test status
Simulation time 2323691366 ps
CPU time 2144.8 seconds
Started Jan 03 01:39:52 PM PST 24
Finished Jan 03 02:15:39 PM PST 24
Peak memory 572440 kb
Host smart-1c6809ee-3ec4-4f9c-8ea7-66ac38ff77de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=290630308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.290630308
Directory /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.3018208023
Short name T103
Test name
Test status
Simulation time 6329616290 ps
CPU time 483.25 seconds
Started Jan 03 01:39:50 PM PST 24
Finished Jan 03 01:47:55 PM PST 24
Peak memory 202176 kb
Host smart-f33309e3-5c81-42e6-8999-c99cbf60cd3c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018208023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_stress_pipeline.3018208023
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3366778748
Short name T707
Test name
Test status
Simulation time 1677543220 ps
CPU time 124.6 seconds
Started Jan 03 01:39:51 PM PST 24
Finished Jan 03 01:41:58 PM PST 24
Peak memory 374996 kb
Host smart-18f5cc84-6da4-4f3e-9137-69ecf01ca886
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366778748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.3366778748
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.616170047
Short name T656
Test name
Test status
Simulation time 8565735491 ps
CPU time 995.58 seconds
Started Jan 03 01:39:56 PM PST 24
Finished Jan 03 01:56:33 PM PST 24
Peak memory 380100 kb
Host smart-35374dda-f541-4fe7-8e7a-6408aa45640d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616170047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.sram_ctrl_access_during_key_req.616170047
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.819701896
Short name T700
Test name
Test status
Simulation time 18458924 ps
CPU time 0.7 seconds
Started Jan 03 01:39:37 PM PST 24
Finished Jan 03 01:39:46 PM PST 24
Peak memory 201416 kb
Host smart-3293446d-6d5a-41b1-9a75-fce16bcd70f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819701896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_alert_test.819701896
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.2860954042
Short name T523
Test name
Test status
Simulation time 52603100969 ps
CPU time 1628.14 seconds
Started Jan 03 01:39:54 PM PST 24
Finished Jan 03 02:07:04 PM PST 24
Peak memory 202168 kb
Host smart-ca889c7f-9930-4061-8123-11a376ae2fce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860954042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.
2860954042
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_lc_escalation.1631142127
Short name T815
Test name
Test status
Simulation time 1396328292 ps
CPU time 15.76 seconds
Started Jan 03 01:39:51 PM PST 24
Finished Jan 03 01:40:09 PM PST 24
Peak memory 210352 kb
Host smart-aa4246bf-bd60-4db8-af60-a0f648c3ca11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631142127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc
alation.1631142127
Directory /workspace/1.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.1824946883
Short name T814
Test name
Test status
Simulation time 3049041998 ps
CPU time 93.1 seconds
Started Jan 03 01:39:59 PM PST 24
Finished Jan 03 01:41:41 PM PST 24
Peak memory 316068 kb
Host smart-2b3e53b9-0294-42ad-b43c-64526bbe4f71
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824946883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_max_throughput.1824946883
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1612354065
Short name T72
Test name
Test status
Simulation time 18051411557 ps
CPU time 156.16 seconds
Started Jan 03 01:39:53 PM PST 24
Finished Jan 03 01:42:31 PM PST 24
Peak memory 214592 kb
Host smart-e9665060-9775-4e90-87ea-faac92c2e33e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612354065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_mem_partial_access.1612354065
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.3697312811
Short name T396
Test name
Test status
Simulation time 1979243107 ps
CPU time 126.72 seconds
Started Jan 03 01:39:57 PM PST 24
Finished Jan 03 01:42:08 PM PST 24
Peak memory 201972 kb
Host smart-333f9a98-1243-49f3-bbf4-f8667b86aa84
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697312811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl
_mem_walk.3697312811
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.2055996800
Short name T784
Test name
Test status
Simulation time 9143574184 ps
CPU time 574.38 seconds
Started Jan 03 01:39:58 PM PST 24
Finished Jan 03 01:49:41 PM PST 24
Peak memory 376980 kb
Host smart-e6ae5f24-bb38-4950-a0ae-870f4867d5cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055996800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip
le_keys.2055996800
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.2680693865
Short name T984
Test name
Test status
Simulation time 567872284 ps
CPU time 163 seconds
Started Jan 03 01:39:52 PM PST 24
Finished Jan 03 01:42:36 PM PST 24
Peak memory 364560 kb
Host smart-5d6a7629-f162-4494-85e0-cda63b6cbdc3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680693865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s
ram_ctrl_partial_access.2680693865
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2715950463
Short name T487
Test name
Test status
Simulation time 26272194015 ps
CPU time 354.8 seconds
Started Jan 03 01:39:59 PM PST 24
Finished Jan 03 01:46:02 PM PST 24
Peak memory 202140 kb
Host smart-9562640c-2998-4bd2-98c0-6d01d6fef18b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715950463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.sram_ctrl_partial_access_b2b.2715950463
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.1235651444
Short name T620
Test name
Test status
Simulation time 695992919 ps
CPU time 6.38 seconds
Started Jan 03 01:39:57 PM PST 24
Finished Jan 03 01:40:07 PM PST 24
Peak memory 202348 kb
Host smart-2ddcef12-7faa-4f22-80b4-acac1427b4d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235651444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.1235651444
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.3930050819
Short name T669
Test name
Test status
Simulation time 18034042027 ps
CPU time 864.58 seconds
Started Jan 03 01:39:58 PM PST 24
Finished Jan 03 01:54:30 PM PST 24
Peak memory 378024 kb
Host smart-cffd888d-1b3c-4e59-8c4d-4171b5283b18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930050819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3930050819
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.2439199723
Short name T35
Test name
Test status
Simulation time 410399772 ps
CPU time 2.09 seconds
Started Jan 03 01:39:48 PM PST 24
Finished Jan 03 01:39:53 PM PST 24
Peak memory 220972 kb
Host smart-1073cce4-bc2a-478a-9e9a-1d8925b93801
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439199723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_sec_cm.2439199723
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.3131758997
Short name T980
Test name
Test status
Simulation time 925735162 ps
CPU time 119.41 seconds
Started Jan 03 01:39:55 PM PST 24
Finished Jan 03 01:41:56 PM PST 24
Peak memory 350376 kb
Host smart-a370d0dc-8b43-4ea8-bd2b-3b8e205d94f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131758997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.3131758997
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all.4036945868
Short name T577
Test name
Test status
Simulation time 188680177942 ps
CPU time 4152.37 seconds
Started Jan 03 01:39:40 PM PST 24
Finished Jan 03 02:49:01 PM PST 24
Peak memory 382204 kb
Host smart-3631169a-3d66-4e95-b9c7-64ed44f60826
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036945868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.sram_ctrl_stress_all.4036945868
Directory /workspace/1.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2417999016
Short name T398
Test name
Test status
Simulation time 6258842343 ps
CPU time 1310.83 seconds
Started Jan 03 01:39:40 PM PST 24
Finished Jan 03 02:01:39 PM PST 24
Peak memory 378996 kb
Host smart-ee370435-3128-4393-bcf7-161b7c3266e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2417999016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.2417999016
Directory /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2215243522
Short name T851
Test name
Test status
Simulation time 7135152630 ps
CPU time 270.73 seconds
Started Jan 03 01:39:54 PM PST 24
Finished Jan 03 01:44:27 PM PST 24
Peak memory 202204 kb
Host smart-626def53-2122-46ca-b9d9-a905746640ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215243522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_stress_pipeline.2215243522
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2320296613
Short name T956
Test name
Test status
Simulation time 784306057 ps
CPU time 96.19 seconds
Started Jan 03 01:39:59 PM PST 24
Finished Jan 03 01:41:44 PM PST 24
Peak memory 325992 kb
Host smart-f720f981-687d-40ca-a13e-fe22f7c170da
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320296613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.2320296613
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2916785734
Short name T21
Test name
Test status
Simulation time 16910136217 ps
CPU time 1482.16 seconds
Started Jan 03 01:42:06 PM PST 24
Finished Jan 03 02:06:55 PM PST 24
Peak memory 379956 kb
Host smart-667e944d-ce8e-4468-94b4-75336a42049d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916785734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_access_during_key_req.2916785734
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.2448120277
Short name T244
Test name
Test status
Simulation time 24840025 ps
CPU time 0.61 seconds
Started Jan 03 01:40:28 PM PST 24
Finished Jan 03 01:40:30 PM PST 24
Peak memory 201580 kb
Host smart-961a9c58-68ff-47ec-b021-b9646114fd63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448120277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_alert_test.2448120277
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.3889024882
Short name T309
Test name
Test status
Simulation time 479404392311 ps
CPU time 2765.76 seconds
Started Jan 03 01:41:17 PM PST 24
Finished Jan 03 02:27:28 PM PST 24
Peak memory 202080 kb
Host smart-04ba3cf2-e096-4a48-81a6-324720775a3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889024882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection
.3889024882
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_executable.3008663931
Short name T803
Test name
Test status
Simulation time 264703202817 ps
CPU time 1726.61 seconds
Started Jan 03 01:42:28 PM PST 24
Finished Jan 03 02:11:17 PM PST 24
Peak memory 378132 kb
Host smart-fd473f4b-f3ed-4206-8333-fe0c99489552
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008663931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab
le.3008663931
Directory /workspace/10.sram_ctrl_executable/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.3348403066
Short name T497
Test name
Test status
Simulation time 11179578228 ps
CPU time 59.02 seconds
Started Jan 03 01:41:15 PM PST 24
Finished Jan 03 01:42:18 PM PST 24
Peak memory 210392 kb
Host smart-ac74feeb-96bf-4bc3-9db7-99abc615bb6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348403066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es
calation.3348403066
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.2203958932
Short name T388
Test name
Test status
Simulation time 13751055787 ps
CPU time 33.25 seconds
Started Jan 03 01:41:41 PM PST 24
Finished Jan 03 01:42:17 PM PST 24
Peak memory 234980 kb
Host smart-7adf609d-ca7c-45a4-ba38-9937d737e1ac
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203958932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_max_throughput.2203958932
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.682099802
Short name T790
Test name
Test status
Simulation time 1615249959 ps
CPU time 141.49 seconds
Started Jan 03 01:42:28 PM PST 24
Finished Jan 03 01:44:52 PM PST 24
Peak memory 213940 kb
Host smart-078439ac-c9d2-4c0e-9460-f4e7c7b6a480
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682099802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.sram_ctrl_mem_partial_access.682099802
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.459352353
Short name T355
Test name
Test status
Simulation time 1981188503 ps
CPU time 130.26 seconds
Started Jan 03 01:42:27 PM PST 24
Finished Jan 03 01:44:39 PM PST 24
Peak memory 202044 kb
Host smart-4a17576d-c693-46ed-ad7b-41cee062becc
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459352353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl
_mem_walk.459352353
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.1825223130
Short name T349
Test name
Test status
Simulation time 9936971881 ps
CPU time 857.68 seconds
Started Jan 03 01:41:13 PM PST 24
Finished Jan 03 01:55:35 PM PST 24
Peak memory 380168 kb
Host smart-8dc6b914-2fb4-462c-afde-f5e2cc1e526e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825223130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi
ple_keys.1825223130
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.4008164224
Short name T702
Test name
Test status
Simulation time 1249956879 ps
CPU time 22.97 seconds
Started Jan 03 01:41:44 PM PST 24
Finished Jan 03 01:42:15 PM PST 24
Peak memory 201996 kb
Host smart-8540cf36-d7dc-4355-ae60-7f3831f80b6f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008164224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
sram_ctrl_partial_access.4008164224
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2715848252
Short name T889
Test name
Test status
Simulation time 4057714918 ps
CPU time 248.61 seconds
Started Jan 03 01:41:42 PM PST 24
Finished Jan 03 01:45:56 PM PST 24
Peak memory 202136 kb
Host smart-7dc86284-e104-48b3-9df0-a2ea6959b52c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715848252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.sram_ctrl_partial_access_b2b.2715848252
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.1013437857
Short name T525
Test name
Test status
Simulation time 715867610 ps
CPU time 6.45 seconds
Started Jan 03 01:42:02 PM PST 24
Finished Jan 03 01:42:16 PM PST 24
Peak memory 202380 kb
Host smart-dc949acc-e6d4-4800-8f02-f30b9b68f754
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013437857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.1013437857
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.1797225906
Short name T548
Test name
Test status
Simulation time 1706816295 ps
CPU time 105.08 seconds
Started Jan 03 01:41:57 PM PST 24
Finished Jan 03 01:43:50 PM PST 24
Peak memory 320540 kb
Host smart-bffdef67-6690-4e86-affe-7cb5fc16fb2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797225906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.1797225906
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.1896221245
Short name T139
Test name
Test status
Simulation time 845890566 ps
CPU time 10.28 seconds
Started Jan 03 01:41:52 PM PST 24
Finished Jan 03 01:42:13 PM PST 24
Peak memory 202100 kb
Host smart-14d82237-3852-4b1b-acdd-ab94f053c9f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896221245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.1896221245
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.582885851
Short name T342
Test name
Test status
Simulation time 2497536529 ps
CPU time 5680.87 seconds
Started Jan 03 01:42:06 PM PST 24
Finished Jan 03 03:16:54 PM PST 24
Peak memory 697836 kb
Host smart-9cc01777-8f08-4700-a0ee-390a76059902
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=582885851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.582885851
Directory /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.2994912856
Short name T658
Test name
Test status
Simulation time 4319828749 ps
CPU time 354.5 seconds
Started Jan 03 01:42:22 PM PST 24
Finished Jan 03 01:48:19 PM PST 24
Peak memory 202124 kb
Host smart-c1cbbd05-1f9b-4e66-b7a7-e46ef3026714
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994912856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_stress_pipeline.2994912856
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3512071808
Short name T919
Test name
Test status
Simulation time 2944479267 ps
CPU time 42.06 seconds
Started Jan 03 01:41:58 PM PST 24
Finished Jan 03 01:42:48 PM PST 24
Peak memory 257252 kb
Host smart-a34a689b-eab6-47f0-827f-b0f2fc205743
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512071808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.3512071808
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.1413709269
Short name T838
Test name
Test status
Simulation time 4774886293 ps
CPU time 283.67 seconds
Started Jan 03 01:40:47 PM PST 24
Finished Jan 03 01:45:36 PM PST 24
Peak memory 344220 kb
Host smart-73db1949-b71c-45a8-abb2-b6e2b36ef581
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413709269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_access_during_key_req.1413709269
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.2575512789
Short name T864
Test name
Test status
Simulation time 20124606 ps
CPU time 0.64 seconds
Started Jan 03 01:40:46 PM PST 24
Finished Jan 03 01:40:52 PM PST 24
Peak memory 201364 kb
Host smart-867f1d8d-ae3c-4087-8478-745ae03b6998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575512789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.2575512789
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.2989949246
Short name T671
Test name
Test status
Simulation time 122048651514 ps
CPU time 1043.72 seconds
Started Jan 03 01:42:28 PM PST 24
Finished Jan 03 01:59:54 PM PST 24
Peak memory 202104 kb
Host smart-4d5dc893-7917-4806-8058-8374d4d3b5e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989949246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection
.2989949246
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_executable.557981286
Short name T580
Test name
Test status
Simulation time 4922281060 ps
CPU time 401.19 seconds
Started Jan 03 01:40:49 PM PST 24
Finished Jan 03 01:47:36 PM PST 24
Peak memory 363572 kb
Host smart-45a78fe6-140f-49c4-8b3e-225ac225878c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557981286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executabl
e.557981286
Directory /workspace/11.sram_ctrl_executable/latest

Test location /workspace/coverage/default/11.sram_ctrl_lc_escalation.474199679
Short name T715
Test name
Test status
Simulation time 4250840706 ps
CPU time 44.41 seconds
Started Jan 03 01:42:27 PM PST 24
Finished Jan 03 01:43:13 PM PST 24
Peak memory 213680 kb
Host smart-f7dd060b-23cf-43c4-a59c-d16b865f81aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474199679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_esc
alation.474199679
Directory /workspace/11.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.1070842206
Short name T778
Test name
Test status
Simulation time 1474003850 ps
CPU time 46.88 seconds
Started Jan 03 01:42:34 PM PST 24
Finished Jan 03 01:43:23 PM PST 24
Peak memory 277828 kb
Host smart-4283ac17-ca7b-44bf-9940-9beacc3b2cf9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070842206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_max_throughput.1070842206
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.983339544
Short name T408
Test name
Test status
Simulation time 2450736758 ps
CPU time 77.53 seconds
Started Jan 03 01:40:47 PM PST 24
Finished Jan 03 01:42:10 PM PST 24
Peak memory 210704 kb
Host smart-9b1c246b-94a9-4d77-bf29-ee6d075c43b8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983339544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.sram_ctrl_mem_partial_access.983339544
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.661671051
Short name T754
Test name
Test status
Simulation time 7886121850 ps
CPU time 250.74 seconds
Started Jan 03 01:41:10 PM PST 24
Finished Jan 03 01:45:26 PM PST 24
Peak memory 202544 kb
Host smart-2f943d69-4011-4a87-904e-20a961f4bfb6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661671051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl
_mem_walk.661671051
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.2936083036
Short name T734
Test name
Test status
Simulation time 2985076969 ps
CPU time 80.85 seconds
Started Jan 03 01:42:31 PM PST 24
Finished Jan 03 01:43:54 PM PST 24
Peak memory 269316 kb
Host smart-dc8dd77a-185d-418b-85ef-e7afbcb444e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936083036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi
ple_keys.2936083036
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.811625315
Short name T254
Test name
Test status
Simulation time 1617145086 ps
CPU time 32.82 seconds
Started Jan 03 01:42:32 PM PST 24
Finished Jan 03 01:43:07 PM PST 24
Peak memory 202076 kb
Host smart-03780643-937f-4dfe-8045-d6066332815c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811625315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.s
ram_ctrl_partial_access.811625315
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.452882274
Short name T717
Test name
Test status
Simulation time 77959106063 ps
CPU time 478.47 seconds
Started Jan 03 01:42:32 PM PST 24
Finished Jan 03 01:50:32 PM PST 24
Peak memory 202140 kb
Host smart-bcccd2b3-6f0c-424c-9af7-f37acf9ff943
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452882274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.sram_ctrl_partial_access_b2b.452882274
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.423706257
Short name T137
Test name
Test status
Simulation time 19281958730 ps
CPU time 1158.37 seconds
Started Jan 03 01:41:35 PM PST 24
Finished Jan 03 02:00:58 PM PST 24
Peak memory 381108 kb
Host smart-60ee8f01-5473-493a-80ec-24ed475432b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423706257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.423706257
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.2632947936
Short name T807
Test name
Test status
Simulation time 1349021212 ps
CPU time 136.94 seconds
Started Jan 03 01:41:55 PM PST 24
Finished Jan 03 01:44:21 PM PST 24
Peak memory 375124 kb
Host smart-6383cab3-548f-4571-8011-cbb0817b1f1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632947936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.2632947936
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all.760124735
Short name T503
Test name
Test status
Simulation time 362773363686 ps
CPU time 2993.37 seconds
Started Jan 03 01:40:51 PM PST 24
Finished Jan 03 02:30:50 PM PST 24
Peak memory 374024 kb
Host smart-ce54aec5-c501-407c-8aef-0b84915ab053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760124735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.sram_ctrl_stress_all.760124735
Directory /workspace/11.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1192948284
Short name T540
Test name
Test status
Simulation time 1354705778 ps
CPU time 2959.87 seconds
Started Jan 03 01:40:43 PM PST 24
Finished Jan 03 02:30:10 PM PST 24
Peak memory 430436 kb
Host smart-4837f2ed-f59c-4178-afc1-607d27888ae6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1192948284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.1192948284
Directory /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.2977948078
Short name T542
Test name
Test status
Simulation time 7616171820 ps
CPU time 208.91 seconds
Started Jan 03 01:42:30 PM PST 24
Finished Jan 03 01:46:01 PM PST 24
Peak memory 202164 kb
Host smart-2dd76dbb-38a0-4819-a74b-1cd6dc5662bc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977948078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_stress_pipeline.2977948078
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.827220544
Short name T486
Test name
Test status
Simulation time 2924296053 ps
CPU time 64.59 seconds
Started Jan 03 01:40:48 PM PST 24
Finished Jan 03 01:41:59 PM PST 24
Peak memory 294180 kb
Host smart-e1403cc4-4d51-4393-8b72-0c1263d7da07
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827220544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_throughput_w_partial_write.827220544
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.2201512385
Short name T547
Test name
Test status
Simulation time 7208689870 ps
CPU time 940.19 seconds
Started Jan 03 01:41:49 PM PST 24
Finished Jan 03 01:57:41 PM PST 24
Peak memory 380432 kb
Host smart-98564147-7b4c-4b29-a806-83a222d133a8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201512385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_access_during_key_req.2201512385
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.3649619625
Short name T728
Test name
Test status
Simulation time 13506454 ps
CPU time 0.64 seconds
Started Jan 03 01:42:00 PM PST 24
Finished Jan 03 01:42:08 PM PST 24
Peak memory 201920 kb
Host smart-5bdfa038-0e6d-4db1-8db7-aa80c0d05315
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649619625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.3649619625
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.208138537
Short name T545
Test name
Test status
Simulation time 28156639739 ps
CPU time 1970.99 seconds
Started Jan 03 01:41:33 PM PST 24
Finished Jan 03 02:14:30 PM PST 24
Peak memory 202172 kb
Host smart-dbbdb8cb-a5db-48db-abff-661b5925d5a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208138537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.
208138537
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_lc_escalation.2595880797
Short name T678
Test name
Test status
Simulation time 9564890144 ps
CPU time 104.86 seconds
Started Jan 03 01:41:55 PM PST 24
Finished Jan 03 01:43:49 PM PST 24
Peak memory 210344 kb
Host smart-ad86ea18-fdca-4a98-b2da-0fd3dbcce130
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595880797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es
calation.2595880797
Directory /workspace/12.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.1030990369
Short name T553
Test name
Test status
Simulation time 2869645603 ps
CPU time 63.06 seconds
Started Jan 03 01:42:30 PM PST 24
Finished Jan 03 01:43:36 PM PST 24
Peak memory 290048 kb
Host smart-e830cfc7-1caf-48a9-8412-420e8a67830f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030990369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_max_throughput.1030990369
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2109987706
Short name T86
Test name
Test status
Simulation time 11154195316 ps
CPU time 138.06 seconds
Started Jan 03 01:41:57 PM PST 24
Finished Jan 03 01:44:23 PM PST 24
Peak memory 211320 kb
Host smart-7690bc9d-ba95-4370-88ec-e0931be7aae7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109987706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_mem_partial_access.2109987706
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.2873162326
Short name T144
Test name
Test status
Simulation time 4109784070 ps
CPU time 249.64 seconds
Started Jan 03 01:42:28 PM PST 24
Finished Jan 03 01:46:40 PM PST 24
Peak memory 202220 kb
Host smart-c1617527-d3dc-43a2-8612-c319764b63de
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873162326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr
l_mem_walk.2873162326
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.2416235090
Short name T457
Test name
Test status
Simulation time 9929271905 ps
CPU time 617.27 seconds
Started Jan 03 01:40:47 PM PST 24
Finished Jan 03 01:51:09 PM PST 24
Peak memory 372016 kb
Host smart-41d75003-1876-4fc7-90f4-c81ed7107c77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416235090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi
ple_keys.2416235090
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.2715254794
Short name T535
Test name
Test status
Simulation time 580380920 ps
CPU time 26.83 seconds
Started Jan 03 01:42:21 PM PST 24
Finished Jan 03 01:42:49 PM PST 24
Peak memory 201972 kb
Host smart-2b616740-5cfe-466e-9989-469214327c9d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715254794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
sram_ctrl_partial_access.2715254794
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2444474239
Short name T104
Test name
Test status
Simulation time 62073758720 ps
CPU time 354.6 seconds
Started Jan 03 01:41:59 PM PST 24
Finished Jan 03 01:48:01 PM PST 24
Peak memory 202116 kb
Host smart-0e4f896d-25cb-45ee-8de9-a4f295c4f6ee
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444474239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.sram_ctrl_partial_access_b2b.2444474239
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.1361510230
Short name T237
Test name
Test status
Simulation time 681603831 ps
CPU time 14.31 seconds
Started Jan 03 01:41:47 PM PST 24
Finished Jan 03 01:42:14 PM PST 24
Peak memory 202420 kb
Host smart-39cd4328-c71a-4872-a533-9865017c397a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361510230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.1361510230
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.2470969131
Short name T831
Test name
Test status
Simulation time 21669941808 ps
CPU time 1097.09 seconds
Started Jan 03 01:41:48 PM PST 24
Finished Jan 03 02:00:17 PM PST 24
Peak memory 371904 kb
Host smart-fcb5a778-2431-48b8-89f8-af1c549c9a9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470969131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.2470969131
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.1171824110
Short name T622
Test name
Test status
Simulation time 4103435183 ps
CPU time 110.78 seconds
Started Jan 03 01:40:48 PM PST 24
Finished Jan 03 01:42:45 PM PST 24
Peak memory 351416 kb
Host smart-bacb8024-f72b-40d1-863d-0ef5d140d31d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171824110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.1171824110
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all.3345118045
Short name T916
Test name
Test status
Simulation time 439547559435 ps
CPU time 7431.45 seconds
Started Jan 03 01:41:58 PM PST 24
Finished Jan 03 03:45:58 PM PST 24
Peak memory 382204 kb
Host smart-6dc9d268-44bd-4c23-92d9-2e26a6ad4713
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345118045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.sram_ctrl_stress_all.3345118045
Directory /workspace/12.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2617920653
Short name T811
Test name
Test status
Simulation time 3278463181 ps
CPU time 1424.92 seconds
Started Jan 03 01:42:21 PM PST 24
Finished Jan 03 02:06:07 PM PST 24
Peak memory 435676 kb
Host smart-d7c4cd09-d75c-4252-a4f1-bcefb04a010d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2617920653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.2617920653
Directory /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2644049939
Short name T960
Test name
Test status
Simulation time 4477575826 ps
CPU time 314.31 seconds
Started Jan 03 01:41:41 PM PST 24
Finished Jan 03 01:46:58 PM PST 24
Peak memory 202184 kb
Host smart-319a7d76-4ece-4adc-b314-243e986ab2c3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644049939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_stress_pipeline.2644049939
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.974883562
Short name T332
Test name
Test status
Simulation time 4975232957 ps
CPU time 36.74 seconds
Started Jan 03 01:41:55 PM PST 24
Finished Jan 03 01:42:41 PM PST 24
Peak memory 243168 kb
Host smart-1139cdfb-b754-4bc4-a665-217a93f073e4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974883562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_throughput_w_partial_write.974883562
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.2619072635
Short name T800
Test name
Test status
Simulation time 6925516545 ps
CPU time 93.86 seconds
Started Jan 03 01:42:26 PM PST 24
Finished Jan 03 01:44:02 PM PST 24
Peak memory 278468 kb
Host smart-c68d34c5-6cff-44a5-b1e1-bffeee474d86
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619072635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_access_during_key_req.2619072635
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.4276893576
Short name T897
Test name
Test status
Simulation time 23100520 ps
CPU time 0.65 seconds
Started Jan 03 01:41:39 PM PST 24
Finished Jan 03 01:41:43 PM PST 24
Peak memory 201452 kb
Host smart-4ba58a56-ab8f-4062-b60c-ca3146d81677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276893576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_alert_test.4276893576
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.2063658878
Short name T9
Test name
Test status
Simulation time 170634111854 ps
CPU time 2657.6 seconds
Started Jan 03 01:42:07 PM PST 24
Finished Jan 03 02:26:31 PM PST 24
Peak memory 202092 kb
Host smart-fc37b16e-0a48-4ee9-9e41-4d6d993b2b75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063658878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection
.2063658878
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.3221591869
Short name T586
Test name
Test status
Simulation time 3033800104 ps
CPU time 74.96 seconds
Started Jan 03 01:42:27 PM PST 24
Finished Jan 03 01:43:44 PM PST 24
Peak memory 295140 kb
Host smart-9f5b7c05-baad-46b2-b907-836a7611c27f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221591869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.sram_ctrl_max_throughput.3221591869
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1818978579
Short name T810
Test name
Test status
Simulation time 3102714289 ps
CPU time 147.15 seconds
Started Jan 03 01:41:11 PM PST 24
Finished Jan 03 01:43:43 PM PST 24
Peak memory 218524 kb
Host smart-b20539b8-adb5-4df4-ad11-32dc11eff1ae
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818978579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_mem_partial_access.1818978579
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.997839759
Short name T637
Test name
Test status
Simulation time 7179826463 ps
CPU time 140.92 seconds
Started Jan 03 01:41:11 PM PST 24
Finished Jan 03 01:43:37 PM PST 24
Peak memory 202208 kb
Host smart-362aac5c-7fcb-4bbc-881d-6fd731357edc
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997839759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl
_mem_walk.997839759
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.1674903013
Short name T3
Test name
Test status
Simulation time 36892399986 ps
CPU time 855.98 seconds
Started Jan 03 01:42:08 PM PST 24
Finished Jan 03 01:56:30 PM PST 24
Peak memory 372776 kb
Host smart-2ffc5400-cf88-49a7-8d3d-db0747812d78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674903013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi
ple_keys.1674903013
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.2608548623
Short name T816
Test name
Test status
Simulation time 6454421846 ps
CPU time 72.01 seconds
Started Jan 03 01:41:57 PM PST 24
Finished Jan 03 01:43:17 PM PST 24
Peak memory 301280 kb
Host smart-4b8f2ddb-961c-4338-b26b-68a9a5f26bcd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608548623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
sram_ctrl_partial_access.2608548623
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2027362446
Short name T447
Test name
Test status
Simulation time 6738752253 ps
CPU time 428.21 seconds
Started Jan 03 01:42:29 PM PST 24
Finished Jan 03 01:49:40 PM PST 24
Peak memory 202176 kb
Host smart-b1b2806d-b0e3-4e69-a310-395c8d103dc6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027362446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.sram_ctrl_partial_access_b2b.2027362446
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.4254601354
Short name T928
Test name
Test status
Simulation time 349947861 ps
CPU time 5.77 seconds
Started Jan 03 01:41:12 PM PST 24
Finished Jan 03 01:41:22 PM PST 24
Peak memory 202452 kb
Host smart-940417ce-a9f9-416b-8a57-300239883eeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254601354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.4254601354
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.407431141
Short name T730
Test name
Test status
Simulation time 40106194724 ps
CPU time 1104.04 seconds
Started Jan 03 01:41:12 PM PST 24
Finished Jan 03 01:59:40 PM PST 24
Peak memory 378052 kb
Host smart-82278045-6da7-4803-b8c9-75f0fccf7d7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407431141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.407431141
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.1844523884
Short name T945
Test name
Test status
Simulation time 823342029 ps
CPU time 6.63 seconds
Started Jan 03 01:41:57 PM PST 24
Finished Jan 03 01:42:12 PM PST 24
Peak memory 201964 kb
Host smart-1db68c26-fbd3-45fd-b997-c3608e392ee3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844523884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.1844523884
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3189074501
Short name T452
Test name
Test status
Simulation time 3873275171 ps
CPU time 6529.55 seconds
Started Jan 03 01:41:40 PM PST 24
Finished Jan 03 03:30:34 PM PST 24
Peak memory 697912 kb
Host smart-ab68b682-4d34-4fbb-bcab-8ec57f0ae495
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3189074501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.3189074501
Directory /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.1640721417
Short name T275
Test name
Test status
Simulation time 3600292591 ps
CPU time 284.26 seconds
Started Jan 03 01:42:08 PM PST 24
Finished Jan 03 01:46:58 PM PST 24
Peak memory 202132 kb
Host smart-f851a52f-9cfc-42f1-8b21-ae5bd9c87aa6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640721417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_stress_pipeline.1640721417
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.353850758
Short name T693
Test name
Test status
Simulation time 14706381388 ps
CPU time 66.53 seconds
Started Jan 03 01:42:06 PM PST 24
Finished Jan 03 01:43:18 PM PST 24
Peak memory 307532 kb
Host smart-73ae10f1-3bfb-4083-a0fb-ca16a3f470d2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353850758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.sram_ctrl_throughput_w_partial_write.353850758
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2303182617
Short name T976
Test name
Test status
Simulation time 8776135586 ps
CPU time 1518.82 seconds
Started Jan 03 01:41:40 PM PST 24
Finished Jan 03 02:07:02 PM PST 24
Peak memory 380172 kb
Host smart-1e57fc45-04e3-4576-8772-d27e112aa100
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303182617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_access_during_key_req.2303182617
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.2510031378
Short name T835
Test name
Test status
Simulation time 33500860 ps
CPU time 0.66 seconds
Started Jan 03 01:41:57 PM PST 24
Finished Jan 03 01:42:06 PM PST 24
Peak memory 201876 kb
Host smart-45ee1b90-b6d7-4ed3-acde-99f5e35d97a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510031378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.2510031378
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.2940596260
Short name T845
Test name
Test status
Simulation time 249085316635 ps
CPU time 959.64 seconds
Started Jan 03 01:41:13 PM PST 24
Finished Jan 03 01:57:18 PM PST 24
Peak memory 210308 kb
Host smart-28b3bf4a-c199-4af3-8b82-c67ed5c089c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940596260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection
.2940596260
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_executable.822879347
Short name T607
Test name
Test status
Simulation time 10817608665 ps
CPU time 176.26 seconds
Started Jan 03 01:41:40 PM PST 24
Finished Jan 03 01:44:40 PM PST 24
Peak memory 326928 kb
Host smart-ea18a920-4728-40fd-82ee-bbf63d4e0e85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822879347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executabl
e.822879347
Directory /workspace/14.sram_ctrl_executable/latest

Test location /workspace/coverage/default/14.sram_ctrl_lc_escalation.4058780005
Short name T642
Test name
Test status
Simulation time 22485869002 ps
CPU time 103.56 seconds
Started Jan 03 01:41:41 PM PST 24
Finished Jan 03 01:43:28 PM PST 24
Peak memory 210348 kb
Host smart-57db492f-7436-469c-bbac-d75ca35d8165
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058780005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es
calation.4058780005
Directory /workspace/14.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.2826423491
Short name T906
Test name
Test status
Simulation time 2800647382 ps
CPU time 29.62 seconds
Started Jan 03 01:41:16 PM PST 24
Finished Jan 03 01:41:50 PM PST 24
Peak memory 219972 kb
Host smart-b4e3169e-1bf7-4092-928b-15de54c8400d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826423491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_max_throughput.2826423491
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.1166603457
Short name T591
Test name
Test status
Simulation time 17500751878 ps
CPU time 161.84 seconds
Started Jan 03 01:42:05 PM PST 24
Finished Jan 03 01:44:54 PM PST 24
Peak memory 210560 kb
Host smart-381d6935-0986-423c-86de-12797900393f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166603457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_mem_partial_access.1166603457
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.3095688192
Short name T496
Test name
Test status
Simulation time 171916215881 ps
CPU time 216.67 seconds
Started Jan 03 01:41:48 PM PST 24
Finished Jan 03 01:45:36 PM PST 24
Peak memory 202204 kb
Host smart-37717487-2710-4afd-8019-c79b3b87ea5e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095688192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr
l_mem_walk.3095688192
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.4117613060
Short name T395
Test name
Test status
Simulation time 66261067571 ps
CPU time 1909.61 seconds
Started Jan 03 01:41:39 PM PST 24
Finished Jan 03 02:13:32 PM PST 24
Peak memory 380196 kb
Host smart-854fa81c-ec8d-4fd4-92d4-301dcaad4a88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117613060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi
ple_keys.4117613060
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.909341412
Short name T946
Test name
Test status
Simulation time 1803790799 ps
CPU time 9.29 seconds
Started Jan 03 01:41:15 PM PST 24
Finished Jan 03 01:41:29 PM PST 24
Peak memory 215236 kb
Host smart-1591ab72-a854-4485-95b1-9575cc33bd79
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909341412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.s
ram_ctrl_partial_access.909341412
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3212760920
Short name T311
Test name
Test status
Simulation time 22482857323 ps
CPU time 291.87 seconds
Started Jan 03 01:41:14 PM PST 24
Finished Jan 03 01:46:11 PM PST 24
Peak memory 202120 kb
Host smart-c8942f26-dfcb-4766-b99f-1eea21f21c60
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212760920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_partial_access_b2b.3212760920
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.2155476051
Short name T539
Test name
Test status
Simulation time 1408468749 ps
CPU time 7.32 seconds
Started Jan 03 01:41:56 PM PST 24
Finished Jan 03 01:42:12 PM PST 24
Peak memory 202400 kb
Host smart-49ce40c7-47ff-444c-8ce6-90da0a8dcca4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155476051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.2155476051
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.3224426547
Short name T126
Test name
Test status
Simulation time 17744632483 ps
CPU time 922.52 seconds
Started Jan 03 01:41:50 PM PST 24
Finished Jan 03 01:57:24 PM PST 24
Peak memory 373980 kb
Host smart-63fa6e55-a622-4cd5-b73e-32b8a00284e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224426547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.3224426547
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.727059951
Short name T60
Test name
Test status
Simulation time 1005560296 ps
CPU time 20.64 seconds
Started Jan 03 01:41:14 PM PST 24
Finished Jan 03 01:41:40 PM PST 24
Peak memory 202076 kb
Host smart-7c7a473c-4b56-4f70-92a1-50b34a621c1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727059951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.727059951
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all.1579304008
Short name T917
Test name
Test status
Simulation time 815741851801 ps
CPU time 6280.96 seconds
Started Jan 03 01:42:25 PM PST 24
Finished Jan 03 03:27:09 PM PST 24
Peak memory 384132 kb
Host smart-f1fc65f4-9a82-4095-bd2b-9bb43db5ffaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579304008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.sram_ctrl_stress_all.1579304008
Directory /workspace/14.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2902492025
Short name T440
Test name
Test status
Simulation time 835926854 ps
CPU time 3795.94 seconds
Started Jan 03 01:42:24 PM PST 24
Finished Jan 03 02:45:42 PM PST 24
Peak memory 632620 kb
Host smart-b344484f-0c0a-472a-bb24-71e0888340fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2902492025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.2902492025
Directory /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.4128973575
Short name T330
Test name
Test status
Simulation time 20315959576 ps
CPU time 347.74 seconds
Started Jan 03 01:41:14 PM PST 24
Finished Jan 03 01:47:07 PM PST 24
Peak memory 202168 kb
Host smart-1df5e3e8-ec70-407c-a522-bc7f9e12d0a7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128973575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_stress_pipeline.4128973575
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2229743834
Short name T288
Test name
Test status
Simulation time 4153716979 ps
CPU time 42.35 seconds
Started Jan 03 01:41:41 PM PST 24
Finished Jan 03 01:42:26 PM PST 24
Peak memory 257156 kb
Host smart-c0554456-8d58-4a69-823d-e709ed04ea6c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229743834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.2229743834
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.3809176905
Short name T716
Test name
Test status
Simulation time 10092702963 ps
CPU time 761.86 seconds
Started Jan 03 01:42:05 PM PST 24
Finished Jan 03 01:54:53 PM PST 24
Peak memory 379032 kb
Host smart-fdec8c6e-a5f8-462e-829e-d44b00a4cbe3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809176905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_access_during_key_req.3809176905
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.315923137
Short name T438
Test name
Test status
Simulation time 17962419 ps
CPU time 0.66 seconds
Started Jan 03 01:42:24 PM PST 24
Finished Jan 03 01:42:27 PM PST 24
Peak memory 201448 kb
Host smart-388d781e-8532-44f2-86f3-ac0cdd093caa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315923137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_alert_test.315923137
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.2750720333
Short name T860
Test name
Test status
Simulation time 967611350726 ps
CPU time 2570.68 seconds
Started Jan 03 01:41:58 PM PST 24
Finished Jan 03 02:24:57 PM PST 24
Peak memory 202236 kb
Host smart-566b77a5-b3a1-490a-ab12-9f834d340768
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750720333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection
.2750720333
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_executable.4162154170
Short name T903
Test name
Test status
Simulation time 95575346980 ps
CPU time 1160.54 seconds
Started Jan 03 01:42:27 PM PST 24
Finished Jan 03 02:01:50 PM PST 24
Peak memory 371972 kb
Host smart-bd42e83f-b36c-4d12-b8cd-4e01d021675e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162154170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab
le.4162154170
Directory /workspace/15.sram_ctrl_executable/latest

Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.1766978538
Short name T614
Test name
Test status
Simulation time 6833321515 ps
CPU time 34.88 seconds
Started Jan 03 01:42:09 PM PST 24
Finished Jan 03 01:42:50 PM PST 24
Peak memory 210360 kb
Host smart-2429f193-8418-4f99-b3ef-cf9ac584355c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766978538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es
calation.1766978538
Directory /workspace/15.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.1664571819
Short name T808
Test name
Test status
Simulation time 774289288 ps
CPU time 102.26 seconds
Started Jan 03 01:42:24 PM PST 24
Finished Jan 03 01:44:08 PM PST 24
Peak memory 334036 kb
Host smart-df14e659-5ecc-49f2-a775-cf3110c21a65
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664571819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_max_throughput.1664571819
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.1461363695
Short name T587
Test name
Test status
Simulation time 956006308 ps
CPU time 70.73 seconds
Started Jan 03 01:42:01 PM PST 24
Finished Jan 03 01:43:19 PM PST 24
Peak memory 210960 kb
Host smart-a6287cf9-fb5a-4132-8a81-7a7e56318867
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461363695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_mem_partial_access.1461363695
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.4149017689
Short name T356
Test name
Test status
Simulation time 17575814611 ps
CPU time 149.99 seconds
Started Jan 03 01:41:58 PM PST 24
Finished Jan 03 01:44:36 PM PST 24
Peak memory 202176 kb
Host smart-b6c2c49f-c207-4c03-a587-7a3b70f031b3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149017689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr
l_mem_walk.4149017689
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.687105083
Short name T285
Test name
Test status
Simulation time 6309846987 ps
CPU time 407.57 seconds
Started Jan 03 01:42:26 PM PST 24
Finished Jan 03 01:49:16 PM PST 24
Peak memory 377944 kb
Host smart-a29408fd-a192-4eb6-b755-ce85275d0d8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687105083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multip
le_keys.687105083
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.2194301557
Short name T654
Test name
Test status
Simulation time 1831431328 ps
CPU time 39.32 seconds
Started Jan 03 01:41:57 PM PST 24
Finished Jan 03 01:42:44 PM PST 24
Peak memory 202100 kb
Host smart-6b51d0e6-c85a-49f1-bb59-117efae9a2aa
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194301557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
sram_ctrl_partial_access.2194301557
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1535172339
Short name T430
Test name
Test status
Simulation time 91240229369 ps
CPU time 471.67 seconds
Started Jan 03 01:42:01 PM PST 24
Finished Jan 03 01:50:01 PM PST 24
Peak memory 202128 kb
Host smart-89488ad0-7897-4385-bb9e-fc64328bfc79
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535172339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_partial_access_b2b.1535172339
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.867639591
Short name T687
Test name
Test status
Simulation time 710853354 ps
CPU time 13.61 seconds
Started Jan 03 01:42:00 PM PST 24
Finished Jan 03 01:42:21 PM PST 24
Peak memory 202448 kb
Host smart-8d7919be-e3da-43fd-beaa-d95f8899267f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867639591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.867639591
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.3169554385
Short name T130
Test name
Test status
Simulation time 89426844659 ps
CPU time 1273.78 seconds
Started Jan 03 01:41:57 PM PST 24
Finished Jan 03 02:03:19 PM PST 24
Peak memory 374048 kb
Host smart-8122728e-8569-4eb2-988b-befe191ecdeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169554385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.3169554385
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.711374985
Short name T777
Test name
Test status
Simulation time 2552222877 ps
CPU time 101.07 seconds
Started Jan 03 01:41:46 PM PST 24
Finished Jan 03 01:43:39 PM PST 24
Peak memory 354576 kb
Host smart-9235f31d-77e5-4c5a-aacf-078844d74d60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711374985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.711374985
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all.3820690223
Short name T947
Test name
Test status
Simulation time 980208744299 ps
CPU time 3750.35 seconds
Started Jan 03 01:41:52 PM PST 24
Finished Jan 03 02:44:33 PM PST 24
Peak memory 381232 kb
Host smart-01340d7b-503b-4824-a24c-88e8ecb2087f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820690223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.sram_ctrl_stress_all.3820690223
Directory /workspace/15.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2704881458
Short name T942
Test name
Test status
Simulation time 4949266911 ps
CPU time 1797.91 seconds
Started Jan 03 01:42:01 PM PST 24
Finished Jan 03 02:12:07 PM PST 24
Peak memory 430412 kb
Host smart-49e9be82-f802-484a-be7c-949853dadd20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2704881458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.2704881458
Directory /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.2268962488
Short name T694
Test name
Test status
Simulation time 8435411389 ps
CPU time 300.72 seconds
Started Jan 03 01:41:42 PM PST 24
Finished Jan 03 01:46:48 PM PST 24
Peak memory 202112 kb
Host smart-f8a03b53-a6ef-46aa-a855-c0efbf544b0b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268962488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_stress_pipeline.2268962488
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.353460709
Short name T628
Test name
Test status
Simulation time 1530448918 ps
CPU time 171.68 seconds
Started Jan 03 01:42:29 PM PST 24
Finished Jan 03 01:45:23 PM PST 24
Peak memory 365636 kb
Host smart-b4626b2c-a7fa-4ec3-8b4c-1dd96e1f3da5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353460709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_throughput_w_partial_write.353460709
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.3468411871
Short name T890
Test name
Test status
Simulation time 23788479318 ps
CPU time 1242.99 seconds
Started Jan 03 01:41:57 PM PST 24
Finished Jan 03 02:02:49 PM PST 24
Peak memory 375104 kb
Host smart-ce64f015-e050-4a1e-86f3-6fdee7f448ca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468411871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_access_during_key_req.3468411871
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.742251912
Short name T913
Test name
Test status
Simulation time 27613327 ps
CPU time 0.64 seconds
Started Jan 03 01:42:28 PM PST 24
Finished Jan 03 01:42:31 PM PST 24
Peak memory 201884 kb
Host smart-1d1580cc-bc10-4bee-babc-b8359c8177e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742251912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.742251912
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.2832590303
Short name T58
Test name
Test status
Simulation time 192608237613 ps
CPU time 1101.56 seconds
Started Jan 03 01:42:31 PM PST 24
Finished Jan 03 02:00:55 PM PST 24
Peak memory 202076 kb
Host smart-9fcf2ae2-eeef-481d-b89b-39e36cb4d5f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832590303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection
.2832590303
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_lc_escalation.1811953793
Short name T583
Test name
Test status
Simulation time 11558671630 ps
CPU time 127.4 seconds
Started Jan 03 01:41:50 PM PST 24
Finished Jan 03 01:44:09 PM PST 24
Peak memory 202228 kb
Host smart-30ac2db2-011a-4878-a58d-83ac58d396c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811953793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es
calation.1811953793
Directory /workspace/16.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.1171032434
Short name T737
Test name
Test status
Simulation time 892995315 ps
CPU time 94.71 seconds
Started Jan 03 01:41:56 PM PST 24
Finished Jan 03 01:43:39 PM PST 24
Peak memory 352428 kb
Host smart-aa6ccb07-328e-46b8-9f63-90db344a8fbd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171032434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_max_throughput.1171032434
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.2736588536
Short name T695
Test name
Test status
Simulation time 1673003630 ps
CPU time 135.72 seconds
Started Jan 03 01:42:26 PM PST 24
Finished Jan 03 01:44:44 PM PST 24
Peak memory 213856 kb
Host smart-f466f4a9-1cbc-4c3e-a102-703c6a95e71f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736588536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_mem_partial_access.2736588536
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.3737423068
Short name T479
Test name
Test status
Simulation time 15769079046 ps
CPU time 255.14 seconds
Started Jan 03 01:42:29 PM PST 24
Finished Jan 03 01:46:47 PM PST 24
Peak memory 202108 kb
Host smart-7053f526-32b9-4f82-a127-83a2f86a34a3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737423068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr
l_mem_walk.3737423068
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.1034784578
Short name T795
Test name
Test status
Simulation time 12830639453 ps
CPU time 945.53 seconds
Started Jan 03 01:42:25 PM PST 24
Finished Jan 03 01:58:13 PM PST 24
Peak memory 381180 kb
Host smart-68ca9a48-51e8-4520-aea9-76a11150d9ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034784578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi
ple_keys.1034784578
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.2491259724
Short name T417
Test name
Test status
Simulation time 710946448 ps
CPU time 11.51 seconds
Started Jan 03 01:42:28 PM PST 24
Finished Jan 03 01:42:42 PM PST 24
Peak memory 202080 kb
Host smart-7594a821-48a4-461e-9a14-8fa3a80dfd9d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491259724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
sram_ctrl_partial_access.2491259724
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2582590824
Short name T610
Test name
Test status
Simulation time 13433880554 ps
CPU time 272.86 seconds
Started Jan 03 01:42:22 PM PST 24
Finished Jan 03 01:46:57 PM PST 24
Peak memory 202092 kb
Host smart-7264d257-b432-4bbb-b10f-c1f066677618
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582590824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 16.sram_ctrl_partial_access_b2b.2582590824
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.1581330924
Short name T377
Test name
Test status
Simulation time 679788081 ps
CPU time 5.98 seconds
Started Jan 03 01:42:29 PM PST 24
Finished Jan 03 01:42:38 PM PST 24
Peak memory 202360 kb
Host smart-5b5b49d7-4c94-4a3c-93b0-3971d7f19ab5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581330924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.1581330924
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.3018625314
Short name T433
Test name
Test status
Simulation time 108897741513 ps
CPU time 1033.36 seconds
Started Jan 03 01:42:02 PM PST 24
Finished Jan 03 01:59:23 PM PST 24
Peak memory 379068 kb
Host smart-23aaf4eb-a224-4400-88fd-1e4d14f64db8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018625314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.3018625314
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.1991866308
Short name T13
Test name
Test status
Simulation time 3036642882 ps
CPU time 111.65 seconds
Started Jan 03 01:42:25 PM PST 24
Finished Jan 03 01:44:18 PM PST 24
Peak memory 340184 kb
Host smart-ba08509b-67cb-4066-8292-507735a00547
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991866308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.1991866308
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all.1233753711
Short name T969
Test name
Test status
Simulation time 175814347812 ps
CPU time 7180.15 seconds
Started Jan 03 01:42:29 PM PST 24
Finished Jan 03 03:42:13 PM PST 24
Peak memory 381140 kb
Host smart-40393112-12fc-4e75-879e-cf79ed10bf58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233753711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.sram_ctrl_stress_all.1233753711
Directory /workspace/16.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.306598583
Short name T482
Test name
Test status
Simulation time 4521153276 ps
CPU time 3319.68 seconds
Started Jan 03 01:42:25 PM PST 24
Finished Jan 03 02:37:47 PM PST 24
Peak memory 690940 kb
Host smart-89ada099-95ce-456a-9ba8-886a413536b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=306598583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.306598583
Directory /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.2544719607
Short name T785
Test name
Test status
Simulation time 5002503548 ps
CPU time 371.96 seconds
Started Jan 03 01:42:08 PM PST 24
Finished Jan 03 01:48:26 PM PST 24
Peak memory 202192 kb
Host smart-bbcd9469-2416-4b35-b564-d35aa21dd2ff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544719607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_stress_pipeline.2544719607
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2435052535
Short name T881
Test name
Test status
Simulation time 3243956941 ps
CPU time 123.39 seconds
Started Jan 03 01:41:55 PM PST 24
Finished Jan 03 01:44:07 PM PST 24
Peak memory 364388 kb
Host smart-2ab85f4a-76da-4d67-a1f0-940994f961a8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435052535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.2435052535
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.1355009466
Short name T286
Test name
Test status
Simulation time 12318069629 ps
CPU time 422.02 seconds
Started Jan 03 01:42:50 PM PST 24
Finished Jan 03 01:49:54 PM PST 24
Peak memory 338140 kb
Host smart-9a35dfbb-7085-46fd-9460-7ab4a6f7442f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355009466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_access_during_key_req.1355009466
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.4224759351
Short name T421
Test name
Test status
Simulation time 57097330 ps
CPU time 0.64 seconds
Started Jan 03 01:42:51 PM PST 24
Finished Jan 03 01:42:54 PM PST 24
Peak memory 201432 kb
Host smart-38d96dab-cd34-48b5-bf36-e7dc6e05630a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224759351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_alert_test.4224759351
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.345103961
Short name T597
Test name
Test status
Simulation time 517150322761 ps
CPU time 2130.92 seconds
Started Jan 03 01:42:26 PM PST 24
Finished Jan 03 02:17:59 PM PST 24
Peak memory 202104 kb
Host smart-3d2108c0-f149-48a6-b80f-89f3264cc8d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345103961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.
345103961
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.2175188983
Short name T738
Test name
Test status
Simulation time 3016676735 ps
CPU time 72.31 seconds
Started Jan 03 01:42:33 PM PST 24
Finished Jan 03 01:43:47 PM PST 24
Peak memory 297260 kb
Host smart-842022f3-c3b5-4f31-a458-80779a9bc1d8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175188983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_max_throughput.2175188983
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.3212305425
Short name T827
Test name
Test status
Simulation time 4475307928 ps
CPU time 157.93 seconds
Started Jan 03 01:42:49 PM PST 24
Finished Jan 03 01:45:29 PM PST 24
Peak memory 211156 kb
Host smart-be8afeac-b524-47be-9f4e-12ed2cccbca2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212305425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_mem_partial_access.3212305425
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.4238519325
Short name T394
Test name
Test status
Simulation time 28090840845 ps
CPU time 288.27 seconds
Started Jan 03 01:42:50 PM PST 24
Finished Jan 03 01:47:40 PM PST 24
Peak memory 202292 kb
Host smart-23add377-2bd0-4819-b887-25d7885f3fbd
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238519325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr
l_mem_walk.4238519325
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.2242127837
Short name T348
Test name
Test status
Simulation time 31127300800 ps
CPU time 1427.22 seconds
Started Jan 03 01:42:08 PM PST 24
Finished Jan 03 02:06:01 PM PST 24
Peak memory 374068 kb
Host smart-445e26df-b7f2-44e4-8d30-1a79725be276
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242127837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi
ple_keys.2242127837
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.1978626993
Short name T924
Test name
Test status
Simulation time 673750170 ps
CPU time 30.44 seconds
Started Jan 03 01:42:52 PM PST 24
Finished Jan 03 01:43:25 PM PST 24
Peak memory 263256 kb
Host smart-c366e0a4-86f4-4298-853b-c7ec9730a937
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978626993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
sram_ctrl_partial_access.1978626993
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1651721510
Short name T933
Test name
Test status
Simulation time 41569116969 ps
CPU time 256.11 seconds
Started Jan 03 01:42:27 PM PST 24
Finished Jan 03 01:46:46 PM PST 24
Peak memory 202156 kb
Host smart-06cf42b6-53d5-4003-86a5-c5ae7d197af9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651721510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_partial_access_b2b.1651721510
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.2535767370
Short name T625
Test name
Test status
Simulation time 350983481 ps
CPU time 5.35 seconds
Started Jan 03 01:42:52 PM PST 24
Finished Jan 03 01:43:00 PM PST 24
Peak memory 202452 kb
Host smart-1c674535-e60d-4129-bc1a-6519f699945e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535767370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.2535767370
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.2110717634
Short name T606
Test name
Test status
Simulation time 39224364142 ps
CPU time 1380.92 seconds
Started Jan 03 01:42:37 PM PST 24
Finished Jan 03 02:05:39 PM PST 24
Peak memory 377940 kb
Host smart-44c10f25-1a76-4fc0-8ba3-cc94a4c2904b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110717634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.2110717634
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.3535967836
Short name T39
Test name
Test status
Simulation time 942315016 ps
CPU time 18.98 seconds
Started Jan 03 01:42:01 PM PST 24
Finished Jan 03 01:42:28 PM PST 24
Peak memory 202068 kb
Host smart-c6c4a117-a2fa-4b8e-abeb-5a83036fc5fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535967836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.3535967836
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3121867876
Short name T680
Test name
Test status
Simulation time 417291953 ps
CPU time 4258.6 seconds
Started Jan 03 01:42:51 PM PST 24
Finished Jan 03 02:53:53 PM PST 24
Peak memory 698544 kb
Host smart-13b1ab92-98bb-433e-92b5-60969d953228
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3121867876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.3121867876
Directory /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.2479988428
Short name T387
Test name
Test status
Simulation time 10214399400 ps
CPU time 408.34 seconds
Started Jan 03 01:42:28 PM PST 24
Finished Jan 03 01:49:18 PM PST 24
Peak memory 202180 kb
Host smart-e26ec3a7-4d4f-437a-a2a5-da1ced238bad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479988428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_stress_pipeline.2479988428
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1394788734
Short name T746
Test name
Test status
Simulation time 4981874799 ps
CPU time 85.37 seconds
Started Jan 03 01:42:51 PM PST 24
Finished Jan 03 01:44:18 PM PST 24
Peak memory 317576 kb
Host smart-fc06a969-0b61-4a53-bc1c-fc083c949424
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394788734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.1394788734
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.1369172658
Short name T314
Test name
Test status
Simulation time 96858996144 ps
CPU time 1461.07 seconds
Started Jan 03 01:42:51 PM PST 24
Finished Jan 03 02:07:14 PM PST 24
Peak memory 378020 kb
Host smart-404215a1-a97e-4381-843f-e15b7ab158ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369172658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_access_during_key_req.1369172658
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.2345985658
Short name T660
Test name
Test status
Simulation time 25299613 ps
CPU time 0.65 seconds
Started Jan 03 01:42:58 PM PST 24
Finished Jan 03 01:43:01 PM PST 24
Peak memory 201464 kb
Host smart-b9788da6-9503-4786-a54e-f4268390aab6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345985658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_alert_test.2345985658
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.4121823867
Short name T461
Test name
Test status
Simulation time 50783683723 ps
CPU time 1090.41 seconds
Started Jan 03 01:42:31 PM PST 24
Finished Jan 03 02:00:44 PM PST 24
Peak memory 202140 kb
Host smart-3d0e9ffc-06bc-45c0-9659-2ebf468233a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121823867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection
.4121823867
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_executable.3202238979
Short name T543
Test name
Test status
Simulation time 14499868484 ps
CPU time 438.27 seconds
Started Jan 03 01:42:53 PM PST 24
Finished Jan 03 01:50:13 PM PST 24
Peak memory 371596 kb
Host smart-9e157bd0-cf94-4e2f-a98a-0c1c8eb3bade
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202238979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab
le.3202238979
Directory /workspace/18.sram_ctrl_executable/latest

Test location /workspace/coverage/default/18.sram_ctrl_lc_escalation.957173543
Short name T111
Test name
Test status
Simulation time 16115758408 ps
CPU time 131.9 seconds
Started Jan 03 01:42:33 PM PST 24
Finished Jan 03 01:44:47 PM PST 24
Peak memory 210392 kb
Host smart-2483bbf3-702a-407c-adf0-3e2788c917da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957173543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_esc
alation.957173543
Directory /workspace/18.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.3286573680
Short name T371
Test name
Test status
Simulation time 2655387420 ps
CPU time 26.72 seconds
Started Jan 03 01:42:33 PM PST 24
Finished Jan 03 01:43:02 PM PST 24
Peak memory 210436 kb
Host smart-f267e9d7-e2f0-4da1-8668-0071096a2b48
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286573680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_max_throughput.3286573680
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.2309214023
Short name T88
Test name
Test status
Simulation time 30899280047 ps
CPU time 135.91 seconds
Started Jan 03 01:42:56 PM PST 24
Finished Jan 03 01:45:14 PM PST 24
Peak memory 214672 kb
Host smart-81b03815-3c1b-44c5-997e-da993694bc7d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309214023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_mem_partial_access.2309214023
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.1175881217
Short name T338
Test name
Test status
Simulation time 19701837024 ps
CPU time 259.71 seconds
Started Jan 03 01:42:53 PM PST 24
Finished Jan 03 01:47:15 PM PST 24
Peak memory 202176 kb
Host smart-f7a62afa-edd0-4867-be21-c4477883e043
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175881217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr
l_mem_walk.1175881217
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.1537435410
Short name T741
Test name
Test status
Simulation time 9170346388 ps
CPU time 61.31 seconds
Started Jan 03 01:42:28 PM PST 24
Finished Jan 03 01:43:32 PM PST 24
Peak memory 279904 kb
Host smart-ab85b46f-b812-4241-bc4e-5aaad4d29a95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537435410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi
ple_keys.1537435410
Directory /workspace/18.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.4187930213
Short name T281
Test name
Test status
Simulation time 1896064145 ps
CPU time 30.21 seconds
Started Jan 03 01:42:31 PM PST 24
Finished Jan 03 01:43:03 PM PST 24
Peak memory 263416 kb
Host smart-6eaa0967-e382-4595-8208-404613141f31
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187930213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
sram_ctrl_partial_access.4187930213
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3510778535
Short name T951
Test name
Test status
Simulation time 285320687901 ps
CPU time 536.55 seconds
Started Jan 03 01:42:28 PM PST 24
Finished Jan 03 01:51:27 PM PST 24
Peak memory 202180 kb
Host smart-4183d128-3b10-40ed-ba51-618240279cc7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510778535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.sram_ctrl_partial_access_b2b.3510778535
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.3952161819
Short name T8
Test name
Test status
Simulation time 1351868427 ps
CPU time 5.81 seconds
Started Jan 03 01:42:51 PM PST 24
Finished Jan 03 01:42:59 PM PST 24
Peak memory 202332 kb
Host smart-2d5b2a43-65ae-4202-8d30-4f12d2268db3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952161819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.3952161819
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.1366799453
Short name T436
Test name
Test status
Simulation time 7138874035 ps
CPU time 967.19 seconds
Started Jan 03 01:42:35 PM PST 24
Finished Jan 03 01:58:44 PM PST 24
Peak memory 380016 kb
Host smart-dade5fbb-f287-4dfa-a93c-ad8f65583ae8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366799453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1366799453
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.1644828903
Short name T826
Test name
Test status
Simulation time 4101689454 ps
CPU time 115.02 seconds
Started Jan 03 01:42:31 PM PST 24
Finished Jan 03 01:44:28 PM PST 24
Peak memory 351256 kb
Host smart-64763e27-172f-4563-b716-c7f42570520b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644828903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.1644828903
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all.328785523
Short name T888
Test name
Test status
Simulation time 34259698683 ps
CPU time 3404 seconds
Started Jan 03 01:42:59 PM PST 24
Finished Jan 03 02:39:47 PM PST 24
Peak memory 381756 kb
Host smart-fad6753a-9ed3-41c9-926e-0435d1abc62f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328785523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.sram_ctrl_stress_all.328785523
Directory /workspace/18.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1609090013
Short name T929
Test name
Test status
Simulation time 4068450271 ps
CPU time 4065.34 seconds
Started Jan 03 01:42:50 PM PST 24
Finished Jan 03 02:50:37 PM PST 24
Peak memory 728972 kb
Host smart-21e55051-8396-42f7-9a0c-00881bbefd02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1609090013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.1609090013
Directory /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.2539524110
Short name T527
Test name
Test status
Simulation time 11131935393 ps
CPU time 372.75 seconds
Started Jan 03 01:42:37 PM PST 24
Finished Jan 03 01:48:51 PM PST 24
Peak memory 202196 kb
Host smart-fb88f079-296d-48b8-91b8-e3ce781b9048
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539524110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_stress_pipeline.2539524110
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3822325315
Short name T552
Test name
Test status
Simulation time 1993783977 ps
CPU time 61.95 seconds
Started Jan 03 01:42:54 PM PST 24
Finished Jan 03 01:43:57 PM PST 24
Peak memory 299964 kb
Host smart-2fe02634-85be-4caa-9f3f-638c26d301c7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822325315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.3822325315
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3986696755
Short name T294
Test name
Test status
Simulation time 35978836451 ps
CPU time 1129.29 seconds
Started Jan 03 01:43:09 PM PST 24
Finished Jan 03 02:02:00 PM PST 24
Peak memory 372880 kb
Host smart-3dfedd9b-e990-4981-955a-70413ab557e4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986696755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_access_during_key_req.3986696755
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.2404452753
Short name T874
Test name
Test status
Simulation time 55803044 ps
CPU time 0.66 seconds
Started Jan 03 01:43:13 PM PST 24
Finished Jan 03 01:43:16 PM PST 24
Peak memory 201868 kb
Host smart-b66afa92-7bbc-4d9b-861d-5337ea849d14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404452753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.2404452753
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.2271388479
Short name T617
Test name
Test status
Simulation time 258375988293 ps
CPU time 622.29 seconds
Started Jan 03 01:42:57 PM PST 24
Finished Jan 03 01:53:21 PM PST 24
Peak memory 202156 kb
Host smart-0fe7eef4-e390-40f7-ad65-5a91b57647bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271388479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection
.2271388479
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_executable.187143823
Short name T668
Test name
Test status
Simulation time 39298675310 ps
CPU time 585.18 seconds
Started Jan 03 01:43:14 PM PST 24
Finished Jan 03 01:53:01 PM PST 24
Peak memory 367776 kb
Host smart-306e4aa2-4581-454f-b947-78a6aed80611
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187143823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executabl
e.187143823
Directory /workspace/19.sram_ctrl_executable/latest

Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.1520434502
Short name T797
Test name
Test status
Simulation time 8679016520 ps
CPU time 75.61 seconds
Started Jan 03 01:43:11 PM PST 24
Finished Jan 03 01:44:28 PM PST 24
Peak memory 202132 kb
Host smart-1e185470-e414-4bbd-9e75-d07f76b9353c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520434502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es
calation.1520434502
Directory /workspace/19.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.2562408152
Short name T556
Test name
Test status
Simulation time 776277467 ps
CPU time 89.02 seconds
Started Jan 03 01:42:59 PM PST 24
Finished Jan 03 01:44:30 PM PST 24
Peak memory 337084 kb
Host smart-cf5ebae8-cd50-485c-b2dd-ad17abd6ed0d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562408152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_max_throughput.2562408152
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.667181198
Short name T410
Test name
Test status
Simulation time 3811775782 ps
CPU time 78.18 seconds
Started Jan 03 01:43:11 PM PST 24
Finished Jan 03 01:44:31 PM PST 24
Peak memory 211248 kb
Host smart-0c6b9cf2-ed5a-403f-99a8-c17819f22f7e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667181198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.sram_ctrl_mem_partial_access.667181198
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.2737991011
Short name T407
Test name
Test status
Simulation time 57436876577 ps
CPU time 303.07 seconds
Started Jan 03 01:43:09 PM PST 24
Finished Jan 03 01:48:14 PM PST 24
Peak memory 202152 kb
Host smart-d6440424-dc89-4bb1-89b5-1adb7e305786
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737991011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr
l_mem_walk.2737991011
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.8918636
Short name T938
Test name
Test status
Simulation time 36460556155 ps
CPU time 1205.28 seconds
Started Jan 03 01:42:50 PM PST 24
Finished Jan 03 02:02:58 PM PST 24
Peak memory 380224 kb
Host smart-fc847ede-6ba4-4cf6-9f8b-38a525842a92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8918636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multipl
e_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple
_keys.8918636
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.1505975146
Short name T915
Test name
Test status
Simulation time 1493377600 ps
CPU time 27.76 seconds
Started Jan 03 01:42:58 PM PST 24
Finished Jan 03 01:43:28 PM PST 24
Peak memory 259972 kb
Host smart-783346d2-67d1-41f3-8e2b-c019ee0c6cd5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505975146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
sram_ctrl_partial_access.1505975146
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1567914183
Short name T674
Test name
Test status
Simulation time 5656791513 ps
CPU time 382.96 seconds
Started Jan 03 01:43:12 PM PST 24
Finished Jan 03 01:49:37 PM PST 24
Peak memory 202120 kb
Host smart-21664339-64ba-4337-863b-2c38f4f94ccb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567914183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_partial_access_b2b.1567914183
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.3167981757
Short name T373
Test name
Test status
Simulation time 351533100 ps
CPU time 6.36 seconds
Started Jan 03 01:43:11 PM PST 24
Finished Jan 03 01:43:19 PM PST 24
Peak memory 202412 kb
Host smart-0bee846e-d97c-4df0-ac22-459aa1c5d0a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167981757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.3167981757
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.320211566
Short name T511
Test name
Test status
Simulation time 25344630848 ps
CPU time 69.86 seconds
Started Jan 03 01:43:32 PM PST 24
Finished Jan 03 01:44:43 PM PST 24
Peak memory 259316 kb
Host smart-cce07f25-d77f-4bc6-8d68-d2ae5d1082d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320211566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.320211566
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.1485122561
Short name T936
Test name
Test status
Simulation time 788386302 ps
CPU time 31.75 seconds
Started Jan 03 01:42:54 PM PST 24
Finished Jan 03 01:43:27 PM PST 24
Peak memory 202092 kb
Host smart-9ad55f4b-4cf6-4140-a23c-5897d2af1933
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485122561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.1485122561
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2078329222
Short name T261
Test name
Test status
Simulation time 1485477111 ps
CPU time 4104.11 seconds
Started Jan 03 01:43:11 PM PST 24
Finished Jan 03 02:51:37 PM PST 24
Peak memory 527156 kb
Host smart-b37b5727-1e14-44d6-8720-599b189d8e50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2078329222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.2078329222
Directory /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.820748005
Short name T792
Test name
Test status
Simulation time 3240399452 ps
CPU time 238.54 seconds
Started Jan 03 01:42:56 PM PST 24
Finished Jan 03 01:46:57 PM PST 24
Peak memory 202128 kb
Host smart-c42c6a76-a0a2-4daf-a17e-9b7bbdce1e56
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820748005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.sram_ctrl_stress_pipeline.820748005
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3365221616
Short name T361
Test name
Test status
Simulation time 1579770319 ps
CPU time 102.57 seconds
Started Jan 03 01:43:10 PM PST 24
Finished Jan 03 01:44:55 PM PST 24
Peak memory 327820 kb
Host smart-09a5809f-fc18-46e8-b23c-1a4d6106c0f3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365221616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.3365221616
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.2632469666
Short name T943
Test name
Test status
Simulation time 10698484114 ps
CPU time 780.74 seconds
Started Jan 03 01:40:14 PM PST 24
Finished Jan 03 01:53:25 PM PST 24
Peak memory 379236 kb
Host smart-38d2b0d9-47f2-479d-a61b-708a5a422e14
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632469666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_access_during_key_req.2632469666
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.1992984981
Short name T804
Test name
Test status
Simulation time 13121259 ps
CPU time 0.66 seconds
Started Jan 03 01:40:22 PM PST 24
Finished Jan 03 01:40:28 PM PST 24
Peak memory 201496 kb
Host smart-875cbf42-6dd8-41a4-9993-812ac6c9fadb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992984981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.1992984981
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.2418577626
Short name T696
Test name
Test status
Simulation time 96291223580 ps
CPU time 1066.01 seconds
Started Jan 03 01:39:39 PM PST 24
Finished Jan 03 01:57:34 PM PST 24
Peak memory 202144 kb
Host smart-8b2f56ec-25ca-4372-a8c3-99c8f7d99450
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418577626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.
2418577626
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_executable.2117480448
Short name T752
Test name
Test status
Simulation time 2769994957 ps
CPU time 610.45 seconds
Started Jan 03 01:40:14 PM PST 24
Finished Jan 03 01:50:35 PM PST 24
Peak memory 367812 kb
Host smart-77e2f52c-d60b-4935-a409-071d6b18810d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117480448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl
e.2117480448
Directory /workspace/2.sram_ctrl_executable/latest

Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.2848632564
Short name T844
Test name
Test status
Simulation time 18762687893 ps
CPU time 149.96 seconds
Started Jan 03 01:40:31 PM PST 24
Finished Jan 03 01:43:06 PM PST 24
Peak memory 202196 kb
Host smart-9aa26eec-d83a-44ae-a9cc-526bda6b968e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848632564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc
alation.2848632564
Directory /workspace/2.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.3369218063
Short name T529
Test name
Test status
Simulation time 743503446 ps
CPU time 103.19 seconds
Started Jan 03 01:39:52 PM PST 24
Finished Jan 03 01:41:37 PM PST 24
Peak memory 327724 kb
Host smart-830380b4-7dcf-4dd5-81b9-b10e66c0fb3c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369218063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_max_throughput.3369218063
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.4042787692
Short name T569
Test name
Test status
Simulation time 1383998190 ps
CPU time 71.61 seconds
Started Jan 03 01:40:13 PM PST 24
Finished Jan 03 01:41:35 PM PST 24
Peak memory 210596 kb
Host smart-f688b46d-ea0a-40d1-8c90-ad4389c6993d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042787692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_mem_partial_access.4042787692
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.4284555447
Short name T226
Test name
Test status
Simulation time 14358897769 ps
CPU time 277.8 seconds
Started Jan 03 01:40:15 PM PST 24
Finished Jan 03 01:45:03 PM PST 24
Peak memory 202264 kb
Host smart-ba51a2a6-570d-461b-ac25-e737cfbc160b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284555447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl
_mem_walk.4284555447
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.3112056885
Short name T809
Test name
Test status
Simulation time 36582551841 ps
CPU time 630.58 seconds
Started Jan 03 01:39:52 PM PST 24
Finished Jan 03 01:50:25 PM PST 24
Peak memory 375044 kb
Host smart-a7e325dc-f287-44e3-843a-5e578be317ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112056885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip
le_keys.3112056885
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.1891911080
Short name T757
Test name
Test status
Simulation time 2831627752 ps
CPU time 62.97 seconds
Started Jan 03 01:39:50 PM PST 24
Finished Jan 03 01:40:55 PM PST 24
Peak memory 293268 kb
Host smart-c5f252ff-14f6-4b20-a161-beb925f160f6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891911080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s
ram_ctrl_partial_access.1891911080
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.344128676
Short name T712
Test name
Test status
Simulation time 1695980789 ps
CPU time 7.01 seconds
Started Jan 03 01:40:15 PM PST 24
Finished Jan 03 01:40:32 PM PST 24
Peak memory 202432 kb
Host smart-4362d3c6-5b9a-40c5-bd06-44e2ab2187c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344128676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.344128676
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.2546861366
Short name T344
Test name
Test status
Simulation time 19746504639 ps
CPU time 448.27 seconds
Started Jan 03 01:40:15 PM PST 24
Finished Jan 03 01:47:53 PM PST 24
Peak memory 365744 kb
Host smart-644b176d-0b3a-4625-9937-a5db9a2daec9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546861366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.2546861366
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.1987412610
Short name T25
Test name
Test status
Simulation time 674189404 ps
CPU time 3.28 seconds
Started Jan 03 01:40:28 PM PST 24
Finished Jan 03 01:40:34 PM PST 24
Peak memory 223872 kb
Host smart-063d8a7b-9c4c-4974-a312-fa797cba43cd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987412610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_sec_cm.1987412610
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.2583580356
Short name T305
Test name
Test status
Simulation time 449150893 ps
CPU time 108.53 seconds
Started Jan 03 01:39:37 PM PST 24
Finished Jan 03 01:41:34 PM PST 24
Peak memory 349220 kb
Host smart-6495eb9e-1bec-4cb1-934b-ec8a77b16fff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583580356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.2583580356
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all.1242306486
Short name T466
Test name
Test status
Simulation time 26010397906 ps
CPU time 1672.02 seconds
Started Jan 03 01:40:15 PM PST 24
Finished Jan 03 02:08:17 PM PST 24
Peak memory 379800 kb
Host smart-57c4a3d2-db5e-4392-b811-72eb54e14af8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242306486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.sram_ctrl_stress_all.1242306486
Directory /workspace/2.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3808980927
Short name T882
Test name
Test status
Simulation time 880170901 ps
CPU time 4293.46 seconds
Started Jan 03 01:40:24 PM PST 24
Finished Jan 03 02:52:02 PM PST 24
Peak memory 756420 kb
Host smart-99f69e4f-d182-4fe5-ba4d-805e4cfd5f1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3808980927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.3808980927
Directory /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.1940550440
Short name T333
Test name
Test status
Simulation time 63622879028 ps
CPU time 461.08 seconds
Started Jan 03 01:39:50 PM PST 24
Finished Jan 03 01:47:33 PM PST 24
Peak memory 202168 kb
Host smart-5546ed96-3ae6-4c87-8832-abda187a4c28
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940550440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_stress_pipeline.1940550440
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1603984191
Short name T743
Test name
Test status
Simulation time 1596225434 ps
CPU time 142.04 seconds
Started Jan 03 01:40:15 PM PST 24
Finished Jan 03 01:42:47 PM PST 24
Peak memory 365712 kb
Host smart-be48b428-6f5c-4944-88ef-e44a26e57db9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603984191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.1603984191
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.2082746723
Short name T635
Test name
Test status
Simulation time 14847808115 ps
CPU time 957.58 seconds
Started Jan 03 01:42:32 PM PST 24
Finished Jan 03 01:58:31 PM PST 24
Peak memory 372356 kb
Host smart-cfe40773-bfaf-4841-a923-a4a1fd581411
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082746723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.sram_ctrl_access_during_key_req.2082746723
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.3542203747
Short name T258
Test name
Test status
Simulation time 14903820 ps
CPU time 0.67 seconds
Started Jan 03 01:42:48 PM PST 24
Finished Jan 03 01:42:50 PM PST 24
Peak memory 201884 kb
Host smart-9656e5ea-2169-4636-9295-adfa1edcb4b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542203747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.sram_ctrl_alert_test.3542203747
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.400949543
Short name T307
Test name
Test status
Simulation time 37680921776 ps
CPU time 1773.55 seconds
Started Jan 03 01:43:39 PM PST 24
Finished Jan 03 02:13:14 PM PST 24
Peak memory 202120 kb
Host smart-73e71091-30f1-4666-90ac-d4940fbbf438
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400949543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.
400949543
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.310055923
Short name T824
Test name
Test status
Simulation time 702772779 ps
CPU time 39.18 seconds
Started Jan 03 01:43:14 PM PST 24
Finished Jan 03 01:43:55 PM PST 24
Peak memory 256672 kb
Host smart-f687ad91-1611-4b35-874e-d709424c9f72
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310055923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.sram_ctrl_max_throughput.310055923
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.507390139
Short name T572
Test name
Test status
Simulation time 8887029046 ps
CPU time 141.84 seconds
Started Jan 03 01:43:14 PM PST 24
Finished Jan 03 01:45:38 PM PST 24
Peak memory 214416 kb
Host smart-0f9c8ba9-6ff5-400a-85f5-159180f5bc89
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507390139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.sram_ctrl_mem_partial_access.507390139
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.2309035752
Short name T274
Test name
Test status
Simulation time 18258038189 ps
CPU time 297.72 seconds
Started Jan 03 01:43:13 PM PST 24
Finished Jan 03 01:48:13 PM PST 24
Peak memory 202168 kb
Host smart-0fa081df-3e8d-4657-8cd7-7d3690b8972a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309035752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr
l_mem_walk.2309035752
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.394299854
Short name T425
Test name
Test status
Simulation time 3800755851 ps
CPU time 697.16 seconds
Started Jan 03 01:43:31 PM PST 24
Finished Jan 03 01:55:09 PM PST 24
Peak memory 372908 kb
Host smart-1b3df753-1aa1-4e33-9a89-471e38cc9ee3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394299854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multip
le_keys.394299854
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.1919155014
Short name T334
Test name
Test status
Simulation time 813804455 ps
CPU time 32.9 seconds
Started Jan 03 01:43:10 PM PST 24
Finished Jan 03 01:43:45 PM PST 24
Peak memory 202108 kb
Host smart-a0737241-1b80-48ba-afa5-21d2c0f34762
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919155014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
sram_ctrl_partial_access.1919155014
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2815903515
Short name T974
Test name
Test status
Simulation time 35817017988 ps
CPU time 583.33 seconds
Started Jan 03 01:42:33 PM PST 24
Finished Jan 03 01:52:19 PM PST 24
Peak memory 202112 kb
Host smart-af03aa82-2b3f-4b5d-8fd6-941eaf6d52a4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815903515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_partial_access_b2b.2815903515
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.2639729807
Short name T491
Test name
Test status
Simulation time 1301432623 ps
CPU time 6.74 seconds
Started Jan 03 01:43:32 PM PST 24
Finished Jan 03 01:43:40 PM PST 24
Peak memory 202276 kb
Host smart-d6e4caa3-c230-40f9-8cbe-876ea7ba6ba9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639729807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.2639729807
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.3675468739
Short name T782
Test name
Test status
Simulation time 16715437236 ps
CPU time 860.63 seconds
Started Jan 03 01:42:27 PM PST 24
Finished Jan 03 01:56:50 PM PST 24
Peak memory 375060 kb
Host smart-ae4b1940-2370-4460-ad58-7f537f572b1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675468739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.3675468739
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.1130812157
Short name T142
Test name
Test status
Simulation time 1924842052 ps
CPU time 21.69 seconds
Started Jan 03 01:43:29 PM PST 24
Finished Jan 03 01:43:52 PM PST 24
Peak memory 233768 kb
Host smart-df8461c5-b511-40ed-b1b1-364466f4e2e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130812157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.1130812157
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all.2089887861
Short name T12
Test name
Test status
Simulation time 382632526419 ps
CPU time 2487.48 seconds
Started Jan 03 01:42:32 PM PST 24
Finished Jan 03 02:24:02 PM PST 24
Peak memory 380180 kb
Host smart-dc7e8dc7-87a7-446c-84dc-18837cae7334
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089887861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.sram_ctrl_stress_all.2089887861
Directory /workspace/20.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.3748849213
Short name T736
Test name
Test status
Simulation time 8422646693 ps
CPU time 250.13 seconds
Started Jan 03 01:43:13 PM PST 24
Finished Jan 03 01:47:25 PM PST 24
Peak memory 202176 kb
Host smart-e02e4d49-0f66-45b4-bf98-dad88a3d49ef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748849213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_stress_pipeline.3748849213
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.153533456
Short name T260
Test name
Test status
Simulation time 799986043 ps
CPU time 120.42 seconds
Started Jan 03 01:42:28 PM PST 24
Finished Jan 03 01:44:31 PM PST 24
Peak memory 344008 kb
Host smart-100f9b28-217b-4a84-8974-be40bc60ab2e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153533456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_throughput_w_partial_write.153533456
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.106539158
Short name T609
Test name
Test status
Simulation time 14619998627 ps
CPU time 1731.52 seconds
Started Jan 03 01:42:37 PM PST 24
Finished Jan 03 02:11:30 PM PST 24
Peak memory 378972 kb
Host smart-4ef36cb8-1c5d-4373-8b56-3a419b018e80
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106539158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 21.sram_ctrl_access_during_key_req.106539158
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.54426900
Short name T264
Test name
Test status
Simulation time 121554254 ps
CPU time 0.64 seconds
Started Jan 03 01:42:50 PM PST 24
Finished Jan 03 01:42:52 PM PST 24
Peak memory 201864 kb
Host smart-d0c2c814-c456-4fe3-8a39-35fe372ecddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54426900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_alert_test.54426900
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.3412183820
Short name T460
Test name
Test status
Simulation time 110189319126 ps
CPU time 1646.97 seconds
Started Jan 03 01:42:48 PM PST 24
Finished Jan 03 02:10:17 PM PST 24
Peak memory 202136 kb
Host smart-8589bf9d-ed42-40b9-a5aa-2015ca8c6377
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412183820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection
.3412183820
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_executable.1554463607
Short name T699
Test name
Test status
Simulation time 20157781779 ps
CPU time 1696.05 seconds
Started Jan 03 01:42:51 PM PST 24
Finished Jan 03 02:11:09 PM PST 24
Peak memory 376012 kb
Host smart-e73655d7-8591-4bf4-b904-94e9cd535279
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554463607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab
le.1554463607
Directory /workspace/21.sram_ctrl_executable/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.1602249389
Short name T598
Test name
Test status
Simulation time 694026027 ps
CPU time 25.26 seconds
Started Jan 03 01:42:47 PM PST 24
Finished Jan 03 01:43:15 PM PST 24
Peak memory 202152 kb
Host smart-9fee6494-074b-4aab-b2d8-84086770780f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602249389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.sram_ctrl_max_throughput.1602249389
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.1519763685
Short name T84
Test name
Test status
Simulation time 13252528625 ps
CPU time 156.21 seconds
Started Jan 03 01:42:50 PM PST 24
Finished Jan 03 01:45:28 PM PST 24
Peak memory 211184 kb
Host smart-096b8463-0baf-4df0-af32-fec7a2d1c076
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519763685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_mem_partial_access.1519763685
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.82607235
Short name T247
Test name
Test status
Simulation time 17902663047 ps
CPU time 279.11 seconds
Started Jan 03 01:42:59 PM PST 24
Finished Jan 03 01:47:40 PM PST 24
Peak memory 202316 kb
Host smart-5fa49827-54a0-49f6-ba0e-cc56684d944a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82607235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_
mem_walk.82607235
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.490920642
Short name T450
Test name
Test status
Simulation time 120393328819 ps
CPU time 1167.89 seconds
Started Jan 03 01:42:32 PM PST 24
Finished Jan 03 02:02:02 PM PST 24
Peak memory 379064 kb
Host smart-e2f544e3-36c2-4e51-bc5c-cadf673f0666
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490920642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multip
le_keys.490920642
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.4049009060
Short name T880
Test name
Test status
Simulation time 2670407411 ps
CPU time 31.13 seconds
Started Jan 03 01:42:34 PM PST 24
Finished Jan 03 01:43:07 PM PST 24
Peak memory 277588 kb
Host smart-6c9c77a4-dd42-4d81-9e39-a355983da5d2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049009060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
sram_ctrl_partial_access.4049009060
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1500386796
Short name T409
Test name
Test status
Simulation time 70112979561 ps
CPU time 398.91 seconds
Started Jan 03 01:42:47 PM PST 24
Finished Jan 03 01:49:28 PM PST 24
Peak memory 202164 kb
Host smart-c55cec45-abe6-404d-a651-3b53d90c13f1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500386796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.sram_ctrl_partial_access_b2b.1500386796
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.292880223
Short name T949
Test name
Test status
Simulation time 3060598648 ps
CPU time 5.66 seconds
Started Jan 03 01:42:50 PM PST 24
Finished Jan 03 01:42:57 PM PST 24
Peak memory 202424 kb
Host smart-0ee63382-e93b-4846-8224-2d64c68b53e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292880223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.292880223
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.852889694
Short name T600
Test name
Test status
Simulation time 36250801184 ps
CPU time 793.1 seconds
Started Jan 03 01:42:51 PM PST 24
Finished Jan 03 01:56:07 PM PST 24
Peak memory 379092 kb
Host smart-faadadbe-26fe-4104-901c-8c61cf2a5aa2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852889694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.852889694
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.1374901964
Short name T362
Test name
Test status
Simulation time 1795653929 ps
CPU time 23.18 seconds
Started Jan 03 01:42:33 PM PST 24
Finished Jan 03 01:42:58 PM PST 24
Peak memory 202000 kb
Host smart-c6fb89e8-7a61-4cf5-964d-dc99c4c3d728
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374901964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.1374901964
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all.94182083
Short name T481
Test name
Test status
Simulation time 277744975191 ps
CPU time 4256.27 seconds
Started Jan 03 01:42:52 PM PST 24
Finished Jan 03 02:53:51 PM PST 24
Peak memory 381168 kb
Host smart-0e781a3b-25fc-4b49-801f-87fe2d87ab93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94182083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +
UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.sram_ctrl_stress_all.94182083
Directory /workspace/21.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.693193501
Short name T706
Test name
Test status
Simulation time 473129431 ps
CPU time 5198.57 seconds
Started Jan 03 01:42:49 PM PST 24
Finished Jan 03 03:09:30 PM PST 24
Peak memory 488980 kb
Host smart-849590de-aaf4-4f3d-a957-dafa32a72515
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=693193501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.693193501
Directory /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.4143158245
Short name T70
Test name
Test status
Simulation time 14105437750 ps
CPU time 193.51 seconds
Started Jan 03 01:42:37 PM PST 24
Finished Jan 03 01:45:52 PM PST 24
Peak memory 202120 kb
Host smart-1d6861bf-600b-4a88-b07c-8a2d15c42421
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143158245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_stress_pipeline.4143158245
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2149936146
Short name T879
Test name
Test status
Simulation time 2815236255 ps
CPU time 28.58 seconds
Started Jan 03 01:42:49 PM PST 24
Finished Jan 03 01:43:19 PM PST 24
Peak memory 218420 kb
Host smart-fae475aa-6ca3-4236-ad17-57701529c9a8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149936146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.2149936146
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.3220870186
Short name T677
Test name
Test status
Simulation time 36788207814 ps
CPU time 1082.58 seconds
Started Jan 03 01:43:41 PM PST 24
Finished Jan 03 02:01:45 PM PST 24
Peak memory 378016 kb
Host smart-c8b645d2-cdd6-4a28-bf5c-63775410a6f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220870186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.sram_ctrl_access_during_key_req.3220870186
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.849767988
Short name T279
Test name
Test status
Simulation time 26116433 ps
CPU time 0.66 seconds
Started Jan 03 01:43:38 PM PST 24
Finished Jan 03 01:43:40 PM PST 24
Peak memory 201784 kb
Host smart-3803a7f9-aaac-447c-89f8-a98b927ff14f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849767988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.sram_ctrl_alert_test.849767988
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_bijection.3056314952
Short name T618
Test name
Test status
Simulation time 67572831608 ps
CPU time 752.71 seconds
Started Jan 03 01:42:55 PM PST 24
Finished Jan 03 01:55:29 PM PST 24
Peak memory 202148 kb
Host smart-0ec14a0e-1f02-48df-803f-6673b3146128
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056314952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection
.3056314952
Directory /workspace/22.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/22.sram_ctrl_executable.614523099
Short name T685
Test name
Test status
Simulation time 23373216091 ps
CPU time 1004.95 seconds
Started Jan 03 01:43:41 PM PST 24
Finished Jan 03 02:00:28 PM PST 24
Peak memory 377068 kb
Host smart-8e42ffca-4d95-45f7-a8f6-ddfd57a3685c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614523099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executabl
e.614523099
Directory /workspace/22.sram_ctrl_executable/latest

Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.3248296621
Short name T509
Test name
Test status
Simulation time 4013644463 ps
CPU time 33.89 seconds
Started Jan 03 01:43:34 PM PST 24
Finished Jan 03 01:44:09 PM PST 24
Peak memory 202184 kb
Host smart-0a6ce5dc-16f1-4c90-a341-53eb1b253077
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248296621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es
calation.3248296621
Directory /workspace/22.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.3687907828
Short name T229
Test name
Test status
Simulation time 2698464925 ps
CPU time 29.98 seconds
Started Jan 03 01:43:35 PM PST 24
Finished Jan 03 01:44:06 PM PST 24
Peak memory 218508 kb
Host smart-530723e0-aec8-41bb-8e1e-669b5a209694
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687907828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sram_ctrl_max_throughput.3687907828
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.32532090
Short name T391
Test name
Test status
Simulation time 8723635284 ps
CPU time 160.22 seconds
Started Jan 03 01:43:38 PM PST 24
Finished Jan 03 01:46:19 PM PST 24
Peak memory 211264 kb
Host smart-28e04ad4-8489-4135-a9e5-c078479ad3da
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32532090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
sram_ctrl_mem_partial_access.32532090
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.3738460389
Short name T852
Test name
Test status
Simulation time 43098228638 ps
CPU time 162.83 seconds
Started Jan 03 01:43:42 PM PST 24
Finished Jan 03 01:46:27 PM PST 24
Peak memory 202252 kb
Host smart-eafea55e-3617-4db4-b699-30a4f18a0650
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738460389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr
l_mem_walk.3738460389
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.3979031512
Short name T432
Test name
Test status
Simulation time 18311470038 ps
CPU time 778.53 seconds
Started Jan 03 01:42:54 PM PST 24
Finished Jan 03 01:55:54 PM PST 24
Peak memory 380108 kb
Host smart-b657cdf8-b828-470e-93fd-2f7d6e16b826
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979031512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi
ple_keys.3979031512
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.1588295010
Short name T555
Test name
Test status
Simulation time 3323420824 ps
CPU time 61.16 seconds
Started Jan 03 01:42:55 PM PST 24
Finished Jan 03 01:43:57 PM PST 24
Peak memory 309300 kb
Host smart-e5aa8a84-7ef8-4337-8a3d-3a62918efc2e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588295010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
sram_ctrl_partial_access.1588295010
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3979131664
Short name T670
Test name
Test status
Simulation time 19474494122 ps
CPU time 303.37 seconds
Started Jan 03 01:43:12 PM PST 24
Finished Jan 03 01:48:17 PM PST 24
Peak memory 202184 kb
Host smart-989c4882-46b2-497c-9cac-08270ff7f321
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979131664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.sram_ctrl_partial_access_b2b.3979131664
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.3742490724
Short name T537
Test name
Test status
Simulation time 718599657 ps
CPU time 6.51 seconds
Started Jan 03 01:43:39 PM PST 24
Finished Jan 03 01:43:47 PM PST 24
Peak memory 202336 kb
Host smart-ccc701d3-0c89-4e49-ab03-792e6b688334
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742490724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.3742490724
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_regwen.65601882
Short name T673
Test name
Test status
Simulation time 52361252024 ps
CPU time 1609.59 seconds
Started Jan 03 01:43:37 PM PST 24
Finished Jan 03 02:10:27 PM PST 24
Peak memory 377900 kb
Host smart-20cb2a8c-ad2e-4f9e-87ad-668ce1711848
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65601882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.65601882
Directory /workspace/22.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.1160240655
Short name T426
Test name
Test status
Simulation time 829967066 ps
CPU time 17.12 seconds
Started Jan 03 01:42:56 PM PST 24
Finished Jan 03 01:43:15 PM PST 24
Peak memory 202104 kb
Host smart-a2c9fb3e-575d-48f5-bfa7-437750596653
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160240655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.1160240655
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all.2551002611
Short name T627
Test name
Test status
Simulation time 223946121980 ps
CPU time 4100.75 seconds
Started Jan 03 01:43:41 PM PST 24
Finished Jan 03 02:52:05 PM PST 24
Peak memory 373864 kb
Host smart-55427254-4b5a-44d1-9416-7bebd710d75f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551002611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.sram_ctrl_stress_all.2551002611
Directory /workspace/22.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3835610014
Short name T321
Test name
Test status
Simulation time 719722972 ps
CPU time 2269.87 seconds
Started Jan 03 01:43:37 PM PST 24
Finished Jan 03 02:21:28 PM PST 24
Peak memory 458040 kb
Host smart-3f69a0c7-6d91-466d-9b1f-3c3a5969dd6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3835610014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.3835610014
Directory /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.613819289
Short name T399
Test name
Test status
Simulation time 8953258207 ps
CPU time 326.39 seconds
Started Jan 03 01:42:55 PM PST 24
Finished Jan 03 01:48:24 PM PST 24
Peak memory 202148 kb
Host smart-7ef5c98f-7da9-4000-940b-1647b3b4d3f4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613819289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.sram_ctrl_stress_pipeline.613819289
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1804026719
Short name T353
Test name
Test status
Simulation time 3969441147 ps
CPU time 102.4 seconds
Started Jan 03 01:43:33 PM PST 24
Finished Jan 03 01:45:17 PM PST 24
Peak memory 329988 kb
Host smart-6004ab66-a660-4b1d-ac9e-e2fcf046f183
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804026719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.1804026719
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.517474648
Short name T476
Test name
Test status
Simulation time 34097087760 ps
CPU time 566.91 seconds
Started Jan 03 01:43:45 PM PST 24
Finished Jan 03 01:53:15 PM PST 24
Peak memory 379988 kb
Host smart-2417c3dd-2c5b-42c6-91aa-40a16143396f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517474648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 23.sram_ctrl_access_during_key_req.517474648
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.3336889708
Short name T327
Test name
Test status
Simulation time 34846875 ps
CPU time 0.65 seconds
Started Jan 03 01:44:16 PM PST 24
Finished Jan 03 01:44:18 PM PST 24
Peak memory 201784 kb
Host smart-93731785-7e84-483f-a637-42c0442475d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336889708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.3336889708
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.1563134631
Short name T847
Test name
Test status
Simulation time 33143119470 ps
CPU time 2203.45 seconds
Started Jan 03 01:43:44 PM PST 24
Finished Jan 03 02:20:31 PM PST 24
Peak memory 202224 kb
Host smart-188c7dc3-72be-4857-b7b8-983a89e0d853
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563134631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection
.1563134631
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_executable.2769159287
Short name T802
Test name
Test status
Simulation time 26659280529 ps
CPU time 454.32 seconds
Started Jan 03 01:44:28 PM PST 24
Finished Jan 03 01:52:09 PM PST 24
Peak memory 323060 kb
Host smart-a39e8ded-0b34-4b8d-94f9-9b7449d24b49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769159287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab
le.2769159287
Directory /workspace/23.sram_ctrl_executable/latest

Test location /workspace/coverage/default/23.sram_ctrl_lc_escalation.3284733532
Short name T315
Test name
Test status
Simulation time 3691271331 ps
CPU time 87.69 seconds
Started Jan 03 01:43:39 PM PST 24
Finished Jan 03 01:45:08 PM PST 24
Peak memory 210316 kb
Host smart-c180cda8-c457-48bf-be5c-699b2f715310
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284733532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es
calation.3284733532
Directory /workspace/23.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.2293915812
Short name T703
Test name
Test status
Simulation time 799193645 ps
CPU time 153.78 seconds
Started Jan 03 01:44:02 PM PST 24
Finished Jan 03 01:46:39 PM PST 24
Peak memory 365796 kb
Host smart-9af07df5-fb12-48af-b632-fd52ecc0ca88
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293915812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_max_throughput.2293915812
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.2230490137
Short name T89
Test name
Test status
Simulation time 39171193036 ps
CPU time 81.51 seconds
Started Jan 03 01:44:30 PM PST 24
Finished Jan 03 01:45:57 PM PST 24
Peak memory 211796 kb
Host smart-ccb396fc-0510-4894-bd08-ce32a4605b6b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230490137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_mem_partial_access.2230490137
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.2462914182
Short name T727
Test name
Test status
Simulation time 2152452097 ps
CPU time 125.76 seconds
Started Jan 03 01:43:44 PM PST 24
Finished Jan 03 01:45:52 PM PST 24
Peak memory 202084 kb
Host smart-b9a082d7-23b7-46c8-af67-6c10a4b41b99
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462914182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr
l_mem_walk.2462914182
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.3217141996
Short name T280
Test name
Test status
Simulation time 8358915026 ps
CPU time 447.57 seconds
Started Jan 03 01:43:43 PM PST 24
Finished Jan 03 01:51:14 PM PST 24
Peak memory 380168 kb
Host smart-d20101b6-cb03-4397-8557-c46645794ebe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217141996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi
ple_keys.3217141996
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.715802562
Short name T774
Test name
Test status
Simulation time 2086930237 ps
CPU time 18.18 seconds
Started Jan 03 01:44:01 PM PST 24
Finished Jan 03 01:44:23 PM PST 24
Peak memory 202096 kb
Host smart-942c0fe5-a6e9-4dee-9a9e-aa247d5bd008
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715802562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.s
ram_ctrl_partial_access.715802562
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3404543479
Short name T544
Test name
Test status
Simulation time 45524720939 ps
CPU time 300.51 seconds
Started Jan 03 01:43:42 PM PST 24
Finished Jan 03 01:48:45 PM PST 24
Peak memory 202084 kb
Host smart-7b2bf8f3-67c0-4b43-99b7-915cbf452e86
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404543479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.sram_ctrl_partial_access_b2b.3404543479
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.2500327078
Short name T304
Test name
Test status
Simulation time 349549087 ps
CPU time 6.56 seconds
Started Jan 03 01:43:45 PM PST 24
Finished Jan 03 01:43:54 PM PST 24
Peak memory 202364 kb
Host smart-56a4c312-9d7f-45fb-b4a0-3ada4996cab4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500327078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2500327078
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.3643017924
Short name T941
Test name
Test status
Simulation time 15710142028 ps
CPU time 1184.36 seconds
Started Jan 03 01:43:39 PM PST 24
Finished Jan 03 02:03:25 PM PST 24
Peak memory 380128 kb
Host smart-23448627-4af5-4784-b027-53cfbb7dc88f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643017924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.3643017924
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.4048157845
Short name T958
Test name
Test status
Simulation time 3275426161 ps
CPU time 37.19 seconds
Started Jan 03 01:43:38 PM PST 24
Finished Jan 03 01:44:16 PM PST 24
Peak memory 202128 kb
Host smart-18c4c166-50d6-4a0b-95c3-ee021f574504
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048157845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.4048157845
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.4009564247
Short name T364
Test name
Test status
Simulation time 1225049343 ps
CPU time 2446.21 seconds
Started Jan 03 01:43:10 PM PST 24
Finished Jan 03 02:23:58 PM PST 24
Peak memory 532952 kb
Host smart-ad0c5bf5-1ddb-4a2c-906a-48f07db36f92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4009564247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.4009564247
Directory /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.3249048887
Short name T986
Test name
Test status
Simulation time 4880529939 ps
CPU time 327.95 seconds
Started Jan 03 01:44:27 PM PST 24
Finished Jan 03 01:50:03 PM PST 24
Peak memory 202192 kb
Host smart-245dca5b-fce1-402c-94bb-1e069fcd2a3b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249048887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_stress_pipeline.3249048887
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.510973040
Short name T772
Test name
Test status
Simulation time 777287371 ps
CPU time 66.44 seconds
Started Jan 03 01:43:45 PM PST 24
Finished Jan 03 01:44:54 PM PST 24
Peak memory 296132 kb
Host smart-dc70b1d4-32eb-4fe7-8c2c-62b8a7ca69fd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510973040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_throughput_w_partial_write.510973040
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.1578672272
Short name T359
Test name
Test status
Simulation time 18638610341 ps
CPU time 2041.34 seconds
Started Jan 03 01:43:11 PM PST 24
Finished Jan 03 02:17:14 PM PST 24
Peak memory 379040 kb
Host smart-2e8c4b71-5ebd-4482-8c0f-802131ffd06d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578672272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.sram_ctrl_access_during_key_req.1578672272
Directory /workspace/24.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.2746073911
Short name T443
Test name
Test status
Simulation time 64309505 ps
CPU time 0.65 seconds
Started Jan 03 01:43:13 PM PST 24
Finished Jan 03 01:43:16 PM PST 24
Peak memory 201760 kb
Host smart-4b6b46f0-50ee-4d58-941a-036090ffaad3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746073911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.sram_ctrl_alert_test.2746073911
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.3301334483
Short name T532
Test name
Test status
Simulation time 150643380825 ps
CPU time 689.9 seconds
Started Jan 03 01:43:31 PM PST 24
Finished Jan 03 01:55:02 PM PST 24
Peak memory 202228 kb
Host smart-dfe059b5-4f7d-467b-b10c-bff447f31ff6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301334483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection
.3301334483
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.801875206
Short name T522
Test name
Test status
Simulation time 10432493071 ps
CPU time 90.88 seconds
Started Jan 03 01:43:33 PM PST 24
Finished Jan 03 01:45:05 PM PST 24
Peak memory 313672 kb
Host smart-601b334c-0b75-4fe1-8073-9fb4cc9a7dc3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801875206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.sram_ctrl_max_throughput.801875206
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.720516064
Short name T513
Test name
Test status
Simulation time 18034057914 ps
CPU time 152.27 seconds
Started Jan 03 01:43:34 PM PST 24
Finished Jan 03 01:46:08 PM PST 24
Peak memory 211068 kb
Host smart-6ba0ac4d-3184-4b4d-87c8-c6f3d4b701de
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720516064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.sram_ctrl_mem_partial_access.720516064
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.598297532
Short name T363
Test name
Test status
Simulation time 111890853997 ps
CPU time 165.75 seconds
Started Jan 03 01:43:14 PM PST 24
Finished Jan 03 01:46:02 PM PST 24
Peak memory 202140 kb
Host smart-dd55b9d1-e59d-44eb-b12c-96116dae22f9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598297532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl
_mem_walk.598297532
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.3603519982
Short name T517
Test name
Test status
Simulation time 45173456775 ps
CPU time 1607.75 seconds
Started Jan 03 01:43:12 PM PST 24
Finished Jan 03 02:10:02 PM PST 24
Peak memory 379048 kb
Host smart-c4cc7909-a288-4a03-ac48-2503b539cdf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603519982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi
ple_keys.3603519982
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.3751299729
Short name T594
Test name
Test status
Simulation time 1528138248 ps
CPU time 6.85 seconds
Started Jan 03 01:43:30 PM PST 24
Finished Jan 03 01:43:37 PM PST 24
Peak memory 201992 kb
Host smart-5ff60ede-0791-4fa1-84fe-dd3aab69b1d3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751299729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
sram_ctrl_partial_access.3751299729
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1526621673
Short name T840
Test name
Test status
Simulation time 28061759995 ps
CPU time 549.41 seconds
Started Jan 03 01:43:33 PM PST 24
Finished Jan 03 01:52:43 PM PST 24
Peak memory 202192 kb
Host smart-734ed1ec-3b87-480f-9fed-84516f688246
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526621673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.sram_ctrl_partial_access_b2b.1526621673
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.4019917318
Short name T776
Test name
Test status
Simulation time 355937362 ps
CPU time 5.88 seconds
Started Jan 03 01:43:16 PM PST 24
Finished Jan 03 01:43:23 PM PST 24
Peak memory 202392 kb
Host smart-8747656d-e09d-481b-8ef2-140ed0c10f6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019917318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.4019917318
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.2392196641
Short name T18
Test name
Test status
Simulation time 2970205141 ps
CPU time 62.68 seconds
Started Jan 03 01:43:34 PM PST 24
Finished Jan 03 01:44:38 PM PST 24
Peak memory 296592 kb
Host smart-b89b072d-ca85-40a2-be61-030e44abe268
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392196641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.2392196641
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.3726698777
Short name T823
Test name
Test status
Simulation time 1517669519 ps
CPU time 16.09 seconds
Started Jan 03 01:43:06 PM PST 24
Finished Jan 03 01:43:24 PM PST 24
Peak memory 202052 kb
Host smart-8d57b462-f7c2-4c6b-8083-99891ab2a916
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726698777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.3726698777
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3503290624
Short name T346
Test name
Test status
Simulation time 15006749779 ps
CPU time 2155.04 seconds
Started Jan 03 01:43:37 PM PST 24
Finished Jan 03 02:19:34 PM PST 24
Peak memory 417256 kb
Host smart-ecc26794-8476-46c4-ba2e-d1cc3b7f5635
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3503290624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.3503290624
Directory /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.3140146520
Short name T574
Test name
Test status
Simulation time 19296681082 ps
CPU time 341.5 seconds
Started Jan 03 01:43:13 PM PST 24
Finished Jan 03 01:48:56 PM PST 24
Peak memory 202164 kb
Host smart-311a89ab-3682-4a60-9b91-53e53eae1d9b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140146520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_stress_pipeline.3140146520
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3930103002
Short name T729
Test name
Test status
Simulation time 679943349 ps
CPU time 29.48 seconds
Started Jan 03 01:43:14 PM PST 24
Finished Jan 03 01:43:45 PM PST 24
Peak memory 211604 kb
Host smart-0878dbe4-44a3-4866-adba-916944832139
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930103002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.3930103002
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.2369020536
Short name T434
Test name
Test status
Simulation time 18353257204 ps
CPU time 943.33 seconds
Started Jan 03 01:43:38 PM PST 24
Finished Jan 03 01:59:22 PM PST 24
Peak memory 377988 kb
Host smart-7f895d57-c380-421f-987f-94718c43a105
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369020536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.sram_ctrl_access_during_key_req.2369020536
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.2386869088
Short name T861
Test name
Test status
Simulation time 26956146 ps
CPU time 0.68 seconds
Started Jan 03 01:43:42 PM PST 24
Finished Jan 03 01:43:46 PM PST 24
Peak memory 201852 kb
Host smart-f93c6680-992a-45b2-b5cf-33afe9260384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386869088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.2386869088
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.126956037
Short name T664
Test name
Test status
Simulation time 49219944081 ps
CPU time 476.73 seconds
Started Jan 03 01:43:41 PM PST 24
Finished Jan 03 01:51:40 PM PST 24
Peak memory 202244 kb
Host smart-6afe0101-fdb6-41bb-bc76-3e6295708952
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126956037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.
126956037
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_executable.84614525
Short name T464
Test name
Test status
Simulation time 10768159286 ps
CPU time 60.82 seconds
Started Jan 03 01:43:39 PM PST 24
Finished Jan 03 01:44:42 PM PST 24
Peak memory 256588 kb
Host smart-fd0adfa8-0d8a-4609-91c4-aa2792ab1d7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84614525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut
able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable
.84614525
Directory /workspace/25.sram_ctrl_executable/latest

Test location /workspace/coverage/default/25.sram_ctrl_lc_escalation.2913938654
Short name T29
Test name
Test status
Simulation time 36862640053 ps
CPU time 204.43 seconds
Started Jan 03 01:43:40 PM PST 24
Finished Jan 03 01:47:06 PM PST 24
Peak memory 210424 kb
Host smart-1f7ccd60-f90c-4ab8-8769-7e6ce6fa0f15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913938654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es
calation.2913938654
Directory /workspace/25.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.1623339201
Short name T378
Test name
Test status
Simulation time 2266575474 ps
CPU time 29.35 seconds
Started Jan 03 01:43:35 PM PST 24
Finished Jan 03 01:44:06 PM PST 24
Peak memory 217488 kb
Host smart-d7df2391-d1b9-44ec-bc4a-7f2fac6388a4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623339201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.sram_ctrl_max_throughput.1623339201
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.240661695
Short name T828
Test name
Test status
Simulation time 6243379150 ps
CPU time 141.06 seconds
Started Jan 03 01:43:41 PM PST 24
Finished Jan 03 01:46:04 PM PST 24
Peak memory 214392 kb
Host smart-dceb1c61-be21-426c-ad7b-33b894a2c394
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240661695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.sram_ctrl_mem_partial_access.240661695
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.3425987013
Short name T242
Test name
Test status
Simulation time 41383673424 ps
CPU time 149.54 seconds
Started Jan 03 01:43:44 PM PST 24
Finished Jan 03 01:46:16 PM PST 24
Peak memory 202100 kb
Host smart-f01cca16-8abf-42d0-b813-28421940a520
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425987013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr
l_mem_walk.3425987013
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.3741404047
Short name T914
Test name
Test status
Simulation time 19453773959 ps
CPU time 1100.21 seconds
Started Jan 03 01:43:15 PM PST 24
Finished Jan 03 02:01:37 PM PST 24
Peak memory 380252 kb
Host smart-403d5e8c-fabd-42d1-b666-fd48d5288bd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741404047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi
ple_keys.3741404047
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.1265614142
Short name T295
Test name
Test status
Simulation time 886345512 ps
CPU time 101.28 seconds
Started Jan 03 01:43:39 PM PST 24
Finished Jan 03 01:45:21 PM PST 24
Peak memory 324656 kb
Host smart-c3479a8d-7080-42d1-8d5a-fde7bda26e26
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265614142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
sram_ctrl_partial_access.1265614142
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.196921946
Short name T681
Test name
Test status
Simulation time 84986111991 ps
CPU time 409.6 seconds
Started Jan 03 01:43:36 PM PST 24
Finished Jan 03 01:50:27 PM PST 24
Peak memory 202160 kb
Host smart-69ca61f8-6457-499f-9306-b48aac0498f3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196921946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.sram_ctrl_partial_access_b2b.196921946
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.3836240742
Short name T508
Test name
Test status
Simulation time 362600469 ps
CPU time 5.91 seconds
Started Jan 03 01:43:38 PM PST 24
Finished Jan 03 01:43:45 PM PST 24
Peak memory 202460 kb
Host smart-0c5f499d-dc17-4908-bf3a-aa22d29cd536
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836240742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.3836240742
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.86645424
Short name T898
Test name
Test status
Simulation time 20086904499 ps
CPU time 666.68 seconds
Started Jan 03 01:43:40 PM PST 24
Finished Jan 03 01:54:49 PM PST 24
Peak memory 364916 kb
Host smart-e4981ae5-c5f8-41fb-9686-07826a964dfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86645424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.86645424
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.2137252537
Short name T950
Test name
Test status
Simulation time 1146882226 ps
CPU time 22.2 seconds
Started Jan 03 01:43:39 PM PST 24
Finished Jan 03 01:44:02 PM PST 24
Peak memory 202032 kb
Host smart-13d62521-d656-482e-a614-2132cbf3329b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137252537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.2137252537
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all.1092039408
Short name T721
Test name
Test status
Simulation time 569746856335 ps
CPU time 4948.37 seconds
Started Jan 03 01:43:41 PM PST 24
Finished Jan 03 03:06:12 PM PST 24
Peak memory 381080 kb
Host smart-5fff2e88-4289-4440-af8b-f0c0e21972e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092039408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.sram_ctrl_stress_all.1092039408
Directory /workspace/25.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.4010555495
Short name T514
Test name
Test status
Simulation time 2815466862 ps
CPU time 4316.57 seconds
Started Jan 03 01:43:42 PM PST 24
Finished Jan 03 02:55:42 PM PST 24
Peak memory 653536 kb
Host smart-425c8709-f36b-4460-8727-f72c6ce871b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4010555495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.4010555495
Directory /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.2126729450
Short name T676
Test name
Test status
Simulation time 2683696002 ps
CPU time 181.9 seconds
Started Jan 03 01:43:40 PM PST 24
Finished Jan 03 01:46:44 PM PST 24
Peak memory 202100 kb
Host smart-cc722db4-ab53-4534-89e3-4a88af063121
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126729450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_stress_pipeline.2126729450
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.603231295
Short name T245
Test name
Test status
Simulation time 13666319980 ps
CPU time 31.55 seconds
Started Jan 03 01:43:40 PM PST 24
Finished Jan 03 01:44:13 PM PST 24
Peak memory 226788 kb
Host smart-a23a77c7-f267-4e57-858d-4145930f0808
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603231295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.sram_ctrl_throughput_w_partial_write.603231295
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.31109691
Short name T819
Test name
Test status
Simulation time 42710970861 ps
CPU time 1713.07 seconds
Started Jan 03 01:44:16 PM PST 24
Finished Jan 03 02:12:50 PM PST 24
Peak memory 380084 kb
Host smart-4dc0e921-5370-4f0c-9880-7210ca9760c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31109691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.sram_ctrl_access_during_key_req.31109691
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.3114163252
Short name T647
Test name
Test status
Simulation time 27106318 ps
CPU time 0.7 seconds
Started Jan 03 01:44:56 PM PST 24
Finished Jan 03 01:44:59 PM PST 24
Peak memory 201792 kb
Host smart-a574f81a-77cb-4e33-aa51-49c7c7de34dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114163252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.3114163252
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.1230806167
Short name T61
Test name
Test status
Simulation time 239939950362 ps
CPU time 1423.92 seconds
Started Jan 03 01:43:45 PM PST 24
Finished Jan 03 02:07:32 PM PST 24
Peak memory 202216 kb
Host smart-6df97976-f696-4952-8067-c0cfbbe4edf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230806167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection
.1230806167
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_lc_escalation.3390010177
Short name T599
Test name
Test status
Simulation time 44428232992 ps
CPU time 322.38 seconds
Started Jan 03 01:44:36 PM PST 24
Finished Jan 03 01:50:03 PM PST 24
Peak memory 202160 kb
Host smart-444b34ed-55b5-4696-b484-0e9f04e02337
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390010177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es
calation.3390010177
Directory /workspace/26.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.2377089153
Short name T789
Test name
Test status
Simulation time 2973331551 ps
CPU time 31.91 seconds
Started Jan 03 01:44:31 PM PST 24
Finished Jan 03 01:45:07 PM PST 24
Peak memory 234556 kb
Host smart-b14a0eaa-657c-4b03-841e-3a8f3bcc366a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377089153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_max_throughput.2377089153
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.425174159
Short name T401
Test name
Test status
Simulation time 9175049114 ps
CPU time 79.64 seconds
Started Jan 03 01:44:56 PM PST 24
Finished Jan 03 01:46:18 PM PST 24
Peak memory 211464 kb
Host smart-61bac12f-e911-4b60-a31c-7cb26e3aaf7b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425174159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.sram_ctrl_mem_partial_access.425174159
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.2932788412
Short name T232
Test name
Test status
Simulation time 1999790685 ps
CPU time 120.64 seconds
Started Jan 03 01:44:56 PM PST 24
Finished Jan 03 01:46:59 PM PST 24
Peak memory 202036 kb
Host smart-fd0807ed-a7d5-4874-92c9-7664f61d8276
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932788412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr
l_mem_walk.2932788412
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.3818593466
Short name T842
Test name
Test status
Simulation time 28564834614 ps
CPU time 744.37 seconds
Started Jan 03 01:43:42 PM PST 24
Finished Jan 03 01:56:10 PM PST 24
Peak memory 370856 kb
Host smart-ae27b6c1-99c6-4393-b623-eeb68115a87b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818593466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi
ple_keys.3818593466
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.327936577
Short name T873
Test name
Test status
Simulation time 2294294639 ps
CPU time 21.03 seconds
Started Jan 03 01:43:59 PM PST 24
Finished Jan 03 01:44:22 PM PST 24
Peak memory 254584 kb
Host smart-713f79ca-5a74-4301-8712-542e7c4d4548
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327936577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.s
ram_ctrl_partial_access.327936577
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1444262096
Short name T588
Test name
Test status
Simulation time 94412351152 ps
CPU time 535.51 seconds
Started Jan 03 01:44:52 PM PST 24
Finished Jan 03 01:53:49 PM PST 24
Peak memory 202176 kb
Host smart-34765297-b1c3-4439-9960-819a675846ff
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444262096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.sram_ctrl_partial_access_b2b.1444262096
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.4061313783
Short name T257
Test name
Test status
Simulation time 1534047636 ps
CPU time 14.21 seconds
Started Jan 03 01:44:55 PM PST 24
Finished Jan 03 01:45:11 PM PST 24
Peak memory 202420 kb
Host smart-99a27f06-e12a-41fc-8b03-2a4547bc523d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061313783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.4061313783
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.3892428113
Short name T131
Test name
Test status
Simulation time 22900925652 ps
CPU time 1050.04 seconds
Started Jan 03 01:44:53 PM PST 24
Finished Jan 03 02:02:25 PM PST 24
Peak memory 377056 kb
Host smart-431db055-36ca-4bf9-9795-ef348d2e7db9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892428113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.3892428113
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.4211640854
Short name T278
Test name
Test status
Simulation time 3258608511 ps
CPU time 14.31 seconds
Started Jan 03 01:43:41 PM PST 24
Finished Jan 03 01:43:58 PM PST 24
Peak memory 202096 kb
Host smart-fba8e674-6b35-4b5c-a2f8-5be068aad657
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211640854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.4211640854
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all.1819533310
Short name T907
Test name
Test status
Simulation time 35727303472 ps
CPU time 2323.82 seconds
Started Jan 03 01:44:59 PM PST 24
Finished Jan 03 02:23:45 PM PST 24
Peak memory 377260 kb
Host smart-5f4d2e07-875f-4de3-89ef-3e4596ff4764
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819533310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.sram_ctrl_stress_all.1819533310
Directory /workspace/26.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.860319205
Short name T967
Test name
Test status
Simulation time 3190510166 ps
CPU time 2701.7 seconds
Started Jan 03 01:44:56 PM PST 24
Finished Jan 03 02:29:59 PM PST 24
Peak memory 610248 kb
Host smart-30b278a1-7a7d-42c2-8910-962ed26a9623
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=860319205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.860319205
Directory /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.330767658
Short name T337
Test name
Test status
Simulation time 7901775277 ps
CPU time 270.86 seconds
Started Jan 03 01:44:02 PM PST 24
Finished Jan 03 01:48:37 PM PST 24
Peak memory 202132 kb
Host smart-84f6573e-388a-41a7-8068-03c86c085974
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330767658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.sram_ctrl_stress_pipeline.330767658
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3012269489
Short name T241
Test name
Test status
Simulation time 5847769454 ps
CPU time 41.4 seconds
Started Jan 03 01:44:56 PM PST 24
Finished Jan 03 01:45:39 PM PST 24
Peak memory 253352 kb
Host smart-bb37a950-a836-4bec-a159-a5f756a067aa
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012269489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.3012269489
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.2460150576
Short name T595
Test name
Test status
Simulation time 11682325079 ps
CPU time 508.33 seconds
Started Jan 03 01:43:39 PM PST 24
Finished Jan 03 01:52:09 PM PST 24
Peak memory 354512 kb
Host smart-3c820b63-db1b-4dc2-b2e4-7b0196f34239
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460150576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.sram_ctrl_access_during_key_req.2460150576
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.272833305
Short name T393
Test name
Test status
Simulation time 89495964 ps
CPU time 0.65 seconds
Started Jan 03 01:43:39 PM PST 24
Finished Jan 03 01:43:41 PM PST 24
Peak memory 201404 kb
Host smart-e196a4cc-fe07-4d72-a06b-b87832f5d712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272833305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.sram_ctrl_alert_test.272833305
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.346729792
Short name T970
Test name
Test status
Simulation time 15342941539 ps
CPU time 666.5 seconds
Started Jan 03 01:43:37 PM PST 24
Finished Jan 03 01:54:44 PM PST 24
Peak memory 202116 kb
Host smart-736f1b51-2b36-416d-8d04-64b904996820
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346729792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.
346729792
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_lc_escalation.2270237277
Short name T711
Test name
Test status
Simulation time 33720061390 ps
CPU time 164.84 seconds
Started Jan 03 01:43:41 PM PST 24
Finished Jan 03 01:46:28 PM PST 24
Peak memory 210380 kb
Host smart-38b59dbb-9683-4d5f-9c09-758be859f792
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270237277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es
calation.2270237277
Directory /workspace/27.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.1540373137
Short name T384
Test name
Test status
Simulation time 8439920017 ps
CPU time 29.99 seconds
Started Jan 03 01:43:43 PM PST 24
Finished Jan 03 01:44:16 PM PST 24
Peak memory 219960 kb
Host smart-fa3f3e84-4cb7-4804-b878-a34ffca0bfc1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540373137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.sram_ctrl_max_throughput.1540373137
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.1183163833
Short name T733
Test name
Test status
Simulation time 3810065947 ps
CPU time 76.14 seconds
Started Jan 03 01:43:41 PM PST 24
Finished Jan 03 01:45:00 PM PST 24
Peak memory 211164 kb
Host smart-ccbb44b2-d232-494f-b3c8-e86f3dc5893d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183163833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_mem_partial_access.1183163833
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.3902221818
Short name T339
Test name
Test status
Simulation time 3943313816 ps
CPU time 249.12 seconds
Started Jan 03 01:43:41 PM PST 24
Finished Jan 03 01:47:52 PM PST 24
Peak memory 202084 kb
Host smart-0757b1ff-387f-4a67-abf5-339fb89db774
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902221818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr
l_mem_walk.3902221818
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.1047505421
Short name T248
Test name
Test status
Simulation time 149343736254 ps
CPU time 913.51 seconds
Started Jan 03 01:45:00 PM PST 24
Finished Jan 03 02:00:16 PM PST 24
Peak memory 379080 kb
Host smart-76a1bd88-b45b-4d6e-a50e-598ac79a9deb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047505421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi
ple_keys.1047505421
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.3416088692
Short name T722
Test name
Test status
Simulation time 3674269683 ps
CPU time 34.55 seconds
Started Jan 03 01:45:02 PM PST 24
Finished Jan 03 01:45:40 PM PST 24
Peak memory 202088 kb
Host smart-bd9f5cc8-6864-488f-a393-4cb491d77b48
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416088692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
sram_ctrl_partial_access.3416088692
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2731910027
Short name T866
Test name
Test status
Simulation time 7431425788 ps
CPU time 220.26 seconds
Started Jan 03 01:45:14 PM PST 24
Finished Jan 03 01:49:03 PM PST 24
Peak memory 202188 kb
Host smart-b95cdc85-1683-46bc-9f29-c36831c67a68
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731910027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_partial_access_b2b.2731910027
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.3899094541
Short name T273
Test name
Test status
Simulation time 1356433548 ps
CPU time 13.62 seconds
Started Jan 03 01:43:36 PM PST 24
Finished Jan 03 01:43:51 PM PST 24
Peak memory 202396 kb
Host smart-3fe5caa7-33b7-49ec-8572-cded785ea9fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899094541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.3899094541
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.2746452046
Short name T854
Test name
Test status
Simulation time 1752725420 ps
CPU time 155.23 seconds
Started Jan 03 01:43:39 PM PST 24
Finished Jan 03 01:46:17 PM PST 24
Peak memory 368660 kb
Host smart-163a4397-7088-4dfb-8c39-7892d70a3d4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746452046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.2746452046
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.3694986147
Short name T895
Test name
Test status
Simulation time 1416904779 ps
CPU time 13.42 seconds
Started Jan 03 01:44:58 PM PST 24
Finished Jan 03 01:45:13 PM PST 24
Peak memory 202104 kb
Host smart-a473e5b8-0b9b-48ff-83ad-0b74cc256a2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694986147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.3694986147
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all.131652366
Short name T582
Test name
Test status
Simulation time 124171783220 ps
CPU time 4864.63 seconds
Started Jan 03 01:43:39 PM PST 24
Finished Jan 03 03:04:45 PM PST 24
Peak memory 379024 kb
Host smart-ca1fd25d-8b95-4934-8dd3-3b1abd436718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131652366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_stress_all.131652366
Directory /workspace/27.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2956512770
Short name T406
Test name
Test status
Simulation time 14676016465 ps
CPU time 2198.83 seconds
Started Jan 03 01:43:39 PM PST 24
Finished Jan 03 02:20:21 PM PST 24
Peak memory 632040 kb
Host smart-9722a609-ac5b-427b-8309-140510bd2520
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2956512770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.2956512770
Directory /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.2131500969
Short name T762
Test name
Test status
Simulation time 6979688404 ps
CPU time 230.8 seconds
Started Jan 03 01:44:59 PM PST 24
Finished Jan 03 01:48:52 PM PST 24
Peak memory 202188 kb
Host smart-24db25a1-5805-48b3-9fb1-e8686a301691
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131500969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_stress_pipeline.2131500969
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.4219671036
Short name T59
Test name
Test status
Simulation time 5047445538 ps
CPU time 106.93 seconds
Started Jan 03 01:43:39 PM PST 24
Finished Jan 03 01:45:27 PM PST 24
Peak memory 335300 kb
Host smart-d91c18bd-840e-4399-8db6-9999f827aab9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219671036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.4219671036
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.2398240425
Short name T40
Test name
Test status
Simulation time 9361405822 ps
CPU time 2388.42 seconds
Started Jan 03 01:45:40 PM PST 24
Finished Jan 03 02:25:31 PM PST 24
Peak memory 380112 kb
Host smart-56e2983b-849b-43e0-a197-32f15b313490
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398240425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.sram_ctrl_access_during_key_req.2398240425
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.3665151144
Short name T374
Test name
Test status
Simulation time 14147633 ps
CPU time 0.62 seconds
Started Jan 03 01:44:16 PM PST 24
Finished Jan 03 01:44:18 PM PST 24
Peak memory 201808 kb
Host smart-77a8efcd-8483-4dee-89f0-028575c4f220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665151144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.3665151144
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.2099811147
Short name T4
Test name
Test status
Simulation time 331532291621 ps
CPU time 1382.64 seconds
Started Jan 03 01:45:27 PM PST 24
Finished Jan 03 02:08:41 PM PST 24
Peak memory 202128 kb
Host smart-e50871d7-5290-44a0-bc30-513784bd74c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099811147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection
.2099811147
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_lc_escalation.3500809144
Short name T557
Test name
Test status
Simulation time 10256941133 ps
CPU time 197.29 seconds
Started Jan 03 01:45:31 PM PST 24
Finished Jan 03 01:48:57 PM PST 24
Peak memory 202228 kb
Host smart-f1d18969-1479-4e19-82be-41c8c206ec1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500809144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es
calation.3500809144
Directory /workspace/28.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.865130521
Short name T382
Test name
Test status
Simulation time 2794162975 ps
CPU time 27.51 seconds
Started Jan 03 01:45:24 PM PST 24
Finished Jan 03 01:46:03 PM PST 24
Peak memory 216024 kb
Host smart-2ff82578-eeb0-45a3-83ea-01d10effa8cb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865130521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.sram_ctrl_max_throughput.865130521
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.3581417234
Short name T787
Test name
Test status
Simulation time 2645253405 ps
CPU time 74.36 seconds
Started Jan 03 01:44:32 PM PST 24
Finished Jan 03 01:45:51 PM PST 24
Peak memory 218508 kb
Host smart-a5b9d3d0-0e3d-4181-bf50-6c6c09cf54f8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581417234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_mem_partial_access.3581417234
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.431158795
Short name T849
Test name
Test status
Simulation time 4106560901 ps
CPU time 243.22 seconds
Started Jan 03 01:45:29 PM PST 24
Finished Jan 03 01:49:42 PM PST 24
Peak memory 202136 kb
Host smart-443c6eca-cf3a-4e72-9a14-c66e47e10500
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431158795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl
_mem_walk.431158795
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.1667674708
Short name T665
Test name
Test status
Simulation time 12770914053 ps
CPU time 332.41 seconds
Started Jan 03 01:45:04 PM PST 24
Finished Jan 03 01:50:40 PM PST 24
Peak memory 347964 kb
Host smart-f13feda1-f9e6-4a14-a1df-534252d6f31f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667674708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi
ple_keys.1667674708
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.1257930195
Short name T145
Test name
Test status
Simulation time 2681101901 ps
CPU time 31.88 seconds
Started Jan 03 01:45:27 PM PST 24
Finished Jan 03 01:46:10 PM PST 24
Peak memory 202052 kb
Host smart-5575469b-246f-474b-a5c2-82a9fb3c8fc5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257930195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
sram_ctrl_partial_access.1257930195
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2146341548
Short name T507
Test name
Test status
Simulation time 4414803410 ps
CPU time 275.12 seconds
Started Jan 03 01:45:20 PM PST 24
Finished Jan 03 01:50:04 PM PST 24
Peak memory 202108 kb
Host smart-2f224c3d-1d57-4e5d-bfe1-b6ce05ef5542
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146341548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.sram_ctrl_partial_access_b2b.2146341548
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.2198293717
Short name T265
Test name
Test status
Simulation time 1398866437 ps
CPU time 13.47 seconds
Started Jan 03 01:45:40 PM PST 24
Finished Jan 03 01:45:56 PM PST 24
Peak memory 202396 kb
Host smart-f181e7d4-f683-4ddb-9800-652fbefde200
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198293717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.2198293717
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.2420706356
Short name T366
Test name
Test status
Simulation time 3965597713 ps
CPU time 860.23 seconds
Started Jan 03 01:45:43 PM PST 24
Finished Jan 03 02:00:05 PM PST 24
Peak memory 377888 kb
Host smart-8c05c1cb-5326-414f-aef0-0cd5e459187f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420706356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.2420706356
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.2005344693
Short name T971
Test name
Test status
Simulation time 1471158367 ps
CPU time 66.2 seconds
Started Jan 03 01:43:44 PM PST 24
Finished Jan 03 01:44:53 PM PST 24
Peak memory 291500 kb
Host smart-a3f16a33-dc0d-4562-945a-edb3aa4075cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005344693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.2005344693
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all.2564055207
Short name T469
Test name
Test status
Simulation time 15444991768 ps
CPU time 2386 seconds
Started Jan 03 01:44:17 PM PST 24
Finished Jan 03 02:24:05 PM PST 24
Peak memory 376060 kb
Host smart-8239c614-1c73-4dea-97b1-cb1d0db5b669
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564055207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.sram_ctrl_stress_all.2564055207
Directory /workspace/28.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2988661047
Short name T982
Test name
Test status
Simulation time 623299054 ps
CPU time 435.26 seconds
Started Jan 03 01:44:53 PM PST 24
Finished Jan 03 01:52:10 PM PST 24
Peak memory 401920 kb
Host smart-010cf8bf-008d-423a-a81f-9edcda4d3742
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2988661047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.2988661047
Directory /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.3917948617
Short name T786
Test name
Test status
Simulation time 5193153041 ps
CPU time 400.82 seconds
Started Jan 03 01:45:27 PM PST 24
Finished Jan 03 01:52:19 PM PST 24
Peak memory 202148 kb
Host smart-d5e1b39a-b7b0-4b58-86e2-d878b032295f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917948617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_stress_pipeline.3917948617
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1260117768
Short name T753
Test name
Test status
Simulation time 7462222812 ps
CPU time 29.38 seconds
Started Jan 03 01:45:31 PM PST 24
Finished Jan 03 01:46:09 PM PST 24
Peak memory 217744 kb
Host smart-f9a39045-0097-4be1-ab69-b1833318002c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260117768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.1260117768
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.4263238943
Short name T843
Test name
Test status
Simulation time 9347391716 ps
CPU time 1748.88 seconds
Started Jan 03 01:44:54 PM PST 24
Finished Jan 03 02:14:04 PM PST 24
Peak memory 379052 kb
Host smart-72cbad62-1a1d-4d41-bed1-5c5fcf0f8d89
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263238943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.sram_ctrl_access_during_key_req.4263238943
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.3707376512
Short name T767
Test name
Test status
Simulation time 15106103 ps
CPU time 0.64 seconds
Started Jan 03 01:45:16 PM PST 24
Finished Jan 03 01:45:28 PM PST 24
Peak memory 201916 kb
Host smart-96abc2a9-b52b-479a-be12-2070669c1344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707376512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.sram_ctrl_alert_test.3707376512
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.951378350
Short name T836
Test name
Test status
Simulation time 244256856869 ps
CPU time 2303.38 seconds
Started Jan 03 01:44:16 PM PST 24
Finished Jan 03 02:22:40 PM PST 24
Peak memory 202204 kb
Host smart-b48eff41-6d5a-4a52-868d-b45484c0e1a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951378350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.
951378350
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_executable.2920618365
Short name T640
Test name
Test status
Simulation time 15640555339 ps
CPU time 746.37 seconds
Started Jan 03 01:44:33 PM PST 24
Finished Jan 03 01:57:03 PM PST 24
Peak memory 370808 kb
Host smart-c5173c19-ef97-4071-9999-65168ccb7eb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920618365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab
le.2920618365
Directory /workspace/29.sram_ctrl_executable/latest

Test location /workspace/coverage/default/29.sram_ctrl_lc_escalation.1311600738
Short name T518
Test name
Test status
Simulation time 7214337834 ps
CPU time 73.3 seconds
Started Jan 03 01:44:54 PM PST 24
Finished Jan 03 01:46:09 PM PST 24
Peak memory 210420 kb
Host smart-ae4704f5-afb7-4191-9662-a109b7fd98db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311600738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es
calation.1311600738
Directory /workspace/29.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.3832468191
Short name T538
Test name
Test status
Simulation time 1406031294 ps
CPU time 35.07 seconds
Started Jan 03 01:44:35 PM PST 24
Finished Jan 03 01:45:14 PM PST 24
Peak memory 236268 kb
Host smart-020008ba-956d-47d8-89d2-7bbed9e5e459
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832468191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_max_throughput.3832468191
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.470642284
Short name T488
Test name
Test status
Simulation time 2672000853 ps
CPU time 79.08 seconds
Started Jan 03 01:44:57 PM PST 24
Finished Jan 03 01:46:17 PM PST 24
Peak memory 218480 kb
Host smart-35934f15-a5e8-4414-88ed-b8277597f0b7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470642284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.sram_ctrl_mem_partial_access.470642284
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.1201641091
Short name T900
Test name
Test status
Simulation time 20681656895 ps
CPU time 160.34 seconds
Started Jan 03 01:44:57 PM PST 24
Finished Jan 03 01:47:39 PM PST 24
Peak memory 202164 kb
Host smart-9a07afe4-9ce2-4002-bec3-c0b1887fe869
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201641091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr
l_mem_walk.1201641091
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.3625053497
Short name T894
Test name
Test status
Simulation time 133788900219 ps
CPU time 646.63 seconds
Started Jan 03 01:44:33 PM PST 24
Finished Jan 03 01:55:23 PM PST 24
Peak memory 362396 kb
Host smart-cbcb4eb1-225c-43a8-942d-493691df5d0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625053497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi
ple_keys.3625053497
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.1185535431
Short name T877
Test name
Test status
Simulation time 1442942267 ps
CPU time 17.1 seconds
Started Jan 03 01:44:52 PM PST 24
Finished Jan 03 01:45:11 PM PST 24
Peak memory 217904 kb
Host smart-0718db38-6e40-4ad9-a068-5bbb21b4b54b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185535431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
sram_ctrl_partial_access.1185535431
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.712489128
Short name T565
Test name
Test status
Simulation time 42798987705 ps
CPU time 466.79 seconds
Started Jan 03 01:44:33 PM PST 24
Finished Jan 03 01:52:24 PM PST 24
Peak memory 202156 kb
Host smart-419aa1ee-839a-4f2d-bea7-6aa07b5de3e4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712489128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.sram_ctrl_partial_access_b2b.712489128
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.2865605807
Short name T306
Test name
Test status
Simulation time 499469499 ps
CPU time 6.58 seconds
Started Jan 03 01:44:55 PM PST 24
Finished Jan 03 01:45:02 PM PST 24
Peak memory 202396 kb
Host smart-628d21b7-f3af-4d60-b24c-bea45f660f0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865605807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.2865605807
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.2466036902
Short name T981
Test name
Test status
Simulation time 10668556778 ps
CPU time 564.21 seconds
Started Jan 03 01:44:56 PM PST 24
Finished Jan 03 01:54:22 PM PST 24
Peak memory 361576 kb
Host smart-b7c34529-2afd-4815-9ef5-40f2d7e5c78e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466036902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.2466036902
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.2585983300
Short name T863
Test name
Test status
Simulation time 2761821867 ps
CPU time 25.18 seconds
Started Jan 03 01:44:53 PM PST 24
Finished Jan 03 01:45:20 PM PST 24
Peak memory 202108 kb
Host smart-d79e165d-5138-48df-9bde-b2230cd120da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585983300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.2585983300
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1480357493
Short name T32
Test name
Test status
Simulation time 2951868420 ps
CPU time 2401.97 seconds
Started Jan 03 01:45:00 PM PST 24
Finished Jan 03 02:25:04 PM PST 24
Peak memory 421420 kb
Host smart-eb8ea530-9f7b-4aae-942c-fa34076cb35a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1480357493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.1480357493
Directory /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.608347214
Short name T271
Test name
Test status
Simulation time 7063756227 ps
CPU time 260.76 seconds
Started Jan 03 01:44:15 PM PST 24
Finished Jan 03 01:48:37 PM PST 24
Peak memory 202188 kb
Host smart-a378d114-38a2-49cc-ba6c-9ac21793beda
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608347214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.sram_ctrl_stress_pipeline.608347214
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1660970369
Short name T238
Test name
Test status
Simulation time 2754378213 ps
CPU time 35.97 seconds
Started Jan 03 01:44:15 PM PST 24
Finished Jan 03 01:44:52 PM PST 24
Peak memory 234972 kb
Host smart-241fa3f3-d690-4fbf-ab0e-cbbdbcc0fd3b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660970369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.1660970369
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.1801413630
Short name T277
Test name
Test status
Simulation time 4042410373 ps
CPU time 709.93 seconds
Started Jan 03 01:40:20 PM PST 24
Finished Jan 03 01:52:17 PM PST 24
Peak memory 380128 kb
Host smart-aa3d99e1-74a8-46da-b113-303ab23ceb70
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801413630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_access_during_key_req.1801413630
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.3621287834
Short name T240
Test name
Test status
Simulation time 85731852 ps
CPU time 0.62 seconds
Started Jan 03 01:40:28 PM PST 24
Finished Jan 03 01:40:30 PM PST 24
Peak memory 201916 kb
Host smart-56b42ce5-c714-4545-b16d-7cfeedac5bd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621287834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_alert_test.3621287834
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.3253637157
Short name T42
Test name
Test status
Simulation time 264315313841 ps
CPU time 2179.36 seconds
Started Jan 03 01:40:17 PM PST 24
Finished Jan 03 02:16:45 PM PST 24
Peak memory 202176 kb
Host smart-c3716631-9c15-4cd3-90db-5ee2f782f431
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253637157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.
3253637157
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.1230219936
Short name T471
Test name
Test status
Simulation time 74664377583 ps
CPU time 79.29 seconds
Started Jan 03 01:40:32 PM PST 24
Finished Jan 03 01:41:57 PM PST 24
Peak memory 210388 kb
Host smart-1e51283f-4886-448b-8847-2aba0bc8b0f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230219936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc
alation.1230219936
Directory /workspace/3.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.4134018344
Short name T742
Test name
Test status
Simulation time 2804513081 ps
CPU time 171.25 seconds
Started Jan 03 01:40:32 PM PST 24
Finished Jan 03 01:43:29 PM PST 24
Peak memory 355620 kb
Host smart-94c20136-8e62-4816-b0b6-c83f6676c04e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134018344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_max_throughput.4134018344
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.1216730635
Short name T100
Test name
Test status
Simulation time 8582559544 ps
CPU time 151.25 seconds
Started Jan 03 01:40:15 PM PST 24
Finished Jan 03 01:42:56 PM PST 24
Peak memory 211176 kb
Host smart-9ef88b56-1a0f-47e0-8583-e7ac7c336f12
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216730635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_mem_partial_access.1216730635
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.1133413470
Short name T768
Test name
Test status
Simulation time 18666433196 ps
CPU time 326.02 seconds
Started Jan 03 01:40:15 PM PST 24
Finished Jan 03 01:45:51 PM PST 24
Peak memory 202340 kb
Host smart-bb8c2ef9-31e9-4f8e-bb7b-e5af1a4798ec
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133413470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl
_mem_walk.1133413470
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.193481208
Short name T550
Test name
Test status
Simulation time 25489442690 ps
CPU time 1064.88 seconds
Started Jan 03 01:40:21 PM PST 24
Finished Jan 03 01:58:12 PM PST 24
Peak memory 371144 kb
Host smart-a9b3d174-fdbf-4e17-8b6b-a1bcf64b7a31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193481208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multipl
e_keys.193481208
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.449265961
Short name T806
Test name
Test status
Simulation time 2950187393 ps
CPU time 36.83 seconds
Started Jan 03 01:40:17 PM PST 24
Finished Jan 03 01:41:02 PM PST 24
Peak memory 202132 kb
Host smart-ed425b9c-1695-492a-8624-aa07044dd8c2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449265961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sr
am_ctrl_partial_access.449265961
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.27083349
Short name T446
Test name
Test status
Simulation time 108336973567 ps
CPU time 325.75 seconds
Started Jan 03 01:40:17 PM PST 24
Finished Jan 03 01:45:51 PM PST 24
Peak memory 202168 kb
Host smart-bc5b9837-e49a-4579-ad6e-f182ea69aa73
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27083349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_partial_access_b2b.27083349
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.978104534
Short name T698
Test name
Test status
Simulation time 711355137 ps
CPU time 5.54 seconds
Started Jan 03 01:40:33 PM PST 24
Finished Jan 03 01:40:45 PM PST 24
Peak memory 202440 kb
Host smart-bd15d6c9-33b6-4074-a76b-fddc65d5b7e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978104534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.978104534
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.2391492600
Short name T428
Test name
Test status
Simulation time 7342775967 ps
CPU time 418.22 seconds
Started Jan 03 01:40:15 PM PST 24
Finished Jan 03 01:47:23 PM PST 24
Peak memory 362588 kb
Host smart-2872d863-be9e-45d6-8f38-b0e513b03a2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391492600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.2391492600
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.1145534299
Short name T24
Test name
Test status
Simulation time 515179011 ps
CPU time 3.41 seconds
Started Jan 03 01:40:16 PM PST 24
Finished Jan 03 01:40:28 PM PST 24
Peak memory 223768 kb
Host smart-6ff26c23-3a81-4188-8a73-4240c0e6529f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145534299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_sec_cm.1145534299
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.925387433
Short name T954
Test name
Test status
Simulation time 889949168 ps
CPU time 19.27 seconds
Started Jan 03 01:40:13 PM PST 24
Finished Jan 03 01:40:43 PM PST 24
Peak memory 202088 kb
Host smart-f94cb49a-361f-4037-8376-0c55dbfb93fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925387433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.925387433
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.834519561
Short name T268
Test name
Test status
Simulation time 966350892 ps
CPU time 1891.28 seconds
Started Jan 03 01:40:18 PM PST 24
Finished Jan 03 02:11:57 PM PST 24
Peak memory 535700 kb
Host smart-be299f1e-c1b1-4aad-a4e5-417e084588fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=834519561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.834519561
Directory /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.1076784317
Short name T796
Test name
Test status
Simulation time 22498930293 ps
CPU time 235.56 seconds
Started Jan 03 01:40:14 PM PST 24
Finished Jan 03 01:44:20 PM PST 24
Peak memory 202184 kb
Host smart-638038cb-9313-4d03-9179-4e575daa17a0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076784317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_stress_pipeline.1076784317
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.71041624
Short name T758
Test name
Test status
Simulation time 699394067 ps
CPU time 29.9 seconds
Started Jan 03 01:40:18 PM PST 24
Finished Jan 03 01:40:56 PM PST 24
Peak memory 223524 kb
Host smart-758a2fd9-b511-42cd-aa12-f527ef88e740
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71041624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.sram_ctrl_throughput_w_partial_write.71041624
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.1639537378
Short name T596
Test name
Test status
Simulation time 3743243587 ps
CPU time 684.65 seconds
Started Jan 03 01:45:19 PM PST 24
Finished Jan 03 01:56:53 PM PST 24
Peak memory 364752 kb
Host smart-e5573cc7-2051-45a8-acc6-1267d2af4df3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639537378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.sram_ctrl_access_during_key_req.1639537378
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.3883099440
Short name T818
Test name
Test status
Simulation time 81810126 ps
CPU time 0.66 seconds
Started Jan 03 01:45:40 PM PST 24
Finished Jan 03 01:45:44 PM PST 24
Peak memory 201796 kb
Host smart-69505bbd-f1f1-4fbd-be35-a5d49b97e7f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883099440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.3883099440
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.1373542644
Short name T603
Test name
Test status
Simulation time 828681406859 ps
CPU time 1501.24 seconds
Started Jan 03 01:45:01 PM PST 24
Finished Jan 03 02:10:06 PM PST 24
Peak memory 202136 kb
Host smart-ef909345-0890-49f3-96ec-7674c1b6517b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373542644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection
.1373542644
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_executable.2644517247
Short name T822
Test name
Test status
Simulation time 2893499624 ps
CPU time 356.28 seconds
Started Jan 03 01:45:03 PM PST 24
Finished Jan 03 01:51:03 PM PST 24
Peak memory 371912 kb
Host smart-ae283fba-32d4-42ad-a677-d4126440b382
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644517247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab
le.2644517247
Directory /workspace/30.sram_ctrl_executable/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.2563610387
Short name T343
Test name
Test status
Simulation time 779149567 ps
CPU time 117.89 seconds
Started Jan 03 01:45:01 PM PST 24
Finished Jan 03 01:47:02 PM PST 24
Peak memory 345432 kb
Host smart-6da8286a-9fda-4eab-86da-9534cc8d7171
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563610387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sram_ctrl_max_throughput.2563610387
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.72527900
Short name T688
Test name
Test status
Simulation time 4903504518 ps
CPU time 78.16 seconds
Started Jan 03 01:45:23 PM PST 24
Finished Jan 03 01:46:51 PM PST 24
Peak memory 211160 kb
Host smart-30ec1699-217c-4bb6-a5f5-4145c00e928a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72527900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
sram_ctrl_mem_partial_access.72527900
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.2281847659
Short name T376
Test name
Test status
Simulation time 7180284335 ps
CPU time 149.97 seconds
Started Jan 03 01:45:27 PM PST 24
Finished Jan 03 01:48:08 PM PST 24
Peak memory 202024 kb
Host smart-b5b42598-9653-45b7-b122-7c05c7961f12
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281847659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr
l_mem_walk.2281847659
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.3155421994
Short name T234
Test name
Test status
Simulation time 2860420894 ps
CPU time 513.39 seconds
Started Jan 03 01:45:16 PM PST 24
Finished Jan 03 01:54:01 PM PST 24
Peak memory 370860 kb
Host smart-ee71f41b-a05b-49c0-811f-a5c78cee702e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155421994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi
ple_keys.3155421994
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.1301083134
Short name T883
Test name
Test status
Simulation time 840589959 ps
CPU time 19.07 seconds
Started Jan 03 01:44:58 PM PST 24
Finished Jan 03 01:45:19 PM PST 24
Peak memory 240452 kb
Host smart-7f0158ef-a2f8-4371-9c92-069e8871ad23
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301083134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
sram_ctrl_partial_access.1301083134
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.4234509336
Short name T516
Test name
Test status
Simulation time 2547076683 ps
CPU time 166.4 seconds
Started Jan 03 01:45:01 PM PST 24
Finished Jan 03 01:47:50 PM PST 24
Peak memory 202216 kb
Host smart-f1841a67-e0ce-4ae8-a74b-7d8adbb6dd67
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234509336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_partial_access_b2b.4234509336
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.1681887155
Short name T141
Test name
Test status
Simulation time 1416068145 ps
CPU time 5.95 seconds
Started Jan 03 01:45:25 PM PST 24
Finished Jan 03 01:45:42 PM PST 24
Peak memory 202456 kb
Host smart-b83016bd-01e9-4ca5-91d0-9dcb62c181a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681887155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.1681887155
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.2651608745
Short name T483
Test name
Test status
Simulation time 4717306557 ps
CPU time 651.33 seconds
Started Jan 03 01:45:22 PM PST 24
Finished Jan 03 01:56:23 PM PST 24
Peak memory 370820 kb
Host smart-147210a2-908e-45eb-a34f-620659e50fa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651608745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.2651608745
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.1811513179
Short name T604
Test name
Test status
Simulation time 1231893499 ps
CPU time 19.97 seconds
Started Jan 03 01:44:58 PM PST 24
Finished Jan 03 01:45:20 PM PST 24
Peak memory 202072 kb
Host smart-030ba4ef-2b7e-4460-bfb6-2fc046af396f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811513179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.1811513179
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all.327831535
Short name T489
Test name
Test status
Simulation time 547127528824 ps
CPU time 5495.82 seconds
Started Jan 03 01:45:21 PM PST 24
Finished Jan 03 03:17:05 PM PST 24
Peak memory 379148 kb
Host smart-41ee9e2d-0582-4247-8595-d3e95e3e513e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327831535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_stress_all.327831535
Directory /workspace/30.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.234155310
Short name T316
Test name
Test status
Simulation time 4048772162 ps
CPU time 3471.78 seconds
Started Jan 03 01:45:21 PM PST 24
Finished Jan 03 02:43:21 PM PST 24
Peak memory 696036 kb
Host smart-bdb1254a-83a6-463c-b97c-54191915cdd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=234155310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.234155310
Directory /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2681606502
Short name T345
Test name
Test status
Simulation time 4927707494 ps
CPU time 181.09 seconds
Started Jan 03 01:45:18 PM PST 24
Finished Jan 03 01:48:29 PM PST 24
Peak memory 202064 kb
Host smart-3608a91d-53eb-4d50-8d84-5b51ca7cd2fa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681606502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_stress_pipeline.2681606502
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1665682964
Short name T821
Test name
Test status
Simulation time 9750487120 ps
CPU time 175.17 seconds
Started Jan 03 01:45:01 PM PST 24
Finished Jan 03 01:48:00 PM PST 24
Peak memory 367148 kb
Host smart-208014ed-f482-4799-919f-40683e03bc47
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665682964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.1665682964
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.3497876621
Short name T751
Test name
Test status
Simulation time 21483378978 ps
CPU time 1296.09 seconds
Started Jan 03 01:45:40 PM PST 24
Finished Jan 03 02:07:19 PM PST 24
Peak memory 380212 kb
Host smart-e61fdb79-12f3-4d35-b0b2-58da967d33e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497876621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.sram_ctrl_access_during_key_req.3497876621
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.4062729812
Short name T463
Test name
Test status
Simulation time 43015951 ps
CPU time 0.65 seconds
Started Jan 03 01:45:00 PM PST 24
Finished Jan 03 01:45:04 PM PST 24
Peak memory 201904 kb
Host smart-07c1e319-e946-4134-ac19-9b1c8562fcbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062729812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.4062729812
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.4279859003
Short name T794
Test name
Test status
Simulation time 309555653671 ps
CPU time 2545.97 seconds
Started Jan 03 01:45:40 PM PST 24
Finished Jan 03 02:28:09 PM PST 24
Peak memory 202240 kb
Host smart-9333f618-9091-4f41-81aa-e609ef4b752a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279859003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection
.4279859003
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_lc_escalation.2203600954
Short name T347
Test name
Test status
Simulation time 1283368462 ps
CPU time 18.29 seconds
Started Jan 03 01:45:43 PM PST 24
Finished Jan 03 01:46:04 PM PST 24
Peak memory 202060 kb
Host smart-eacdc563-ba1c-44e1-8f1d-54ecb87a9e12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203600954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es
calation.2203600954
Directory /workspace/31.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.3051086895
Short name T442
Test name
Test status
Simulation time 2781795464 ps
CPU time 137.62 seconds
Started Jan 03 01:45:44 PM PST 24
Finished Jan 03 01:48:04 PM PST 24
Peak memory 349428 kb
Host smart-6f2742d7-45c6-4afa-8bd5-477afc63edf7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051086895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_max_throughput.3051086895
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.1646096217
Short name T448
Test name
Test status
Simulation time 2461446658 ps
CPU time 78.12 seconds
Started Jan 03 01:44:37 PM PST 24
Finished Jan 03 01:46:00 PM PST 24
Peak memory 211024 kb
Host smart-283d296c-2f11-4fa8-9ed5-b69521eb50c1
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646096217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_mem_partial_access.1646096217
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.4223174006
Short name T763
Test name
Test status
Simulation time 2074888621 ps
CPU time 127.01 seconds
Started Jan 03 01:44:55 PM PST 24
Finished Jan 03 01:47:04 PM PST 24
Peak memory 202004 kb
Host smart-3259a76b-58e9-4ef9-b78c-a7c7fa4f0134
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223174006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr
l_mem_walk.4223174006
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.209823157
Short name T867
Test name
Test status
Simulation time 67578427232 ps
CPU time 915.05 seconds
Started Jan 03 01:45:50 PM PST 24
Finished Jan 03 02:01:09 PM PST 24
Peak memory 381216 kb
Host smart-ecc49356-509a-4a2c-8cb6-6874bf419387
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209823157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multip
le_keys.209823157
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.4169860087
Short name T584
Test name
Test status
Simulation time 1949863120 ps
CPU time 16.49 seconds
Started Jan 03 01:45:50 PM PST 24
Finished Jan 03 01:46:09 PM PST 24
Peak memory 210312 kb
Host smart-825ea761-d595-4a7c-b776-e5060eaab449
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169860087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
sram_ctrl_partial_access.4169860087
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.775135014
Short name T934
Test name
Test status
Simulation time 13771278824 ps
CPU time 284.68 seconds
Started Jan 03 01:45:47 PM PST 24
Finished Jan 03 01:50:33 PM PST 24
Peak memory 202196 kb
Host smart-8be771d3-cc4b-47fc-8771-87622e354eb8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775135014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.sram_ctrl_partial_access_b2b.775135014
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.167758948
Short name T477
Test name
Test status
Simulation time 2785503888 ps
CPU time 13.44 seconds
Started Jan 03 01:45:41 PM PST 24
Finished Jan 03 01:45:57 PM PST 24
Peak memory 202336 kb
Host smart-5579bb90-9e4d-4682-a73d-a6f41ac081ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167758948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.167758948
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.1797127698
Short name T710
Test name
Test status
Simulation time 40862374633 ps
CPU time 741.04 seconds
Started Jan 03 01:44:36 PM PST 24
Finished Jan 03 01:57:02 PM PST 24
Peak memory 379116 kb
Host smart-805218d4-ac6a-45f3-9537-dc3e36593316
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797127698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.1797127698
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.4243482236
Short name T904
Test name
Test status
Simulation time 700205573 ps
CPU time 11.46 seconds
Started Jan 03 01:45:40 PM PST 24
Finished Jan 03 01:45:54 PM PST 24
Peak memory 202104 kb
Host smart-509c5607-b083-4398-84f6-d62ca7c7df6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243482236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.4243482236
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all.3855230242
Short name T319
Test name
Test status
Simulation time 166240926179 ps
CPU time 2254.83 seconds
Started Jan 03 01:44:54 PM PST 24
Finished Jan 03 02:22:30 PM PST 24
Peak memory 210396 kb
Host smart-ca1e99c8-b92b-456d-b285-54af81e1d92d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855230242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.sram_ctrl_stress_all.3855230242
Directory /workspace/31.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3676132056
Short name T965
Test name
Test status
Simulation time 2397778989 ps
CPU time 3963.78 seconds
Started Jan 03 01:44:55 PM PST 24
Finished Jan 03 02:51:00 PM PST 24
Peak memory 690924 kb
Host smart-bb0a6dd0-e74a-4c78-942c-f59b68fb35ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3676132056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.3676132056
Directory /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.474991351
Short name T270
Test name
Test status
Simulation time 7954947388 ps
CPU time 270.76 seconds
Started Jan 03 01:45:29 PM PST 24
Finished Jan 03 01:50:09 PM PST 24
Peak memory 202124 kb
Host smart-796a78b9-1020-4c20-8b97-9458df836f98
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474991351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.sram_ctrl_stress_pipeline.474991351
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.3676357147
Short name T444
Test name
Test status
Simulation time 2825480732 ps
CPU time 77.56 seconds
Started Jan 03 01:45:46 PM PST 24
Finished Jan 03 01:47:05 PM PST 24
Peak memory 301428 kb
Host smart-9a2e39cb-f796-42d9-a997-009a0ff1123c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676357147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.3676357147
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.1914760364
Short name T335
Test name
Test status
Simulation time 39623150280 ps
CPU time 1413.3 seconds
Started Jan 03 01:44:58 PM PST 24
Finished Jan 03 02:08:34 PM PST 24
Peak memory 380076 kb
Host smart-98dd8f8e-0e44-4ac3-b718-8649128b3275
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914760364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.sram_ctrl_access_during_key_req.1914760364
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.1423305223
Short name T272
Test name
Test status
Simulation time 32527995 ps
CPU time 0.66 seconds
Started Jan 03 01:45:05 PM PST 24
Finished Jan 03 01:45:08 PM PST 24
Peak memory 201800 kb
Host smart-cbd202d1-33fc-47e7-ba17-34db7d4453ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423305223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.sram_ctrl_alert_test.1423305223
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.1892242021
Short name T783
Test name
Test status
Simulation time 689679837995 ps
CPU time 2754.65 seconds
Started Jan 03 01:44:54 PM PST 24
Finished Jan 03 02:30:50 PM PST 24
Peak memory 202152 kb
Host smart-7e414539-fd06-4f4b-ba22-05eeb3268948
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892242021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection
.1892242021
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.1379348219
Short name T27
Test name
Test status
Simulation time 11295963189 ps
CPU time 287.09 seconds
Started Jan 03 01:44:58 PM PST 24
Finished Jan 03 01:49:47 PM PST 24
Peak memory 202380 kb
Host smart-aa9624a0-a163-40ea-83aa-c9911c9c549c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379348219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es
calation.1379348219
Directory /workspace/32.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.64601367
Short name T414
Test name
Test status
Simulation time 3472141230 ps
CPU time 171.43 seconds
Started Jan 03 01:44:59 PM PST 24
Finished Jan 03 01:47:53 PM PST 24
Peak memory 355492 kb
Host smart-6da56d0e-beb3-41d3-b1c4-0382b1ca6df4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64601367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.sram_ctrl_max_throughput.64601367
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.3442847192
Short name T605
Test name
Test status
Simulation time 24250259714 ps
CPU time 77.79 seconds
Started Jan 03 01:45:24 PM PST 24
Finished Jan 03 01:46:52 PM PST 24
Peak memory 211680 kb
Host smart-2c1d9599-a3c6-468a-b524-28687d425b6b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442847192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_mem_partial_access.3442847192
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.2799671352
Short name T506
Test name
Test status
Simulation time 4109362766 ps
CPU time 240.85 seconds
Started Jan 03 01:45:25 PM PST 24
Finished Jan 03 01:49:36 PM PST 24
Peak memory 202212 kb
Host smart-e99fa4ee-df4a-41e8-b8fa-165592cc3028
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799671352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr
l_mem_walk.2799671352
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.1650483596
Short name T612
Test name
Test status
Simulation time 34667397240 ps
CPU time 1294.88 seconds
Started Jan 03 01:44:36 PM PST 24
Finished Jan 03 02:06:16 PM PST 24
Peak memory 367836 kb
Host smart-4971125f-fb0c-4057-859d-f6e271918a76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650483596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi
ple_keys.1650483596
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.82051886
Short name T646
Test name
Test status
Simulation time 1190854384 ps
CPU time 100.77 seconds
Started Jan 03 01:44:57 PM PST 24
Finished Jan 03 01:46:40 PM PST 24
Peak memory 336004 kb
Host smart-c86cafdc-521b-41ae-8278-920b8ffa3893
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82051886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sr
am_ctrl_partial_access.82051886
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.716860372
Short name T955
Test name
Test status
Simulation time 26426837777 ps
CPU time 446.25 seconds
Started Jan 03 01:45:14 PM PST 24
Finished Jan 03 01:52:50 PM PST 24
Peak memory 202084 kb
Host smart-f2e1305d-5cae-4156-8553-71e6fd1af98c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716860372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.sram_ctrl_partial_access_b2b.716860372
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.4131612268
Short name T939
Test name
Test status
Simulation time 1347105084 ps
CPU time 5.95 seconds
Started Jan 03 01:45:21 PM PST 24
Finished Jan 03 01:45:35 PM PST 24
Peak memory 202404 kb
Host smart-52ba4342-1d54-4193-864b-9fa26563f844
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131612268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.4131612268
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.2580809021
Short name T962
Test name
Test status
Simulation time 10049978274 ps
CPU time 578.73 seconds
Started Jan 03 01:45:01 PM PST 24
Finished Jan 03 01:54:44 PM PST 24
Peak memory 375988 kb
Host smart-1debda55-54ea-4cd6-afe3-28afc078a97d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580809021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.2580809021
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.742881119
Short name T37
Test name
Test status
Simulation time 5305447644 ps
CPU time 23.05 seconds
Started Jan 03 01:44:36 PM PST 24
Finished Jan 03 01:45:04 PM PST 24
Peak memory 202076 kb
Host smart-dc2933ce-013d-482c-8645-07115a6fd802
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742881119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.742881119
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all.2757860093
Short name T127
Test name
Test status
Simulation time 728126102627 ps
CPU time 6596.05 seconds
Started Jan 03 01:45:21 PM PST 24
Finished Jan 03 03:35:26 PM PST 24
Peak memory 380116 kb
Host smart-6066cbfc-9789-43ec-8380-04b4b86f93fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757860093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.sram_ctrl_stress_all.2757860093
Directory /workspace/32.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.4039484845
Short name T708
Test name
Test status
Simulation time 2101797191 ps
CPU time 3690.29 seconds
Started Jan 03 01:45:04 PM PST 24
Finished Jan 03 02:46:38 PM PST 24
Peak memory 697488 kb
Host smart-9f7b3bb5-a71c-4fe1-b8c8-d131f7593375
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4039484845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.4039484845
Directory /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.1416502526
Short name T549
Test name
Test status
Simulation time 8888486081 ps
CPU time 471.87 seconds
Started Jan 03 01:44:57 PM PST 24
Finished Jan 03 01:52:50 PM PST 24
Peak memory 202108 kb
Host smart-4bfb96fb-eabb-42c0-a715-dbcbc8bca6f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416502526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_stress_pipeline.1416502526
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2640637041
Short name T972
Test name
Test status
Simulation time 834917077 ps
CPU time 109.49 seconds
Started Jan 03 01:45:20 PM PST 24
Finished Jan 03 01:47:19 PM PST 24
Peak memory 338136 kb
Host smart-7e1270d9-d5f7-4da3-ae09-cf9f76a6d335
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640637041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.2640637041
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.59262502
Short name T541
Test name
Test status
Simulation time 19622026160 ps
CPU time 418.84 seconds
Started Jan 03 01:45:21 PM PST 24
Finished Jan 03 01:52:28 PM PST 24
Peak memory 377068 kb
Host smart-63ce1d72-4584-411f-bc28-75673677af98
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59262502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.sram_ctrl_access_during_key_req.59262502
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.687692314
Short name T862
Test name
Test status
Simulation time 16860863 ps
CPU time 0.64 seconds
Started Jan 03 01:45:42 PM PST 24
Finished Jan 03 01:45:44 PM PST 24
Peak memory 201820 kb
Host smart-6e2698ae-beca-4f66-bc30-2b8a352a25ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687692314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.687692314
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.2473661308
Short name T871
Test name
Test status
Simulation time 271448785430 ps
CPU time 1001.28 seconds
Started Jan 03 01:45:05 PM PST 24
Finished Jan 03 02:01:49 PM PST 24
Peak memory 202144 kb
Host smart-e77aec8b-d386-4dd6-ab50-14f62b404ab7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473661308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection
.2473661308
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.2115521825
Short name T266
Test name
Test status
Simulation time 730710626 ps
CPU time 79.69 seconds
Started Jan 03 01:45:27 PM PST 24
Finished Jan 03 01:46:58 PM PST 24
Peak memory 302280 kb
Host smart-c4c50ac8-19d3-467e-90ce-802c0a6961a6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115521825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_max_throughput.2115521825
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.1612524114
Short name T336
Test name
Test status
Simulation time 2691916120 ps
CPU time 76.25 seconds
Started Jan 03 01:45:49 PM PST 24
Finished Jan 03 01:47:08 PM PST 24
Peak memory 210620 kb
Host smart-e4e2e938-4478-42d4-8950-42fd562e4dd5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612524114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_mem_partial_access.1612524114
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.2228343929
Short name T963
Test name
Test status
Simulation time 413464393500 ps
CPU time 437.83 seconds
Started Jan 03 01:45:38 PM PST 24
Finished Jan 03 01:53:00 PM PST 24
Peak memory 202412 kb
Host smart-8b8539c1-4dfc-47a8-9581-b5d95c838454
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228343929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr
l_mem_walk.2228343929
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.4060397864
Short name T276
Test name
Test status
Simulation time 8438587854 ps
CPU time 565.89 seconds
Started Jan 03 01:45:23 PM PST 24
Finished Jan 03 01:54:59 PM PST 24
Peak memory 375044 kb
Host smart-1c0b6c3b-c4f0-4304-aaa1-c9018f409716
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060397864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi
ple_keys.4060397864
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.3393861173
Short name T472
Test name
Test status
Simulation time 5084640517 ps
CPU time 23.77 seconds
Started Jan 03 01:45:24 PM PST 24
Finished Jan 03 01:45:59 PM PST 24
Peak memory 202092 kb
Host smart-51b0f951-c03d-4da6-a72f-9aec15ce6bb0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393861173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
sram_ctrl_partial_access.3393861173
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.451991849
Short name T256
Test name
Test status
Simulation time 7428041730 ps
CPU time 459.05 seconds
Started Jan 03 01:45:23 PM PST 24
Finished Jan 03 01:53:13 PM PST 24
Peak memory 202108 kb
Host smart-cda5e517-f35c-441f-9d19-344142ec3638
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451991849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.sram_ctrl_partial_access_b2b.451991849
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.1276081188
Short name T745
Test name
Test status
Simulation time 757025862 ps
CPU time 14.05 seconds
Started Jan 03 01:45:38 PM PST 24
Finished Jan 03 01:45:56 PM PST 24
Peak memory 202416 kb
Host smart-df073648-3d8b-4dbd-b3ec-c3190ed9f4bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276081188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.1276081188
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.3218574494
Short name T402
Test name
Test status
Simulation time 38684039913 ps
CPU time 843.92 seconds
Started Jan 03 01:45:29 PM PST 24
Finished Jan 03 01:59:43 PM PST 24
Peak memory 379892 kb
Host smart-a19f44ac-c234-4515-846a-28428eb35bf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218574494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.3218574494
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.2435756974
Short name T925
Test name
Test status
Simulation time 3031253061 ps
CPU time 26.72 seconds
Started Jan 03 01:45:27 PM PST 24
Finished Jan 03 01:46:05 PM PST 24
Peak memory 202136 kb
Host smart-f6ae5fba-c629-4cef-ad63-585d9f8b9c7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435756974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.2435756974
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3034626744
Short name T439
Test name
Test status
Simulation time 6492597988 ps
CPU time 1413.54 seconds
Started Jan 03 01:45:22 PM PST 24
Finished Jan 03 02:09:03 PM PST 24
Peak memory 521484 kb
Host smart-348831a1-4bfb-4646-abd9-0647b665525c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3034626744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.3034626744
Directory /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.2225454896
Short name T475
Test name
Test status
Simulation time 2678063116 ps
CPU time 193.51 seconds
Started Jan 03 01:45:23 PM PST 24
Finished Jan 03 01:48:47 PM PST 24
Peak memory 202176 kb
Host smart-e188b152-7a5c-4f6a-bcad-5160e810edd9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225454896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_stress_pipeline.2225454896
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1724959229
Short name T493
Test name
Test status
Simulation time 757015680 ps
CPU time 44.47 seconds
Started Jan 03 01:45:26 PM PST 24
Finished Jan 03 01:46:21 PM PST 24
Peak memory 267628 kb
Host smart-075b4f6b-9461-4085-9e49-3d98ea495d32
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724959229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.1724959229
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2056849384
Short name T581
Test name
Test status
Simulation time 143991431615 ps
CPU time 1467.58 seconds
Started Jan 03 01:45:41 PM PST 24
Finished Jan 03 02:10:11 PM PST 24
Peak memory 373988 kb
Host smart-b9bb0eca-9bee-4b38-97fe-96f7293707a3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056849384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.sram_ctrl_access_during_key_req.2056849384
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.3961042472
Short name T709
Test name
Test status
Simulation time 16026562 ps
CPU time 0.69 seconds
Started Jan 03 01:44:59 PM PST 24
Finished Jan 03 01:45:02 PM PST 24
Peak memory 201912 kb
Host smart-4e0e1b64-8920-4496-9efe-d6c630071ad0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961042472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.sram_ctrl_alert_test.3961042472
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.3080085971
Short name T724
Test name
Test status
Simulation time 441137698944 ps
CPU time 2391.05 seconds
Started Jan 03 01:45:39 PM PST 24
Finished Jan 03 02:25:34 PM PST 24
Peak memory 202132 kb
Host smart-fff50e54-f135-410f-8460-230b29db6d49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080085971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection
.3080085971
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.36761450
Short name T498
Test name
Test status
Simulation time 6751959478 ps
CPU time 142.86 seconds
Started Jan 03 01:45:50 PM PST 24
Finished Jan 03 01:48:17 PM PST 24
Peak memory 210372 kb
Host smart-22780c3b-edf6-4bb2-a167-033d9a00774d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36761450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_esca
lation.36761450
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.1620524827
Short name T749
Test name
Test status
Simulation time 3162166619 ps
CPU time 76.33 seconds
Started Jan 03 01:45:48 PM PST 24
Finished Jan 03 01:47:06 PM PST 24
Peak memory 307616 kb
Host smart-1f9afda3-3347-448d-bad5-7bf62ae7024d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620524827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sram_ctrl_max_throughput.1620524827
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.2659296809
Short name T570
Test name
Test status
Simulation time 5050180909 ps
CPU time 143.89 seconds
Started Jan 03 01:45:00 PM PST 24
Finished Jan 03 01:47:26 PM PST 24
Peak memory 210572 kb
Host smart-116504c9-c5e5-48f0-b4d6-d12cba6586d7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659296809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_mem_partial_access.2659296809
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.1315652034
Short name T531
Test name
Test status
Simulation time 37333645012 ps
CPU time 159.28 seconds
Started Jan 03 01:45:41 PM PST 24
Finished Jan 03 01:48:23 PM PST 24
Peak memory 202216 kb
Host smart-a8e77bec-481a-4b45-8a11-f5483ee990ad
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315652034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr
l_mem_walk.1315652034
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.664498142
Short name T405
Test name
Test status
Simulation time 6342640129 ps
CPU time 930.21 seconds
Started Jan 03 01:45:40 PM PST 24
Finished Jan 03 02:01:13 PM PST 24
Peak memory 381144 kb
Host smart-66a8febb-24f6-4fc4-bacc-f09cb4d8ad72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664498142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multip
le_keys.664498142
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.2549001269
Short name T571
Test name
Test status
Simulation time 1949499522 ps
CPU time 18.42 seconds
Started Jan 03 01:45:43 PM PST 24
Finished Jan 03 01:46:03 PM PST 24
Peak memory 201940 kb
Host smart-0b3543f8-4a97-4f35-b30f-410e7a1d904a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549001269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
sram_ctrl_partial_access.2549001269
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.699290422
Short name T239
Test name
Test status
Simulation time 27963192145 ps
CPU time 447.72 seconds
Started Jan 03 01:45:41 PM PST 24
Finished Jan 03 01:53:11 PM PST 24
Peak memory 202112 kb
Host smart-7bae0205-6dcd-4969-9669-913065b15a32
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699290422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.sram_ctrl_partial_access_b2b.699290422
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.1866079178
Short name T922
Test name
Test status
Simulation time 365700196 ps
CPU time 6.49 seconds
Started Jan 03 01:45:43 PM PST 24
Finished Jan 03 01:45:52 PM PST 24
Peak memory 202412 kb
Host smart-c8113077-b392-49b8-a32f-7494cefe1985
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866079178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.1866079178
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.3326837815
Short name T930
Test name
Test status
Simulation time 43160823235 ps
CPU time 1016.15 seconds
Started Jan 03 01:45:43 PM PST 24
Finished Jan 03 02:02:42 PM PST 24
Peak memory 380000 kb
Host smart-7bd426be-3c34-4012-98c9-6972c448fc7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326837815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.3326837815
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.2224102973
Short name T801
Test name
Test status
Simulation time 1599368193 ps
CPU time 8.14 seconds
Started Jan 03 01:45:41 PM PST 24
Finished Jan 03 01:45:51 PM PST 24
Peak memory 203732 kb
Host smart-ceb7bed1-ab56-4c12-8bae-4d8add2fe14d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224102973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.2224102973
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all.234211110
Short name T910
Test name
Test status
Simulation time 994860844344 ps
CPU time 5215.88 seconds
Started Jan 03 01:45:19 PM PST 24
Finished Jan 03 03:12:25 PM PST 24
Peak memory 376012 kb
Host smart-23a08769-7dee-45d5-9763-7199b0e77926
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234211110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.sram_ctrl_stress_all.234211110
Directory /workspace/34.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2306181136
Short name T961
Test name
Test status
Simulation time 166636842 ps
CPU time 2378.95 seconds
Started Jan 03 01:45:43 PM PST 24
Finished Jan 03 02:25:25 PM PST 24
Peak memory 416776 kb
Host smart-40df866e-ae5c-4e00-bdf9-adf12ae7d8c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2306181136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.2306181136
Directory /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.1971702032
Short name T935
Test name
Test status
Simulation time 12101052453 ps
CPU time 508.54 seconds
Started Jan 03 01:45:41 PM PST 24
Finished Jan 03 01:54:12 PM PST 24
Peak memory 202184 kb
Host smart-630a147f-f5f4-4167-a157-fbcc745a3344
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971702032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_stress_pipeline.1971702032
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1877174766
Short name T228
Test name
Test status
Simulation time 1499327986 ps
CPU time 58.62 seconds
Started Jan 03 01:45:45 PM PST 24
Finished Jan 03 01:46:46 PM PST 24
Peak memory 296240 kb
Host smart-374ca4e0-b7b8-4b08-a313-4e298a147fae
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877174766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.1877174766
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.2979874898
Short name T292
Test name
Test status
Simulation time 39609451657 ps
CPU time 1010.85 seconds
Started Jan 03 01:45:02 PM PST 24
Finished Jan 03 02:01:56 PM PST 24
Peak memory 380128 kb
Host smart-15ec52df-f1ca-42f9-b7d7-c866799f2dd9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979874898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.sram_ctrl_access_during_key_req.2979874898
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.2994067317
Short name T22
Test name
Test status
Simulation time 38607196 ps
CPU time 0.65 seconds
Started Jan 03 01:45:26 PM PST 24
Finished Jan 03 01:45:37 PM PST 24
Peak memory 201476 kb
Host smart-86f9b251-982b-44aa-99b8-5aa3155959cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994067317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.2994067317
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.3589704637
Short name T267
Test name
Test status
Simulation time 52752067933 ps
CPU time 857.15 seconds
Started Jan 03 01:45:17 PM PST 24
Finished Jan 03 01:59:45 PM PST 24
Peak memory 202096 kb
Host smart-ae25c3ed-ff51-4e79-b08a-3ace7eb317e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589704637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection
.3589704637
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_executable.2344997131
Short name T593
Test name
Test status
Simulation time 14987651782 ps
CPU time 747.29 seconds
Started Jan 03 01:45:04 PM PST 24
Finished Jan 03 01:57:35 PM PST 24
Peak memory 378020 kb
Host smart-bea2898d-4ab0-4986-8c7f-c27c27b4f961
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344997131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab
le.2344997131
Directory /workspace/35.sram_ctrl_executable/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.649958860
Short name T575
Test name
Test status
Simulation time 70105848826 ps
CPU time 136.79 seconds
Started Jan 03 01:45:03 PM PST 24
Finished Jan 03 01:47:23 PM PST 24
Peak memory 202200 kb
Host smart-4a98ab51-205a-4d2b-b3e7-3e0e31ae10b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649958860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_esc
alation.649958860
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.4053561308
Short name T848
Test name
Test status
Simulation time 2684401348 ps
CPU time 65.07 seconds
Started Jan 03 01:45:24 PM PST 24
Finished Jan 03 01:46:40 PM PST 24
Peak memory 296220 kb
Host smart-640bd5c7-3a13-4f17-8672-f312fb2c200a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053561308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_max_throughput.4053561308
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2627045948
Short name T909
Test name
Test status
Simulation time 2450348405 ps
CPU time 79.6 seconds
Started Jan 03 01:45:23 PM PST 24
Finished Jan 03 01:46:54 PM PST 24
Peak memory 211168 kb
Host smart-8806537e-e13e-4a0d-aac7-da8106eaf6a2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627045948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_mem_partial_access.2627045948
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.4045149374
Short name T38
Test name
Test status
Simulation time 8051722940 ps
CPU time 249.62 seconds
Started Jan 03 01:45:23 PM PST 24
Finished Jan 03 01:49:44 PM PST 24
Peak memory 202172 kb
Host smart-0bd0c4f0-160f-4ec7-9b8e-34182335fa04
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045149374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr
l_mem_walk.4045149374
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.427955928
Short name T655
Test name
Test status
Simulation time 27944227087 ps
CPU time 866.45 seconds
Started Jan 03 01:44:58 PM PST 24
Finished Jan 03 01:59:26 PM PST 24
Peak memory 380160 kb
Host smart-8704518c-c585-4f95-8e9b-e57ead43eb2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427955928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multip
le_keys.427955928
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.1106385644
Short name T675
Test name
Test status
Simulation time 5582872487 ps
CPU time 16.19 seconds
Started Jan 03 01:45:01 PM PST 24
Finished Jan 03 01:45:21 PM PST 24
Peak memory 202184 kb
Host smart-47f8c56a-8afa-4de8-b4cc-76ea4e49f03b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106385644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
sram_ctrl_partial_access.1106385644
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3553793825
Short name T318
Test name
Test status
Simulation time 16890670501 ps
CPU time 420.1 seconds
Started Jan 03 01:45:01 PM PST 24
Finished Jan 03 01:52:05 PM PST 24
Peak memory 202104 kb
Host smart-d10428d1-f792-4ef4-a36c-cb435c69898e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553793825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 35.sram_ctrl_partial_access_b2b.3553793825
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.3025029426
Short name T932
Test name
Test status
Simulation time 350381441 ps
CPU time 5.32 seconds
Started Jan 03 01:45:24 PM PST 24
Finished Jan 03 01:45:40 PM PST 24
Peak memory 202396 kb
Host smart-fc1f823a-e9a4-46b1-b0df-3ecdf79ef829
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025029426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.3025029426
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.1833420392
Short name T397
Test name
Test status
Simulation time 15004055337 ps
CPU time 654.99 seconds
Started Jan 03 01:45:03 PM PST 24
Finished Jan 03 01:56:01 PM PST 24
Peak memory 373952 kb
Host smart-4a0da648-2f41-4fc1-b26b-85ae10559a9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833420392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.1833420392
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.3039793170
Short name T615
Test name
Test status
Simulation time 398597226 ps
CPU time 18.71 seconds
Started Jan 03 01:44:59 PM PST 24
Finished Jan 03 01:45:21 PM PST 24
Peak memory 226452 kb
Host smart-78e2cc6b-21ef-47c4-adc0-de946a9479b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039793170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.3039793170
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2113383011
Short name T495
Test name
Test status
Simulation time 1125807066 ps
CPU time 3754.57 seconds
Started Jan 03 01:45:24 PM PST 24
Finished Jan 03 02:48:10 PM PST 24
Peak memory 698536 kb
Host smart-af9ed797-aa7a-4368-aa6e-124e94dac4ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2113383011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.2113383011
Directory /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.795733765
Short name T412
Test name
Test status
Simulation time 10810478669 ps
CPU time 359.91 seconds
Started Jan 03 01:45:20 PM PST 24
Finished Jan 03 01:51:28 PM PST 24
Peak memory 202176 kb
Host smart-1d2d8e56-941a-4077-af9b-260ed30fd41b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795733765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.sram_ctrl_stress_pipeline.795733765
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2038653154
Short name T775
Test name
Test status
Simulation time 758742198 ps
CPU time 59.65 seconds
Started Jan 03 01:44:57 PM PST 24
Finished Jan 03 01:45:59 PM PST 24
Peak memory 292588 kb
Host smart-df3b810b-7434-4b2d-8fc4-0ba512110374
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038653154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.2038653154
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.2489026451
Short name T500
Test name
Test status
Simulation time 42516096142 ps
CPU time 2008.09 seconds
Started Jan 03 01:45:39 PM PST 24
Finished Jan 03 02:19:11 PM PST 24
Peak memory 379120 kb
Host smart-993284a7-233d-48f4-89d6-ff63f4f2b9b6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489026451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.sram_ctrl_access_during_key_req.2489026451
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.1491227883
Short name T255
Test name
Test status
Simulation time 22132906 ps
CPU time 0.65 seconds
Started Jan 03 01:44:59 PM PST 24
Finished Jan 03 01:45:02 PM PST 24
Peak memory 201384 kb
Host smart-8f5ab6c2-ba0e-435f-b7d6-6af54a56f505
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491227883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.sram_ctrl_alert_test.1491227883
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.4188333413
Short name T515
Test name
Test status
Simulation time 371808502874 ps
CPU time 1606.51 seconds
Started Jan 03 01:45:26 PM PST 24
Finished Jan 03 02:12:24 PM PST 24
Peak memory 201940 kb
Host smart-5208a4e8-e215-4398-8ac2-0a8f016fdf5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188333413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection
.4188333413
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_executable.3718410316
Short name T370
Test name
Test status
Simulation time 1777095778 ps
CPU time 132.04 seconds
Started Jan 03 01:45:47 PM PST 24
Finished Jan 03 01:48:01 PM PST 24
Peak memory 288652 kb
Host smart-ce28ee72-4e4f-4847-805d-3d12fe5b7d91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718410316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab
le.3718410316
Directory /workspace/36.sram_ctrl_executable/latest

Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.4150026380
Short name T744
Test name
Test status
Simulation time 3336329254 ps
CPU time 32.66 seconds
Started Jan 03 01:45:40 PM PST 24
Finished Jan 03 01:46:15 PM PST 24
Peak memory 210424 kb
Host smart-3acc7b54-334b-49b5-b42b-4f594c72c908
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150026380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es
calation.4150026380
Directory /workspace/36.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.4062758742
Short name T328
Test name
Test status
Simulation time 2318940344 ps
CPU time 129.76 seconds
Started Jan 03 01:45:29 PM PST 24
Finished Jan 03 01:47:48 PM PST 24
Peak memory 366852 kb
Host smart-5665a999-7f23-4ab2-b9e5-b58f417372cd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062758742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_max_throughput.4062758742
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.1487092552
Short name T379
Test name
Test status
Simulation time 957235384 ps
CPU time 75.8 seconds
Started Jan 03 01:45:50 PM PST 24
Finished Jan 03 01:47:09 PM PST 24
Peak memory 218424 kb
Host smart-6989f392-6e93-4cbc-8116-dc6b30ca8899
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487092552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_mem_partial_access.1487092552
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.1885108648
Short name T392
Test name
Test status
Simulation time 41418374789 ps
CPU time 163.88 seconds
Started Jan 03 01:45:43 PM PST 24
Finished Jan 03 01:48:29 PM PST 24
Peak memory 202176 kb
Host smart-dc73b32a-7a93-4255-bdb4-c8b440937815
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885108648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr
l_mem_walk.1885108648
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.3657412066
Short name T340
Test name
Test status
Simulation time 25106683001 ps
CPU time 909.14 seconds
Started Jan 03 01:45:24 PM PST 24
Finished Jan 03 02:00:44 PM PST 24
Peak memory 379040 kb
Host smart-ec987ed6-cfae-4c1f-9be3-79371a36caca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657412066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi
ple_keys.3657412066
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.1146551359
Short name T383
Test name
Test status
Simulation time 1429932647 ps
CPU time 6.53 seconds
Started Jan 03 01:45:31 PM PST 24
Finished Jan 03 01:45:46 PM PST 24
Peak memory 202140 kb
Host smart-10a66ae9-2ffd-402f-855a-2c283d805190
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146551359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
sram_ctrl_partial_access.1146551359
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.329289449
Short name T619
Test name
Test status
Simulation time 58965038835 ps
CPU time 326.37 seconds
Started Jan 03 01:45:47 PM PST 24
Finished Jan 03 01:51:15 PM PST 24
Peak memory 202176 kb
Host smart-9f1bebf0-de43-4153-b6e1-7fc1634517f6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329289449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.sram_ctrl_partial_access_b2b.329289449
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.1429249920
Short name T296
Test name
Test status
Simulation time 406991181 ps
CPU time 5.28 seconds
Started Jan 03 01:45:44 PM PST 24
Finished Jan 03 01:45:51 PM PST 24
Peak memory 202324 kb
Host smart-798dee29-2adb-4623-b491-3a39faf9c92c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429249920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.1429249920
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.2145352737
Short name T798
Test name
Test status
Simulation time 22982448463 ps
CPU time 302.62 seconds
Started Jan 03 01:45:41 PM PST 24
Finished Jan 03 01:50:46 PM PST 24
Peak memory 373936 kb
Host smart-2467eb71-276e-4d97-a3a7-1fabb0190b79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145352737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.2145352737
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.314591728
Short name T657
Test name
Test status
Simulation time 758200267 ps
CPU time 20.19 seconds
Started Jan 03 01:45:24 PM PST 24
Finished Jan 03 01:45:54 PM PST 24
Peak memory 229608 kb
Host smart-84b846e3-3e82-44cf-aac0-d59a9537730f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314591728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.314591728
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3087794856
Short name T650
Test name
Test status
Simulation time 12704881362 ps
CPU time 1745.72 seconds
Started Jan 03 01:45:50 PM PST 24
Finished Jan 03 02:15:00 PM PST 24
Peak memory 572480 kb
Host smart-3c95c17b-dc10-4a6f-8b92-e5514ef562f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3087794856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.3087794856
Directory /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.3298863791
Short name T300
Test name
Test status
Simulation time 6685870951 ps
CPU time 513.42 seconds
Started Jan 03 01:45:21 PM PST 24
Finished Jan 03 01:54:03 PM PST 24
Peak memory 202152 kb
Host smart-66a0ef78-5bd1-4000-8b8f-d20491cf4948
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298863791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_stress_pipeline.3298863791
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.950131829
Short name T564
Test name
Test status
Simulation time 725432087 ps
CPU time 51.11 seconds
Started Jan 03 01:45:43 PM PST 24
Finished Jan 03 01:46:36 PM PST 24
Peak memory 278668 kb
Host smart-98702c62-b445-4a33-b892-b2e460627c18
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950131829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_throughput_w_partial_write.950131829
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.1049534011
Short name T465
Test name
Test status
Simulation time 7059477548 ps
CPU time 948.37 seconds
Started Jan 03 01:45:18 PM PST 24
Finished Jan 03 02:01:17 PM PST 24
Peak memory 370832 kb
Host smart-d11e8573-0089-4299-b21a-f4e28574faf2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049534011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.sram_ctrl_access_during_key_req.1049534011
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.675668810
Short name T445
Test name
Test status
Simulation time 11720563 ps
CPU time 0.63 seconds
Started Jan 03 01:45:23 PM PST 24
Finished Jan 03 01:45:34 PM PST 24
Peak memory 201716 kb
Host smart-34b53169-0129-4d5f-bae8-1397db5e6e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675668810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.675668810
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.1903809550
Short name T799
Test name
Test status
Simulation time 60593264022 ps
CPU time 1894.34 seconds
Started Jan 03 01:45:18 PM PST 24
Finished Jan 03 02:17:03 PM PST 24
Peak memory 202076 kb
Host smart-330c1981-c3a6-4858-ae8e-c6eb47564681
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903809550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection
.1903809550
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_executable.740658949
Short name T653
Test name
Test status
Simulation time 15139696734 ps
CPU time 406.76 seconds
Started Jan 03 01:45:18 PM PST 24
Finished Jan 03 01:52:15 PM PST 24
Peak memory 370444 kb
Host smart-f752e334-ec76-4598-9218-9a7c2388a7fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740658949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executabl
e.740658949
Directory /workspace/37.sram_ctrl_executable/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.3505706012
Short name T672
Test name
Test status
Simulation time 749753847 ps
CPU time 47.76 seconds
Started Jan 03 01:45:15 PM PST 24
Finished Jan 03 01:46:12 PM PST 24
Peak memory 274152 kb
Host smart-cdac3e75-6d41-4cf4-be86-422d7f625e5b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505706012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_max_throughput.3505706012
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.3359974491
Short name T633
Test name
Test status
Simulation time 19776318629 ps
CPU time 159.92 seconds
Started Jan 03 01:45:27 PM PST 24
Finished Jan 03 01:48:18 PM PST 24
Peak memory 214584 kb
Host smart-7be1faa6-9863-4086-ade5-68b2e5fc46b0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359974491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_mem_partial_access.3359974491
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.2833919275
Short name T621
Test name
Test status
Simulation time 14342466758 ps
CPU time 273.5 seconds
Started Jan 03 01:45:24 PM PST 24
Finished Jan 03 01:50:09 PM PST 24
Peak memory 202276 kb
Host smart-2fba345c-20a4-4602-839f-c483ecf76634
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833919275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr
l_mem_walk.2833919275
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.1818655438
Short name T16
Test name
Test status
Simulation time 34778846755 ps
CPU time 222.09 seconds
Started Jan 03 01:45:00 PM PST 24
Finished Jan 03 01:48:44 PM PST 24
Peak memory 315960 kb
Host smart-24a6b075-ab80-4e9c-8724-58ded3b25c43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818655438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi
ple_keys.1818655438
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.2531492330
Short name T233
Test name
Test status
Simulation time 3943845104 ps
CPU time 36.19 seconds
Started Jan 03 01:45:00 PM PST 24
Finished Jan 03 01:45:38 PM PST 24
Peak memory 274628 kb
Host smart-b9cac53d-6cea-40da-aec8-b8a0c88e4274
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531492330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
sram_ctrl_partial_access.2531492330
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2377312512
Short name T952
Test name
Test status
Simulation time 20557471453 ps
CPU time 335.72 seconds
Started Jan 03 01:44:59 PM PST 24
Finished Jan 03 01:50:37 PM PST 24
Peak memory 202104 kb
Host smart-b7f08667-eaba-4492-933a-2ce45f5992b2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377312512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_partial_access_b2b.2377312512
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.3665208404
Short name T530
Test name
Test status
Simulation time 1021026755 ps
CPU time 6.65 seconds
Started Jan 03 01:45:16 PM PST 24
Finished Jan 03 01:45:33 PM PST 24
Peak memory 202416 kb
Host smart-a547f745-130c-453b-8f46-f35b19609b7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665208404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.3665208404
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.3347889239
Short name T128
Test name
Test status
Simulation time 11227000658 ps
CPU time 1193.49 seconds
Started Jan 03 01:45:24 PM PST 24
Finished Jan 03 02:05:29 PM PST 24
Peak memory 373984 kb
Host smart-ba75eb41-fe31-46cf-8454-91cec03f1dc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347889239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.3347889239
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.217218166
Short name T287
Test name
Test status
Simulation time 731774998 ps
CPU time 22.42 seconds
Started Jan 03 01:44:59 PM PST 24
Finished Jan 03 01:45:23 PM PST 24
Peak memory 238424 kb
Host smart-eb516c8b-421e-4e41-b60c-25a9b597f221
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217218166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.217218166
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.920696773
Short name T390
Test name
Test status
Simulation time 1410445779 ps
CPU time 3662.77 seconds
Started Jan 03 01:45:24 PM PST 24
Finished Jan 03 02:46:38 PM PST 24
Peak memory 414408 kb
Host smart-b5a07d20-c8ae-4185-aa11-768e63ca0ebb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=920696773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.920696773
Directory /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.2978601532
Short name T683
Test name
Test status
Simulation time 9322012653 ps
CPU time 388.74 seconds
Started Jan 03 01:45:01 PM PST 24
Finished Jan 03 01:51:33 PM PST 24
Peak memory 202148 kb
Host smart-28efb47b-1c82-4fcb-b85e-ef06ee4c8366
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978601532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_stress_pipeline.2978601532
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2331075256
Short name T110
Test name
Test status
Simulation time 3863663377 ps
CPU time 32.44 seconds
Started Jan 03 01:45:01 PM PST 24
Finished Jan 03 01:45:36 PM PST 24
Peak memory 239832 kb
Host smart-1f048dcb-930f-4de9-a808-487495f0707f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331075256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.2331075256
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.1192557102
Short name T902
Test name
Test status
Simulation time 15912283303 ps
CPU time 777.14 seconds
Started Jan 03 01:45:27 PM PST 24
Finished Jan 03 01:58:35 PM PST 24
Peak memory 371860 kb
Host smart-a98f080b-2f69-4247-8d99-f607cf5779e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192557102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.sram_ctrl_access_during_key_req.1192557102
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.2993114516
Short name T875
Test name
Test status
Simulation time 63509023 ps
CPU time 0.63 seconds
Started Jan 03 01:45:25 PM PST 24
Finished Jan 03 01:45:37 PM PST 24
Peak memory 201444 kb
Host smart-68f314c3-fe1d-4eb1-b0a9-b129752c57c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993114516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.sram_ctrl_alert_test.2993114516
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.3002277155
Short name T283
Test name
Test status
Simulation time 551817491304 ps
CPU time 2436.6 seconds
Started Jan 03 01:45:23 PM PST 24
Finished Jan 03 02:26:11 PM PST 24
Peak memory 202168 kb
Host smart-4802a865-3eff-46f1-9b22-e2ef54b2e1bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002277155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection
.3002277155
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_executable.179072846
Short name T869
Test name
Test status
Simulation time 5922991999 ps
CPU time 184.91 seconds
Started Jan 03 01:45:25 PM PST 24
Finished Jan 03 01:48:41 PM PST 24
Peak memory 350440 kb
Host smart-525d543b-98a8-4a43-a6e8-ea78ade5a4b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179072846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executabl
e.179072846
Directory /workspace/38.sram_ctrl_executable/latest

Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.1932294954
Short name T431
Test name
Test status
Simulation time 10551735911 ps
CPU time 91.83 seconds
Started Jan 03 01:45:23 PM PST 24
Finished Jan 03 01:47:06 PM PST 24
Peak memory 210500 kb
Host smart-4cb5c246-a7a8-4f61-8a52-ff505696be30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932294954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es
calation.1932294954
Directory /workspace/38.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.2569537864
Short name T966
Test name
Test status
Simulation time 824812065 ps
CPU time 172.34 seconds
Started Jan 03 01:45:23 PM PST 24
Finished Jan 03 01:48:26 PM PST 24
Peak memory 354504 kb
Host smart-b0601642-2fe8-4d87-ac9d-1b9db4256c55
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569537864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_max_throughput.2569537864
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.1262320056
Short name T755
Test name
Test status
Simulation time 18248243458 ps
CPU time 158.99 seconds
Started Jan 03 01:45:20 PM PST 24
Finished Jan 03 01:48:08 PM PST 24
Peak memory 218552 kb
Host smart-cbb4f0ee-be23-4542-b09e-0123fa82dac7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262320056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_mem_partial_access.1262320056
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.3734779496
Short name T512
Test name
Test status
Simulation time 10752184234 ps
CPU time 154.44 seconds
Started Jan 03 01:45:21 PM PST 24
Finished Jan 03 01:48:04 PM PST 24
Peak memory 202192 kb
Host smart-80e583e1-29ed-4d27-9ea7-34e2f51105a6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734779496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr
l_mem_walk.3734779496
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.825713752
Short name T562
Test name
Test status
Simulation time 20668528485 ps
CPU time 1031.18 seconds
Started Jan 03 01:45:24 PM PST 24
Finished Jan 03 02:02:46 PM PST 24
Peak memory 378064 kb
Host smart-5eb4a26e-3d00-493f-846d-618ce9ad1003
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825713752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multip
le_keys.825713752
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.508040449
Short name T666
Test name
Test status
Simulation time 5817681684 ps
CPU time 132.86 seconds
Started Jan 03 01:45:24 PM PST 24
Finished Jan 03 01:47:47 PM PST 24
Peak memory 357504 kb
Host smart-f383c44b-9c8d-4dee-848a-d0f1c0d7c9aa
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508040449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.s
ram_ctrl_partial_access.508040449
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.4187991670
Short name T868
Test name
Test status
Simulation time 83979742388 ps
CPU time 539.91 seconds
Started Jan 03 01:45:25 PM PST 24
Finished Jan 03 01:54:36 PM PST 24
Peak memory 201960 kb
Host smart-5dd8536c-8561-48fe-a070-704d5ede48fe
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187991670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.sram_ctrl_partial_access_b2b.4187991670
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.1368647621
Short name T585
Test name
Test status
Simulation time 365316846 ps
CPU time 6.56 seconds
Started Jan 03 01:45:21 PM PST 24
Finished Jan 03 01:45:36 PM PST 24
Peak memory 202348 kb
Host smart-d2a6b9ad-d6b8-4bfb-af24-08a316b6da4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368647621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.1368647621
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.2344921866
Short name T505
Test name
Test status
Simulation time 14783332387 ps
CPU time 1028.56 seconds
Started Jan 03 01:45:27 PM PST 24
Finished Jan 03 02:02:47 PM PST 24
Peak memory 374856 kb
Host smart-abe53329-6199-41ad-91e8-92073e32d3ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344921866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.2344921866
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.4072642153
Short name T723
Test name
Test status
Simulation time 562781740 ps
CPU time 22.53 seconds
Started Jan 03 01:45:17 PM PST 24
Finished Jan 03 01:45:51 PM PST 24
Peak memory 258332 kb
Host smart-fa69d759-fc7e-4cb6-8158-de8945200181
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072642153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.4072642153
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1558137134
Short name T46
Test name
Test status
Simulation time 905837704 ps
CPU time 2159.1 seconds
Started Jan 03 01:45:26 PM PST 24
Finished Jan 03 02:21:36 PM PST 24
Peak memory 539416 kb
Host smart-4fb3bb5e-c0d9-4cb8-a0f9-1de89ac83988
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1558137134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.1558137134
Directory /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.2082192761
Short name T590
Test name
Test status
Simulation time 2560314438 ps
CPU time 208.11 seconds
Started Jan 03 01:45:25 PM PST 24
Finished Jan 03 01:49:04 PM PST 24
Peak memory 201968 kb
Host smart-84a525ea-731d-40b7-8596-8c9163f7d9e0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082192761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_stress_pipeline.2082192761
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.749705341
Short name T246
Test name
Test status
Simulation time 3872790715 ps
CPU time 196.18 seconds
Started Jan 03 01:45:16 PM PST 24
Finished Jan 03 01:48:42 PM PST 24
Peak memory 359932 kb
Host smart-abc8e1ca-e98f-4451-8aaf-bb64a89eb821
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749705341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_throughput_w_partial_write.749705341
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.2317127223
Short name T832
Test name
Test status
Simulation time 9953913287 ps
CPU time 1785 seconds
Started Jan 03 01:46:27 PM PST 24
Finished Jan 03 02:16:16 PM PST 24
Peak memory 380116 kb
Host smart-d728347b-e7e3-4a45-9f2d-d104ad77279a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317127223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.sram_ctrl_access_during_key_req.2317127223
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.83601441
Short name T23
Test name
Test status
Simulation time 13472736 ps
CPU time 0.68 seconds
Started Jan 03 01:46:30 PM PST 24
Finished Jan 03 01:46:36 PM PST 24
Peak memory 201916 kb
Host smart-4255f1e3-2934-45f6-9680-55a2001e462c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83601441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_alert_test.83601441
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.70287027
Short name T690
Test name
Test status
Simulation time 149972436396 ps
CPU time 1386.42 seconds
Started Jan 03 01:45:26 PM PST 24
Finished Jan 03 02:08:43 PM PST 24
Peak memory 202228 kb
Host smart-bba7825d-3a2c-4398-a2bd-331ea52adf54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70287027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.70287027
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.801439978
Short name T458
Test name
Test status
Simulation time 3523514728 ps
CPU time 77.13 seconds
Started Jan 03 01:46:32 PM PST 24
Finished Jan 03 01:47:56 PM PST 24
Peak memory 318796 kb
Host smart-b5838d29-4941-4807-bf6e-bd270d247f76
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801439978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.sram_ctrl_max_throughput.801439978
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2120863091
Short name T979
Test name
Test status
Simulation time 21756953407 ps
CPU time 81.36 seconds
Started Jan 03 01:46:26 PM PST 24
Finished Jan 03 01:47:50 PM PST 24
Peak memory 211348 kb
Host smart-6548dd06-3b9d-420a-b39f-51b55caebe74
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120863091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_mem_partial_access.2120863091
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.433838468
Short name T441
Test name
Test status
Simulation time 125139103509 ps
CPU time 305.39 seconds
Started Jan 03 01:46:29 PM PST 24
Finished Jan 03 01:51:38 PM PST 24
Peak memory 202284 kb
Host smart-fba836a5-75b5-4d2c-8468-b2b48f71720e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433838468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl
_mem_walk.433838468
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.1651057301
Short name T735
Test name
Test status
Simulation time 15021962421 ps
CPU time 1072.43 seconds
Started Jan 03 01:45:23 PM PST 24
Finished Jan 03 02:03:26 PM PST 24
Peak memory 379172 kb
Host smart-f2a200e0-7da5-48a8-ad91-04dc3406b2b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651057301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi
ple_keys.1651057301
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.2021085247
Short name T927
Test name
Test status
Simulation time 3989516063 ps
CPU time 42 seconds
Started Jan 03 01:45:26 PM PST 24
Finished Jan 03 01:46:19 PM PST 24
Peak memory 276740 kb
Host smart-8ad55223-e454-427c-bafc-e7cb66c8e940
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021085247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
sram_ctrl_partial_access.2021085247
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2186865451
Short name T987
Test name
Test status
Simulation time 48450097522 ps
CPU time 356.54 seconds
Started Jan 03 01:45:25 PM PST 24
Finished Jan 03 01:51:32 PM PST 24
Peak memory 202152 kb
Host smart-a12c4615-8d25-4150-9a8f-23813d1ecae8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186865451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.sram_ctrl_partial_access_b2b.2186865451
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.20401011
Short name T297
Test name
Test status
Simulation time 1399194484 ps
CPU time 13.89 seconds
Started Jan 03 01:46:32 PM PST 24
Finished Jan 03 01:46:53 PM PST 24
Peak memory 202356 kb
Host smart-d35949a3-cfc8-48f0-a3a3-e5bce8462e63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20401011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.20401011
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.1798747032
Short name T44
Test name
Test status
Simulation time 12971072917 ps
CPU time 710.96 seconds
Started Jan 03 01:46:28 PM PST 24
Finished Jan 03 01:58:23 PM PST 24
Peak memory 378084 kb
Host smart-32d44482-044c-471f-b7f3-fe6ad6e36405
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798747032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.1798747032
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.3959648379
Short name T424
Test name
Test status
Simulation time 1045683122 ps
CPU time 15.58 seconds
Started Jan 03 01:45:21 PM PST 24
Finished Jan 03 01:45:45 PM PST 24
Peak memory 202072 kb
Host smart-e24486f1-61bc-4762-abec-c2e1c351be44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959648379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.3959648379
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all.406143155
Short name T112
Test name
Test status
Simulation time 30624626138 ps
CPU time 3098.78 seconds
Started Jan 03 01:46:33 PM PST 24
Finished Jan 03 02:38:21 PM PST 24
Peak memory 381148 kb
Host smart-739845a2-843f-4ee6-bbf0-979380a5f1f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406143155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.sram_ctrl_stress_all.406143155
Directory /workspace/39.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3101105732
Short name T573
Test name
Test status
Simulation time 15593554639 ps
CPU time 5103.95 seconds
Started Jan 03 01:46:26 PM PST 24
Finished Jan 03 03:11:34 PM PST 24
Peak memory 616076 kb
Host smart-06728b14-452d-4e60-b22e-8388325601e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3101105732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.3101105732
Directory /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.237419348
Short name T451
Test name
Test status
Simulation time 8805433125 ps
CPU time 323.19 seconds
Started Jan 03 01:45:18 PM PST 24
Finished Jan 03 01:50:51 PM PST 24
Peak memory 202104 kb
Host smart-3b023c6f-a457-4f08-a0b2-e224d2f6463c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237419348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.sram_ctrl_stress_pipeline.237419348
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.1511137175
Short name T358
Test name
Test status
Simulation time 15571576466 ps
CPU time 155.68 seconds
Started Jan 03 01:46:27 PM PST 24
Finished Jan 03 01:49:06 PM PST 24
Peak memory 362612 kb
Host smart-e3acfc7a-688b-4d09-993c-aa341db2988b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511137175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.1511137175
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.3336972410
Short name T788
Test name
Test status
Simulation time 15263714928 ps
CPU time 839.49 seconds
Started Jan 03 01:40:30 PM PST 24
Finished Jan 03 01:54:34 PM PST 24
Peak memory 371652 kb
Host smart-813a9a10-116f-4e95-95a0-9feb85b5a142
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336972410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_access_during_key_req.3336972410
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.3231491073
Short name T354
Test name
Test status
Simulation time 18504243 ps
CPU time 0.67 seconds
Started Jan 03 01:40:49 PM PST 24
Finished Jan 03 01:40:56 PM PST 24
Peak memory 201456 kb
Host smart-aea09d6d-5979-4731-ba1a-a6951f4349f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231491073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.3231491073
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.283115756
Short name T449
Test name
Test status
Simulation time 229478595340 ps
CPU time 1251.8 seconds
Started Jan 03 01:40:17 PM PST 24
Finished Jan 03 02:01:17 PM PST 24
Peak memory 202052 kb
Host smart-65e82be6-55d0-4391-8361-5e873fcd9379
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283115756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.283115756
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_executable.871465706
Short name T720
Test name
Test status
Simulation time 24630351596 ps
CPU time 1143.08 seconds
Started Jan 03 01:40:43 PM PST 24
Finished Jan 03 01:59:53 PM PST 24
Peak memory 377936 kb
Host smart-d1c4821e-27ea-4d0f-9868-329a1a12b5d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871465706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable
.871465706
Directory /workspace/4.sram_ctrl_executable/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.2785668258
Short name T1
Test name
Test status
Simulation time 6074552499 ps
CPU time 169.63 seconds
Started Jan 03 01:40:16 PM PST 24
Finished Jan 03 01:43:15 PM PST 24
Peak memory 202252 kb
Host smart-0d91e1aa-90e2-494f-8ebd-8eced76c5793
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785668258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc
alation.2785668258
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.206718363
Short name T773
Test name
Test status
Simulation time 1550769481 ps
CPU time 85.43 seconds
Started Jan 03 01:40:18 PM PST 24
Finished Jan 03 01:41:51 PM PST 24
Peak memory 322772 kb
Host smart-dae1688d-3b99-4e6e-99b2-29bf01dcbb45
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206718363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.sram_ctrl_max_throughput.206718363
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.3465611867
Short name T427
Test name
Test status
Simulation time 3973326103 ps
CPU time 75.92 seconds
Started Jan 03 01:40:45 PM PST 24
Finished Jan 03 01:42:07 PM PST 24
Peak memory 211116 kb
Host smart-14261996-9247-4a75-aa9b-b728624a6c4f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465611867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_mem_partial_access.3465611867
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.731149057
Short name T791
Test name
Test status
Simulation time 43005243656 ps
CPU time 169.65 seconds
Started Jan 03 01:40:32 PM PST 24
Finished Jan 03 01:43:27 PM PST 24
Peak memory 202160 kb
Host smart-a5001121-3305-4d08-a7c0-c6a6bd061ed9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731149057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_
mem_walk.731149057
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.1301063103
Short name T896
Test name
Test status
Simulation time 72781035000 ps
CPU time 1774.67 seconds
Started Jan 03 01:40:24 PM PST 24
Finished Jan 03 02:10:03 PM PST 24
Peak memory 379144 kb
Host smart-2c7f855e-c65e-47a1-9abf-6399073f22da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301063103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip
le_keys.1301063103
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.3210944170
Short name T648
Test name
Test status
Simulation time 1825790838 ps
CPU time 34.2 seconds
Started Jan 03 01:40:17 PM PST 24
Finished Jan 03 01:41:00 PM PST 24
Peak memory 202052 kb
Host smart-0675adee-1bbc-49eb-8e9a-accc47d9ca21
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210944170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s
ram_ctrl_partial_access.3210944170
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1058327531
Short name T953
Test name
Test status
Simulation time 47387664759 ps
CPU time 316.78 seconds
Started Jan 03 01:40:18 PM PST 24
Finished Jan 03 01:45:43 PM PST 24
Peak memory 202168 kb
Host smart-5a7fc4e8-db2e-4177-8c1e-4976f10e2912
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058327531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.sram_ctrl_partial_access_b2b.1058327531
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.3341185046
Short name T227
Test name
Test status
Simulation time 709366597 ps
CPU time 13.24 seconds
Started Jan 03 01:40:32 PM PST 24
Finished Jan 03 01:40:51 PM PST 24
Peak memory 202416 kb
Host smart-d2d2b994-e0f7-49d2-9158-a634d524b0a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341185046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.3341185046
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.1424406378
Short name T28
Test name
Test status
Simulation time 28416782397 ps
CPU time 797.58 seconds
Started Jan 03 01:40:33 PM PST 24
Finished Jan 03 01:53:56 PM PST 24
Peak memory 378380 kb
Host smart-1fdb71b0-5499-4365-a51a-dcfc480ecda5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424406378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.1424406378
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.3523899034
Short name T26
Test name
Test status
Simulation time 759437212 ps
CPU time 4.12 seconds
Started Jan 03 01:40:48 PM PST 24
Finished Jan 03 01:40:58 PM PST 24
Peak memory 220852 kb
Host smart-34d1d45e-3296-4581-bc03-c2a53f70d2d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523899034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_sec_cm.3523899034
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.3033113400
Short name T293
Test name
Test status
Simulation time 441809125 ps
CPU time 101.54 seconds
Started Jan 03 01:40:13 PM PST 24
Finished Jan 03 01:42:05 PM PST 24
Peak memory 341844 kb
Host smart-a2b9fb55-059d-4a80-aa89-ff825d5f0161
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033113400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.3033113400
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2033736357
Short name T985
Test name
Test status
Simulation time 16958298521 ps
CPU time 6336.58 seconds
Started Jan 03 01:40:44 PM PST 24
Finished Jan 03 03:26:28 PM PST 24
Peak memory 673044 kb
Host smart-70258772-bd0c-44b1-8918-d3755c13ff1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2033736357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.2033736357
Directory /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.3298131132
Short name T630
Test name
Test status
Simulation time 13312232721 ps
CPU time 244.57 seconds
Started Jan 03 01:40:19 PM PST 24
Finished Jan 03 01:44:31 PM PST 24
Peak memory 202216 kb
Host smart-413bfb70-4c58-4a8f-86e8-2e660b392ca3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298131132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_stress_pipeline.3298131132
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.4275270926
Short name T692
Test name
Test status
Simulation time 3047685256 ps
CPU time 40.14 seconds
Started Jan 03 01:40:21 PM PST 24
Finished Jan 03 01:41:07 PM PST 24
Peak memory 251196 kb
Host smart-21b3323b-62f1-4e50-a8d5-d2a90d4200a4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275270926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.4275270926
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.1992426496
Short name T413
Test name
Test status
Simulation time 18524478926 ps
CPU time 1520.2 seconds
Started Jan 03 01:46:27 PM PST 24
Finished Jan 03 02:11:51 PM PST 24
Peak memory 380080 kb
Host smart-454dbfe8-6608-4431-ac6d-61a34fd4bb65
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992426496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.sram_ctrl_access_during_key_req.1992426496
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.435222322
Short name T830
Test name
Test status
Simulation time 48120176 ps
CPU time 0.65 seconds
Started Jan 03 01:46:32 PM PST 24
Finished Jan 03 01:46:39 PM PST 24
Peak memory 201856 kb
Host smart-54581371-527c-4f90-9891-aca0c35041d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435222322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.sram_ctrl_alert_test.435222322
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.2374119479
Short name T561
Test name
Test status
Simulation time 135123387774 ps
CPU time 749.55 seconds
Started Jan 03 01:46:26 PM PST 24
Finished Jan 03 01:58:59 PM PST 24
Peak memory 202208 kb
Host smart-36713859-cb0e-41fa-9d85-33576eaac88b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374119479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection
.2374119479
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_executable.662762847
Short name T651
Test name
Test status
Simulation time 25718400891 ps
CPU time 270.95 seconds
Started Jan 03 01:46:30 PM PST 24
Finished Jan 03 01:51:06 PM PST 24
Peak memory 309332 kb
Host smart-10140e2c-5406-4a44-bf98-744304be8b34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662762847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executabl
e.662762847
Directory /workspace/40.sram_ctrl_executable/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.1746273105
Short name T663
Test name
Test status
Simulation time 45085116790 ps
CPU time 222.98 seconds
Started Jan 03 01:46:26 PM PST 24
Finished Jan 03 01:50:13 PM PST 24
Peak memory 210364 kb
Host smart-f328f7cb-5bfa-4f5c-9844-c07f2ef09326
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746273105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es
calation.1746273105
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.2947367374
Short name T719
Test name
Test status
Simulation time 3688431778 ps
CPU time 47.13 seconds
Started Jan 03 01:46:27 PM PST 24
Finished Jan 03 01:47:18 PM PST 24
Peak memory 267632 kb
Host smart-7825913d-c153-4180-a045-d6b42c44cbfd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947367374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.sram_ctrl_max_throughput.2947367374
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.1834531909
Short name T310
Test name
Test status
Simulation time 4613780255 ps
CPU time 159.44 seconds
Started Jan 03 01:46:30 PM PST 24
Finished Jan 03 01:49:15 PM PST 24
Peak memory 211172 kb
Host smart-579892e2-4326-42ed-a2e9-5b581bf1147e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834531909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_mem_partial_access.1834531909
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.626855950
Short name T325
Test name
Test status
Simulation time 66284267502 ps
CPU time 317.11 seconds
Started Jan 03 01:46:31 PM PST 24
Finished Jan 03 01:51:54 PM PST 24
Peak memory 202576 kb
Host smart-718bb32a-7ff2-464a-b326-9054d868a881
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626855950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl
_mem_walk.626855950
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.205438555
Short name T559
Test name
Test status
Simulation time 65469691417 ps
CPU time 1178.63 seconds
Started Jan 03 01:46:26 PM PST 24
Finished Jan 03 02:06:09 PM PST 24
Peak memory 380124 kb
Host smart-320e317e-2c3d-4e79-8ff0-12796fa8f4bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205438555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multip
le_keys.205438555
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.3674447666
Short name T887
Test name
Test status
Simulation time 1012095545 ps
CPU time 14.79 seconds
Started Jan 03 01:46:26 PM PST 24
Finished Jan 03 01:46:44 PM PST 24
Peak memory 202080 kb
Host smart-90d660d7-258e-4918-876a-562cf0c47705
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674447666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
sram_ctrl_partial_access.3674447666
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.488846647
Short name T865
Test name
Test status
Simulation time 132890031900 ps
CPU time 484.41 seconds
Started Jan 03 01:46:29 PM PST 24
Finished Jan 03 01:54:38 PM PST 24
Peak memory 202200 kb
Host smart-79d03f9c-4e6d-43eb-b880-20b7433bb04c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488846647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.sram_ctrl_partial_access_b2b.488846647
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.2510574698
Short name T813
Test name
Test status
Simulation time 1349303809 ps
CPU time 6.07 seconds
Started Jan 03 01:46:28 PM PST 24
Finished Jan 03 01:46:37 PM PST 24
Peak memory 202412 kb
Host smart-12d238b8-163c-46a6-bf62-54acfa7fbce9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510574698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2510574698
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.657625159
Short name T462
Test name
Test status
Simulation time 18029849152 ps
CPU time 351.25 seconds
Started Jan 03 01:46:29 PM PST 24
Finished Jan 03 01:52:23 PM PST 24
Peak memory 355512 kb
Host smart-a9a2c763-cc6c-429e-a732-3e6badc931f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657625159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.657625159
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.1968982194
Short name T893
Test name
Test status
Simulation time 796992270 ps
CPU time 15.11 seconds
Started Jan 03 01:46:27 PM PST 24
Finished Jan 03 01:46:45 PM PST 24
Peak memory 202060 kb
Host smart-464fc581-c618-4ad2-96db-bfdfc0d61e06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968982194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.1968982194
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all.3413097408
Short name T578
Test name
Test status
Simulation time 65248072424 ps
CPU time 1876.83 seconds
Started Jan 03 01:46:32 PM PST 24
Finished Jan 03 02:17:56 PM PST 24
Peak memory 379080 kb
Host smart-a9adab07-1c45-4e62-8868-bffdfe1a4739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413097408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.sram_ctrl_stress_all.3413097408
Directory /workspace/40.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1393412462
Short name T437
Test name
Test status
Simulation time 621338009 ps
CPU time 3991.87 seconds
Started Jan 03 01:46:30 PM PST 24
Finished Jan 03 02:53:08 PM PST 24
Peak memory 693752 kb
Host smart-8e1ec391-ffcf-4a39-b123-0f32fa299186
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1393412462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.1393412462
Directory /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.2736615811
Short name T108
Test name
Test status
Simulation time 5734109995 ps
CPU time 427.07 seconds
Started Jan 03 01:46:26 PM PST 24
Finished Jan 03 01:53:36 PM PST 24
Peak memory 202080 kb
Host smart-6d11845f-4d7d-4b5a-8895-3943d2ff8bc6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736615811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_stress_pipeline.2736615811
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.911792643
Short name T793
Test name
Test status
Simulation time 788788630 ps
CPU time 106.02 seconds
Started Jan 03 01:46:25 PM PST 24
Finished Jan 03 01:48:13 PM PST 24
Peak memory 349316 kb
Host smart-14f5303c-326b-4151-bd33-f374410b1325
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911792643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.sram_ctrl_throughput_w_partial_write.911792643
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.586816740
Short name T20
Test name
Test status
Simulation time 16043125224 ps
CPU time 363.41 seconds
Started Jan 03 01:46:35 PM PST 24
Finished Jan 03 01:52:47 PM PST 24
Peak memory 369776 kb
Host smart-440d8a60-ae82-4c11-aac0-1c6d8fa31f8e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586816740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 41.sram_ctrl_access_during_key_req.586816740
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.2914627966
Short name T360
Test name
Test status
Simulation time 14631636 ps
CPU time 0.67 seconds
Started Jan 03 01:46:33 PM PST 24
Finished Jan 03 01:46:41 PM PST 24
Peak memory 201448 kb
Host smart-e64d6129-c8ac-4a60-bef9-5fd9ea86fdf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914627966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.2914627966
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.1222520085
Short name T453
Test name
Test status
Simulation time 21313569716 ps
CPU time 1424.91 seconds
Started Jan 03 01:46:32 PM PST 24
Finished Jan 03 02:10:25 PM PST 24
Peak memory 202216 kb
Host smart-d36cadd9-1b2a-40ac-aab6-83d6b5525412
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222520085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection
.1222520085
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_executable.1566800301
Short name T926
Test name
Test status
Simulation time 5056830411 ps
CPU time 256.23 seconds
Started Jan 03 01:46:55 PM PST 24
Finished Jan 03 01:51:16 PM PST 24
Peak memory 371188 kb
Host smart-6977b1fa-3153-4b2e-882f-ea3cdb59ef28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566800301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab
le.1566800301
Directory /workspace/41.sram_ctrl_executable/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.3174556050
Short name T944
Test name
Test status
Simulation time 22989076724 ps
CPU time 61.26 seconds
Started Jan 03 01:46:38 PM PST 24
Finished Jan 03 01:47:51 PM PST 24
Peak memory 210392 kb
Host smart-b23cc763-46f9-41fd-bbd9-c6b004e4cd1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174556050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es
calation.3174556050
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.444585075
Short name T731
Test name
Test status
Simulation time 3102607637 ps
CPU time 107.84 seconds
Started Jan 03 01:46:35 PM PST 24
Finished Jan 03 01:48:32 PM PST 24
Peak memory 339256 kb
Host smart-daa0937a-b3f5-4ca0-b8e8-f9c5271516cd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444585075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.sram_ctrl_max_throughput.444585075
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.1855724734
Short name T85
Test name
Test status
Simulation time 974038013 ps
CPU time 78.12 seconds
Started Jan 03 01:47:00 PM PST 24
Finished Jan 03 01:48:26 PM PST 24
Peak memory 211144 kb
Host smart-7cc4593e-003e-4642-813c-17ec1fc7f44e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855724734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_mem_partial_access.1855724734
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.3779942446
Short name T485
Test name
Test status
Simulation time 18720145874 ps
CPU time 159.72 seconds
Started Jan 03 01:46:36 PM PST 24
Finished Jan 03 01:49:26 PM PST 24
Peak memory 202288 kb
Host smart-3d7199c8-9797-420b-b4b0-4dda2da7396e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779942446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr
l_mem_walk.3779942446
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.4142444295
Short name T253
Test name
Test status
Simulation time 15354497743 ps
CPU time 270.87 seconds
Started Jan 03 01:46:32 PM PST 24
Finished Jan 03 01:51:10 PM PST 24
Peak memory 364076 kb
Host smart-95b31054-6964-448c-890d-093b4e1ab025
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142444295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi
ple_keys.4142444295
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.1875862467
Short name T558
Test name
Test status
Simulation time 2588863680 ps
CPU time 12.88 seconds
Started Jan 03 01:46:36 PM PST 24
Finished Jan 03 01:47:00 PM PST 24
Peak memory 202160 kb
Host smart-114eb997-93c5-4f05-b2c8-d00ae241e555
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875862467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
sram_ctrl_partial_access.1875862467
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3847829909
Short name T135
Test name
Test status
Simulation time 118697697666 ps
CPU time 503.71 seconds
Started Jan 03 01:46:36 PM PST 24
Finished Jan 03 01:55:10 PM PST 24
Peak memory 202184 kb
Host smart-389bc195-ede4-4067-82dd-a816c3b9699c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847829909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 41.sram_ctrl_partial_access_b2b.3847829909
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.1486930656
Short name T303
Test name
Test status
Simulation time 4807326561 ps
CPU time 6.09 seconds
Started Jan 03 01:46:38 PM PST 24
Finished Jan 03 01:46:56 PM PST 24
Peak memory 202488 kb
Host smart-a0957fbc-01c2-43fc-a2cf-b52169e50c4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486930656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.1486930656
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.4286053962
Short name T891
Test name
Test status
Simulation time 7756367695 ps
CPU time 497.47 seconds
Started Jan 03 01:46:58 PM PST 24
Finished Jan 03 01:55:23 PM PST 24
Peak memory 379028 kb
Host smart-9dd2f38d-5fe3-423e-a9b5-9dd2e3b5754b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286053962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.4286053962
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.2948151042
Short name T302
Test name
Test status
Simulation time 3081655078 ps
CPU time 27.5 seconds
Started Jan 03 01:46:31 PM PST 24
Finished Jan 03 01:47:05 PM PST 24
Peak memory 202112 kb
Host smart-db2f0e41-4974-4343-8fc5-4ee91ee7b92f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948151042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.2948151042
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.666980708
Short name T626
Test name
Test status
Simulation time 664654062 ps
CPU time 1530.35 seconds
Started Jan 03 01:46:34 PM PST 24
Finished Jan 03 02:12:13 PM PST 24
Peak memory 431928 kb
Host smart-9bd91f8a-083c-49ac-8c9e-ff891ed0da49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=666980708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.666980708
Directory /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3774032966
Short name T416
Test name
Test status
Simulation time 9724970848 ps
CPU time 345.34 seconds
Started Jan 03 01:46:32 PM PST 24
Finished Jan 03 01:52:25 PM PST 24
Peak memory 202244 kb
Host smart-257aa7e3-4424-45a9-9b21-f4cc937f7fad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774032966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_stress_pipeline.3774032966
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2333781012
Short name T249
Test name
Test status
Simulation time 3769611828 ps
CPU time 46.69 seconds
Started Jan 03 01:46:33 PM PST 24
Finished Jan 03 01:47:28 PM PST 24
Peak memory 274096 kb
Host smart-24b54ded-0f6f-4e72-888a-8c8571271332
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333781012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.2333781012
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.1992663837
Short name T87
Test name
Test status
Simulation time 57433507680 ps
CPU time 1651.75 seconds
Started Jan 03 01:46:28 PM PST 24
Finished Jan 03 02:14:04 PM PST 24
Peak memory 379056 kb
Host smart-962df8af-6889-4f08-8a6b-bd324e455bcb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992663837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.sram_ctrl_access_during_key_req.1992663837
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.4009676107
Short name T634
Test name
Test status
Simulation time 14918948 ps
CPU time 0.67 seconds
Started Jan 03 01:46:31 PM PST 24
Finished Jan 03 01:46:39 PM PST 24
Peak memory 201420 kb
Host smart-5911b28c-7f87-4721-908b-a4f90c51a870
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009676107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.4009676107
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.915915090
Short name T748
Test name
Test status
Simulation time 187062106587 ps
CPU time 1478.52 seconds
Started Jan 03 01:46:30 PM PST 24
Finished Jan 03 02:11:14 PM PST 24
Peak memory 202080 kb
Host smart-2ff01741-8244-44a9-bce6-7e084261cbe0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915915090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.
915915090
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_executable.2874247193
Short name T129
Test name
Test status
Simulation time 15994511908 ps
CPU time 918.01 seconds
Started Jan 03 01:46:32 PM PST 24
Finished Jan 03 02:01:58 PM PST 24
Peak memory 368844 kb
Host smart-7928f36a-9c72-49e8-8e76-db8206916fce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874247193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab
le.2874247193
Directory /workspace/42.sram_ctrl_executable/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.287574622
Short name T386
Test name
Test status
Simulation time 2965259422 ps
CPU time 45.54 seconds
Started Jan 03 01:46:29 PM PST 24
Finished Jan 03 01:47:19 PM PST 24
Peak memory 278836 kb
Host smart-6a1ca617-fa2b-45c5-a1f9-de2f6d336e62
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287574622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.sram_ctrl_max_throughput.287574622
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.1241127867
Short name T520
Test name
Test status
Simulation time 1631324369 ps
CPU time 139.76 seconds
Started Jan 03 01:46:30 PM PST 24
Finished Jan 03 01:48:56 PM PST 24
Peak memory 211236 kb
Host smart-ef7b7550-aab3-4a15-a3a3-cce64217dd61
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241127867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_mem_partial_access.1241127867
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.647751536
Short name T886
Test name
Test status
Simulation time 16417343410 ps
CPU time 246.29 seconds
Started Jan 03 01:46:32 PM PST 24
Finished Jan 03 01:50:45 PM PST 24
Peak memory 202336 kb
Host smart-7ece88aa-0933-406e-a946-9d5322e36626
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647751536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl
_mem_walk.647751536
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.307736865
Short name T631
Test name
Test status
Simulation time 38289243278 ps
CPU time 506.76 seconds
Started Jan 03 01:46:30 PM PST 24
Finished Jan 03 01:55:03 PM PST 24
Peak memory 379540 kb
Host smart-145ed338-05b6-4b54-b2eb-103bd0ab9c46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307736865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multip
le_keys.307736865
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.1793365052
Short name T140
Test name
Test status
Simulation time 1051698635 ps
CPU time 25.36 seconds
Started Jan 03 01:46:34 PM PST 24
Finished Jan 03 01:47:09 PM PST 24
Peak memory 202088 kb
Host smart-837b3557-3dd6-4ef8-b341-de8608524f3b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793365052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
sram_ctrl_partial_access.1793365052
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1242281983
Short name T106
Test name
Test status
Simulation time 70269842763 ps
CPU time 465.3 seconds
Started Jan 03 01:46:28 PM PST 24
Finished Jan 03 01:54:17 PM PST 24
Peak memory 202124 kb
Host smart-d4e48e6e-8c9c-43bc-92b1-1c1a49f038d9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242281983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.sram_ctrl_partial_access_b2b.1242281983
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.199143813
Short name T400
Test name
Test status
Simulation time 345899247 ps
CPU time 12.93 seconds
Started Jan 03 01:46:32 PM PST 24
Finished Jan 03 01:46:52 PM PST 24
Peak memory 202424 kb
Host smart-8df9e8ac-9440-45c8-b9fb-edce6c460d6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199143813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.199143813
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.1437761061
Short name T912
Test name
Test status
Simulation time 4447365220 ps
CPU time 451 seconds
Started Jan 03 01:46:33 PM PST 24
Finished Jan 03 01:54:12 PM PST 24
Peak memory 368888 kb
Host smart-ed1de924-e48c-4cb0-9117-785ace929841
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437761061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.1437761061
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.360131198
Short name T884
Test name
Test status
Simulation time 355540963 ps
CPU time 13.96 seconds
Started Jan 03 01:46:27 PM PST 24
Finished Jan 03 01:46:44 PM PST 24
Peak memory 202004 kb
Host smart-2734eaf1-60f5-45a1-bf95-b5b077a0d4d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360131198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.360131198
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2238628524
Short name T31
Test name
Test status
Simulation time 670683898 ps
CPU time 2503.56 seconds
Started Jan 03 01:46:31 PM PST 24
Finished Jan 03 02:28:22 PM PST 24
Peak memory 418232 kb
Host smart-b972fe26-ba82-428f-8f33-02d8a8ec4d26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2238628524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.2238628524
Directory /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.859622077
Short name T468
Test name
Test status
Simulation time 2886083613 ps
CPU time 233.89 seconds
Started Jan 03 01:46:29 PM PST 24
Finished Jan 03 01:50:26 PM PST 24
Peak memory 202100 kb
Host smart-17befa30-1a8f-41cf-8f84-2909d0e8dab1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859622077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.sram_ctrl_stress_pipeline.859622077
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.606068661
Short name T474
Test name
Test status
Simulation time 803033140 ps
CPU time 116.41 seconds
Started Jan 03 01:46:30 PM PST 24
Finished Jan 03 01:48:33 PM PST 24
Peak memory 342288 kb
Host smart-84e615f8-7a1d-4a87-a1e9-ee544e7d6dec
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606068661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.sram_ctrl_throughput_w_partial_write.606068661
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2712865437
Short name T639
Test name
Test status
Simulation time 5890483244 ps
CPU time 265.6 seconds
Started Jan 03 01:46:36 PM PST 24
Finished Jan 03 01:51:11 PM PST 24
Peak memory 353440 kb
Host smart-643d4af2-8463-45e3-92f0-995bc9f6924a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712865437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.sram_ctrl_access_during_key_req.2712865437
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.2307216110
Short name T282
Test name
Test status
Simulation time 27931361 ps
CPU time 0.68 seconds
Started Jan 03 01:46:36 PM PST 24
Finished Jan 03 01:46:46 PM PST 24
Peak memory 201848 kb
Host smart-7ed1aa00-c56c-4ce8-ab79-2f57ac072600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307216110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.2307216110
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.4091590237
Short name T324
Test name
Test status
Simulation time 32281226494 ps
CPU time 2141.81 seconds
Started Jan 03 01:46:32 PM PST 24
Finished Jan 03 02:22:21 PM PST 24
Peak memory 202380 kb
Host smart-501b9daa-87e0-4a4a-99fe-3e5ed4d8dbea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091590237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection
.4091590237
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_lc_escalation.225165574
Short name T435
Test name
Test status
Simulation time 8024751318 ps
CPU time 80.55 seconds
Started Jan 03 01:46:38 PM PST 24
Finished Jan 03 01:48:10 PM PST 24
Peak memory 202116 kb
Host smart-52a8aa1c-aabe-41ba-a7ec-dddc4d0eabb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225165574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_esc
alation.225165574
Directory /workspace/43.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.147727640
Short name T490
Test name
Test status
Simulation time 1509200707 ps
CPU time 59.46 seconds
Started Jan 03 01:46:32 PM PST 24
Finished Jan 03 01:47:40 PM PST 24
Peak memory 293132 kb
Host smart-0b792341-cac8-43f1-9485-4802bad08d85
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147727640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.sram_ctrl_max_throughput.147727640
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.3320303785
Short name T983
Test name
Test status
Simulation time 5171199975 ps
CPU time 146.59 seconds
Started Jan 03 01:46:37 PM PST 24
Finished Jan 03 01:49:15 PM PST 24
Peak memory 214484 kb
Host smart-24aa168a-f17c-4eb6-a432-0679fd8d8613
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320303785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_mem_partial_access.3320303785
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.1598560536
Short name T331
Test name
Test status
Simulation time 7902826175 ps
CPU time 127.92 seconds
Started Jan 03 01:46:54 PM PST 24
Finished Jan 03 01:49:07 PM PST 24
Peak memory 202124 kb
Host smart-ee72047a-b2fa-4ffd-8fb8-b484bd222b95
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598560536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr
l_mem_walk.1598560536
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.90156642
Short name T519
Test name
Test status
Simulation time 7902788285 ps
CPU time 414.51 seconds
Started Jan 03 01:46:34 PM PST 24
Finished Jan 03 01:53:37 PM PST 24
Peak memory 374956 kb
Host smart-b7b737f9-7fd8-418d-928f-a950ff91f17c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90156642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multipl
e_keys.90156642
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.923995527
Short name T661
Test name
Test status
Simulation time 675852867 ps
CPU time 26.72 seconds
Started Jan 03 01:46:31 PM PST 24
Finished Jan 03 01:47:05 PM PST 24
Peak memory 202092 kb
Host smart-6a854c43-202e-4ad4-83da-b896c1707778
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923995527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.s
ram_ctrl_partial_access.923995527
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.676874993
Short name T725
Test name
Test status
Simulation time 23202599998 ps
CPU time 553.04 seconds
Started Jan 03 01:46:34 PM PST 24
Finished Jan 03 01:55:55 PM PST 24
Peak memory 202160 kb
Host smart-8a8eb8d6-bb51-407a-9986-50d7b8e1cc63
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676874993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.sram_ctrl_partial_access_b2b.676874993
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.1274901546
Short name T899
Test name
Test status
Simulation time 695703711 ps
CPU time 6.97 seconds
Started Jan 03 01:46:33 PM PST 24
Finished Jan 03 01:46:48 PM PST 24
Peak memory 202340 kb
Host smart-854e2e5f-f2e9-451d-ac36-cf72d0746422
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274901546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.1274901546
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.3194134401
Short name T718
Test name
Test status
Simulation time 41006004723 ps
CPU time 1376.13 seconds
Started Jan 03 01:46:32 PM PST 24
Finished Jan 03 02:09:37 PM PST 24
Peak memory 380104 kb
Host smart-d8895c3a-69e8-42e2-8fea-fbfed637de7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194134401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.3194134401
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_smoke.1651082590
Short name T322
Test name
Test status
Simulation time 375289553 ps
CPU time 19.22 seconds
Started Jan 03 01:46:32 PM PST 24
Finished Jan 03 01:46:59 PM PST 24
Peak memory 227624 kb
Host smart-ef3bfd38-fbb9-47c0-a6b4-6b34064dc64a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651082590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.1651082590
Directory /workspace/43.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all.2816321446
Short name T662
Test name
Test status
Simulation time 526136441755 ps
CPU time 3937.03 seconds
Started Jan 03 01:46:35 PM PST 24
Finished Jan 03 02:52:22 PM PST 24
Peak memory 382084 kb
Host smart-629b64f9-ee1d-4083-9dd5-6792fc914f0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816321446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.sram_ctrl_stress_all.2816321446
Directory /workspace/43.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1863617593
Short name T820
Test name
Test status
Simulation time 5320773310 ps
CPU time 3041.39 seconds
Started Jan 03 01:46:37 PM PST 24
Finished Jan 03 02:37:29 PM PST 24
Peak memory 698740 kb
Host smart-4d998fb2-6d40-4c1a-adf3-0f2e14037e48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1863617593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.1863617593
Directory /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1061557085
Short name T892
Test name
Test status
Simulation time 2960313130 ps
CPU time 202.1 seconds
Started Jan 03 01:46:35 PM PST 24
Finished Jan 03 01:50:07 PM PST 24
Peak memory 202200 kb
Host smart-c94e38b7-2a4c-470a-ac93-9434a6122203
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061557085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_stress_pipeline.1061557085
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1298189757
Short name T146
Test name
Test status
Simulation time 1149629869 ps
CPU time 50.02 seconds
Started Jan 03 01:46:33 PM PST 24
Finished Jan 03 01:47:32 PM PST 24
Peak memory 275452 kb
Host smart-86707b3e-7b55-4792-b1ec-d565b860d217
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298189757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.1298189757
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.3237628579
Short name T291
Test name
Test status
Simulation time 45735786451 ps
CPU time 1972.05 seconds
Started Jan 03 01:46:36 PM PST 24
Finished Jan 03 02:19:37 PM PST 24
Peak memory 380176 kb
Host smart-e851aefc-ad64-4a34-89ce-f8abb89be97b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237628579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.sram_ctrl_access_during_key_req.3237628579
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.3894479284
Short name T11
Test name
Test status
Simulation time 15270812 ps
CPU time 0.65 seconds
Started Jan 03 01:46:30 PM PST 24
Finished Jan 03 01:46:37 PM PST 24
Peak memory 201880 kb
Host smart-c7b803ef-3871-4d07-82be-8a7c5609476e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894479284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.3894479284
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.160008814
Short name T601
Test name
Test status
Simulation time 303409589281 ps
CPU time 828.46 seconds
Started Jan 03 01:46:35 PM PST 24
Finished Jan 03 02:00:34 PM PST 24
Peak memory 202228 kb
Host smart-9974942e-a9c5-47e8-9661-7c14d5decf0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160008814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.
160008814
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.1516220843
Short name T138
Test name
Test status
Simulation time 18089248398 ps
CPU time 322.8 seconds
Started Jan 03 01:46:37 PM PST 24
Finished Jan 03 01:52:11 PM PST 24
Peak memory 210328 kb
Host smart-b151a78d-5616-4b64-b545-124aa53061fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516220843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es
calation.1516220843
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.2171100829
Short name T968
Test name
Test status
Simulation time 12592162791 ps
CPU time 144.11 seconds
Started Jan 03 01:46:38 PM PST 24
Finished Jan 03 01:49:14 PM PST 24
Peak memory 355704 kb
Host smart-e03e5423-031e-4e1d-beb5-12cd4ffc2435
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171100829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_max_throughput.2171100829
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.818889016
Short name T732
Test name
Test status
Simulation time 1574713635 ps
CPU time 134.83 seconds
Started Jan 03 01:46:38 PM PST 24
Finished Jan 03 01:49:05 PM PST 24
Peak memory 213696 kb
Host smart-5a3d71a4-5001-4f1a-80b5-20e967a43f87
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818889016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.sram_ctrl_mem_partial_access.818889016
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.593401319
Short name T551
Test name
Test status
Simulation time 43080262833 ps
CPU time 160.62 seconds
Started Jan 03 01:46:31 PM PST 24
Finished Jan 03 01:49:19 PM PST 24
Peak memory 202348 kb
Host smart-f0aa1611-17b3-42e2-beda-ff95fd3b9a5d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593401319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl
_mem_walk.593401319
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.3857196423
Short name T236
Test name
Test status
Simulation time 3290444676 ps
CPU time 139.96 seconds
Started Jan 03 01:46:35 PM PST 24
Finished Jan 03 01:49:05 PM PST 24
Peak memory 371884 kb
Host smart-9406a64c-d20d-4a1b-bd68-16fadb22ddae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857196423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi
ple_keys.3857196423
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.3920200777
Short name T478
Test name
Test status
Simulation time 3247201491 ps
CPU time 64.35 seconds
Started Jan 03 01:46:39 PM PST 24
Finished Jan 03 01:47:55 PM PST 24
Peak memory 312472 kb
Host smart-ddcf2faf-bab9-4067-bc17-70b67e6c67e5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920200777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
sram_ctrl_partial_access.3920200777
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3929898658
Short name T136
Test name
Test status
Simulation time 76204421067 ps
CPU time 418.7 seconds
Started Jan 03 01:46:53 PM PST 24
Finished Jan 03 01:53:57 PM PST 24
Peak memory 202116 kb
Host smart-7c161310-5b7d-41a7-a761-9d02ea69c503
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929898658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.sram_ctrl_partial_access_b2b.3929898658
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.258272135
Short name T554
Test name
Test status
Simulation time 481564084 ps
CPU time 5.32 seconds
Started Jan 03 01:46:57 PM PST 24
Finished Jan 03 01:47:08 PM PST 24
Peak memory 202444 kb
Host smart-424b000a-9da9-45eb-a05a-b3142beb1550
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258272135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.258272135
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.1834324869
Short name T133
Test name
Test status
Simulation time 82316669238 ps
CPU time 1243.18 seconds
Started Jan 03 01:46:57 PM PST 24
Finished Jan 03 02:07:47 PM PST 24
Peak memory 380056 kb
Host smart-0ad9d38a-4452-44bc-9c1c-d89a0b9a1a5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834324869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.1834324869
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.1026402248
Short name T713
Test name
Test status
Simulation time 775810939 ps
CPU time 25.34 seconds
Started Jan 03 01:46:36 PM PST 24
Finished Jan 03 01:47:12 PM PST 24
Peak memory 249016 kb
Host smart-8794c20d-b413-4c37-92b0-776830f5ce81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026402248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.1026402248
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all.4236770805
Short name T805
Test name
Test status
Simulation time 25372317131 ps
CPU time 2429.07 seconds
Started Jan 03 01:46:28 PM PST 24
Finished Jan 03 02:27:00 PM PST 24
Peak memory 380072 kb
Host smart-e062a6dd-7d07-4070-ae17-5aa51727bbb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236770805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.sram_ctrl_stress_all.4236770805
Directory /workspace/44.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1708459921
Short name T975
Test name
Test status
Simulation time 1094879962 ps
CPU time 3243.65 seconds
Started Jan 03 01:46:27 PM PST 24
Finished Jan 03 02:40:34 PM PST 24
Peak memory 778212 kb
Host smart-78634536-db4a-4a59-9975-e2fb4254bf9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1708459921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.1708459921
Directory /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3613658259
Short name T769
Test name
Test status
Simulation time 15861642862 ps
CPU time 314.57 seconds
Started Jan 03 01:46:37 PM PST 24
Finished Jan 03 01:52:03 PM PST 24
Peak memory 202076 kb
Host smart-02263347-d504-4112-890d-cc3578460101
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613658259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_stress_pipeline.3613658259
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2548685395
Short name T389
Test name
Test status
Simulation time 785091338 ps
CPU time 72.92 seconds
Started Jan 03 01:46:54 PM PST 24
Finished Jan 03 01:48:12 PM PST 24
Peak memory 322780 kb
Host smart-93122ba6-35a9-4900-9d76-429f94fd8ab5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548685395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.2548685395
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.2533317367
Short name T856
Test name
Test status
Simulation time 2040230994 ps
CPU time 343.33 seconds
Started Jan 03 01:46:33 PM PST 24
Finished Jan 03 01:52:24 PM PST 24
Peak memory 352240 kb
Host smart-7abbf7aa-727f-413d-b05a-8bfe794062c3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533317367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.sram_ctrl_access_during_key_req.2533317367
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.567944776
Short name T592
Test name
Test status
Simulation time 21712773 ps
CPU time 0.66 seconds
Started Jan 03 01:46:36 PM PST 24
Finished Jan 03 01:46:48 PM PST 24
Peak memory 201880 kb
Host smart-f7f21f9b-15e3-4691-b1bf-86f55e3d3ec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567944776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.sram_ctrl_alert_test.567944776
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.3900560508
Short name T870
Test name
Test status
Simulation time 923038766904 ps
CPU time 1230.12 seconds
Started Jan 03 01:46:29 PM PST 24
Finished Jan 03 02:07:04 PM PST 24
Peak memory 210272 kb
Host smart-9157d8ac-5f79-48c2-9716-997b87c4786c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900560508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection
.3900560508
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_executable.816180875
Short name T459
Test name
Test status
Simulation time 19537890713 ps
CPU time 1114.64 seconds
Started Jan 03 01:46:32 PM PST 24
Finished Jan 03 02:05:14 PM PST 24
Peak memory 376020 kb
Host smart-7978c17d-e0cb-4c4e-a74e-dd7eea026467
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816180875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executabl
e.816180875
Directory /workspace/45.sram_ctrl_executable/latest

Test location /workspace/coverage/default/45.sram_ctrl_lc_escalation.2795901030
Short name T499
Test name
Test status
Simulation time 34880071982 ps
CPU time 202 seconds
Started Jan 03 01:46:32 PM PST 24
Finished Jan 03 01:50:02 PM PST 24
Peak memory 210380 kb
Host smart-d1ffe33d-13c3-4bc8-8cdf-04975835c407
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795901030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es
calation.2795901030
Directory /workspace/45.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.2599133709
Short name T643
Test name
Test status
Simulation time 2847615729 ps
CPU time 31.88 seconds
Started Jan 03 01:46:29 PM PST 24
Finished Jan 03 01:47:05 PM PST 24
Peak memory 234932 kb
Host smart-31a535e3-eaa4-4a03-a373-fffcebb72d15
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599133709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_max_throughput.2599133709
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.3938028936
Short name T71
Test name
Test status
Simulation time 3171295275 ps
CPU time 132.57 seconds
Started Jan 03 01:46:33 PM PST 24
Finished Jan 03 01:48:54 PM PST 24
Peak memory 211092 kb
Host smart-23ca78f8-ae0b-4794-994a-95b7ae37c500
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938028936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_mem_partial_access.3938028936
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.3369584616
Short name T726
Test name
Test status
Simulation time 21087772958 ps
CPU time 156.43 seconds
Started Jan 03 01:46:32 PM PST 24
Finished Jan 03 01:49:15 PM PST 24
Peak memory 202228 kb
Host smart-3ab29178-e432-47e2-a8be-eeaebed53f77
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369584616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr
l_mem_walk.3369584616
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.4224910395
Short name T740
Test name
Test status
Simulation time 39971992973 ps
CPU time 522.75 seconds
Started Jan 03 01:46:32 PM PST 24
Finished Jan 03 01:55:22 PM PST 24
Peak memory 339160 kb
Host smart-4de38c2d-8ff3-4b76-a288-5ee60b998a9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224910395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi
ple_keys.4224910395
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.4134317372
Short name T403
Test name
Test status
Simulation time 1285788341 ps
CPU time 13.02 seconds
Started Jan 03 01:46:30 PM PST 24
Finished Jan 03 01:46:49 PM PST 24
Peak memory 202108 kb
Host smart-1fb9bccb-dfde-4494-b9bf-0096b817895d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134317372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
sram_ctrl_partial_access.4134317372
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1984848822
Short name T454
Test name
Test status
Simulation time 19380158069 ps
CPU time 357.77 seconds
Started Jan 03 01:46:35 PM PST 24
Finished Jan 03 01:52:42 PM PST 24
Peak memory 202024 kb
Host smart-1fecb224-564a-4005-b374-f6272f6b08b2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984848822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.sram_ctrl_partial_access_b2b.1984848822
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.2640987096
Short name T817
Test name
Test status
Simulation time 369721236 ps
CPU time 13.23 seconds
Started Jan 03 01:46:36 PM PST 24
Finished Jan 03 01:47:00 PM PST 24
Peak memory 202428 kb
Host smart-5fccad68-73ca-4ff5-82b3-8dc5234b9e52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640987096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.2640987096
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.439659625
Short name T921
Test name
Test status
Simulation time 22540982800 ps
CPU time 209.21 seconds
Started Jan 03 01:46:32 PM PST 24
Finished Jan 03 01:50:08 PM PST 24
Peak memory 315588 kb
Host smart-81a6c02e-3a2e-4c73-96dd-2a55d7886aa9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439659625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.439659625
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.1515977267
Short name T546
Test name
Test status
Simulation time 3134266917 ps
CPU time 65.01 seconds
Started Jan 03 01:46:34 PM PST 24
Finished Jan 03 01:47:49 PM PST 24
Peak memory 326236 kb
Host smart-8967aabc-c5a1-4ff0-894a-aed6f72889c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515977267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.1515977267
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3641807694
Short name T857
Test name
Test status
Simulation time 313035424 ps
CPU time 2497.93 seconds
Started Jan 03 01:46:31 PM PST 24
Finished Jan 03 02:28:16 PM PST 24
Peak memory 466708 kb
Host smart-4f95ded8-cbc1-4f15-8a15-d60bc47987ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3641807694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.3641807694
Directory /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.129071488
Short name T357
Test name
Test status
Simulation time 6724153670 ps
CPU time 252.95 seconds
Started Jan 03 01:46:30 PM PST 24
Finished Jan 03 01:50:50 PM PST 24
Peak memory 202100 kb
Host smart-385ed06b-0e5a-48cc-badf-07f178b232da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129071488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.sram_ctrl_stress_pipeline.129071488
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2514803670
Short name T455
Test name
Test status
Simulation time 744634230 ps
CPU time 44.99 seconds
Started Jan 03 01:46:30 PM PST 24
Finished Jan 03 01:47:20 PM PST 24
Peak memory 258164 kb
Host smart-4491be89-7aaa-4d84-a794-b3f796b4e2e4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514803670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.2514803670
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.3391342531
Short name T320
Test name
Test status
Simulation time 7915475105 ps
CPU time 712.31 seconds
Started Jan 03 01:46:36 PM PST 24
Finished Jan 03 01:58:39 PM PST 24
Peak memory 378872 kb
Host smart-35546540-2b17-4868-b932-7d31abc6884e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391342531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.sram_ctrl_access_during_key_req.3391342531
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.3917543214
Short name T940
Test name
Test status
Simulation time 20248678 ps
CPU time 0.66 seconds
Started Jan 03 01:46:56 PM PST 24
Finished Jan 03 01:47:03 PM PST 24
Peak memory 201896 kb
Host smart-32ec6dfb-a3a4-493a-af95-1d919d4dda2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917543214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.3917543214
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.3798980020
Short name T143
Test name
Test status
Simulation time 27585275258 ps
CPU time 1816.59 seconds
Started Jan 03 01:46:33 PM PST 24
Finished Jan 03 02:16:58 PM PST 24
Peak memory 202100 kb
Host smart-8a866a1b-37da-4100-b59b-cb6e1d2e6109
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798980020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection
.3798980020
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.1178939928
Short name T415
Test name
Test status
Simulation time 23896649464 ps
CPU time 65.86 seconds
Started Jan 03 01:46:35 PM PST 24
Finished Jan 03 01:47:51 PM PST 24
Peak memory 210396 kb
Host smart-30a66b29-19de-42c9-b4b3-08afd673d9ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178939928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es
calation.1178939928
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.497532274
Short name T649
Test name
Test status
Simulation time 2843534354 ps
CPU time 49.67 seconds
Started Jan 03 01:46:57 PM PST 24
Finished Jan 03 01:47:52 PM PST 24
Peak memory 277852 kb
Host smart-0b643bb7-d7b3-49e3-93fb-89e3c76935c9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497532274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.sram_ctrl_max_throughput.497532274
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.2306340413
Short name T563
Test name
Test status
Simulation time 10374072993 ps
CPU time 151.09 seconds
Started Jan 03 01:46:36 PM PST 24
Finished Jan 03 01:49:16 PM PST 24
Peak memory 211176 kb
Host smart-e046245a-2611-47f8-8a79-ce6958d724c5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306340413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_mem_partial_access.2306340413
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.1218764762
Short name T262
Test name
Test status
Simulation time 14338471666 ps
CPU time 282.05 seconds
Started Jan 03 01:46:35 PM PST 24
Finished Jan 03 01:51:26 PM PST 24
Peak memory 202124 kb
Host smart-9cd62635-2e27-4315-b3bc-7b47f0f3bc82
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218764762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr
l_mem_walk.1218764762
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.2157045265
Short name T381
Test name
Test status
Simulation time 32400641191 ps
CPU time 1022.56 seconds
Started Jan 03 01:46:34 PM PST 24
Finished Jan 03 02:03:45 PM PST 24
Peak memory 371400 kb
Host smart-708a0fa2-836a-4b42-8bdb-c9aba765f684
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157045265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi
ple_keys.2157045265
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.1641263213
Short name T641
Test name
Test status
Simulation time 863114758 ps
CPU time 113.27 seconds
Started Jan 03 01:46:37 PM PST 24
Finished Jan 03 01:48:42 PM PST 24
Peak memory 329028 kb
Host smart-1be9e3ff-7cc8-4e57-b0d0-bb44f1102927
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641263213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
sram_ctrl_partial_access.1641263213
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1956961173
Short name T317
Test name
Test status
Simulation time 6366119013 ps
CPU time 405.63 seconds
Started Jan 03 01:46:35 PM PST 24
Finished Jan 03 01:53:30 PM PST 24
Peak memory 202156 kb
Host smart-2dc02ce8-4b6b-4e5b-80b0-46b92c826740
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956961173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_partial_access_b2b.1956961173
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.3122286212
Short name T560
Test name
Test status
Simulation time 696018048 ps
CPU time 12.19 seconds
Started Jan 03 01:46:54 PM PST 24
Finished Jan 03 01:47:11 PM PST 24
Peak memory 202448 kb
Host smart-9351dad9-3585-4a9f-8136-8683d65f306a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122286212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.3122286212
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.821270018
Short name T839
Test name
Test status
Simulation time 12160909703 ps
CPU time 336.38 seconds
Started Jan 03 01:46:58 PM PST 24
Finished Jan 03 01:52:43 PM PST 24
Peak memory 368408 kb
Host smart-386875c5-ec78-48b9-83bf-69b9f88e8f41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821270018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.821270018
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.2899043071
Short name T905
Test name
Test status
Simulation time 3707667512 ps
CPU time 28.61 seconds
Started Jan 03 01:46:33 PM PST 24
Finished Jan 03 01:47:11 PM PST 24
Peak memory 254968 kb
Host smart-9749d804-9e8c-4484-aca3-eb3592f4bf28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899043071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.2899043071
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all.1267502698
Short name T829
Test name
Test status
Simulation time 81335328166 ps
CPU time 2449.17 seconds
Started Jan 03 01:46:58 PM PST 24
Finished Jan 03 02:27:54 PM PST 24
Peak memory 371604 kb
Host smart-b84cae06-116d-428a-8b77-8c24cc221056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267502698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.sram_ctrl_stress_all.1267502698
Directory /workspace/46.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3670457808
Short name T977
Test name
Test status
Simulation time 2343869386 ps
CPU time 4103.1 seconds
Started Jan 03 01:46:39 PM PST 24
Finished Jan 03 02:55:14 PM PST 24
Peak memory 418048 kb
Host smart-bc0fb085-503d-4bf6-b123-4aacfb087699
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3670457808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.3670457808
Directory /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1864955986
Short name T299
Test name
Test status
Simulation time 7329071007 ps
CPU time 266.18 seconds
Started Jan 03 01:46:38 PM PST 24
Finished Jan 03 01:51:16 PM PST 24
Peak memory 202112 kb
Host smart-8b808fea-3d1e-4803-bd6b-ba3c787fd82a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864955986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_stress_pipeline.1864955986
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2604339198
Short name T375
Test name
Test status
Simulation time 756235669 ps
CPU time 85.17 seconds
Started Jan 03 01:46:32 PM PST 24
Finished Jan 03 01:48:06 PM PST 24
Peak memory 326900 kb
Host smart-647ddcca-1b35-4118-a732-4bb29b8b3d48
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604339198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.2604339198
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.533387805
Short name T367
Test name
Test status
Simulation time 24668902626 ps
CPU time 1020.58 seconds
Started Jan 03 01:46:57 PM PST 24
Finished Jan 03 02:04:04 PM PST 24
Peak memory 361700 kb
Host smart-2014995c-04ba-4a2e-aeba-b5d5ed57142f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533387805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 47.sram_ctrl_access_during_key_req.533387805
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.425560971
Short name T812
Test name
Test status
Simulation time 20969016 ps
CPU time 0.63 seconds
Started Jan 03 01:46:58 PM PST 24
Finished Jan 03 01:47:07 PM PST 24
Peak memory 201444 kb
Host smart-c6f98b47-d980-44bb-8061-037df1471af7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425560971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.425560971
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.2167208562
Short name T841
Test name
Test status
Simulation time 25715267129 ps
CPU time 680.44 seconds
Started Jan 03 01:46:56 PM PST 24
Finished Jan 03 01:58:22 PM PST 24
Peak memory 202252 kb
Host smart-ab4b7b1f-5caa-47f2-9741-e96e3df8a9d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167208562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection
.2167208562
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_executable.3349627453
Short name T467
Test name
Test status
Simulation time 3570475488 ps
CPU time 138.59 seconds
Started Jan 03 01:46:54 PM PST 24
Finished Jan 03 01:49:18 PM PST 24
Peak memory 337108 kb
Host smart-b0bf3de1-9351-4c93-816a-0b6f0c81e138
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349627453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab
le.3349627453
Directory /workspace/47.sram_ctrl_executable/latest

Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.3909336537
Short name T524
Test name
Test status
Simulation time 52072217439 ps
CPU time 138.55 seconds
Started Jan 03 01:46:58 PM PST 24
Finished Jan 03 01:49:25 PM PST 24
Peak memory 210416 kb
Host smart-db64cef8-e535-4d05-ad6a-8e3d49e913d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909336537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es
calation.3909336537
Directory /workspace/47.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.3503116098
Short name T502
Test name
Test status
Simulation time 749907513 ps
CPU time 61.48 seconds
Started Jan 03 01:47:00 PM PST 24
Finished Jan 03 01:48:10 PM PST 24
Peak memory 287996 kb
Host smart-27bba441-0215-4a07-984b-2cf56647192f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503116098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_max_throughput.3503116098
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3488994473
Short name T761
Test name
Test status
Simulation time 3939445498 ps
CPU time 74.64 seconds
Started Jan 03 01:46:59 PM PST 24
Finished Jan 03 01:48:21 PM PST 24
Peak memory 211316 kb
Host smart-ee439bd8-895b-4b45-a081-def01054d432
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488994473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_mem_partial_access.3488994473
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.812961872
Short name T964
Test name
Test status
Simulation time 17955428675 ps
CPU time 131.96 seconds
Started Jan 03 01:46:55 PM PST 24
Finished Jan 03 01:49:13 PM PST 24
Peak memory 202320 kb
Host smart-69ac5073-78c2-431e-b7d1-f2959ba887d3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812961872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl
_mem_walk.812961872
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.3184052239
Short name T284
Test name
Test status
Simulation time 35502834053 ps
CPU time 1108.37 seconds
Started Jan 03 01:46:54 PM PST 24
Finished Jan 03 02:05:28 PM PST 24
Peak memory 376668 kb
Host smart-149d791f-fede-43cd-b89e-a0b81c7a7edc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184052239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi
ple_keys.3184052239
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.738824633
Short name T251
Test name
Test status
Simulation time 3757329040 ps
CPU time 44.65 seconds
Started Jan 03 01:46:59 PM PST 24
Finished Jan 03 01:47:52 PM PST 24
Peak memory 202172 kb
Host smart-7c32be71-8ea3-4df9-ab8f-3a3de087c1d6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738824633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.s
ram_ctrl_partial_access.738824633
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.644414331
Short name T589
Test name
Test status
Simulation time 67334783300 ps
CPU time 385.35 seconds
Started Jan 03 01:46:57 PM PST 24
Finished Jan 03 01:53:28 PM PST 24
Peak memory 202196 kb
Host smart-e7f4dffc-7be5-477d-9665-5f32c9c2a133
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644414331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.sram_ctrl_partial_access_b2b.644414331
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.4114073089
Short name T602
Test name
Test status
Simulation time 4802198520 ps
CPU time 14.19 seconds
Started Jan 03 01:46:59 PM PST 24
Finished Jan 03 01:47:21 PM PST 24
Peak memory 202464 kb
Host smart-f2ab1617-b747-4e27-afbf-420d11f6c195
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114073089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.4114073089
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.687049416
Short name T855
Test name
Test status
Simulation time 34377754029 ps
CPU time 507.18 seconds
Started Jan 03 01:46:57 PM PST 24
Finished Jan 03 01:55:30 PM PST 24
Peak memory 377808 kb
Host smart-4c7fd251-a008-4cdf-931e-e061a1bfc981
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687049416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.687049416
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.3464282795
Short name T616
Test name
Test status
Simulation time 8409435966 ps
CPU time 14.52 seconds
Started Jan 03 01:46:33 PM PST 24
Finished Jan 03 01:46:57 PM PST 24
Peak memory 202120 kb
Host smart-4ecd6537-4c9b-4c00-8b49-fb52a19f3252
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464282795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.3464282795
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3135852101
Short name T470
Test name
Test status
Simulation time 303859975 ps
CPU time 2061.88 seconds
Started Jan 03 01:46:54 PM PST 24
Finished Jan 03 02:21:21 PM PST 24
Peak memory 431952 kb
Host smart-a312706d-5786-474b-8ac1-68151da40496
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3135852101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.3135852101
Directory /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2931423302
Short name T423
Test name
Test status
Simulation time 16505817591 ps
CPU time 340.09 seconds
Started Jan 03 01:46:57 PM PST 24
Finished Jan 03 01:52:43 PM PST 24
Peak memory 202152 kb
Host smart-de469d50-361c-4df2-a38d-34c7182bc59f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931423302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_stress_pipeline.2931423302
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.901589572
Short name T750
Test name
Test status
Simulation time 701154644 ps
CPU time 27.38 seconds
Started Jan 03 01:46:58 PM PST 24
Finished Jan 03 01:47:33 PM PST 24
Peak memory 210352 kb
Host smart-b11738b5-62df-4c61-9033-17be143df970
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901589572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_throughput_w_partial_write.901589572
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1833701955
Short name T289
Test name
Test status
Simulation time 7103482492 ps
CPU time 1776.08 seconds
Started Jan 03 01:46:55 PM PST 24
Finished Jan 03 02:16:36 PM PST 24
Peak memory 378116 kb
Host smart-91c569a0-7fde-4e01-88e1-783703e07b0b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833701955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.sram_ctrl_access_during_key_req.1833701955
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.2428520832
Short name T948
Test name
Test status
Simulation time 60548305 ps
CPU time 0.68 seconds
Started Jan 03 01:46:58 PM PST 24
Finished Jan 03 01:47:07 PM PST 24
Peak memory 201904 kb
Host smart-2792c124-9564-4efc-89cc-a82c5819a7d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428520832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.2428520832
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.246837763
Short name T613
Test name
Test status
Simulation time 402998841800 ps
CPU time 2177.55 seconds
Started Jan 03 01:46:58 PM PST 24
Finished Jan 03 02:23:23 PM PST 24
Peak memory 202076 kb
Host smart-5ff7847b-569b-4b4b-b245-fcd541be4e44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246837763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.
246837763
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.4187725372
Short name T771
Test name
Test status
Simulation time 31334235557 ps
CPU time 86.42 seconds
Started Jan 03 01:46:57 PM PST 24
Finished Jan 03 01:48:29 PM PST 24
Peak memory 210408 kb
Host smart-095a01ca-dfb2-4222-a10e-65b7c20ec82a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187725372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es
calation.4187725372
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.878683623
Short name T350
Test name
Test status
Simulation time 2955279066 ps
CPU time 45.63 seconds
Started Jan 03 01:46:56 PM PST 24
Finished Jan 03 01:47:48 PM PST 24
Peak memory 271776 kb
Host smart-0d9872c6-88e8-4abc-9362-c710cfb29629
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878683623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.sram_ctrl_max_throughput.878683623
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3421589072
Short name T480
Test name
Test status
Simulation time 991368687 ps
CPU time 73.24 seconds
Started Jan 03 01:46:56 PM PST 24
Finished Jan 03 01:48:15 PM PST 24
Peak memory 210484 kb
Host smart-db43f38b-27e0-44e3-a3be-4e99e8384c94
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421589072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_mem_partial_access.3421589072
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.4238603079
Short name T492
Test name
Test status
Simulation time 4023908736 ps
CPU time 242.24 seconds
Started Jan 03 01:46:55 PM PST 24
Finished Jan 03 01:51:03 PM PST 24
Peak memory 202160 kb
Host smart-16efaabf-1de5-4994-837b-eb9db7e97d47
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238603079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr
l_mem_walk.4238603079
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.1946759790
Short name T419
Test name
Test status
Simulation time 8136473140 ps
CPU time 854.63 seconds
Started Jan 03 01:46:58 PM PST 24
Finished Jan 03 02:01:21 PM PST 24
Peak memory 381260 kb
Host smart-0c5c3d99-99fa-4aa8-97f1-773095b0d8e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946759790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi
ple_keys.1946759790
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.2248494187
Short name T920
Test name
Test status
Simulation time 1355287700 ps
CPU time 13.65 seconds
Started Jan 03 01:46:57 PM PST 24
Finished Jan 03 01:47:16 PM PST 24
Peak memory 202112 kb
Host smart-e9851ae2-01de-459a-bdf0-32470563b73f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248494187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
sram_ctrl_partial_access.2248494187
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1024072409
Short name T369
Test name
Test status
Simulation time 15131735933 ps
CPU time 418.77 seconds
Started Jan 03 01:46:54 PM PST 24
Finished Jan 03 01:53:58 PM PST 24
Peak memory 202116 kb
Host smart-a4abc1d0-66c4-42e6-acae-b4d60991e03b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024072409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.sram_ctrl_partial_access_b2b.1024072409
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.2866494768
Short name T978
Test name
Test status
Simulation time 1348730840 ps
CPU time 13.03 seconds
Started Jan 03 01:46:58 PM PST 24
Finished Jan 03 01:47:17 PM PST 24
Peak memory 202448 kb
Host smart-28e62a7f-0be2-4563-a8ce-6c7408f9c5ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866494768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2866494768
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.1932549808
Short name T837
Test name
Test status
Simulation time 38873396765 ps
CPU time 869.02 seconds
Started Jan 03 01:46:59 PM PST 24
Finished Jan 03 02:01:36 PM PST 24
Peak memory 377032 kb
Host smart-97bc5a59-dcf2-4714-aebe-45030769028e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932549808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.1932549808
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.3387247304
Short name T259
Test name
Test status
Simulation time 5483479860 ps
CPU time 156.09 seconds
Started Jan 03 01:46:55 PM PST 24
Finished Jan 03 01:49:37 PM PST 24
Peak memory 369888 kb
Host smart-5eb0597e-80eb-492e-bacc-053aae846fef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387247304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.3387247304
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2347427857
Short name T825
Test name
Test status
Simulation time 14539979446 ps
CPU time 4020.56 seconds
Started Jan 03 01:46:58 PM PST 24
Finished Jan 03 02:54:07 PM PST 24
Peak memory 697904 kb
Host smart-0ec6c0e3-a7bf-40a4-8c3e-b84a7c8acbec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2347427857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.2347427857
Directory /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.941733837
Short name T536
Test name
Test status
Simulation time 82895379374 ps
CPU time 443.99 seconds
Started Jan 03 01:46:58 PM PST 24
Finished Jan 03 01:54:29 PM PST 24
Peak memory 202172 kb
Host smart-81be4b28-96df-4cff-8e9e-413bdbd41784
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941733837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.sram_ctrl_stress_pipeline.941733837
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.792656379
Short name T739
Test name
Test status
Simulation time 833610175 ps
CPU time 134.79 seconds
Started Jan 03 01:46:55 PM PST 24
Finished Jan 03 01:49:15 PM PST 24
Peak memory 366748 kb
Host smart-4f6c99c7-7e95-4e71-a558-e37d78f2193f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792656379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_throughput_w_partial_write.792656379
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2138802398
Short name T290
Test name
Test status
Simulation time 9971197029 ps
CPU time 472.17 seconds
Started Jan 03 01:46:59 PM PST 24
Finished Jan 03 01:54:59 PM PST 24
Peak memory 363748 kb
Host smart-7f762925-3edf-486f-ae1b-80950b634dcf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138802398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.sram_ctrl_access_during_key_req.2138802398
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.70856187
Short name T846
Test name
Test status
Simulation time 14585605 ps
CPU time 0.64 seconds
Started Jan 03 01:46:58 PM PST 24
Finished Jan 03 01:47:07 PM PST 24
Peak memory 201856 kb
Host smart-f5d321c5-d953-485d-841d-8f765ce8c4ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70856187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_alert_test.70856187
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.234615957
Short name T567
Test name
Test status
Simulation time 239792697946 ps
CPU time 1451.35 seconds
Started Jan 03 01:46:58 PM PST 24
Finished Jan 03 02:11:17 PM PST 24
Peak memory 202292 kb
Host smart-be14d9d7-f78d-44d2-94b6-eabf74ae97dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234615957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.
234615957
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.4138635303
Short name T456
Test name
Test status
Simulation time 750768642 ps
CPU time 70.66 seconds
Started Jan 03 01:46:55 PM PST 24
Finished Jan 03 01:48:11 PM PST 24
Peak memory 303332 kb
Host smart-99a4b326-d5ed-4ce0-8a5b-78e4b1ee2ac2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138635303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sram_ctrl_max_throughput.4138635303
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.3833223201
Short name T326
Test name
Test status
Simulation time 69914967290 ps
CPU time 156.22 seconds
Started Jan 03 01:46:57 PM PST 24
Finished Jan 03 01:49:39 PM PST 24
Peak memory 211396 kb
Host smart-fc88cbfa-233d-4913-8cc8-47ca4e77d238
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833223201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_mem_partial_access.3833223201
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.4097620835
Short name T911
Test name
Test status
Simulation time 13524523250 ps
CPU time 148.27 seconds
Started Jan 03 01:46:58 PM PST 24
Finished Jan 03 01:49:34 PM PST 24
Peak memory 202152 kb
Host smart-24404fc3-be50-42eb-ac90-d30ea67ef239
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097620835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr
l_mem_walk.4097620835
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.38551576
Short name T534
Test name
Test status
Simulation time 37312872395 ps
CPU time 1053.91 seconds
Started Jan 03 01:46:57 PM PST 24
Finished Jan 03 02:04:38 PM PST 24
Peak memory 372240 kb
Host smart-1ffcd656-c324-4ca2-9e3a-a2cbfcdf5fcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38551576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multipl
e_keys.38551576
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.3548371181
Short name T691
Test name
Test status
Simulation time 3800391627 ps
CPU time 169.69 seconds
Started Jan 03 01:46:56 PM PST 24
Finished Jan 03 01:49:52 PM PST 24
Peak memory 369864 kb
Host smart-13937a0c-5876-4f49-833d-bf180241e84c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548371181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
sram_ctrl_partial_access.3548371181
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.11471344
Short name T901
Test name
Test status
Simulation time 14558143779 ps
CPU time 434.6 seconds
Started Jan 03 01:46:55 PM PST 24
Finished Jan 03 01:54:15 PM PST 24
Peak memory 202156 kb
Host smart-cd80401f-8217-4d7b-b206-24a4d039362c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11471344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.sram_ctrl_partial_access_b2b.11471344
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.866330097
Short name T770
Test name
Test status
Simulation time 1307958699 ps
CPU time 6.61 seconds
Started Jan 03 01:46:58 PM PST 24
Finished Jan 03 01:47:12 PM PST 24
Peak memory 202336 kb
Host smart-652fc9f9-9733-41f0-8b10-3bf547fb8318
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866330097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.866330097
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.3369913912
Short name T45
Test name
Test status
Simulation time 71648977405 ps
CPU time 814.71 seconds
Started Jan 03 01:46:59 PM PST 24
Finished Jan 03 02:00:41 PM PST 24
Peak memory 370948 kb
Host smart-20b7d01e-8c38-446d-a41f-0192f5077061
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369913912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.3369913912
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.752608168
Short name T885
Test name
Test status
Simulation time 2994082443 ps
CPU time 54.83 seconds
Started Jan 03 01:46:58 PM PST 24
Finished Jan 03 01:47:59 PM PST 24
Peak memory 284916 kb
Host smart-caf9c1ee-5111-4b32-8ec1-4f2c11fbc961
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752608168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.752608168
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all.3233108731
Short name T878
Test name
Test status
Simulation time 20776759916 ps
CPU time 2770.06 seconds
Started Jan 03 01:46:58 PM PST 24
Finished Jan 03 02:33:15 PM PST 24
Peak memory 380180 kb
Host smart-fe2cd79d-3e8b-47af-8527-3d31c8ffc996
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233108731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.sram_ctrl_stress_all.3233108731
Directory /workspace/49.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.362360899
Short name T701
Test name
Test status
Simulation time 71495068 ps
CPU time 3361.03 seconds
Started Jan 03 01:46:57 PM PST 24
Finished Jan 03 02:43:04 PM PST 24
Peak memory 772808 kb
Host smart-384d23cf-65e2-44cb-a84c-c083e6937065
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=362360899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.362360899
Directory /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2709946866
Short name T352
Test name
Test status
Simulation time 3089111378 ps
CPU time 227.15 seconds
Started Jan 03 01:46:54 PM PST 24
Finished Jan 03 01:50:46 PM PST 24
Peak memory 202228 kb
Host smart-0d47a3ac-e5ac-467b-ab1b-795c0ee7c3b5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709946866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_stress_pipeline.2709946866
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3650508472
Short name T853
Test name
Test status
Simulation time 1521638206 ps
CPU time 81.6 seconds
Started Jan 03 01:46:59 PM PST 24
Finished Jan 03 01:48:29 PM PST 24
Peak memory 313628 kb
Host smart-1398a747-ae52-4e3f-b7c5-16074281e76a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650508472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.3650508472
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.4005448888
Short name T644
Test name
Test status
Simulation time 15284942690 ps
CPU time 1610.58 seconds
Started Jan 03 01:41:39 PM PST 24
Finished Jan 03 02:08:33 PM PST 24
Peak memory 380212 kb
Host smart-3913523a-f105-4f5a-b498-392a9ff51616
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005448888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_access_during_key_req.4005448888
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.781021549
Short name T780
Test name
Test status
Simulation time 21668882 ps
CPU time 0.67 seconds
Started Jan 03 01:41:35 PM PST 24
Finished Jan 03 01:41:41 PM PST 24
Peak memory 201448 kb
Host smart-c01ba561-c960-4e24-849e-33c7198bfdc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781021549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_alert_test.781021549
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.721818719
Short name T624
Test name
Test status
Simulation time 8206733244 ps
CPU time 572.12 seconds
Started Jan 03 01:41:30 PM PST 24
Finished Jan 03 01:51:06 PM PST 24
Peak memory 202164 kb
Host smart-accd41e3-5ccb-406f-8ecf-33fcb0ea0c9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721818719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.721818719
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_executable.881610133
Short name T684
Test name
Test status
Simulation time 3436829827 ps
CPU time 635.72 seconds
Started Jan 03 01:40:48 PM PST 24
Finished Jan 03 01:51:30 PM PST 24
Peak memory 370860 kb
Host smart-1f3383c4-c03d-42b3-a2bf-963abcc4ccee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881610133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable
.881610133
Directory /workspace/5.sram_ctrl_executable/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.3239139486
Short name T230
Test name
Test status
Simulation time 3890911294 ps
CPU time 115.3 seconds
Started Jan 03 01:40:48 PM PST 24
Finished Jan 03 01:42:49 PM PST 24
Peak memory 332144 kb
Host smart-577a5c04-30d5-4084-ac3d-b80ad2b18e0d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239139486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_max_throughput.3239139486
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3598799205
Short name T629
Test name
Test status
Simulation time 13421358584 ps
CPU time 79.61 seconds
Started Jan 03 01:41:47 PM PST 24
Finished Jan 03 01:43:18 PM PST 24
Peak memory 211468 kb
Host smart-e7a395a4-564c-489e-a670-0f806423c36e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598799205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.3598799205
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.502800679
Short name T659
Test name
Test status
Simulation time 8041495633 ps
CPU time 252.08 seconds
Started Jan 03 01:40:53 PM PST 24
Finished Jan 03 01:45:09 PM PST 24
Peak memory 202092 kb
Host smart-e8d74488-0064-4043-b10d-547ce1098195
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502800679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_
mem_walk.502800679
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.1432873574
Short name T269
Test name
Test status
Simulation time 20025376107 ps
CPU time 1075.38 seconds
Started Jan 03 01:40:48 PM PST 24
Finished Jan 03 01:58:50 PM PST 24
Peak memory 371016 kb
Host smart-58c5e349-cfe8-41a9-ac81-fc2d1e262a83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432873574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip
le_keys.1432873574
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.1979890937
Short name T14
Test name
Test status
Simulation time 1380117375 ps
CPU time 23.74 seconds
Started Jan 03 01:41:10 PM PST 24
Finished Jan 03 01:41:39 PM PST 24
Peak memory 202032 kb
Host smart-f7404a5e-7f3d-476f-976a-0c3dc358ef65
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979890937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s
ram_ctrl_partial_access.1979890937
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3004517733
Short name T510
Test name
Test status
Simulation time 29923752153 ps
CPU time 449.32 seconds
Started Jan 03 01:41:34 PM PST 24
Finished Jan 03 01:49:09 PM PST 24
Peak memory 202104 kb
Host smart-9f242701-8f57-46d9-b211-59ecc56884fb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004517733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.sram_ctrl_partial_access_b2b.3004517733
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.1548362380
Short name T252
Test name
Test status
Simulation time 4823040250 ps
CPU time 5.35 seconds
Started Jan 03 01:40:50 PM PST 24
Finished Jan 03 01:41:01 PM PST 24
Peak memory 202428 kb
Host smart-6efe8317-0044-4531-8033-0b17bac38849
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548362380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.1548362380
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.76016233
Short name T368
Test name
Test status
Simulation time 7534199933 ps
CPU time 665.22 seconds
Started Jan 03 01:40:55 PM PST 24
Finished Jan 03 01:52:03 PM PST 24
Peak memory 369888 kb
Host smart-bc547780-56c2-49f7-b079-e669d8d93522
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76016233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.76016233
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.1234773967
Short name T611
Test name
Test status
Simulation time 830002505 ps
CPU time 75.71 seconds
Started Jan 03 01:40:46 PM PST 24
Finished Jan 03 01:42:07 PM PST 24
Peak memory 330848 kb
Host smart-d1a984b3-10fd-4f9d-ad42-23947ed6c939
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234773967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.1234773967
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all.2770977118
Short name T109
Test name
Test status
Simulation time 1136615332978 ps
CPU time 6371.31 seconds
Started Jan 03 01:40:54 PM PST 24
Finished Jan 03 03:27:09 PM PST 24
Peak memory 379116 kb
Host smart-83faf16c-1f81-4640-9984-174be334a141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770977118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.sram_ctrl_stress_all.2770977118
Directory /workspace/5.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3872675701
Short name T250
Test name
Test status
Simulation time 12283919755 ps
CPU time 4584.43 seconds
Started Jan 03 01:40:51 PM PST 24
Finished Jan 03 02:57:21 PM PST 24
Peak memory 729084 kb
Host smart-7253e081-0bbd-4e71-924c-c5526de68d6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3872675701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.3872675701
Directory /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.2875821309
Short name T105
Test name
Test status
Simulation time 5793807499 ps
CPU time 454.78 seconds
Started Jan 03 01:41:12 PM PST 24
Finished Jan 03 01:48:51 PM PST 24
Peak memory 202152 kb
Host smart-13c7e44c-213d-445d-b876-5544a533dba6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875821309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_stress_pipeline.2875821309
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3609535518
Short name T5
Test name
Test status
Simulation time 3208484092 ps
CPU time 118.05 seconds
Started Jan 03 01:40:48 PM PST 24
Finished Jan 03 01:42:53 PM PST 24
Peak memory 349384 kb
Host smart-740d0b61-285a-4ed5-8a24-da5ef5b02c80
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609535518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.3609535518
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.1549443025
Short name T689
Test name
Test status
Simulation time 45901324959 ps
CPU time 883.52 seconds
Started Jan 03 01:40:52 PM PST 24
Finished Jan 03 01:55:40 PM PST 24
Peak memory 338068 kb
Host smart-6456baf6-2104-46ae-9a28-89fbc626d170
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549443025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_access_during_key_req.1549443025
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.2721083437
Short name T781
Test name
Test status
Simulation time 55449294 ps
CPU time 0.65 seconds
Started Jan 03 01:40:16 PM PST 24
Finished Jan 03 01:40:26 PM PST 24
Peak memory 201800 kb
Host smart-acb7e109-d119-4228-8b30-2600bea46fe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721083437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.2721083437
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.4107724138
Short name T298
Test name
Test status
Simulation time 163212931828 ps
CPU time 1770.39 seconds
Started Jan 03 01:40:53 PM PST 24
Finished Jan 03 02:10:28 PM PST 24
Peak memory 202172 kb
Host smart-27871e57-65ee-4548-b106-5de8e3276de7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107724138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.
4107724138
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_executable.944786660
Short name T697
Test name
Test status
Simulation time 39648805337 ps
CPU time 217.19 seconds
Started Jan 03 01:40:19 PM PST 24
Finished Jan 03 01:44:04 PM PST 24
Peak memory 282940 kb
Host smart-8e2f55b5-0129-418e-9338-470d53abd0fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944786660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable
.944786660
Directory /workspace/6.sram_ctrl_executable/latest

Test location /workspace/coverage/default/6.sram_ctrl_lc_escalation.880060458
Short name T243
Test name
Test status
Simulation time 6051669692 ps
CPU time 42.8 seconds
Started Jan 03 01:40:32 PM PST 24
Finished Jan 03 01:41:21 PM PST 24
Peak memory 202232 kb
Host smart-4a7cef7e-db4a-4c8d-84b1-48ba45fc6184
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880060458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esca
lation.880060458
Directory /workspace/6.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.2620424061
Short name T533
Test name
Test status
Simulation time 3061931763 ps
CPU time 43.56 seconds
Started Jan 03 01:41:46 PM PST 24
Finished Jan 03 01:42:41 PM PST 24
Peak memory 267692 kb
Host smart-09735a59-2664-48f2-9a4a-a431b54839b0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620424061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_max_throughput.2620424061
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.882326926
Short name T765
Test name
Test status
Simulation time 4610296963 ps
CPU time 80.72 seconds
Started Jan 03 01:40:17 PM PST 24
Finished Jan 03 01:41:46 PM PST 24
Peak memory 211228 kb
Host smart-3eb5792b-7cea-45ee-b4e9-7ef76e8d3255
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882326926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
sram_ctrl_mem_partial_access.882326926
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.3405331073
Short name T313
Test name
Test status
Simulation time 4064679064 ps
CPU time 246.91 seconds
Started Jan 03 01:40:13 PM PST 24
Finished Jan 03 01:44:30 PM PST 24
Peak memory 202200 kb
Host smart-0b143f20-4007-444e-9af2-a9f7f7963a9e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405331073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl
_mem_walk.3405331073
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.1927549725
Short name T385
Test name
Test status
Simulation time 53363024184 ps
CPU time 750.27 seconds
Started Jan 03 01:40:28 PM PST 24
Finished Jan 03 01:53:01 PM PST 24
Peak memory 371656 kb
Host smart-0c8c5014-373f-4b81-a907-635dcdba2423
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927549725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip
le_keys.1927549725
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.3634451647
Short name T645
Test name
Test status
Simulation time 9804165505 ps
CPU time 24.92 seconds
Started Jan 03 01:41:37 PM PST 24
Finished Jan 03 01:42:06 PM PST 24
Peak memory 202156 kb
Host smart-b93cc197-27f3-43d3-a82c-25083e821803
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634451647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s
ram_ctrl_partial_access.3634451647
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2558772781
Short name T501
Test name
Test status
Simulation time 13938631335 ps
CPU time 308.77 seconds
Started Jan 03 01:40:14 PM PST 24
Finished Jan 03 01:45:33 PM PST 24
Peak memory 202148 kb
Host smart-f12085e5-6f66-499b-b895-86a4c87718e9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558772781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 6.sram_ctrl_partial_access_b2b.2558772781
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.532844586
Short name T705
Test name
Test status
Simulation time 356471388 ps
CPU time 6.62 seconds
Started Jan 03 01:40:15 PM PST 24
Finished Jan 03 01:40:32 PM PST 24
Peak memory 202388 kb
Host smart-bae064c4-93d1-4919-bcaf-d3ad9b19456a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532844586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.532844586
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.1845544618
Short name T134
Test name
Test status
Simulation time 11177859767 ps
CPU time 929.68 seconds
Started Jan 03 01:40:14 PM PST 24
Finished Jan 03 01:55:54 PM PST 24
Peak memory 375940 kb
Host smart-a52dba45-08d0-4dae-b179-4e82d4fd60a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845544618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.1845544618
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.376350278
Short name T43
Test name
Test status
Simulation time 3041492992 ps
CPU time 15.85 seconds
Started Jan 03 01:40:51 PM PST 24
Finished Jan 03 01:41:12 PM PST 24
Peak memory 202228 kb
Host smart-9c159a29-b8e2-4953-a35d-592b0b12dcf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376350278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.376350278
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all.1647650738
Short name T652
Test name
Test status
Simulation time 64386356901 ps
CPU time 3559.81 seconds
Started Jan 03 01:40:29 PM PST 24
Finished Jan 03 02:39:51 PM PST 24
Peak memory 382148 kb
Host smart-a50e16af-440b-469f-91d0-ae8f4d0aa4c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647650738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.sram_ctrl_stress_all.1647650738
Directory /workspace/6.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3461560152
Short name T521
Test name
Test status
Simulation time 315164889 ps
CPU time 2770.62 seconds
Started Jan 03 01:40:32 PM PST 24
Finished Jan 03 02:26:48 PM PST 24
Peak memory 432352 kb
Host smart-4df9d3b8-a492-4f91-b5cf-2312a38f8362
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3461560152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.3461560152
Directory /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2455634254
Short name T429
Test name
Test status
Simulation time 9686171085 ps
CPU time 366.33 seconds
Started Jan 03 01:40:16 PM PST 24
Finished Jan 03 01:46:31 PM PST 24
Peak memory 202128 kb
Host smart-c1dc998d-9d46-4723-99d0-00d5ac7d06da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455634254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_stress_pipeline.2455634254
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3337277544
Short name T231
Test name
Test status
Simulation time 2800485497 ps
CPU time 36.31 seconds
Started Jan 03 01:40:14 PM PST 24
Finished Jan 03 01:41:01 PM PST 24
Peak memory 250624 kb
Host smart-8bb3aec2-cf79-4354-9ffa-e911c513cb8c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337277544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.3337277544
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.69428566
Short name T638
Test name
Test status
Simulation time 44796732 ps
CPU time 0.66 seconds
Started Jan 03 01:41:44 PM PST 24
Finished Jan 03 01:41:51 PM PST 24
Peak memory 201764 kb
Host smart-f59cbd0d-760c-4943-ad9e-a19d85bd9e68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69428566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_alert_test.69428566
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.2087420109
Short name T576
Test name
Test status
Simulation time 27108166815 ps
CPU time 1814.6 seconds
Started Jan 03 01:40:55 PM PST 24
Finished Jan 03 02:11:12 PM PST 24
Peak memory 202160 kb
Host smart-bc1afec8-425d-400e-b519-46d7c946e831
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087420109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.
2087420109
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_executable.663556590
Short name T937
Test name
Test status
Simulation time 83131781650 ps
CPU time 1329.68 seconds
Started Jan 03 01:41:42 PM PST 24
Finished Jan 03 02:03:55 PM PST 24
Peak memory 380152 kb
Host smart-4db24d1d-3b07-4f5a-a25a-94c4332b59a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663556590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable
.663556590
Directory /workspace/7.sram_ctrl_executable/latest

Test location /workspace/coverage/default/7.sram_ctrl_lc_escalation.1783912423
Short name T834
Test name
Test status
Simulation time 6926315547 ps
CPU time 110.2 seconds
Started Jan 03 01:41:14 PM PST 24
Finished Jan 03 01:43:09 PM PST 24
Peak memory 210320 kb
Host smart-9c4cf541-23cb-45cd-9ee1-0b4ee46a4dc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783912423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc
alation.1783912423
Directory /workspace/7.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.628496441
Short name T908
Test name
Test status
Simulation time 753400483 ps
CPU time 121.9 seconds
Started Jan 03 01:41:38 PM PST 24
Finished Jan 03 01:43:43 PM PST 24
Peak memory 342468 kb
Host smart-981ac401-3cfd-4200-a126-912ee57c7852
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628496441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.sram_ctrl_max_throughput.628496441
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1689286413
Short name T418
Test name
Test status
Simulation time 12361237742 ps
CPU time 79.45 seconds
Started Jan 03 01:41:43 PM PST 24
Finished Jan 03 01:43:09 PM PST 24
Peak memory 211132 kb
Host smart-07bef5e4-e249-48fd-a9ca-c441a60a6d4d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689286413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_mem_partial_access.1689286413
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.3262204853
Short name T682
Test name
Test status
Simulation time 8981461262 ps
CPU time 123.48 seconds
Started Jan 03 01:41:15 PM PST 24
Finished Jan 03 01:43:23 PM PST 24
Peak memory 202132 kb
Host smart-1548926a-016a-4301-bca1-0c5bdac3b412
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262204853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl
_mem_walk.3262204853
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.4177168258
Short name T918
Test name
Test status
Simulation time 123961723550 ps
CPU time 1136.58 seconds
Started Jan 03 01:40:16 PM PST 24
Finished Jan 03 01:59:22 PM PST 24
Peak memory 375024 kb
Host smart-a60f05fe-cda6-411c-9729-4a5c0873cfa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177168258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip
le_keys.4177168258
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.1468218505
Short name T704
Test name
Test status
Simulation time 1703300959 ps
CPU time 24.11 seconds
Started Jan 03 01:40:53 PM PST 24
Finished Jan 03 01:41:21 PM PST 24
Peak memory 239892 kb
Host smart-37efeb87-92f8-4a0e-a8c9-4d3b2be78c03
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468218505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s
ram_ctrl_partial_access.1468218505
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1488541325
Short name T422
Test name
Test status
Simulation time 67537051006 ps
CPU time 439.54 seconds
Started Jan 03 01:41:37 PM PST 24
Finished Jan 03 01:49:00 PM PST 24
Peak memory 202176 kb
Host smart-db6b82c4-0d98-4bf8-86c4-fc435f9c8ff6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488541325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_partial_access_b2b.1488541325
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.173705285
Short name T308
Test name
Test status
Simulation time 3053876453 ps
CPU time 7.46 seconds
Started Jan 03 01:41:18 PM PST 24
Finished Jan 03 01:41:31 PM PST 24
Peak memory 202480 kb
Host smart-22bfde10-0601-4b82-8b66-2d64fb9799dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173705285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.173705285
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.829767869
Short name T312
Test name
Test status
Simulation time 124120026998 ps
CPU time 611.66 seconds
Started Jan 03 01:41:42 PM PST 24
Finished Jan 03 01:51:57 PM PST 24
Peak memory 379060 kb
Host smart-c04833ff-c92d-445d-b624-90eaf3386a96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829767869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.829767869
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.3456007949
Short name T686
Test name
Test status
Simulation time 428178285 ps
CPU time 18.33 seconds
Started Jan 03 01:40:19 PM PST 24
Finished Jan 03 01:40:45 PM PST 24
Peak memory 202136 kb
Host smart-a95d2064-3a21-49f6-adfe-87f9a93341a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456007949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.3456007949
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all.3787119658
Short name T850
Test name
Test status
Simulation time 236683047720 ps
CPU time 3941.02 seconds
Started Jan 03 01:41:50 PM PST 24
Finished Jan 03 02:47:43 PM PST 24
Peak memory 374588 kb
Host smart-287d451a-91f0-4332-a3ef-43ea0e9932e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787119658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.sram_ctrl_stress_all.3787119658
Directory /workspace/7.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.206905465
Short name T566
Test name
Test status
Simulation time 1027628782 ps
CPU time 2257.29 seconds
Started Jan 03 01:41:47 PM PST 24
Finished Jan 03 02:19:36 PM PST 24
Peak memory 406668 kb
Host smart-af9648f7-7fba-485f-92f2-160a84e0aae5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=206905465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.206905465
Directory /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.570357788
Short name T959
Test name
Test status
Simulation time 29945132297 ps
CPU time 310.68 seconds
Started Jan 03 01:41:09 PM PST 24
Finished Jan 03 01:46:24 PM PST 24
Peak memory 202088 kb
Host smart-75c7c098-5c1d-4180-8c1f-657830e391b4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570357788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
sram_ctrl_stress_pipeline.570357788
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1405426644
Short name T833
Test name
Test status
Simulation time 2075806044 ps
CPU time 50.88 seconds
Started Jan 03 01:41:39 PM PST 24
Finished Jan 03 01:42:33 PM PST 24
Peak memory 278600 kb
Host smart-0bb5b0fe-9c8c-4d48-8879-c826d15b2dba
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405426644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.1405426644
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2707324713
Short name T764
Test name
Test status
Simulation time 5845825376 ps
CPU time 779.32 seconds
Started Jan 03 01:40:32 PM PST 24
Finished Jan 03 01:53:37 PM PST 24
Peak memory 372868 kb
Host smart-1e52c0a4-4ca1-49a7-a293-3fea8bae6739
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707324713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_access_during_key_req.2707324713
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.1858280879
Short name T484
Test name
Test status
Simulation time 19031925 ps
CPU time 0.72 seconds
Started Jan 03 01:41:32 PM PST 24
Finished Jan 03 01:41:37 PM PST 24
Peak memory 201872 kb
Host smart-66999f9c-bbe3-4602-9552-91a64cec4bb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858280879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.1858280879
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_bijection.2027793270
Short name T957
Test name
Test status
Simulation time 135120543269 ps
CPU time 735.07 seconds
Started Jan 03 01:42:07 PM PST 24
Finished Jan 03 01:54:28 PM PST 24
Peak memory 202152 kb
Host smart-6efdc988-2251-4110-944e-574e2f5714e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027793270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.
2027793270
Directory /workspace/8.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.370922849
Short name T623
Test name
Test status
Simulation time 14233316841 ps
CPU time 151.29 seconds
Started Jan 03 01:40:33 PM PST 24
Finished Jan 03 01:43:11 PM PST 24
Peak memory 210404 kb
Host smart-f8591bfa-61bf-4969-b75f-6cc5f4d82148
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370922849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esca
lation.370922849
Directory /workspace/8.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.2637862703
Short name T973
Test name
Test status
Simulation time 3177292435 ps
CPU time 168.8 seconds
Started Jan 03 01:40:30 PM PST 24
Finished Jan 03 01:43:22 PM PST 24
Peak memory 366752 kb
Host smart-cb90dd3f-de8d-4b3d-b69a-665befd2e235
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637862703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_max_throughput.2637862703
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1258762087
Short name T766
Test name
Test status
Simulation time 4561949954 ps
CPU time 154.22 seconds
Started Jan 03 01:41:13 PM PST 24
Finished Jan 03 01:43:51 PM PST 24
Peak memory 214524 kb
Host smart-57b10426-1f53-4591-976a-3727f8d30695
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258762087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_mem_partial_access.1258762087
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.1023484422
Short name T779
Test name
Test status
Simulation time 15767053619 ps
CPU time 247 seconds
Started Jan 03 01:40:47 PM PST 24
Finished Jan 03 01:44:59 PM PST 24
Peak memory 202148 kb
Host smart-b963066e-5fa1-4424-b65c-4622ad8c5eca
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023484422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl
_mem_walk.1023484422
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.67541070
Short name T679
Test name
Test status
Simulation time 42621930383 ps
CPU time 750.73 seconds
Started Jan 03 01:41:55 PM PST 24
Finished Jan 03 01:54:35 PM PST 24
Peak memory 378712 kb
Host smart-a9557cf9-7a7a-499f-922f-d02ff24b5fee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67541070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple
_keys.67541070
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.3810751218
Short name T235
Test name
Test status
Simulation time 974466423 ps
CPU time 44.35 seconds
Started Jan 03 01:40:20 PM PST 24
Finished Jan 03 01:41:11 PM PST 24
Peak memory 202052 kb
Host smart-6866f026-0343-46bf-82c4-7bcf702cb4eb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810751218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s
ram_ctrl_partial_access.3810751218
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2161812393
Short name T568
Test name
Test status
Simulation time 8089942924 ps
CPU time 548.43 seconds
Started Jan 03 01:40:33 PM PST 24
Finished Jan 03 01:49:48 PM PST 24
Peak memory 210416 kb
Host smart-cde56b3c-1198-4e77-926b-e945f3bf13a5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161812393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_partial_access_b2b.2161812393
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.1944158471
Short name T760
Test name
Test status
Simulation time 1406218737 ps
CPU time 6.82 seconds
Started Jan 03 01:40:22 PM PST 24
Finished Jan 03 01:40:34 PM PST 24
Peak memory 202432 kb
Host smart-b19d5183-7eef-42fb-a1c1-e81394c7a1ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944158471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.1944158471
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.1094465279
Short name T858
Test name
Test status
Simulation time 12981857647 ps
CPU time 387.19 seconds
Started Jan 03 01:40:33 PM PST 24
Finished Jan 03 01:47:06 PM PST 24
Peak memory 353492 kb
Host smart-0609b1e7-20c3-4d47-85f8-0c20a0dfc95b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094465279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.1094465279
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.3983731847
Short name T923
Test name
Test status
Simulation time 758862478 ps
CPU time 15.37 seconds
Started Jan 03 01:42:25 PM PST 24
Finished Jan 03 01:42:42 PM PST 24
Peak memory 202028 kb
Host smart-86a301e8-17fd-4090-b02a-2716d16c03dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983731847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.3983731847
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3595636594
Short name T608
Test name
Test status
Simulation time 2377036384 ps
CPU time 3499.63 seconds
Started Jan 03 01:40:48 PM PST 24
Finished Jan 03 02:39:14 PM PST 24
Peak memory 521448 kb
Host smart-411692d1-2bc3-44d0-9a65-3e84d921b408
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3595636594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.3595636594
Directory /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.864021073
Short name T372
Test name
Test status
Simulation time 4977417121 ps
CPU time 333.84 seconds
Started Jan 03 01:40:33 PM PST 24
Finished Jan 03 01:46:13 PM PST 24
Peak memory 202220 kb
Host smart-f24f052d-964d-431a-b0b5-82deb1cf0a22
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864021073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
sram_ctrl_stress_pipeline.864021073
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2847275003
Short name T714
Test name
Test status
Simulation time 10532616399 ps
CPU time 83.34 seconds
Started Jan 03 01:40:33 PM PST 24
Finished Jan 03 01:42:03 PM PST 24
Peak memory 303476 kb
Host smart-1aaf11ac-39df-44c1-a39f-8efa575d7bde
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847275003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.2847275003
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.860300124
Short name T411
Test name
Test status
Simulation time 14821596408 ps
CPU time 1029.97 seconds
Started Jan 03 01:40:51 PM PST 24
Finished Jan 03 01:58:06 PM PST 24
Peak memory 379004 kb
Host smart-142a8556-f076-45f9-a8b0-8ee6988bb783
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860300124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 9.sram_ctrl_access_during_key_req.860300124
Directory /workspace/9.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.1576339274
Short name T747
Test name
Test status
Simulation time 13678891 ps
CPU time 0.65 seconds
Started Jan 03 01:41:41 PM PST 24
Finished Jan 03 01:41:45 PM PST 24
Peak memory 201876 kb
Host smart-3e66d662-dc3f-4a89-b838-b49225e2c9b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576339274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_alert_test.1576339274
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_lc_escalation.411487541
Short name T931
Test name
Test status
Simulation time 8222032518 ps
CPU time 169.74 seconds
Started Jan 03 01:40:51 PM PST 24
Finished Jan 03 01:43:46 PM PST 24
Peak memory 210344 kb
Host smart-5388bdfc-54ab-4ca6-bc97-c798e66f1bf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411487541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esca
lation.411487541
Directory /workspace/9.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.2133971847
Short name T351
Test name
Test status
Simulation time 3160249811 ps
CPU time 166.32 seconds
Started Jan 03 01:40:49 PM PST 24
Finished Jan 03 01:43:41 PM PST 24
Peak memory 356652 kb
Host smart-2adecb50-3c2b-46f0-a772-4e3699c23bec
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133971847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_max_throughput.2133971847
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.3217372285
Short name T876
Test name
Test status
Simulation time 8889556721 ps
CPU time 145.31 seconds
Started Jan 03 01:41:38 PM PST 24
Finished Jan 03 01:44:07 PM PST 24
Peak memory 210572 kb
Host smart-da3dfa08-2158-4370-94aa-95a991371eb1
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217372285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_mem_partial_access.3217372285
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.2129753028
Short name T759
Test name
Test status
Simulation time 11480072885 ps
CPU time 149.27 seconds
Started Jan 03 01:41:37 PM PST 24
Finished Jan 03 01:44:10 PM PST 24
Peak memory 202184 kb
Host smart-7c97fec5-4315-40b1-8750-5f3e6d17fced
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129753028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl
_mem_walk.2129753028
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.3955041499
Short name T632
Test name
Test status
Simulation time 9027914557 ps
CPU time 631.81 seconds
Started Jan 03 01:40:49 PM PST 24
Finished Jan 03 01:51:27 PM PST 24
Peak memory 379132 kb
Host smart-0701fb06-55c8-433d-ba03-883a218f27fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955041499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip
le_keys.3955041499
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.2214610330
Short name T404
Test name
Test status
Simulation time 928593330 ps
CPU time 15.94 seconds
Started Jan 03 01:41:33 PM PST 24
Finished Jan 03 01:41:55 PM PST 24
Peak memory 202096 kb
Host smart-04825a2c-6c54-49ca-8b55-aa84d63cbed9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214610330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s
ram_ctrl_partial_access.2214610330
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.4067384044
Short name T528
Test name
Test status
Simulation time 18524306696 ps
CPU time 385.44 seconds
Started Jan 03 01:40:54 PM PST 24
Finished Jan 03 01:47:23 PM PST 24
Peak memory 202092 kb
Host smart-9f5ec290-0d24-47bf-88e6-e3e5f3106fa1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067384044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.sram_ctrl_partial_access_b2b.4067384044
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.3495681310
Short name T34
Test name
Test status
Simulation time 1468698697 ps
CPU time 5.77 seconds
Started Jan 03 01:41:14 PM PST 24
Finished Jan 03 01:41:24 PM PST 24
Peak memory 202332 kb
Host smart-86924798-8ac1-4368-bc85-b958ecac4002
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495681310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3495681310
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.712536593
Short name T667
Test name
Test status
Simulation time 3562833510 ps
CPU time 901.51 seconds
Started Jan 03 01:41:34 PM PST 24
Finished Jan 03 01:56:41 PM PST 24
Peak memory 379076 kb
Host smart-8e3e4f49-b13f-49fe-a9e7-47ea212dd0b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712536593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.712536593
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.920187762
Short name T494
Test name
Test status
Simulation time 1810853954 ps
CPU time 10.71 seconds
Started Jan 03 01:40:49 PM PST 24
Finished Jan 03 01:41:06 PM PST 24
Peak memory 220380 kb
Host smart-6dd535ae-d546-4257-9d16-0933a3a4debd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920187762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.920187762
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.565888547
Short name T859
Test name
Test status
Simulation time 1992556023 ps
CPU time 3071.59 seconds
Started Jan 03 01:41:38 PM PST 24
Finished Jan 03 02:32:54 PM PST 24
Peak memory 587048 kb
Host smart-9d3a4731-1a1c-4bad-b03b-f8526d5f371c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=565888547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.565888547
Directory /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1105028953
Short name T15
Test name
Test status
Simulation time 12037791688 ps
CPU time 404.09 seconds
Started Jan 03 01:40:46 PM PST 24
Finished Jan 03 01:47:36 PM PST 24
Peak memory 202092 kb
Host smart-6bd3d20e-2a5a-4d94-b98c-5979cfdd8d28
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105028953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_stress_pipeline.1105028953
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3826816841
Short name T10
Test name
Test status
Simulation time 827179749 ps
CPU time 169.04 seconds
Started Jan 03 01:40:48 PM PST 24
Finished Jan 03 01:43:44 PM PST 24
Peak memory 365740 kb
Host smart-7fa803de-1a63-4dc3-aefe-14ed954fcc4c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826816841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.3826816841
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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