Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	223762753	1			T1	12421		T2	655360		T3	134672
instr_valid_dis	207108178	1			T1	12421		T2	655360		T3	134672
instr_en	11575412	1			T12	572926		T24	67238		T33	88860

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	5609137	1			T12	9286		T24	85154		T33	13514
sram_ifetch_valid_disable	204750193	1			T1	12421		T2	655360		T3	134672
sram_ifetch_enable	13403423	1			T12	282930		T24	23220		T33	67712

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	223762753	1			T1	12421		T2	655360		T3	134672
hw_debug_en_valid_off	207511671	1			T1	12421		T2	655360		T3	134672
hw_debug_en_on	10860140	1			T12	146450		T24	110176		T33	167130

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	204750193	1			T1	12421		T2	655360		T3	134672
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	197512925	1			T1	12421		T2	655360		T3	134672
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	4767733	1			T12	280710		T24	56		T33	69036
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	2281326	1			T24	20000		T20	32320		T19	12632
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1037248	1			T113	32858		T114	67950		T104	46306
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	855142	1			T24	20000		T20	32320		T19	12632
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	2141499	1			T24	27734		T33	13514		T116	47828
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	816724	1			T114	18244		T117	88		T115	55040
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	782633	1			T24	27734		T33	13514		T116	47828
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	4911230	1			T12	69036		T24	59222		T33	153616
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2196472	1			T24	59166		T33	94226		T19	17306
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	1767092	1			T12	69036		T24	56		T33	20000

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	4798594	1			T12	282930		T24	19448		T33	6310
lc_exec_en	3807411	1			T12	77414		T24	23220		T20	42472
valid_exec_dis	204792298	1			T1	12421		T2	655360		T3	134672
invalid_exec_dis	19012560	1			T12	292216		T24	108374		T33	81226