Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	93620991	1			T2	327680		T3	61147		T4	113637
triple_byte_access	1975144	1			T3	1192		T4	2330		T9	957
halfword_access	3030582	1			T3	1883		T4	3406		T9	1393
byte_access	4246933	1			T3	2489		T4	4529		T9	1920
zero_access	1296376	1			T3	625		T4	1169		T9	499

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51689962

1

T2

163840

T3

33642

T4

62402

auto[1]

52480064

1

T2

163840

T3

33694

T4

62669

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	46334141	1			T2	163840		T3	30524		T4	56717
auto[0]	triple_byte_access	935178	1			T3	626		T4	1163		T9	492
auto[0]	halfword_access	1473381	1			T3	938		T4	1675		T9	721
auto[0]	byte_access	2169866	1			T3	1249		T4	2267		T9	942
auto[0]	zero_access	777396	1			T3	305		T4	580		T9	243
auto[1]	word_access	47286850	1			T2	163840		T3	30623		T4	56920
auto[1]	triple_byte_access	1039966	1			T3	566		T4	1167		T9	465
auto[1]	halfword_access	1557201	1			T3	945		T4	1731		T9	672
auto[1]	byte_access	2077067	1			T3	1240		T4	2262		T9	978
auto[1]	zero_access	518980	1			T3	320		T4	589		T9	256