| T52 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3974952407 |
|
|
Jan 07 01:42:15 PM PST 24 |
Jan 07 01:44:13 PM PST 24 |
29588037824 ps |
| T53 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3300444758 |
|
|
Jan 07 01:43:07 PM PST 24 |
Jan 07 01:43:23 PM PST 24 |
447037983 ps |
| T35 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2646864292 |
|
|
Jan 07 01:41:40 PM PST 24 |
Jan 07 01:41:57 PM PST 24 |
362489459 ps |
| T58 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2921840495 |
|
|
Jan 07 01:42:08 PM PST 24 |
Jan 07 01:42:18 PM PST 24 |
32238580 ps |
| T77 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2886455493 |
|
|
Jan 07 01:41:37 PM PST 24 |
Jan 07 01:41:49 PM PST 24 |
100114421 ps |
| T78 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2368115315 |
|
|
Jan 07 01:43:00 PM PST 24 |
Jan 07 01:43:20 PM PST 24 |
840539537 ps |
| T59 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2724967106 |
|
|
Jan 07 01:43:09 PM PST 24 |
Jan 07 01:45:43 PM PST 24 |
40938414361 ps |
| T79 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.673906448 |
|
|
Jan 07 01:41:35 PM PST 24 |
Jan 07 01:41:44 PM PST 24 |
182766400 ps |
| T60 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.43057865 |
|
|
Jan 07 01:42:28 PM PST 24 |
Jan 07 01:42:47 PM PST 24 |
26615796 ps |
| T80 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3981340458 |
|
|
Jan 07 01:41:26 PM PST 24 |
Jan 07 01:41:38 PM PST 24 |
1197332617 ps |
| T61 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2238338891 |
|
|
Jan 07 01:41:38 PM PST 24 |
Jan 07 01:41:50 PM PST 24 |
19120961 ps |
| T68 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1731445174 |
|
|
Jan 07 01:42:00 PM PST 24 |
Jan 07 01:44:25 PM PST 24 |
88074077296 ps |
| T288 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2186985637 |
|
|
Jan 07 01:42:24 PM PST 24 |
Jan 07 01:42:43 PM PST 24 |
26836343 ps |
| T289 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3834140708 |
|
|
Jan 07 01:41:37 PM PST 24 |
Jan 07 01:41:47 PM PST 24 |
87226147 ps |
| T290 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1058073192 |
|
|
Jan 07 01:41:59 PM PST 24 |
Jan 07 01:42:10 PM PST 24 |
25153057 ps |
| T291 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4148216509 |
|
|
Jan 07 01:41:29 PM PST 24 |
Jan 07 01:41:35 PM PST 24 |
31920065 ps |
| T69 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.527944174 |
|
|
Jan 07 01:42:11 PM PST 24 |
Jan 07 01:42:20 PM PST 24 |
12472997 ps |
| T36 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2867691355 |
|
|
Jan 07 01:41:51 PM PST 24 |
Jan 07 01:42:05 PM PST 24 |
367198649 ps |
| T292 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.624451832 |
|
|
Jan 07 01:41:39 PM PST 24 |
Jan 07 01:41:53 PM PST 24 |
26913472 ps |
| T293 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2911313935 |
|
|
Jan 07 01:43:10 PM PST 24 |
Jan 07 01:43:26 PM PST 24 |
401229675 ps |
| T294 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1548331533 |
|
|
Jan 07 01:41:27 PM PST 24 |
Jan 07 01:41:37 PM PST 24 |
404776553 ps |
| T295 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2244582406 |
|
|
Jan 07 01:42:32 PM PST 24 |
Jan 07 01:43:00 PM PST 24 |
344287492 ps |
| T296 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1428691375 |
|
|
Jan 07 01:41:38 PM PST 24 |
Jan 07 01:42:03 PM PST 24 |
1409386853 ps |
| T297 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1706022167 |
|
|
Jan 07 01:41:35 PM PST 24 |
Jan 07 01:41:47 PM PST 24 |
466144826 ps |
| T107 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2886050338 |
|
|
Jan 07 01:42:32 PM PST 24 |
Jan 07 01:42:48 PM PST 24 |
337675385 ps |
| T298 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3387553663 |
|
|
Jan 07 01:41:59 PM PST 24 |
Jan 07 01:42:22 PM PST 24 |
362878304 ps |
| T108 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2620898834 |
|
|
Jan 07 01:41:27 PM PST 24 |
Jan 07 01:41:34 PM PST 24 |
356729007 ps |
| T70 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1057742523 |
|
|
Jan 07 01:42:23 PM PST 24 |
Jan 07 01:44:24 PM PST 24 |
14398243291 ps |
| T105 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.651912462 |
|
|
Jan 07 01:42:10 PM PST 24 |
Jan 07 01:42:21 PM PST 24 |
368810801 ps |
| T299 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.131708872 |
|
|
Jan 07 01:42:00 PM PST 24 |
Jan 07 01:42:10 PM PST 24 |
42762021 ps |
| T71 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3224493369 |
|
|
Jan 07 01:42:16 PM PST 24 |
Jan 07 01:46:59 PM PST 24 |
14127336502 ps |
| T72 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1645114604 |
|
|
Jan 07 01:41:30 PM PST 24 |
Jan 07 01:42:27 PM PST 24 |
4654874328 ps |
| T300 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2449887137 |
|
|
Jan 07 01:41:44 PM PST 24 |
Jan 07 01:41:58 PM PST 24 |
82923034 ps |
| T301 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1758719302 |
|
|
Jan 07 01:41:55 PM PST 24 |
Jan 07 01:42:10 PM PST 24 |
682971185 ps |
| T76 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3069906439 |
|
|
Jan 07 01:42:47 PM PST 24 |
Jan 07 01:47:51 PM PST 24 |
117264327702 ps |
| T112 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1658189373 |
|
|
Jan 07 01:42:35 PM PST 24 |
Jan 07 01:42:57 PM PST 24 |
228115488 ps |
| T302 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1989679239 |
|
|
Jan 07 01:41:41 PM PST 24 |
Jan 07 01:41:56 PM PST 24 |
15019597 ps |
| T303 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3327980170 |
|
|
Jan 07 01:42:42 PM PST 24 |
Jan 07 01:43:06 PM PST 24 |
953608112 ps |
| T304 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3509624487 |
|
|
Jan 07 01:41:34 PM PST 24 |
Jan 07 01:41:45 PM PST 24 |
265228653 ps |
| T305 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3167613384 |
|
|
Jan 07 01:42:46 PM PST 24 |
Jan 07 01:43:07 PM PST 24 |
15389907 ps |
| T306 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.569053730 |
|
|
Jan 07 01:42:35 PM PST 24 |
Jan 07 01:43:57 PM PST 24 |
23174066279 ps |
| T307 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1860856858 |
|
|
Jan 07 01:42:11 PM PST 24 |
Jan 07 01:42:20 PM PST 24 |
42592882 ps |
| T308 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.462215133 |
|
|
Jan 07 01:41:28 PM PST 24 |
Jan 07 01:41:34 PM PST 24 |
19548237 ps |
| T309 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1813715739 |
|
|
Jan 07 01:42:23 PM PST 24 |
Jan 07 01:42:40 PM PST 24 |
77981839 ps |
| T310 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.21374696 |
|
|
Jan 07 01:42:29 PM PST 24 |
Jan 07 01:42:48 PM PST 24 |
487644819 ps |
| T311 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1877312327 |
|
|
Jan 07 01:41:24 PM PST 24 |
Jan 07 01:41:32 PM PST 24 |
539448762 ps |
| T312 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2863490936 |
|
|
Jan 07 01:43:33 PM PST 24 |
Jan 07 01:43:53 PM PST 24 |
10863184 ps |
| T110 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3044588593 |
|
|
Jan 07 01:41:47 PM PST 24 |
Jan 07 01:42:02 PM PST 24 |
455908786 ps |
| T313 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.662094211 |
|
|
Jan 07 01:41:31 PM PST 24 |
Jan 07 01:42:38 PM PST 24 |
19498574617 ps |
| T86 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2965118057 |
|
|
Jan 07 01:42:43 PM PST 24 |
Jan 07 01:43:04 PM PST 24 |
12414244 ps |
| T314 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1390710271 |
|
|
Jan 07 01:43:06 PM PST 24 |
Jan 07 01:43:19 PM PST 24 |
18677309 ps |
| T315 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3399276632 |
|
|
Jan 07 01:41:38 PM PST 24 |
Jan 07 01:41:52 PM PST 24 |
39317519 ps |
| T87 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.79806495 |
|
|
Jan 07 01:42:39 PM PST 24 |
Jan 07 01:44:06 PM PST 24 |
18466615527 ps |
| T316 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3868057896 |
|
|
Jan 07 01:42:28 PM PST 24 |
Jan 07 01:42:47 PM PST 24 |
78004153 ps |
| T81 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1035024154 |
|
|
Jan 07 01:42:23 PM PST 24 |
Jan 07 01:44:20 PM PST 24 |
29401034830 ps |
| T317 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3152148294 |
|
|
Jan 07 01:41:33 PM PST 24 |
Jan 07 01:41:44 PM PST 24 |
118980799 ps |
| T318 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2138064726 |
|
|
Jan 07 01:42:27 PM PST 24 |
Jan 07 01:42:47 PM PST 24 |
42056618 ps |
| T88 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.779757796 |
|
|
Jan 07 01:41:35 PM PST 24 |
Jan 07 01:46:14 PM PST 24 |
19510618243 ps |
| T319 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4021646251 |
|
|
Jan 07 01:42:03 PM PST 24 |
Jan 07 01:42:25 PM PST 24 |
340125845 ps |
| T82 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.970632632 |
|
|
Jan 07 01:42:00 PM PST 24 |
Jan 07 01:43:45 PM PST 24 |
13764723745 ps |
| T83 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2522470918 |
|
|
Jan 07 01:42:09 PM PST 24 |
Jan 07 01:46:56 PM PST 24 |
14993676340 ps |
| T320 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2837167142 |
|
|
Jan 07 01:42:44 PM PST 24 |
Jan 07 01:43:06 PM PST 24 |
194526407 ps |
| T321 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1323953831 |
|
|
Jan 07 01:41:35 PM PST 24 |
Jan 07 01:41:44 PM PST 24 |
24182734 ps |
| T84 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2369879491 |
|
|
Jan 07 01:42:41 PM PST 24 |
Jan 07 01:43:02 PM PST 24 |
20461998 ps |
| T106 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.72279137 |
|
|
Jan 07 01:41:34 PM PST 24 |
Jan 07 01:41:45 PM PST 24 |
1310473965 ps |
| T322 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1657282895 |
|
|
Jan 07 01:42:13 PM PST 24 |
Jan 07 01:42:25 PM PST 24 |
112906804 ps |
| T323 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1568497482 |
|
|
Jan 07 01:43:09 PM PST 24 |
Jan 07 01:43:21 PM PST 24 |
45195541 ps |
| T111 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3504436670 |
|
|
Jan 07 01:43:03 PM PST 24 |
Jan 07 01:43:18 PM PST 24 |
82822331 ps |
| T324 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1541539828 |
|
|
Jan 07 01:41:37 PM PST 24 |
Jan 07 01:41:49 PM PST 24 |
296845297 ps |
| T109 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1279035661 |
|
|
Jan 07 01:43:17 PM PST 24 |
Jan 07 01:43:34 PM PST 24 |
131534451 ps |
| T325 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1285102378 |
|
|
Jan 07 01:42:14 PM PST 24 |
Jan 07 01:42:28 PM PST 24 |
738399067 ps |
| T326 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.746453391 |
|
|
Jan 07 01:41:44 PM PST 24 |
Jan 07 01:41:59 PM PST 24 |
125004586 ps |
| T327 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3143872971 |
|
|
Jan 07 01:42:13 PM PST 24 |
Jan 07 01:42:23 PM PST 24 |
20793390 ps |
| T328 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.538314976 |
|
|
Jan 07 01:41:27 PM PST 24 |
Jan 07 01:41:38 PM PST 24 |
361952425 ps |
| T329 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.542576689 |
|
|
Jan 07 01:42:48 PM PST 24 |
Jan 07 01:43:09 PM PST 24 |
47318204 ps |
| T330 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1677958842 |
|
|
Jan 07 01:43:03 PM PST 24 |
Jan 07 01:43:18 PM PST 24 |
344528314 ps |
| T331 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3423942800 |
|
|
Jan 07 01:42:41 PM PST 24 |
Jan 07 01:43:14 PM PST 24 |
377253934 ps |
| T332 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2812501691 |
|
|
Jan 07 01:42:01 PM PST 24 |
Jan 07 01:42:22 PM PST 24 |
1419604177 ps |
| T333 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1613160872 |
|
|
Jan 07 01:43:17 PM PST 24 |
Jan 07 01:43:45 PM PST 24 |
2147528767 ps |
| T334 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3961588505 |
|
|
Jan 07 01:41:30 PM PST 24 |
Jan 07 01:41:36 PM PST 24 |
19941128 ps |
| T335 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2635912251 |
|
|
Jan 07 01:41:44 PM PST 24 |
Jan 07 01:41:59 PM PST 24 |
13645956 ps |
| T336 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2873334828 |
|
|
Jan 07 01:41:40 PM PST 24 |
Jan 07 01:41:59 PM PST 24 |
705947197 ps |
| T85 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2917457943 |
|
|
Jan 07 01:41:38 PM PST 24 |
Jan 07 01:42:54 PM PST 24 |
15378673375 ps |
| T73 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1978772614 |
|
|
Jan 07 01:41:39 PM PST 24 |
Jan 07 01:41:52 PM PST 24 |
33845299 ps |
| T337 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3621137902 |
|
|
Jan 07 01:41:32 PM PST 24 |
Jan 07 01:42:37 PM PST 24 |
28534494261 ps |
| T338 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2278071877 |
|
|
Jan 07 01:42:32 PM PST 24 |
Jan 07 01:42:51 PM PST 24 |
142855128 ps |
| T339 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.4021698273 |
|
|
Jan 07 01:42:21 PM PST 24 |
Jan 07 01:42:38 PM PST 24 |
42731629 ps |
| T340 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1348961558 |
|
|
Jan 07 01:42:42 PM PST 24 |
Jan 07 01:43:02 PM PST 24 |
17257350 ps |
| T341 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2173307039 |
|
|
Jan 07 01:42:30 PM PST 24 |
Jan 07 01:42:48 PM PST 24 |
200185955 ps |
| T342 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2540097505 |
|
|
Jan 07 01:42:39 PM PST 24 |
Jan 07 01:43:02 PM PST 24 |
127930104 ps |
| T343 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2607031918 |
|
|
Jan 07 01:41:57 PM PST 24 |
Jan 07 01:42:57 PM PST 24 |
3697723726 ps |
| T344 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2285206087 |
|
|
Jan 07 01:42:37 PM PST 24 |
Jan 07 01:43:03 PM PST 24 |
366734666 ps |
| T345 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3660957373 |
|
|
Jan 07 01:41:30 PM PST 24 |
Jan 07 01:41:36 PM PST 24 |
40200683 ps |
| T346 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1702356700 |
|
|
Jan 07 01:41:56 PM PST 24 |
Jan 07 01:42:06 PM PST 24 |
17584893 ps |
| T347 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2926943813 |
|
|
Jan 07 01:42:03 PM PST 24 |
Jan 07 01:42:13 PM PST 24 |
18807680 ps |
| T348 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.363768388 |
|
|
Jan 07 01:42:21 PM PST 24 |
Jan 07 01:42:43 PM PST 24 |
359923889 ps |
| T349 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2571605263 |
|
|
Jan 07 01:41:59 PM PST 24 |
Jan 07 01:42:10 PM PST 24 |
325362124 ps |
| T350 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4011443791 |
|
|
Jan 07 01:42:00 PM PST 24 |
Jan 07 01:42:09 PM PST 24 |
16703770 ps |
| T351 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2481704303 |
|
|
Jan 07 01:43:05 PM PST 24 |
Jan 07 01:43:22 PM PST 24 |
375558448 ps |
| T352 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2180394048 |
|
|
Jan 07 01:42:38 PM PST 24 |
Jan 07 01:43:01 PM PST 24 |
131772413 ps |
| T353 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2053011094 |
|
|
Jan 07 01:42:32 PM PST 24 |
Jan 07 01:42:48 PM PST 24 |
23354171 ps |
| T354 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3486339711 |
|
|
Jan 07 01:41:38 PM PST 24 |
Jan 07 01:41:49 PM PST 24 |
15231486 ps |
| T355 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1608987789 |
|
|
Jan 07 01:41:56 PM PST 24 |
Jan 07 01:42:09 PM PST 24 |
54988651 ps |
| T356 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2951178524 |
|
|
Jan 07 01:42:20 PM PST 24 |
Jan 07 01:42:36 PM PST 24 |
15685628 ps |
| T357 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2530572802 |
|
|
Jan 07 01:41:30 PM PST 24 |
Jan 07 01:41:41 PM PST 24 |
14766024 ps |
| T358 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.47156047 |
|
|
Jan 07 01:43:04 PM PST 24 |
Jan 07 01:43:20 PM PST 24 |
288684375 ps |
| T359 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.528734398 |
|
|
Jan 07 01:41:38 PM PST 24 |
Jan 07 01:41:49 PM PST 24 |
91253939 ps |
| T360 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1930920572 |
|
|
Jan 07 01:42:37 PM PST 24 |
Jan 07 01:42:58 PM PST 24 |
18788075 ps |
| T361 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1788193680 |
|
|
Jan 07 01:42:46 PM PST 24 |
Jan 07 01:43:07 PM PST 24 |
28659432 ps |
| T362 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3786630496 |
|
|
Jan 07 01:42:07 PM PST 24 |
Jan 07 01:42:19 PM PST 24 |
1061680233 ps |
| T363 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3221114130 |
|
|
Jan 07 01:41:55 PM PST 24 |
Jan 07 01:42:11 PM PST 24 |
1434965930 ps |
| T364 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.728776108 |
|
|
Jan 07 01:41:30 PM PST 24 |
Jan 07 01:41:37 PM PST 24 |
28509996 ps |
| T365 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3659440748 |
|
|
Jan 07 01:43:05 PM PST 24 |
Jan 07 01:43:20 PM PST 24 |
680617321 ps |
| T366 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.478437455 |
|
|
Jan 07 01:42:04 PM PST 24 |
Jan 07 01:43:54 PM PST 24 |
14703246461 ps |
| T367 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1313727142 |
|
|
Jan 07 01:41:27 PM PST 24 |
Jan 07 01:41:34 PM PST 24 |
247892511 ps |
| T368 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2821011051 |
|
|
Jan 07 01:42:02 PM PST 24 |
Jan 07 01:42:12 PM PST 24 |
171225884 ps |
| T369 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2736494686 |
|
|
Jan 07 01:42:20 PM PST 24 |
Jan 07 01:42:41 PM PST 24 |
1948094880 ps |
| T370 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1864649324 |
|
|
Jan 07 01:43:12 PM PST 24 |
Jan 07 01:43:26 PM PST 24 |
27700378 ps |
| T371 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1215601745 |
|
|
Jan 07 01:42:37 PM PST 24 |
Jan 07 01:42:58 PM PST 24 |
46284342 ps |
| T372 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1607552082 |
|
|
Jan 07 01:41:40 PM PST 24 |
Jan 07 01:42:01 PM PST 24 |
1434927852 ps |
| T373 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.2132859478 |
|
|
Jan 07 01:00:35 PM PST 24 |
Jan 07 01:04:23 PM PST 24 |
5431686538 ps |
| T374 |
/workspace/coverage/default/35.sram_ctrl_executable.4195517628 |
|
|
Jan 07 01:00:10 PM PST 24 |
Jan 07 01:22:23 PM PST 24 |
20629403659 ps |
| T375 |
/workspace/coverage/default/36.sram_ctrl_executable.3628482059 |
|
|
Jan 07 01:00:10 PM PST 24 |
Jan 07 01:42:06 PM PST 24 |
120337063210 ps |
| T376 |
/workspace/coverage/default/48.sram_ctrl_alert_test.2238591908 |
|
|
Jan 07 01:01:06 PM PST 24 |
Jan 07 01:02:08 PM PST 24 |
15547482 ps |
| T377 |
/workspace/coverage/default/36.sram_ctrl_stress_all.2847234406 |
|
|
Jan 07 01:00:47 PM PST 24 |
Jan 07 03:01:02 PM PST 24 |
1528359060123 ps |
| T378 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.3416747047 |
|
|
Jan 07 01:00:14 PM PST 24 |
Jan 07 01:03:09 PM PST 24 |
12908010329 ps |
| T379 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.19462229 |
|
|
Jan 07 01:00:12 PM PST 24 |
Jan 07 01:03:02 PM PST 24 |
23447620055 ps |
| T380 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.1132571983 |
|
|
Jan 07 12:59:59 PM PST 24 |
Jan 07 01:02:27 PM PST 24 |
3994238711 ps |
| T381 |
/workspace/coverage/default/25.sram_ctrl_executable.1321659370 |
|
|
Jan 07 12:59:58 PM PST 24 |
Jan 07 01:12:03 PM PST 24 |
16327680285 ps |
| T382 |
/workspace/coverage/default/4.sram_ctrl_partial_access.4220488768 |
|
|
Jan 07 12:58:28 PM PST 24 |
Jan 07 01:00:49 PM PST 24 |
4427111797 ps |
| T383 |
/workspace/coverage/default/38.sram_ctrl_smoke.2493563850 |
|
|
Jan 07 01:00:54 PM PST 24 |
Jan 07 01:03:49 PM PST 24 |
465927063 ps |
| T384 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.4277988009 |
|
|
Jan 07 01:01:05 PM PST 24 |
Jan 07 01:04:40 PM PST 24 |
821193538 ps |
| T385 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2309461255 |
|
|
Jan 07 01:01:06 PM PST 24 |
Jan 07 01:08:24 PM PST 24 |
5927366417 ps |
| T386 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1504320718 |
|
|
Jan 07 01:01:16 PM PST 24 |
Jan 07 01:02:00 PM PST 24 |
370751840 ps |
| T387 |
/workspace/coverage/default/34.sram_ctrl_smoke.4189714256 |
|
|
Jan 07 01:00:21 PM PST 24 |
Jan 07 01:02:23 PM PST 24 |
843427687 ps |
| T388 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.3625322816 |
|
|
Jan 07 01:00:16 PM PST 24 |
Jan 07 01:17:15 PM PST 24 |
28918918609 ps |
| T389 |
/workspace/coverage/default/17.sram_ctrl_executable.612680503 |
|
|
Jan 07 12:59:49 PM PST 24 |
Jan 07 01:03:37 PM PST 24 |
5615942576 ps |
| T390 |
/workspace/coverage/default/12.sram_ctrl_bijection.1988879671 |
|
|
Jan 07 12:59:06 PM PST 24 |
Jan 07 01:18:42 PM PST 24 |
22213935396 ps |
| T391 |
/workspace/coverage/default/39.sram_ctrl_partial_access.4194164304 |
|
|
Jan 07 01:00:52 PM PST 24 |
Jan 07 01:02:10 PM PST 24 |
933302646 ps |
| T392 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3709509708 |
|
|
Jan 07 01:00:29 PM PST 24 |
Jan 07 01:02:23 PM PST 24 |
730407024 ps |
| T393 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.1955708862 |
|
|
Jan 07 01:00:38 PM PST 24 |
Jan 07 01:02:07 PM PST 24 |
2790588482 ps |
| T394 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3359123706 |
|
|
Jan 07 01:01:06 PM PST 24 |
Jan 07 01:02:04 PM PST 24 |
1860957347 ps |
| T395 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.2922328732 |
|
|
Jan 07 01:00:19 PM PST 24 |
Jan 07 01:01:51 PM PST 24 |
1402266838 ps |
| T396 |
/workspace/coverage/default/30.sram_ctrl_alert_test.3177399072 |
|
|
Jan 07 01:00:23 PM PST 24 |
Jan 07 01:01:51 PM PST 24 |
10373110 ps |
| T397 |
/workspace/coverage/default/43.sram_ctrl_bijection.277792947 |
|
|
Jan 07 01:00:27 PM PST 24 |
Jan 07 01:36:18 PM PST 24 |
91225223120 ps |
| T398 |
/workspace/coverage/default/46.sram_ctrl_regwen.2428435909 |
|
|
Jan 07 01:01:08 PM PST 24 |
Jan 07 01:14:44 PM PST 24 |
51250616524 ps |
| T399 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.3410343796 |
|
|
Jan 07 12:58:55 PM PST 24 |
Jan 07 01:06:07 PM PST 24 |
17457281699 ps |
| T400 |
/workspace/coverage/default/31.sram_ctrl_partial_access.3647422313 |
|
|
Jan 07 01:00:28 PM PST 24 |
Jan 07 01:02:37 PM PST 24 |
5882895396 ps |
| T401 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1347219579 |
|
|
Jan 07 01:01:09 PM PST 24 |
Jan 07 02:34:32 PM PST 24 |
2659135232 ps |
| T402 |
/workspace/coverage/default/14.sram_ctrl_stress_all.2054745834 |
|
|
Jan 07 12:59:35 PM PST 24 |
Jan 07 02:35:14 PM PST 24 |
777288061863 ps |
| T403 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.3099003284 |
|
|
Jan 07 01:00:27 PM PST 24 |
Jan 07 01:02:17 PM PST 24 |
691623428 ps |
| T404 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1354850668 |
|
|
Jan 07 12:59:02 PM PST 24 |
Jan 07 01:35:08 PM PST 24 |
193234536569 ps |
| T405 |
/workspace/coverage/default/25.sram_ctrl_regwen.1696242026 |
|
|
Jan 07 12:59:58 PM PST 24 |
Jan 07 01:26:04 PM PST 24 |
9182552632 ps |
| T406 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.3185105379 |
|
|
Jan 07 12:59:48 PM PST 24 |
Jan 07 01:06:37 PM PST 24 |
28213612753 ps |
| T407 |
/workspace/coverage/default/33.sram_ctrl_alert_test.3602852479 |
|
|
Jan 07 01:00:35 PM PST 24 |
Jan 07 01:01:46 PM PST 24 |
14088652 ps |
| T408 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1312196455 |
|
|
Jan 07 12:58:53 PM PST 24 |
Jan 07 01:04:13 PM PST 24 |
8066494029 ps |
| T409 |
/workspace/coverage/default/22.sram_ctrl_regwen.3142558103 |
|
|
Jan 07 12:59:55 PM PST 24 |
Jan 07 01:05:54 PM PST 24 |
16650415495 ps |
| T410 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.1214766555 |
|
|
Jan 07 01:00:15 PM PST 24 |
Jan 07 01:02:00 PM PST 24 |
362782341 ps |
| T411 |
/workspace/coverage/default/0.sram_ctrl_executable.352151721 |
|
|
Jan 07 12:59:00 PM PST 24 |
Jan 07 01:13:46 PM PST 24 |
100851804099 ps |
| T412 |
/workspace/coverage/default/17.sram_ctrl_regwen.2875443635 |
|
|
Jan 07 12:59:47 PM PST 24 |
Jan 07 01:09:35 PM PST 24 |
6359773074 ps |
| T413 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.2005471572 |
|
|
Jan 07 01:00:54 PM PST 24 |
Jan 07 01:03:39 PM PST 24 |
20272213891 ps |
| T414 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.3326619453 |
|
|
Jan 07 01:00:45 PM PST 24 |
Jan 07 01:04:26 PM PST 24 |
26047211926 ps |
| T415 |
/workspace/coverage/default/24.sram_ctrl_bijection.498010779 |
|
|
Jan 07 01:00:15 PM PST 24 |
Jan 07 01:34:49 PM PST 24 |
110988385867 ps |
| T416 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.636215393 |
|
|
Jan 07 12:59:47 PM PST 24 |
Jan 07 01:05:34 PM PST 24 |
5330036205 ps |
| T417 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.2789030535 |
|
|
Jan 07 01:00:49 PM PST 24 |
Jan 07 01:01:50 PM PST 24 |
1413152846 ps |
| T418 |
/workspace/coverage/default/47.sram_ctrl_stress_all.3351195397 |
|
|
Jan 07 01:01:20 PM PST 24 |
Jan 07 02:36:46 PM PST 24 |
1052143307487 ps |
| T419 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.1195731213 |
|
|
Jan 07 01:00:08 PM PST 24 |
Jan 07 01:03:07 PM PST 24 |
8204780235 ps |
| T420 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.1885433461 |
|
|
Jan 07 01:00:42 PM PST 24 |
Jan 07 01:01:54 PM PST 24 |
1408879690 ps |
| T421 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.3280456980 |
|
|
Jan 07 01:00:27 PM PST 24 |
Jan 07 01:03:57 PM PST 24 |
4113098233 ps |
| T422 |
/workspace/coverage/default/4.sram_ctrl_smoke.3579570747 |
|
|
Jan 07 12:58:29 PM PST 24 |
Jan 07 01:00:17 PM PST 24 |
659893874 ps |
| T423 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.971042324 |
|
|
Jan 07 12:59:53 PM PST 24 |
Jan 07 01:02:24 PM PST 24 |
708290076 ps |
| T424 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.2296809008 |
|
|
Jan 07 12:59:56 PM PST 24 |
Jan 07 01:03:52 PM PST 24 |
3156125547 ps |
| T425 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.2329938663 |
|
|
Jan 07 01:00:55 PM PST 24 |
Jan 07 01:02:15 PM PST 24 |
3023767910 ps |
| T426 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.2585953293 |
|
|
Jan 07 12:59:48 PM PST 24 |
Jan 07 01:07:12 PM PST 24 |
4377987824 ps |
| T427 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1243367929 |
|
|
Jan 07 01:01:23 PM PST 24 |
Jan 07 01:06:22 PM PST 24 |
3197244546 ps |
| T428 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1097233279 |
|
|
Jan 07 12:59:50 PM PST 24 |
Jan 07 01:40:39 PM PST 24 |
599406443 ps |
| T429 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1223236690 |
|
|
Jan 07 01:00:00 PM PST 24 |
Jan 07 01:08:35 PM PST 24 |
25363078764 ps |
| T430 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.829517114 |
|
|
Jan 07 01:00:06 PM PST 24 |
Jan 07 01:03:06 PM PST 24 |
14681274511 ps |
| T431 |
/workspace/coverage/default/20.sram_ctrl_regwen.1722900428 |
|
|
Jan 07 12:59:43 PM PST 24 |
Jan 07 01:20:04 PM PST 24 |
52896040825 ps |
| T432 |
/workspace/coverage/default/40.sram_ctrl_bijection.4138149406 |
|
|
Jan 07 01:00:51 PM PST 24 |
Jan 07 01:11:01 PM PST 24 |
30259574781 ps |
| T433 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.2038152699 |
|
|
Jan 07 01:00:10 PM PST 24 |
Jan 07 01:04:41 PM PST 24 |
10369706206 ps |
| T434 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.782278211 |
|
|
Jan 07 01:00:12 PM PST 24 |
Jan 07 01:02:29 PM PST 24 |
733521371 ps |
| T435 |
/workspace/coverage/default/14.sram_ctrl_partial_access.3663339640 |
|
|
Jan 07 12:59:32 PM PST 24 |
Jan 07 01:02:41 PM PST 24 |
622128687 ps |
| T436 |
/workspace/coverage/default/46.sram_ctrl_partial_access.2093520781 |
|
|
Jan 07 01:01:18 PM PST 24 |
Jan 07 01:02:11 PM PST 24 |
590637577 ps |
| T437 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.717274140 |
|
|
Jan 07 01:01:04 PM PST 24 |
Jan 07 01:10:21 PM PST 24 |
39647626903 ps |
| T438 |
/workspace/coverage/default/49.sram_ctrl_bijection.4293334615 |
|
|
Jan 07 01:01:15 PM PST 24 |
Jan 07 01:47:41 PM PST 24 |
634206530719 ps |
| T439 |
/workspace/coverage/default/35.sram_ctrl_regwen.1083009313 |
|
|
Jan 07 01:00:52 PM PST 24 |
Jan 07 01:19:28 PM PST 24 |
64953950407 ps |
| T440 |
/workspace/coverage/default/41.sram_ctrl_alert_test.399853504 |
|
|
Jan 07 01:01:15 PM PST 24 |
Jan 07 01:01:55 PM PST 24 |
15144201 ps |
| T441 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.391463080 |
|
|
Jan 07 12:59:35 PM PST 24 |
Jan 07 01:02:51 PM PST 24 |
956912054 ps |
| T442 |
/workspace/coverage/default/8.sram_ctrl_bijection.3770560690 |
|
|
Jan 07 12:58:57 PM PST 24 |
Jan 07 01:29:06 PM PST 24 |
22886442688 ps |
| T443 |
/workspace/coverage/default/44.sram_ctrl_bijection.4154238109 |
|
|
Jan 07 01:01:11 PM PST 24 |
Jan 07 01:12:50 PM PST 24 |
9522565178 ps |
| T444 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.3938803437 |
|
|
Jan 07 12:59:40 PM PST 24 |
Jan 07 01:06:22 PM PST 24 |
55047877361 ps |
| T445 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.3667534636 |
|
|
Jan 07 01:00:59 PM PST 24 |
Jan 07 01:04:36 PM PST 24 |
37543555280 ps |
| T446 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.3879126407 |
|
|
Jan 07 01:00:07 PM PST 24 |
Jan 07 01:03:56 PM PST 24 |
1573068566 ps |
| T447 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.1391052639 |
|
|
Jan 07 01:01:08 PM PST 24 |
Jan 07 01:02:07 PM PST 24 |
707022881 ps |
| T448 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.1018482912 |
|
|
Jan 07 01:01:04 PM PST 24 |
Jan 07 01:02:45 PM PST 24 |
3034013329 ps |
| T449 |
/workspace/coverage/default/23.sram_ctrl_smoke.1840097494 |
|
|
Jan 07 12:59:41 PM PST 24 |
Jan 07 01:02:03 PM PST 24 |
2588020202 ps |
| T450 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2874446239 |
|
|
Jan 07 12:58:28 PM PST 24 |
Jan 07 01:00:04 PM PST 24 |
357207808 ps |
| T451 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3824957817 |
|
|
Jan 07 01:01:15 PM PST 24 |
Jan 07 01:48:18 PM PST 24 |
950968307 ps |
| T452 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.215337995 |
|
|
Jan 07 12:59:59 PM PST 24 |
Jan 07 01:02:33 PM PST 24 |
679075321 ps |
| T453 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.2546102446 |
|
|
Jan 07 01:01:20 PM PST 24 |
Jan 07 01:03:47 PM PST 24 |
4117516175 ps |
| T454 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1631914653 |
|
|
Jan 07 01:01:03 PM PST 24 |
Jan 07 01:15:25 PM PST 24 |
25866209898 ps |
| T455 |
/workspace/coverage/default/34.sram_ctrl_executable.2324031593 |
|
|
Jan 07 01:00:31 PM PST 24 |
Jan 07 01:05:15 PM PST 24 |
2388547129 ps |
| T456 |
/workspace/coverage/default/17.sram_ctrl_alert_test.3081966021 |
|
|
Jan 07 12:59:42 PM PST 24 |
Jan 07 01:01:49 PM PST 24 |
21474345 ps |
| T457 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.2125475067 |
|
|
Jan 07 01:00:25 PM PST 24 |
Jan 07 01:06:25 PM PST 24 |
57453448137 ps |
| T458 |
/workspace/coverage/default/31.sram_ctrl_bijection.3911651318 |
|
|
Jan 07 01:00:46 PM PST 24 |
Jan 07 01:21:41 PM PST 24 |
23608913309 ps |
| T459 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.3332587055 |
|
|
Jan 07 01:00:55 PM PST 24 |
Jan 07 01:06:44 PM PST 24 |
3939435710 ps |
| T460 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1765045680 |
|
|
Jan 07 01:00:48 PM PST 24 |
Jan 07 01:52:50 PM PST 24 |
1701115131 ps |
| T461 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.77483591 |
|
|
Jan 07 01:00:47 PM PST 24 |
Jan 07 01:03:07 PM PST 24 |
2995585439 ps |
| T462 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.1614635232 |
|
|
Jan 07 01:01:03 PM PST 24 |
Jan 07 01:18:24 PM PST 24 |
17931775325 ps |
| T463 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1709165919 |
|
|
Jan 07 01:00:24 PM PST 24 |
Jan 07 02:20:18 PM PST 24 |
5745385825 ps |
| T464 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.2146715479 |
|
|
Jan 07 12:59:49 PM PST 24 |
Jan 07 01:02:00 PM PST 24 |
1460371719 ps |
| T465 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.859405286 |
|
|
Jan 07 01:00:48 PM PST 24 |
Jan 07 01:11:11 PM PST 24 |
81061244806 ps |
| T466 |
/workspace/coverage/default/26.sram_ctrl_bijection.3538947479 |
|
|
Jan 07 01:00:13 PM PST 24 |
Jan 07 01:26:32 PM PST 24 |
68674514645 ps |
| T467 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.975825964 |
|
|
Jan 07 01:00:16 PM PST 24 |
Jan 07 01:04:36 PM PST 24 |
17827057144 ps |
| T468 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.210200168 |
|
|
Jan 07 01:00:19 PM PST 24 |
Jan 07 01:02:56 PM PST 24 |
1107404832 ps |
| T469 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.564618115 |
|
|
Jan 07 01:00:10 PM PST 24 |
Jan 07 01:14:50 PM PST 24 |
49424060812 ps |
| T470 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.2465479290 |
|
|
Jan 07 01:00:35 PM PST 24 |
Jan 07 01:02:48 PM PST 24 |
1490560552 ps |
| T471 |
/workspace/coverage/default/34.sram_ctrl_partial_access.2003126468 |
|
|
Jan 07 01:00:07 PM PST 24 |
Jan 07 01:02:18 PM PST 24 |
1869970912 ps |
| T472 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2068052901 |
|
|
Jan 07 01:01:16 PM PST 24 |
Jan 07 01:28:35 PM PST 24 |
43483084877 ps |
| T473 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.2278141523 |
|
|
Jan 07 01:00:48 PM PST 24 |
Jan 07 01:15:18 PM PST 24 |
11704556903 ps |
| T474 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1658485436 |
|
|
Jan 07 01:00:27 PM PST 24 |
Jan 07 02:21:13 PM PST 24 |
1534079729 ps |
| T475 |
/workspace/coverage/default/40.sram_ctrl_smoke.2035079645 |
|
|
Jan 07 01:00:45 PM PST 24 |
Jan 07 01:03:04 PM PST 24 |
1609314273 ps |
| T476 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.203174728 |
|
|
Jan 07 01:01:15 PM PST 24 |
Jan 07 01:07:07 PM PST 24 |
13103665562 ps |
| T477 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.3973541021 |
|
|
Jan 07 12:58:50 PM PST 24 |
Jan 07 01:14:15 PM PST 24 |
27175255076 ps |
| T478 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.175315771 |
|
|
Jan 07 01:00:20 PM PST 24 |
Jan 07 01:09:36 PM PST 24 |
18617854897 ps |
| T479 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.2216791147 |
|
|
Jan 07 01:00:12 PM PST 24 |
Jan 07 01:02:28 PM PST 24 |
7283920178 ps |
| T480 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.59703220 |
|
|
Jan 07 01:00:08 PM PST 24 |
Jan 07 01:04:12 PM PST 24 |
783848835 ps |
| T481 |
/workspace/coverage/default/4.sram_ctrl_bijection.1503133415 |
|
|
Jan 07 12:58:28 PM PST 24 |
Jan 07 01:19:13 PM PST 24 |
76514099416 ps |
| T482 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.2706285204 |
|
|
Jan 07 01:00:27 PM PST 24 |
Jan 07 01:07:35 PM PST 24 |
6102600127 ps |
| T483 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.2325816853 |
|
|
Jan 07 01:00:28 PM PST 24 |
Jan 07 01:03:02 PM PST 24 |
954353897 ps |
| T484 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.2882476345 |
|
|
Jan 07 01:00:38 PM PST 24 |
Jan 07 01:04:18 PM PST 24 |
4747083948 ps |
| T485 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.519243842 |
|
|
Jan 07 01:00:49 PM PST 24 |
Jan 07 01:04:21 PM PST 24 |
37331357196 ps |
| T486 |
/workspace/coverage/default/32.sram_ctrl_bijection.2797719402 |
|
|
Jan 07 01:00:53 PM PST 24 |
Jan 07 01:29:26 PM PST 24 |
48871418488 ps |
| T487 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.1341614526 |
|
|
Jan 07 12:58:29 PM PST 24 |
Jan 07 01:03:25 PM PST 24 |
43053999511 ps |
| T488 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.4154333700 |
|
|
Jan 07 12:59:01 PM PST 24 |
Jan 07 01:02:02 PM PST 24 |
708896359 ps |
| T489 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.689084227 |
|
|
Jan 07 01:01:01 PM PST 24 |
Jan 07 01:04:33 PM PST 24 |
18251598688 ps |
| T490 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2110697615 |
|
|
Jan 07 01:01:22 PM PST 24 |
Jan 07 01:16:44 PM PST 24 |
28740123882 ps |
| T491 |
/workspace/coverage/default/47.sram_ctrl_executable.3320607802 |
|
|
Jan 07 01:01:02 PM PST 24 |
Jan 07 01:30:53 PM PST 24 |
48202180518 ps |
| T492 |
/workspace/coverage/default/12.sram_ctrl_executable.3799363570 |
|
|
Jan 07 12:59:49 PM PST 24 |
Jan 07 01:09:56 PM PST 24 |
19436632753 ps |
| T493 |
/workspace/coverage/default/46.sram_ctrl_bijection.2040561931 |
|
|
Jan 07 01:00:55 PM PST 24 |
Jan 07 01:16:54 PM PST 24 |
49554514312 ps |
| T494 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.2330660003 |
|
|
Jan 07 01:00:46 PM PST 24 |
Jan 07 01:04:22 PM PST 24 |
22392770841 ps |
| T495 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.2645948152 |
|
|
Jan 07 12:59:56 PM PST 24 |
Jan 07 01:08:22 PM PST 24 |
7718101273 ps |
| T496 |
/workspace/coverage/default/36.sram_ctrl_regwen.884650035 |
|
|
Jan 07 01:00:57 PM PST 24 |
Jan 07 01:03:33 PM PST 24 |
53996551549 ps |
| T497 |
/workspace/coverage/default/34.sram_ctrl_alert_test.164626610 |
|
|
Jan 07 01:00:47 PM PST 24 |
Jan 07 01:01:57 PM PST 24 |
21462545 ps |
| T498 |
/workspace/coverage/default/32.sram_ctrl_regwen.1698373507 |
|
|
Jan 07 01:01:02 PM PST 24 |
Jan 07 01:14:12 PM PST 24 |
18484711722 ps |
| T499 |
/workspace/coverage/default/45.sram_ctrl_partial_access.2496201036 |
|
|
Jan 07 01:01:12 PM PST 24 |
Jan 07 01:02:38 PM PST 24 |
690009951 ps |
| T500 |
/workspace/coverage/default/23.sram_ctrl_bijection.767492799 |
|
|
Jan 07 01:00:31 PM PST 24 |
Jan 07 01:11:11 PM PST 24 |
32829713106 ps |
| T501 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.2138159360 |
|
|
Jan 07 01:00:09 PM PST 24 |
Jan 07 01:04:03 PM PST 24 |
6907438087 ps |
| T502 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3019820242 |
|
|
Jan 07 01:01:17 PM PST 24 |
Jan 07 01:02:05 PM PST 24 |
710503066 ps |