Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	276367398	1			T1	347742		T2	9918		T3	131448
instr_valid_dis	255228191	1			T1	347742		T2	9918		T3	119964
instr_en	17329432	1			T3	114836		T31	17766		T28	44

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	8149368	1			T3	190710		T31	29678		T37	35488
sram_ifetch_valid_disable	254846940	1			T1	347742		T2	9918		T3	677650
sram_ifetch_enable	13371090	1			T3	446124		T31	42400		T25	75556

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	276367398	1			T1	347742		T2	9918		T3	131448
hw_debug_en_valid_off	253017315	1			T1	347742		T2	9918		T3	902712
hw_debug_en_on	14870637	1			T3	239482		T15	32532		T31	41872

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	254846940	1			T1	347742		T2	9918		T3	677650
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	245046051	1			T1	347742		T2	9918		T3	676398
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8257118	1			T3	1252		T31	17766		T28	44
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	2556770	1			T3	90392		T37	35488		T110	4334
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1030086	1			T3	90392		T37	35488		T110	68
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1126006	1			T115	36514		T114	31866		T122	8036
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	2297618	1			T3	95226		T110	31864		T26	24934
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1162322	1			T3	95226		T108	62358		T112	44778
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	970912	1			T26	24934		T109	29230		T114	53370
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	6790069	1			T3	1252		T15	32532		T31	41872
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	1710470	1			T15	32532		T31	24106		T108	94106
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4574802	1			T3	1252		T31	17766		T26	93840

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	6350342	1			T3	113584		T26	159668		T108	66
lc_exec_en	5782950	1			T3	143004		T25	16142		T37	37366
valid_exec_dis	251411097	1			T1	347742		T2	9918		T3	995696
invalid_exec_dis	21520458	1			T3	636834		T31	72078		T25	75556