Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 100.00 98.27 100.00 100.00 99.71 99.70 100.00


Total tests in report: 970
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
93.28 93.28 98.91 98.91 89.75 89.75 97.94 97.94 100.00 100.00 96.54 96.54 94.95 94.95 74.86 74.86 /workspace/coverage/default/41.sram_ctrl_stress_all.1968982965
95.97 2.69 99.27 0.36 93.94 4.18 98.37 0.43 100.00 0.00 97.41 0.86 96.29 1.34 86.49 11.63 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3871892899
97.21 1.25 99.45 0.18 94.81 0.87 98.93 0.57 100.00 0.00 98.27 0.86 96.73 0.45 92.31 5.82 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3401869283
97.86 0.65 99.64 0.18 96.97 2.16 99.29 0.36 100.00 0.00 99.14 0.86 97.33 0.59 92.68 0.38 /workspace/coverage/default/1.sram_ctrl_sec_cm.847405575
98.26 0.40 99.64 0.00 96.97 0.00 99.29 0.00 100.00 0.00 99.14 0.00 97.33 0.00 95.50 2.81 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.4172093042
98.54 0.27 99.91 0.27 97.11 0.14 99.29 0.00 100.00 0.00 99.71 0.58 97.47 0.15 96.25 0.75 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2917262191
98.75 0.21 99.91 0.00 97.11 0.00 99.29 0.00 100.00 0.00 99.71 0.00 97.47 0.00 97.75 1.50 /workspace/coverage/default/33.sram_ctrl_stress_all.1118370678
98.94 0.19 99.91 0.00 97.11 0.00 99.29 0.00 100.00 0.00 99.71 0.00 98.81 1.34 97.75 0.00 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1155483559
99.11 0.17 99.91 0.00 97.40 0.29 99.29 0.00 100.00 0.00 99.71 0.00 99.70 0.89 97.75 0.00 /workspace/coverage/default/15.sram_ctrl_access_during_key_req.18562150
99.22 0.11 100.00 0.09 97.40 0.00 100.00 0.71 100.00 0.00 99.71 0.00 99.70 0.00 97.75 0.00 /workspace/coverage/default/11.sram_ctrl_ram_cfg.3602040154
99.33 0.11 100.00 0.00 97.40 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.70 0.00 98.50 0.75 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1200388279
99.43 0.10 100.00 0.00 97.55 0.14 100.00 0.00 100.00 0.00 99.71 0.00 99.70 0.00 99.06 0.56 /workspace/coverage/default/29.sram_ctrl_stress_all.1487145275
99.49 0.05 100.00 0.00 97.55 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.70 0.00 99.44 0.38 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1993039499
99.54 0.05 100.00 0.00 97.55 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.70 0.00 99.81 0.38 /workspace/coverage/default/1.sram_ctrl_regwen.3922907652
99.58 0.04 100.00 0.00 97.84 0.29 100.00 0.00 100.00 0.00 99.71 0.00 99.70 0.00 99.81 0.00 /workspace/coverage/default/16.sram_ctrl_alert_test.4114299754
99.61 0.03 100.00 0.00 97.84 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.70 0.00 100.00 0.19 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2367991379
99.63 0.02 100.00 0.00 97.98 0.14 100.00 0.00 100.00 0.00 99.71 0.00 99.70 0.00 100.00 0.00 /workspace/coverage/default/10.sram_ctrl_lc_escalation.184155467

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.215683586
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1673582939
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3246300983
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1975025750
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2109292550
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.359111059
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3518007249
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2065122275
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2604326785
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1016710472
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.269394448
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1158835184
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1280182136
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.265347023
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.427187131
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.525153604
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3710274495
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3472647582
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3422427340
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3114677442
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2527957318
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2652828476
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1923001129
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3493394324
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.583808046
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1613669632
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3848945689
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.445139278
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3541193351
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.293147385
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2403649347
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2690530744
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1949666938
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3814060525
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.29849526
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1778418795
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3757499897
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2648607981
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2022516314
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2827369003
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3939003964
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1001829956
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2753989893
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4267284935
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2159441847
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1764612852
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.840662999
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3736000697
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2221557784
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.645541030
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1465411574
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2606274520
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2246734164
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.247969213
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1279044934
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.687167304
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.370126711
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.608030448
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3571664393
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1843808031
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1142735792
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4165448231
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1586406391
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2122576939
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3831877695
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3395046278
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3884539267
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.269881967
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.396963784
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1605608582
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1817278068
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1874297692
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2429306282
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1953578277
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2745840567
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.908322250
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2920631246
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2967579671
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3321844236
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3101703568
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1920555062
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.239999513
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3992412907
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1014916296
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2706427514
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.48694027
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2070251772
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2092235927
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3939612108
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1309729383
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3734348929
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2806347076
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4191240717
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.600589065
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1859504709
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3546405600
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1251351703
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2897190050
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3653457897
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2283161666
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2088186050
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1827794229
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4122516734
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3619350498
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.102386089
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.309874752
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3933895914
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.561866643
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3031525540
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.95646282
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.798438619
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1757529101
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1837676465
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.452429647
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2213962681
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1982181809
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.264530896
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3132828699
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3891889676
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.4005428090
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1939069878
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3380607278
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4291624707
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1929386047
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1796600265
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.716967779
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1501849516
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2729221960
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.952584272
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.180369205
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1115673068
/workspace/coverage/default/0.sram_ctrl_alert_test.1910251717
/workspace/coverage/default/0.sram_ctrl_bijection.1961308298
/workspace/coverage/default/0.sram_ctrl_executable.2234963229
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3327245034
/workspace/coverage/default/0.sram_ctrl_max_throughput.933528442
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.893657463
/workspace/coverage/default/0.sram_ctrl_mem_walk.1140753870
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3705088888
/workspace/coverage/default/0.sram_ctrl_partial_access.995158464
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1366977208
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1947142995
/workspace/coverage/default/0.sram_ctrl_regwen.3745731517
/workspace/coverage/default/0.sram_ctrl_sec_cm.3258514296
/workspace/coverage/default/0.sram_ctrl_smoke.3626634795
/workspace/coverage/default/0.sram_ctrl_stress_all.1874975963
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1305413258
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2582416616
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3544535857
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.285916875
/workspace/coverage/default/1.sram_ctrl_alert_test.2177624103
/workspace/coverage/default/1.sram_ctrl_bijection.1899549816
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1757750115
/workspace/coverage/default/1.sram_ctrl_max_throughput.2050092425
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2681133792
/workspace/coverage/default/1.sram_ctrl_mem_walk.4071614964
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2760555033
/workspace/coverage/default/1.sram_ctrl_partial_access.723539540
/workspace/coverage/default/1.sram_ctrl_ram_cfg.1365599305
/workspace/coverage/default/1.sram_ctrl_smoke.732700841
/workspace/coverage/default/1.sram_ctrl_stress_all.871359900
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1203610046
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1496484395
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.94854546
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2997676520
/workspace/coverage/default/10.sram_ctrl_alert_test.4287563937
/workspace/coverage/default/10.sram_ctrl_bijection.3334947561
/workspace/coverage/default/10.sram_ctrl_executable.153363878
/workspace/coverage/default/10.sram_ctrl_max_throughput.1073217547
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2356613420
/workspace/coverage/default/10.sram_ctrl_mem_walk.3245833286
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1369286121
/workspace/coverage/default/10.sram_ctrl_partial_access.1775282230
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1333285430
/workspace/coverage/default/10.sram_ctrl_ram_cfg.647103853
/workspace/coverage/default/10.sram_ctrl_regwen.217249235
/workspace/coverage/default/10.sram_ctrl_smoke.2491698497
/workspace/coverage/default/10.sram_ctrl_stress_all.2184420098
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3438380449
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2485774168
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.210994100
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.453291746
/workspace/coverage/default/11.sram_ctrl_alert_test.1325331893
/workspace/coverage/default/11.sram_ctrl_bijection.2991012941
/workspace/coverage/default/11.sram_ctrl_lc_escalation.3482753250
/workspace/coverage/default/11.sram_ctrl_max_throughput.3425141943
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.2729938314
/workspace/coverage/default/11.sram_ctrl_mem_walk.92528818
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3662240113
/workspace/coverage/default/11.sram_ctrl_partial_access.772954637
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.791973929
/workspace/coverage/default/11.sram_ctrl_smoke.1401714738
/workspace/coverage/default/11.sram_ctrl_stress_all.898578081
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3868303566
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3434694931
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1662000793
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.1899873180
/workspace/coverage/default/12.sram_ctrl_alert_test.1354458125
/workspace/coverage/default/12.sram_ctrl_bijection.198001683
/workspace/coverage/default/12.sram_ctrl_executable.983433600
/workspace/coverage/default/12.sram_ctrl_max_throughput.657869731
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2525823357
/workspace/coverage/default/12.sram_ctrl_mem_walk.309263168
/workspace/coverage/default/12.sram_ctrl_multiple_keys.1648358006
/workspace/coverage/default/12.sram_ctrl_partial_access.370854715
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2442313992
/workspace/coverage/default/12.sram_ctrl_ram_cfg.796273751
/workspace/coverage/default/12.sram_ctrl_regwen.825772745
/workspace/coverage/default/12.sram_ctrl_smoke.1567310201
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3231508443
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.2972776827
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.597962044
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/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.648813015
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1066712795
/workspace/coverage/default/46.sram_ctrl_alert_test.1636460566
/workspace/coverage/default/46.sram_ctrl_bijection.2194833615
/workspace/coverage/default/46.sram_ctrl_executable.3029450977
/workspace/coverage/default/46.sram_ctrl_lc_escalation.2981538695
/workspace/coverage/default/46.sram_ctrl_max_throughput.3428941748
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1128628750
/workspace/coverage/default/46.sram_ctrl_mem_walk.2700813670
/workspace/coverage/default/46.sram_ctrl_multiple_keys.2890826222
/workspace/coverage/default/46.sram_ctrl_partial_access.3822997840
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1315834746
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3352617199
/workspace/coverage/default/46.sram_ctrl_regwen.1770163993
/workspace/coverage/default/46.sram_ctrl_smoke.3219056332
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3172723502
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.421086552
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2588309235
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1770501024
/workspace/coverage/default/47.sram_ctrl_alert_test.3645947948
/workspace/coverage/default/47.sram_ctrl_bijection.3934273913
/workspace/coverage/default/47.sram_ctrl_lc_escalation.1582656911
/workspace/coverage/default/47.sram_ctrl_max_throughput.1722351477
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3890530624
/workspace/coverage/default/47.sram_ctrl_mem_walk.915028102
/workspace/coverage/default/47.sram_ctrl_multiple_keys.878153429
/workspace/coverage/default/47.sram_ctrl_partial_access.87470455
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2624607583
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2133254368
/workspace/coverage/default/47.sram_ctrl_regwen.404571054
/workspace/coverage/default/47.sram_ctrl_smoke.3212811195
/workspace/coverage/default/47.sram_ctrl_stress_all.4094124573
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2129403675
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2004186627
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1596065353
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.2204280685
/workspace/coverage/default/48.sram_ctrl_alert_test.2888400549
/workspace/coverage/default/48.sram_ctrl_bijection.383520085
/workspace/coverage/default/48.sram_ctrl_executable.2304971775
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1229629004
/workspace/coverage/default/48.sram_ctrl_max_throughput.2961463217
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.4284403857
/workspace/coverage/default/48.sram_ctrl_mem_walk.2789904799
/workspace/coverage/default/48.sram_ctrl_multiple_keys.1077972270
/workspace/coverage/default/48.sram_ctrl_partial_access.1184078715
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.955519033
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2355917381
/workspace/coverage/default/48.sram_ctrl_regwen.2863581583
/workspace/coverage/default/48.sram_ctrl_smoke.2898205234
/workspace/coverage/default/48.sram_ctrl_stress_all.1953927979
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.321599353
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.41027166
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1745079014
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1806808755
/workspace/coverage/default/49.sram_ctrl_alert_test.666935029
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2211618253
/workspace/coverage/default/49.sram_ctrl_max_throughput.1913624795
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.345219656
/workspace/coverage/default/49.sram_ctrl_mem_walk.2160696703
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1481080848
/workspace/coverage/default/49.sram_ctrl_partial_access.3471243028
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3095454630
/workspace/coverage/default/49.sram_ctrl_ram_cfg.1860474506
/workspace/coverage/default/49.sram_ctrl_regwen.2985268413
/workspace/coverage/default/49.sram_ctrl_smoke.3235034900
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.214571261
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.720679141
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.4031177241
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1704792105
/workspace/coverage/default/5.sram_ctrl_alert_test.2369161571
/workspace/coverage/default/5.sram_ctrl_bijection.3441995019
/workspace/coverage/default/5.sram_ctrl_max_throughput.389635410
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.4140206340
/workspace/coverage/default/5.sram_ctrl_mem_walk.2856365282
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2588062483
/workspace/coverage/default/5.sram_ctrl_partial_access.2686231217
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3220951993
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1806227739
/workspace/coverage/default/5.sram_ctrl_regwen.372010396
/workspace/coverage/default/5.sram_ctrl_smoke.1555618485
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4218954054
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.4018727553
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.915472782
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.341895051
/workspace/coverage/default/6.sram_ctrl_alert_test.603748026
/workspace/coverage/default/6.sram_ctrl_bijection.541873981
/workspace/coverage/default/6.sram_ctrl_lc_escalation.66391422
/workspace/coverage/default/6.sram_ctrl_max_throughput.3608730531
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3507945047
/workspace/coverage/default/6.sram_ctrl_mem_walk.3455863196
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1797652454
/workspace/coverage/default/6.sram_ctrl_partial_access.2849531262
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1117017383
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2679322594
/workspace/coverage/default/6.sram_ctrl_regwen.948510193
/workspace/coverage/default/6.sram_ctrl_smoke.3856496586
/workspace/coverage/default/6.sram_ctrl_stress_all.3750991697
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1623031368
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3834076715
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1239654970
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3649932855
/workspace/coverage/default/7.sram_ctrl_alert_test.694952824
/workspace/coverage/default/7.sram_ctrl_bijection.1491353660
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2940569686
/workspace/coverage/default/7.sram_ctrl_max_throughput.2030229319
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.792872457
/workspace/coverage/default/7.sram_ctrl_mem_walk.2350801636
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3948868132
/workspace/coverage/default/7.sram_ctrl_partial_access.2831912743
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.4040513980
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3402089152
/workspace/coverage/default/7.sram_ctrl_regwen.1979547101
/workspace/coverage/default/7.sram_ctrl_smoke.2416454643
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1010595551
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1980828383
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.954848476
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3811453630
/workspace/coverage/default/8.sram_ctrl_alert_test.2370849867
/workspace/coverage/default/8.sram_ctrl_executable.2425643009
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3398968644
/workspace/coverage/default/8.sram_ctrl_max_throughput.2227843578
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.4233225401
/workspace/coverage/default/8.sram_ctrl_mem_walk.2891767920
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1525583476
/workspace/coverage/default/8.sram_ctrl_partial_access.852191049
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3373236843
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2128845892
/workspace/coverage/default/8.sram_ctrl_regwen.3378771520
/workspace/coverage/default/8.sram_ctrl_smoke.1808318382
/workspace/coverage/default/8.sram_ctrl_stress_all.2117381724
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.4196419675
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3234769497
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2416509491
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.2926757477
/workspace/coverage/default/9.sram_ctrl_alert_test.890020247
/workspace/coverage/default/9.sram_ctrl_bijection.4173726323
/workspace/coverage/default/9.sram_ctrl_max_throughput.957847992
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.3780676442
/workspace/coverage/default/9.sram_ctrl_mem_walk.408966145
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3667701015
/workspace/coverage/default/9.sram_ctrl_partial_access.3557694007
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.592860324
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3972320821
/workspace/coverage/default/9.sram_ctrl_regwen.1807168636
/workspace/coverage/default/9.sram_ctrl_smoke.1994926934
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3901821450
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.3158269088
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2253947048



Total test records in report: 970
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.336703565 Jan 10 01:28:18 PM PST 24 Jan 10 01:33:23 PM PST 24 14057055653 ps
T2 /workspace/coverage/default/46.sram_ctrl_partial_access.3822997840 Jan 10 01:28:52 PM PST 24 Jan 10 01:29:51 PM PST 24 3897823582 ps
T3 /workspace/coverage/default/41.sram_ctrl_stress_all.1968982965 Jan 10 01:27:59 PM PST 24 Jan 10 02:47:59 PM PST 24 322520915826 ps
T7 /workspace/coverage/default/24.sram_ctrl_partial_access.4240355024 Jan 10 01:26:57 PM PST 24 Jan 10 01:28:03 PM PST 24 1065193937 ps
T8 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.3234769497 Jan 10 01:26:25 PM PST 24 Jan 10 01:30:42 PM PST 24 3467644235 ps
T9 /workspace/coverage/default/17.sram_ctrl_bijection.3543755012 Jan 10 01:26:53 PM PST 24 Jan 10 02:02:56 PM PST 24 431004546518 ps
T10 /workspace/coverage/default/39.sram_ctrl_max_throughput.1178071705 Jan 10 01:28:52 PM PST 24 Jan 10 01:30:26 PM PST 24 1474575771 ps
T11 /workspace/coverage/default/48.sram_ctrl_multiple_keys.1077972270 Jan 10 01:30:46 PM PST 24 Jan 10 01:58:19 PM PST 24 92873955696 ps
T12 /workspace/coverage/default/5.sram_ctrl_ram_cfg.1806227739 Jan 10 01:26:29 PM PST 24 Jan 10 01:26:48 PM PST 24 684779426 ps
T13 /workspace/coverage/default/42.sram_ctrl_multiple_keys.1511119798 Jan 10 01:28:01 PM PST 24 Jan 10 01:54:39 PM PST 24 22797011548 ps
T14 /workspace/coverage/default/38.sram_ctrl_partial_access.905695654 Jan 10 01:28:21 PM PST 24 Jan 10 01:29:31 PM PST 24 1254872266 ps
T15 /workspace/coverage/default/1.sram_ctrl_regwen.3922907652 Jan 10 01:26:01 PM PST 24 Jan 10 01:27:15 PM PST 24 8603628442 ps
T123 /workspace/coverage/default/15.sram_ctrl_bijection.3633824388 Jan 10 01:26:58 PM PST 24 Jan 10 01:54:38 PM PST 24 24955082114 ps
T16 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3871892899 Jan 10 01:26:57 PM PST 24 Jan 10 02:53:05 PM PST 24 1295658906 ps
T54 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1494375514 Jan 10 01:26:55 PM PST 24 Jan 10 01:28:24 PM PST 24 9759567730 ps
T41 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.1282180527 Jan 10 01:28:12 PM PST 24 Jan 10 01:33:20 PM PST 24 54201323751 ps
T55 /workspace/coverage/default/48.sram_ctrl_bijection.383520085 Jan 10 01:30:44 PM PST 24 Jan 10 02:09:20 PM PST 24 30496991685 ps
T56 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.3657348734 Jan 10 01:28:01 PM PST 24 Jan 10 01:36:21 PM PST 24 7756236598 ps
T20 /workspace/coverage/default/17.sram_ctrl_alert_test.25929883 Jan 10 01:27:02 PM PST 24 Jan 10 01:27:14 PM PST 24 12475752 ps
T57 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2972776827 Jan 10 01:26:50 PM PST 24 Jan 10 01:33:15 PM PST 24 5126746346 ps
T91 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1496484395 Jan 10 01:26:07 PM PST 24 Jan 10 01:32:33 PM PST 24 19869273967 ps
T124 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.954848476 Jan 10 01:26:56 PM PST 24 Jan 10 01:27:37 PM PST 24 2847895209 ps
T125 /workspace/coverage/default/31.sram_ctrl_max_throughput.3223207587 Jan 10 01:28:19 PM PST 24 Jan 10 01:31:02 PM PST 24 955348515 ps
T126 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1244328247 Jan 10 01:28:15 PM PST 24 Jan 10 01:30:15 PM PST 24 1485839923 ps
T31 /workspace/coverage/default/7.sram_ctrl_regwen.1979547101 Jan 10 01:26:55 PM PST 24 Jan 10 01:34:39 PM PST 24 1632580704 ps
T66 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.3507945047 Jan 10 01:26:32 PM PST 24 Jan 10 01:28:01 PM PST 24 4800864320 ps
T32 /workspace/coverage/default/11.sram_ctrl_ram_cfg.3602040154 Jan 10 01:26:46 PM PST 24 Jan 10 01:27:06 PM PST 24 1707380145 ps
T72 /workspace/coverage/default/48.sram_ctrl_max_throughput.2961463217 Jan 10 01:30:42 PM PST 24 Jan 10 01:31:43 PM PST 24 734165410 ps
T25 /workspace/coverage/default/26.sram_ctrl_regwen.488480783 Jan 10 01:27:20 PM PST 24 Jan 10 01:30:36 PM PST 24 14808925740 ps
T6 /workspace/coverage/default/1.sram_ctrl_sec_cm.847405575 Jan 10 01:25:58 PM PST 24 Jan 10 01:26:15 PM PST 24 322687788 ps
T36 /workspace/coverage/default/37.sram_ctrl_partial_access.2204707569 Jan 10 01:28:13 PM PST 24 Jan 10 01:29:36 PM PST 24 2116044544 ps
T37 /workspace/coverage/default/8.sram_ctrl_regwen.3378771520 Jan 10 01:26:34 PM PST 24 Jan 10 01:29:48 PM PST 24 9097459615 ps
T38 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.4289511764 Jan 10 01:28:16 PM PST 24 Jan 10 01:30:30 PM PST 24 37302621748 ps
T21 /workspace/coverage/default/28.sram_ctrl_alert_test.1489528826 Jan 10 01:29:00 PM PST 24 Jan 10 01:29:23 PM PST 24 18588143 ps
T22 /workspace/coverage/default/24.sram_ctrl_alert_test.853998206 Jan 10 01:26:57 PM PST 24 Jan 10 01:27:10 PM PST 24 14914985 ps
T30 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3814060525 Jan 10 12:53:01 PM PST 24 Jan 10 12:54:15 PM PST 24 208187332 ps
T28 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3401869283 Jan 10 12:53:07 PM PST 24 Jan 10 12:54:19 PM PST 24 259505338 ps
T61 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.359111059 Jan 10 12:52:52 PM PST 24 Jan 10 12:58:43 PM PST 24 28157482617 ps
T62 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.716967779 Jan 10 12:53:07 PM PST 24 Jan 10 12:54:19 PM PST 24 12402660 ps
T63 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3031525540 Jan 10 12:53:02 PM PST 24 Jan 10 12:54:14 PM PST 24 19421471 ps
T90 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2652828476 Jan 10 12:55:07 PM PST 24 Jan 10 12:56:13 PM PST 24 21973728 ps
T29 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1778418795 Jan 10 12:53:12 PM PST 24 Jan 10 12:54:31 PM PST 24 1409717541 ps
T60 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2429306282 Jan 10 12:53:19 PM PST 24 Jan 10 12:54:32 PM PST 24 90348022 ps
T64 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3101703568 Jan 10 12:52:53 PM PST 24 Jan 10 12:54:06 PM PST 24 22642118 ps
T44 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.452429647 Jan 10 12:52:52 PM PST 24 Jan 10 12:54:10 PM PST 24 1656809965 ps
T45 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.840662999 Jan 10 12:53:07 PM PST 24 Jan 10 12:54:25 PM PST 24 2313912143 ps
T65 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1016710472 Jan 10 12:53:02 PM PST 24 Jan 10 12:54:17 PM PST 24 19409305 ps
T42 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3571664393 Jan 10 12:53:19 PM PST 24 Jan 10 12:54:45 PM PST 24 363933467 ps
T43 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2604326785 Jan 10 12:53:00 PM PST 24 Jan 10 12:54:14 PM PST 24 620218664 ps
T67 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1155483559 Jan 10 12:53:07 PM PST 24 Jan 10 12:58:49 PM PST 24 14656444535 ps
T73 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4267284935 Jan 10 12:53:06 PM PST 24 Jan 10 12:54:19 PM PST 24 49395384 ps
T58 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1014916296 Jan 10 12:53:00 PM PST 24 Jan 10 12:54:15 PM PST 24 207344247 ps
T46 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1923001129 Jan 10 12:53:11 PM PST 24 Jan 10 12:54:29 PM PST 24 532003522 ps
T74 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3114677442 Jan 10 12:52:58 PM PST 24 Jan 10 12:54:10 PM PST 24 12985598 ps
T68 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2221557784 Jan 10 12:53:07 PM PST 24 Jan 10 12:59:15 PM PST 24 8107489148 ps
T59 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3132828699 Jan 10 12:53:03 PM PST 24 Jan 10 12:54:17 PM PST 24 204872145 ps
T69 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.908322250 Jan 10 12:52:57 PM PST 24 Jan 10 12:54:11 PM PST 24 20432986 ps
T47 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3939003964 Jan 10 12:53:14 PM PST 24 Jan 10 12:54:31 PM PST 24 2022771697 ps
T98 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1975025750 Jan 10 12:52:59 PM PST 24 Jan 10 12:54:16 PM PST 24 385342342 ps
T70 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3246300983 Jan 10 12:53:05 PM PST 24 Jan 10 12:54:20 PM PST 24 33593387 ps
T127 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1001829956 Jan 10 12:53:06 PM PST 24 Jan 10 12:54:19 PM PST 24 13541078 ps
T92 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3380607278 Jan 10 12:54:49 PM PST 24 Jan 10 12:55:56 PM PST 24 151977776 ps
T71 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2967579671 Jan 10 12:52:52 PM PST 24 Jan 10 12:54:05 PM PST 24 42228964 ps
T48 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2088186050 Jan 10 12:53:05 PM PST 24 Jan 10 12:54:23 PM PST 24 127328313 ps
T128 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4165448231 Jan 10 12:53:13 PM PST 24 Jan 10 12:54:26 PM PST 24 18060487 ps
T129 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.427187131 Jan 10 12:52:50 PM PST 24 Jan 10 12:55:01 PM PST 24 6626357380 ps
T75 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3757499897 Jan 10 12:53:07 PM PST 24 Jan 10 12:54:19 PM PST 24 112622633 ps
T130 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2527957318 Jan 10 12:53:02 PM PST 24 Jan 10 12:56:10 PM PST 24 7240182187 ps
T131 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3653457897 Jan 10 12:53:06 PM PST 24 Jan 10 12:56:18 PM PST 24 7344954458 ps
T76 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3619350498 Jan 10 12:52:52 PM PST 24 Jan 10 12:56:33 PM PST 24 14189425883 ps
T132 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2690530744 Jan 10 12:53:28 PM PST 24 Jan 10 12:56:57 PM PST 24 3838607260 ps
T49 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4191240717 Jan 10 12:53:20 PM PST 24 Jan 10 12:54:34 PM PST 24 683885733 ps
T133 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.269394448 Jan 10 12:53:04 PM PST 24 Jan 10 12:54:15 PM PST 24 261481121 ps
T77 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.265347023 Jan 10 12:53:03 PM PST 24 Jan 10 12:54:15 PM PST 24 27250109 ps
T134 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3891889676 Jan 10 12:52:53 PM PST 24 Jan 10 12:54:12 PM PST 24 1453976066 ps
T50 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1929386047 Jan 10 12:55:07 PM PST 24 Jan 10 12:56:13 PM PST 24 112030254 ps
T78 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1142735792 Jan 10 12:53:12 PM PST 24 Jan 10 12:58:55 PM PST 24 14073058796 ps
T51 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.445139278 Jan 10 12:53:04 PM PST 24 Jan 10 12:54:20 PM PST 24 538479987 ps
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T53 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2606274520 Jan 10 12:53:12 PM PST 24 Jan 10 12:54:25 PM PST 24 417800763 ps
T135 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3422427340 Jan 10 12:53:04 PM PST 24 Jan 10 12:54:22 PM PST 24 371851718 ps
T136 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1859504709 Jan 10 12:53:01 PM PST 24 Jan 10 12:54:13 PM PST 24 139930952 ps
T100 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1764612852 Jan 10 12:53:05 PM PST 24 Jan 10 12:54:21 PM PST 24 339366338 ps
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T138 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.247969213 Jan 10 12:53:13 PM PST 24 Jan 10 12:54:26 PM PST 24 15811632 ps
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T141 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2092235927 Jan 10 12:53:03 PM PST 24 Jan 10 12:54:20 PM PST 24 353817156 ps
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T101 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3472647582 Jan 10 12:52:55 PM PST 24 Jan 10 12:54:09 PM PST 24 499674335 ps
T143 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1796600265 Jan 10 12:53:00 PM PST 24 Jan 10 12:54:25 PM PST 24 373994695 ps
T144 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.608030448 Jan 10 12:53:14 PM PST 24 Jan 10 12:54:28 PM PST 24 415883718 ps
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T84 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3736000697 Jan 10 12:53:07 PM PST 24 Jan 10 12:54:19 PM PST 24 177237877 ps
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T148 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3518007249 Jan 10 12:52:54 PM PST 24 Jan 10 12:54:07 PM PST 24 204000076 ps
T149 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3710274495 Jan 10 12:53:00 PM PST 24 Jan 10 12:54:14 PM PST 24 56167334 ps
T150 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.798438619 Jan 10 12:52:52 PM PST 24 Jan 10 12:54:04 PM PST 24 55897967 ps
T83 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2213962681 Jan 10 12:53:02 PM PST 24 Jan 10 12:54:14 PM PST 24 24427572 ps
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T102 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2367991379 Jan 10 12:53:16 PM PST 24 Jan 10 12:54:31 PM PST 24 628988264 ps
T154 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2648607981 Jan 10 12:53:13 PM PST 24 Jan 10 12:56:55 PM PST 24 23041090712 ps
T155 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3831877695 Jan 10 12:53:17 PM PST 24 Jan 10 12:54:35 PM PST 24 683542903 ps
T85 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3884539267 Jan 10 12:53:14 PM PST 24 Jan 10 12:58:53 PM PST 24 7033593780 ps
T156 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.293147385 Jan 10 12:53:08 PM PST 24 Jan 10 12:54:24 PM PST 24 701725868 ps
T103 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.180369205 Jan 10 12:52:59 PM PST 24 Jan 10 12:54:19 PM PST 24 432822837 ps
T157 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2729221960 Jan 10 12:55:06 PM PST 24 Jan 10 12:56:12 PM PST 24 31275718 ps
T158 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1280182136 Jan 10 12:53:04 PM PST 24 Jan 10 12:54:19 PM PST 24 440254278 ps
T86 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1309729383 Jan 10 12:52:53 PM PST 24 Jan 10 12:54:59 PM PST 24 7434112433 ps
T159 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1843808031 Jan 10 12:53:17 PM PST 24 Jan 10 12:54:31 PM PST 24 11496482 ps
T160 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.4005428090 Jan 10 12:52:58 PM PST 24 Jan 10 12:54:10 PM PST 24 19497896 ps
T87 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1501849516 Jan 10 12:53:12 PM PST 24 Jan 10 12:58:44 PM PST 24 7142653188 ps
T161 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.525153604 Jan 10 12:52:58 PM PST 24 Jan 10 12:54:11 PM PST 24 79920644 ps
T88 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.95646282 Jan 10 12:52:58 PM PST 24 Jan 10 12:58:26 PM PST 24 16046163337 ps
T162 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1586406391 Jan 10 12:53:19 PM PST 24 Jan 10 12:54:33 PM PST 24 38459458 ps
T163 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2753989893 Jan 10 12:53:07 PM PST 24 Jan 10 12:55:17 PM PST 24 7424571871 ps
T164 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2897190050 Jan 10 12:55:07 PM PST 24 Jan 10 12:56:12 PM PST 24 39008128 ps
T165 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1251351703 Jan 10 12:52:55 PM PST 24 Jan 10 12:54:20 PM PST 24 343433038 ps
T166 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3493394324 Jan 10 12:52:58 PM PST 24 Jan 10 12:54:15 PM PST 24 680166284 ps
T167 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.48694027 Jan 10 12:53:01 PM PST 24 Jan 10 12:54:13 PM PST 24 86515489 ps
T168 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1465411574 Jan 10 12:53:13 PM PST 24 Jan 10 12:54:28 PM PST 24 77541495 ps
T104 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1993039499 Jan 10 12:52:58 PM PST 24 Jan 10 12:54:12 PM PST 24 873946305 ps
T169 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2706427514 Jan 10 12:52:56 PM PST 24 Jan 10 12:54:09 PM PST 24 20537467 ps
T170 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.264530896 Jan 10 12:53:03 PM PST 24 Jan 10 12:54:21 PM PST 24 198367220 ps
T171 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1673582939 Jan 10 12:53:00 PM PST 24 Jan 10 12:54:13 PM PST 24 41340673 ps
T172 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2246734164 Jan 10 12:53:15 PM PST 24 Jan 10 12:54:40 PM PST 24 404393094 ps
T173 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1200388279 Jan 10 12:54:49 PM PST 24 Jan 10 12:55:58 PM PST 24 546687069 ps
T174 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1827794229 Jan 10 12:53:00 PM PST 24 Jan 10 12:54:17 PM PST 24 362015140 ps
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T177 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2403649347 Jan 10 12:53:01 PM PST 24 Jan 10 12:54:12 PM PST 24 29595733 ps
T178 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1949666938 Jan 10 12:53:06 PM PST 24 Jan 10 12:54:18 PM PST 24 12716194 ps
T179 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.396963784 Jan 10 12:53:21 PM PST 24 Jan 10 12:54:38 PM PST 24 447057800 ps
T180 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2109292550 Jan 10 12:53:03 PM PST 24 Jan 10 12:54:16 PM PST 24 11967313 ps
T89 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1939069878 Jan 10 12:55:06 PM PST 24 Jan 10 12:58:31 PM PST 24 3859899125 ps
T181 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1279044934 Jan 10 12:53:12 PM PST 24 Jan 10 12:55:26 PM PST 24 3956753105 ps
T182 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.583808046 Jan 10 12:53:03 PM PST 24 Jan 10 12:54:15 PM PST 24 41993999 ps
T183 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2283161666 Jan 10 12:53:03 PM PST 24 Jan 10 12:54:15 PM PST 24 64743506 ps
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T185 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.269881967 Jan 10 12:53:12 PM PST 24 Jan 10 12:54:24 PM PST 24 23834071 ps
T186 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3321844236 Jan 10 12:52:48 PM PST 24 Jan 10 12:54:04 PM PST 24 700921122 ps
T187 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1817278068 Jan 10 12:53:15 PM PST 24 Jan 10 12:54:28 PM PST 24 50702694 ps
T188 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.215683586 Jan 10 12:52:52 PM PST 24 Jan 10 12:54:04 PM PST 24 29103198 ps
T189 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2806347076 Jan 10 12:52:55 PM PST 24 Jan 10 12:54:13 PM PST 24 524909480 ps
T190 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.102386089 Jan 10 12:55:07 PM PST 24 Jan 10 12:56:13 PM PST 24 48964855 ps
T191 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1757529101 Jan 10 12:52:56 PM PST 24 Jan 10 12:54:11 PM PST 24 122616471 ps
T107 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3933895914 Jan 10 12:52:58 PM PST 24 Jan 10 12:54:13 PM PST 24 411511712 ps
T192 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3734348929 Jan 10 12:52:58 PM PST 24 Jan 10 12:54:10 PM PST 24 49734197 ps
T193 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1874297692 Jan 10 12:53:15 PM PST 24 Jan 10 12:55:25 PM PST 24 15420275757 ps
T194 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4291624707 Jan 10 12:55:05 PM PST 24 Jan 10 12:56:13 PM PST 24 33477819 ps
T195 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4122516734 Jan 10 12:53:02 PM PST 24 Jan 10 12:54:17 PM PST 24 48705393 ps
T196 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1605608582 Jan 10 12:53:17 PM PST 24 Jan 10 12:54:37 PM PST 24 1413238061 ps
T197 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3992412907 Jan 10 12:53:09 PM PST 24 Jan 10 12:54:25 PM PST 24 936954100 ps
T198 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.561866643 Jan 10 12:53:02 PM PST 24 Jan 10 12:54:19 PM PST 24 1380864458 ps
T199 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.29849526 Jan 10 12:53:01 PM PST 24 Jan 10 12:54:14 PM PST 24 176122276 ps
T106 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2745840567 Jan 10 12:53:13 PM PST 24 Jan 10 12:54:27 PM PST 24 190142182 ps
T200 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2065122275 Jan 10 12:52:54 PM PST 24 Jan 10 12:54:08 PM PST 24 75892558 ps
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T203 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.370126711 Jan 10 12:53:04 PM PST 24 Jan 10 12:54:19 PM PST 24 314824038 ps
T204 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1613669632 Jan 10 12:55:05 PM PST 24 Jan 10 12:58:30 PM PST 24 3859098777 ps
T205 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3541193351 Jan 10 12:53:02 PM PST 24 Jan 10 12:54:14 PM PST 24 214115221 ps
T105 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2122576939 Jan 10 12:53:14 PM PST 24 Jan 10 12:54:28 PM PST 24 211354439 ps
T206 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1837676465 Jan 10 12:52:59 PM PST 24 Jan 10 12:54:15 PM PST 24 145862104 ps
T207 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3939612108 Jan 10 12:53:28 PM PST 24 Jan 10 12:54:41 PM PST 24 14845833 ps
T208 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2159441847 Jan 10 12:53:08 PM PST 24 Jan 10 12:54:22 PM PST 24 58802288 ps
T209 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3395046278 Jan 10 12:53:13 PM PST 24 Jan 10 12:54:26 PM PST 24 18668121 ps
T210 /workspace/coverage/default/31.sram_ctrl_partial_access.1223323341 Jan 10 01:28:18 PM PST 24 Jan 10 01:29:23 PM PST 24 2795999448 ps
T211 /workspace/coverage/default/29.sram_ctrl_alert_test.1547385268 Jan 10 01:27:44 PM PST 24 Jan 10 01:28:54 PM PST 24 14287234 ps
T96 /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3659465522 Jan 10 01:29:01 PM PST 24 Jan 10 02:38:24 PM PST 24 2149573954 ps
T93 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2917262191 Jan 10 01:26:04 PM PST 24 Jan 10 01:34:15 PM PST 24 63684879458 ps
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T213 /workspace/coverage/default/43.sram_ctrl_bijection.2576538014 Jan 10 01:28:19 PM PST 24 Jan 10 01:47:53 PM PST 24 211936161922 ps
T33 /workspace/coverage/default/48.sram_ctrl_ram_cfg.2355917381 Jan 10 01:30:43 PM PST 24 Jan 10 01:30:51 PM PST 24 1546368950 ps
T4 /workspace/coverage/default/42.sram_ctrl_lc_escalation.619916096 Jan 10 01:28:21 PM PST 24 Jan 10 01:31:17 PM PST 24 39178940460 ps
T110 /workspace/coverage/default/8.sram_ctrl_executable.2425643009 Jan 10 01:26:22 PM PST 24 Jan 10 01:29:37 PM PST 24 66385137200 ps
T214 /workspace/coverage/default/23.sram_ctrl_max_throughput.1934549111 Jan 10 01:26:58 PM PST 24 Jan 10 01:29:00 PM PST 24 2902504204 ps
T215 /workspace/coverage/default/8.sram_ctrl_alert_test.2370849867 Jan 10 01:26:29 PM PST 24 Jan 10 01:26:43 PM PST 24 35667796 ps
T216 /workspace/coverage/default/19.sram_ctrl_multiple_keys.3208914852 Jan 10 01:26:58 PM PST 24 Jan 10 01:54:17 PM PST 24 154289761568 ps
T217 /workspace/coverage/default/47.sram_ctrl_smoke.3212811195 Jan 10 01:28:19 PM PST 24 Jan 10 01:29:15 PM PST 24 697012908 ps
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T17 /workspace/coverage/default/16.sram_ctrl_access_during_key_req.2492371701 Jan 10 01:26:57 PM PST 24 Jan 10 01:41:09 PM PST 24 154816222614 ps
T95 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2442313992 Jan 10 01:27:02 PM PST 24 Jan 10 01:30:58 PM PST 24 5116943984 ps
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T97 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.4232287083 Jan 10 01:27:12 PM PST 24 Jan 10 02:45:14 PM PST 24 2135739885 ps
T218 /workspace/coverage/default/16.sram_ctrl_alert_test.4114299754 Jan 10 01:26:58 PM PST 24 Jan 10 01:27:11 PM PST 24 16756361 ps
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T220 /workspace/coverage/default/40.sram_ctrl_alert_test.676977542 Jan 10 01:28:08 PM PST 24 Jan 10 01:29:10 PM PST 24 14748258 ps
T221 /workspace/coverage/default/18.sram_ctrl_bijection.1097890989 Jan 10 01:26:57 PM PST 24 Jan 10 01:43:12 PM PST 24 149414339568 ps
T118 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.4172093042 Jan 10 01:27:16 PM PST 24 Jan 10 01:39:25 PM PST 24 29330942689 ps
T79 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.838536570 Jan 10 01:27:07 PM PST 24 Jan 10 01:29:41 PM PST 24 9211905395 ps
T5 /workspace/coverage/default/38.sram_ctrl_stress_all.4258383388 Jan 10 01:28:22 PM PST 24 Jan 10 02:54:22 PM PST 24 1275452371427 ps
T222 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.653734219 Jan 10 01:26:59 PM PST 24 Jan 10 02:35:57 PM PST 24 636805997 ps
T223 /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3834076715 Jan 10 01:26:38 PM PST 24 Jan 10 01:34:06 PM PST 24 6043341621 ps
T27 /workspace/coverage/default/8.sram_ctrl_lc_escalation.3398968644 Jan 10 01:26:44 PM PST 24 Jan 10 01:28:38 PM PST 24 3643904415 ps
T224 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.955519033 Jan 10 01:30:44 PM PST 24 Jan 10 01:35:28 PM PST 24 12781214062 ps
T80 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2356613420 Jan 10 01:26:42 PM PST 24 Jan 10 01:28:11 PM PST 24 1987390657 ps
T225 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2124773217 Jan 10 01:27:31 PM PST 24 Jan 10 01:30:39 PM PST 24 9877894325 ps
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