Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	114640856	1			T1	158246		T2	912		T3	397067
triple_byte_access	2818476	1			T1	3161		T2	814		T3	7868
halfword_access	4323089	1			T1	4728		T2	1218		T3	11989
byte_access	6035213	1			T1	6143		T2	1619		T3	15828
zero_access	1816955	1			T1	1593		T2	396		T3	3993

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

64215216

1

T1

87342

T2

2494

T3

227143

auto[1]

65419373

1

T1

86529

T2

2465

T3

209602

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	56620917	1			T1	79569		T2	439		T3	206529
auto[0]	triple_byte_access	1338600	1			T1	1559		T2	401		T3	4104
auto[0]	halfword_access	2101619	1			T1	2369		T2	634		T3	6252
auto[0]	byte_access	3077180	1			T1	3050		T2	829		T3	8159
auto[0]	zero_access	1076900	1			T1	795		T2	191		T3	2099
auto[1]	word_access	58019939	1			T1	78677		T2	473		T3	190538
auto[1]	triple_byte_access	1479876	1			T1	1602		T2	413		T3	3764
auto[1]	halfword_access	2221470	1			T1	2359		T2	584		T3	5737
auto[1]	byte_access	2958033	1			T1	3093		T2	790		T3	7669
auto[1]	zero_access	740055	1			T1	798		T2	205		T3	1894