Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	279927357	1			T1	6278		T2	159458		T4	4892
instr_valid_dis	261140910	1			T1	6278		T2	159458		T4	4892
instr_en	13242373	1			T5	140970		T6	18320		T50	88

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9959928	1			T5	18842		T14	328		T18	92250
sram_ifetch_valid_disable	255107681	1			T1	6278		T2	159458		T4	4892
sram_ifetch_enable	14859748	1			T5	110466		T14	55134		T18	135790

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	279927357	1			T1	6278		T2	159458		T4	4892
hw_debug_en_valid_off	255772182	1			T1	6278		T2	159458		T4	4892
hw_debug_en_on	17401393	1			T5	171342		T14	20022		T18	158458

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	255107681	1			T1	6278		T2	159458		T4	4892
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	247892666	1			T1	6278		T2	159458		T4	4892
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	5305933	1			T5	94310		T50	88		T52	5352
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	2392124	1			T14	328		T6	52542		T22	38728
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	928358	1			T14	328		T6	26672		T22	38728
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	960870	1			T6	18320		T135	18520		T131	52834
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	6338728	1			T5	18842		T6	67182		T22	60574
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	4525984	1			T6	31598		T22	60574		T50	78648
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1195564	1			T5	18842		T135	19924		T132	20000
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	5505595	1			T5	139504		T14	20022		T18	48930
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2258476	1			T5	43958		T14	20022		T18	48930
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2386019	1			T5	53784		T52	5352		T135	55706

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	5327370	1			T5	27818		T135	56716		T131	457550
lc_exec_en	5557070	1			T5	12996		T18	109528		T6	100476
valid_exec_dis	254281948	1			T1	6278		T2	159458		T4	4892
invalid_exec_dis	24819676	1			T5	129308		T14	55462		T18	228040